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Add read and write preambles to DDR4.

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This commit is contained in:
Lukas Steiner
2020-08-18 10:12:19 +02:00
parent 911a6cfe7b
commit d2a90773eb
8 changed files with 21 additions and 7 deletions
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2
DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json
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@@ -49,11 +49,13 @@
"RFC2": 150,
"RFC4": 103,
"RL": 13,
"RPRE": 1,
"RP": 13,
"RRD_L": 5,
"RRD_S": 4,
"RTP": 8,
"WL": 12,
"WPRE": 1,
"WR": 14,
"WTR_L": 7,
"WTR_S": 3,

2
DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json
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@@ -49,11 +49,13 @@
"RFC2": 192,
"RFC4": 132,
"RL": 16,
"RPRE": 1,
"RP": 16,
"RRD_L": 6,
"RRD_S": 4,
"RTP": 12,
"WL": 16,
"WPRE": 1,
"WR": 18,
"WTR_L": 9,
"WTR_S": 3,

2
DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json
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@@ -47,11 +47,13 @@
"REFI": 3644,
"RFC": 243,
"RL": 13,
"RPRE": 1,
"RP": 13,
"RRD_L": 5,
"RRD_S": 4,
"RTP": 8,
"WL": 12,
"WPRE": 1,
"WR": 14,
"WTR_L": 7,
"WTR_S": 3,

2
DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json
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@@ -47,11 +47,13 @@
"REFI": 4680,
"RFC": 313,
"RL": 16,
"RPRE": 1,
"RP": 16,
"RRD_L": 6,
"RRD_S": 4,
"RTP": 12,
"WL": 16,
"WPRE": 1,
"WR": 18,
"WTR_L": 9,
"WTR_S": 3,

10
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
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@@ -55,19 +55,17 @@ MemSpecDDR4::MemSpecDDR4(json &memspec)
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tPD (tCKE),
tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tRPRE (tCK * parseUint(memspec["memtimingspec"]["RPRE"], "RPRE")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tWPRE (tCK * parseUint(memspec["memtimingspec"]["WPRE"], "WPRE")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tCCD_S (tCK * parseUint(memspec["memtimingspec"]["CCD_S"], "CCD_S")),
tCCD_L (tCK * parseUint(memspec["memtimingspec"]["CCD_L"], "CCD_L")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tREFI ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 4) ?
(tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 4)) :
((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 2) ?
@@ -79,6 +77,10 @@ MemSpecDDR4::MemSpecDDR4(json &memspec)
(tCK * parseUint(memspec["memtimingspec"]["RFC2"], "RFC2")) :
(tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")))),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
tCCD_S (tCK * parseUint(memspec["memtimingspec"]["CCD_S"], "CCD_S")),
tCCD_L (tCK * parseUint(memspec["memtimingspec"]["CCD_L"], "CCD_L")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tRRD_S (tCK * parseUint(memspec["memtimingspec"]["RRD_S"], "RRD_S")),
tRRD_L (tCK * parseUint(memspec["memtimingspec"]["RRD_L"], "RRD_L")),
tWTR_S (tCK * parseUint(memspec["memtimingspec"]["WTR_S"], "WTR_S")),

2
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
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@@ -52,8 +52,10 @@ public:
const sc_time tRC;
const sc_time tRCD;
const sc_time tRL;
const sc_time tRPRE;
const sc_time tRTP;
const sc_time tWL;
const sc_time tWPRE;
const sc_time tWR;
const sc_time tXP;
const sc_time tXS;

6
DRAMSys/library/src/controller/checker/CheckerDDR4.cpp
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@@ -52,11 +52,11 @@ CheckerDDR4::CheckerDDR4()
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
tRDWR = memSpec->tRL + tBURST - memSpec->tWL + 2 * memSpec->tCK;
tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL;
tRDWR = memSpec->tRL + tBURST + memSpec->tCK - memSpec->tWL + memSpec->tWPRE;
tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL + memSpec->tWPRE;
tWRRD_S = memSpec->tWL + tBURST + memSpec->tWTR_S;
tWRRD_L = memSpec->tWL + tBURST + memSpec->tWTR_L;
tWRRD_R = memSpec->tWL + tBURST + memSpec->tRTRS - memSpec->tRL;
tWRRD_R = memSpec->tWL + tBURST + memSpec->tRTRS - memSpec->tRL + memSpec->tRPRE;
tWRPRE = memSpec->tWL + tBURST + memSpec->tWR;
tRDPDEN = memSpec->tRL + tBURST + memSpec->tCK;
tWRPDEN = memSpec->tWL + tBURST + memSpec->tWR;

2
DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json
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@@ -47,11 +47,13 @@
"REFI": 3644,
"RFC": 243,
"RL": 13,
"RPRE": 1,
"RP": 13,
"RRD_L": 5,
"RRD_S": 4,
"RTP": 8,
"WL": 12,
"WPRE": 1,
"WR": 14,
"WTR_L": 7,
"WTR_S": 3,