From d2a90773eb539f9ec5c48988d1411157ddc4965c Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 18 Aug 2020 10:12:19 +0200 Subject: [PATCH] Add read and write preambles to DDR4. --- .../configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json | 2 ++ .../configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json | 2 ++ .../configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json | 2 ++ .../configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json | 2 ++ .../library/src/configuration/memspec/MemSpecDDR4.cpp | 10 ++++++---- .../library/src/configuration/memspec/MemSpecDDR4.h | 2 ++ DRAMSys/library/src/controller/checker/CheckerDDR4.cpp | 6 +++--- .../configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json | 2 ++ 8 files changed, 21 insertions(+), 7 deletions(-) diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json index f993ede8..229ef834 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json @@ -49,11 +49,13 @@ "RFC2": 150, "RFC4": 103, "RL": 13, + "RPRE": 1, "RP": 13, "RRD_L": 5, "RRD_S": 4, "RTP": 8, "WL": 12, + "WPRE": 1, "WR": 14, "WTR_L": 7, "WTR_S": 3, diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json index 4eec52f5..f6ad7862 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json @@ -49,11 +49,13 @@ "RFC2": 192, "RFC4": 132, "RL": 16, + "RPRE": 1, "RP": 16, "RRD_L": 6, "RRD_S": 4, "RTP": 12, "WL": 16, + "WPRE": 1, "WR": 18, "WTR_L": 9, "WTR_S": 3, diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json index cb4e5e7c..159b0b73 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -47,11 +47,13 @@ "REFI": 3644, "RFC": 243, "RL": 13, + "RPRE": 1, "RP": 13, "RRD_L": 5, "RRD_S": 4, "RTP": 8, "WL": 12, + "WPRE": 1, "WR": 14, "WTR_L": 7, "WTR_S": 3, diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json index 865c7b5b..4973bd10 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json @@ -47,11 +47,13 @@ "REFI": 4680, "RFC": 313, "RL": 16, + "RPRE": 1, "RP": 16, "RRD_L": 6, "RRD_S": 4, "RTP": 12, "WL": 16, + "WPRE": 1, "WR": 18, "WTR_L": 9, "WTR_S": 3, diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index d3bd513c..fdb2f843 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -55,19 +55,17 @@ MemSpecDDR4::MemSpecDDR4(json &memspec) tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), tPD (tCKE), tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), - tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")), tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")), + tRPRE (tCK * parseUint(memspec["memtimingspec"]["RPRE"], "RPRE")), tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")), tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")), + tWPRE (tCK * parseUint(memspec["memtimingspec"]["WPRE"], "WPRE")), tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")), tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")), tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")), - tCCD_S (tCK * parseUint(memspec["memtimingspec"]["CCD_S"], "CCD_S")), - tCCD_L (tCK * parseUint(memspec["memtimingspec"]["CCD_L"], "CCD_L")), - tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")), tREFI ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 4) ? (tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 4)) : ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 2) ? @@ -79,6 +77,10 @@ MemSpecDDR4::MemSpecDDR4(json &memspec) (tCK * parseUint(memspec["memtimingspec"]["RFC2"], "RFC2")) : (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")))), tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), + tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), + tCCD_S (tCK * parseUint(memspec["memtimingspec"]["CCD_S"], "CCD_S")), + tCCD_L (tCK * parseUint(memspec["memtimingspec"]["CCD_L"], "CCD_L")), + tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")), tRRD_S (tCK * parseUint(memspec["memtimingspec"]["RRD_S"], "RRD_S")), tRRD_L (tCK * parseUint(memspec["memtimingspec"]["RRD_L"], "RRD_L")), tWTR_S (tCK * parseUint(memspec["memtimingspec"]["WTR_S"], "WTR_S")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index 9395626c..c702f871 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -52,8 +52,10 @@ public: const sc_time tRC; const sc_time tRCD; const sc_time tRL; + const sc_time tRPRE; const sc_time tRTP; const sc_time tWL; + const sc_time tWPRE; const sc_time tWR; const sc_time tXP; const sc_time tXS; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index a8439903..e2529753 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -52,11 +52,11 @@ CheckerDDR4::CheckerDDR4() last4Activates = std::vector>(memSpec->numberOfRanks); tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; - tRDWR = memSpec->tRL + tBURST - memSpec->tWL + 2 * memSpec->tCK; - tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; + tRDWR = memSpec->tRL + tBURST + memSpec->tCK - memSpec->tWL + memSpec->tWPRE; + tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL + memSpec->tWPRE; tWRRD_S = memSpec->tWL + tBURST + memSpec->tWTR_S; tWRRD_L = memSpec->tWL + tBURST + memSpec->tWTR_L; - tWRRD_R = memSpec->tWL + tBURST + memSpec->tRTRS - memSpec->tRL; + tWRRD_R = memSpec->tWL + tBURST + memSpec->tRTRS - memSpec->tRL + memSpec->tRPRE; tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; tRDPDEN = memSpec->tRL + tBURST + memSpec->tCK; tWRPDEN = memSpec->tWL + tBURST + memSpec->tWR; diff --git a/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json index 35a1dd8c..960db938 100644 --- a/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -47,11 +47,13 @@ "REFI": 3644, "RFC": 243, "RL": 13, + "RPRE": 1, "RP": 13, "RRD_L": 5, "RRD_S": 4, "RTP": 8, "WL": 12, + "WPRE": 1, "WR": 14, "WTR_L": 7, "WTR_S": 3,