Merge branch 'development'
# Conflicts: # .gitlab-ci.yml # DRAMSys/CMakeLists.txt # DRAMSys/gem5/CMakeLists.txt # DRAMSys/library/CMakeLists.txt # DRAMSys/library/resources/configs/mcconfigs/fifo.json # DRAMSys/library/resources/configs/mcconfigs/fifoStrict.json # DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json # DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.json # DRAMSys/library/resources/configs/memspecs/HBM2.json # DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json # DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json # DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json # DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json # DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json # DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json # DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json # DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json # DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json # DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json # DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json # DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json # DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json # DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json # DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json # DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json # DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json # DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json # DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json # DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json # DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json # DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json # DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json # DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json # DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json # DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json # DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json # DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json # DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json # DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json # DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json # DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json # DRAMSys/library/resources/configs/simulator/ddr3.json # DRAMSys/library/resources/configs/simulator/ddr3_ecc.json # DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json # DRAMSys/library/resources/configs/simulator/ddr4.json # DRAMSys/library/resources/configs/simulator/hbm2.json # DRAMSys/library/resources/configs/simulator/lpddr4.json # DRAMSys/library/resources/configs/simulator/wideio.json # DRAMSys/library/resources/configs/simulator/wideio_ecc.json # DRAMSys/library/resources/configs/simulator/wideio_thermal.json # DRAMSys/library/src/common/TlmRecorder.cpp # DRAMSys/library/src/common/utils.cpp # DRAMSys/library/src/common/utils.h # DRAMSys/library/src/configuration/Configuration.cpp # DRAMSys/library/src/configuration/memspec/MemSpec.cpp # DRAMSys/library/src/configuration/memspec/MemSpec.h # DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp # DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp # DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp # DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp # DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp # DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp # DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp # DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp # DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp # DRAMSys/library/src/controller/Controller.cpp # DRAMSys/library/src/controller/ControllerRecordable.cpp # DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp # DRAMSys/library/src/simulation/Arbiter.cpp # DRAMSys/library/src/simulation/DRAMSys.cpp # DRAMSys/library/src/simulation/DRAMSysRecordable.cpp # DRAMSys/library/src/simulation/Setup.h # DRAMSys/library/src/simulation/dram/DramRecordable.cpp # DRAMSys/pct/createPlatform.tcl # DRAMSys/simulator/CMakeLists.txt # DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml # DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml # DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml # DRAMSys/tests/DDR4/configs/simulator/ddr4.json # DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json # DRAMSys/tests/lpddr4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json # README.md
This commit is contained in:
Lukas Steiner
1
.gitignore
vendored
1
.gitignore
vendored
@@ -5,6 +5,7 @@
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||||
/dram/build
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*.user
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*.tdb
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||||
!/DRAMSys/tests/*/expected/*.tdb
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||||
*.tdb-journal
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||||
*.out
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||||
/build-simulation
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||||
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||||
@@ -2,14 +2,12 @@
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||||
image: gcc
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||||
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||||
variables:
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GIT_STRATEGY: clone
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GIT_STRATEGY: fetch
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||||
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||||
stages:
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- build
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- dramsys-gem5-build
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- WIDEIO
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- DDR3
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- Coverage
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- tests
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- coverage
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build:
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stage: build
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@@ -19,12 +17,14 @@ build:
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- rm -rf build
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- mkdir -p build
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- cd build
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- qmake ../DRAMSys/DRAMSys.pro
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- make -j4
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- export COVERAGE=true
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- cmake ../DRAMSys
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- make -j 16
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- find . -name "*.o" -type f -delete
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- rm -rf ${CI_PROJECT_DIR}/coverage
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- mkdir -p ${CI_PROJECT_DIR}/coverage
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cache:
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key: build
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paths:
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@@ -34,23 +34,26 @@ build:
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artifacts:
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paths:
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- coverage/
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coverage:
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stage: Coverage
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stage: coverage
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coverage: '/Total:\|(\d+\.?\d+\%)/'
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script:
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# delete all empty files since they produce errors
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- find coverage -size 0 -type f -delete
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- ls coverage/ -lah
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- lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out
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||||
- lcov --list coverage/final.out
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||||
- lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out
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||||
- lcov --remove coverage/final.out '*/systemc*/include/*' '*/traceAnalyzer/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out
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- lcov --list coverage/final_dramsys.out
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artifacts:
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paths:
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- coverage/final.out
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- coverage/final_dramsys.out
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include:
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- '/DRAMSys/tests/DDR3/ci.yml'
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- '/DRAMSys/tests/WIDEIO/ci.yml'
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#- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used
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- '/DRAMSys/tests/lpddr4/ci.yml'
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- '/DRAMSys/tests/ddr3_multirank/ci.yml'
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- '/DRAMSys/tests/DDR4/ci.yml'
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- '/DRAMSys/tests/HBM2/ci.yml'
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#- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used
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@@ -1,4 +1,4 @@
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# Copyright (c) 2020, Fraunhofer IESE
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# Copyright (c) 2020, Technische Universität Kaiserslautern
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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@@ -28,7 +28,9 @@
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# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Author: Matthias Jung
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# Authors:
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# Matthias Jung
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# Lukas Steiner
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cmake_minimum_required(VERSION 3.10)
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@@ -39,22 +41,21 @@ project(DRAMSys)
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set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
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set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows")
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|
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# Add sqlite3 Dependency:
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set(BUILD_ENABLE_RTREE ON CACHE BOOL "Enable R-Tree Feature")
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set(BUILD_ENABLE_RTREE ON)
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add_subdirectory(library/src/common/third_party/sqlite-amalgamation)
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|
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# Add DRAMSysLibrary:
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add_subdirectory(library)
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|
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# Add TraceAnalyzer:
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add_subdirectory(traceAnalyzer)
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if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/traceAnalyzer)
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message("---- Trace Analyzer included")
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add_subdirectory(traceAnalyzer)
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endif()
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# Build:
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add_executable(DRAMSys simulator/main.cpp)
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target_include_directories(DRAMSys
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PUBLIC library/src/simulation/
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PUBLIC library/src/common/third_party/sqlite-amalgamation/
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)
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target_link_libraries(DRAMSys sqlite3::sqlite3 systemc DRAMSysLibrary)
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# Add DRAMSysSimulator:
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add_subdirectory(simulator)
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|
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# Add DRAMSysgem5
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if(DEFINED ENV{GEM5})
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message("---- gem5 coupling included")
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add_subdirectory(gem5)
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endif()
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||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
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Load Diff
|
Before Width: | Height: | Size: 130 KiB |
File diff suppressed because it is too large
Load Diff
|
Before Width: | Height: | Size: 300 KiB |
File diff suppressed because it is too large
Load Diff
|
Before Width: | Height: | Size: 114 KiB |
File diff suppressed because it is too large
Load Diff
|
Before Width: | Height: | Size: 169 KiB |
File diff suppressed because it is too large
Load Diff
|
Before Width: | Height: | Size: 171 KiB |
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Load Diff
|
Before Width: | Height: | Size: 172 KiB |
File diff suppressed because it is too large
Load Diff
|
Before Width: | Height: | Size: 176 KiB |
@@ -1,247 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN"
|
||||
"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
|
||||
<!-- Generated by graphviz version 2.38.0 (20140413.2041)
|
||||
-->
|
||||
<!-- Title: G Pages: 1 -->
|
||||
<svg width="582pt" height="970pt"
|
||||
viewBox="0.00 0.00 582.00 970.00" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
|
||||
<g id="graph0" class="graph" transform="scale(1 1) rotate(0) translate(4 966)">
|
||||
<title>G</title>
|
||||
<polygon fill="white" stroke="none" points="-4,4 -4,-966 578,-966 578,4 -4,4"/>
|
||||
<g id="clust1" class="cluster"><title>cluster_root</title>
|
||||
<g id="a_clust1"><a xlink:title="eventq_index=0 full_system=false sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000">
|
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<path fill="#bab6ae" stroke="#000000" d="M20,-8C20,-8 554,-8 554,-8 560,-8 566,-14 566,-20 566,-20 566,-942 566,-942 566,-948 560,-954 554,-954 554,-954 20,-954 20,-954 14,-954 8,-948 8,-942 8,-942 8,-20 8,-20 8,-14 14,-8 20,-8"/>
|
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<text text-anchor="middle" x="287" y="-938.8" font-family="Arial" font-size="14.00" fill="#000000">root </text>
|
||||
<text text-anchor="middle" x="287" y="-923.8" font-family="Arial" font-size="14.00" fill="#000000">: Root</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust2" class="cluster"><title>cluster_system</title>
|
||||
<g id="a_clust2"><a xlink:title="boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 kernel= kernel_addr_check=false kernel_extras= load_addr_mask=18446744073709551615 load_offset=0 mem_mode=timing mem_ranges=0:536870911:0:0:0:0 memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= readfile= symbolfile= thermal_components= thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1">
|
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<path fill="#e4e7eb" stroke="#000000" d="M28,-16C28,-16 546,-16 546,-16 552,-16 558,-22 558,-28 558,-28 558,-896 558,-896 558,-902 552,-908 546,-908 546,-908 28,-908 28,-908 22,-908 16,-902 16,-896 16,-896 16,-28 16,-28 16,-22 22,-16 28,-16"/>
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<text text-anchor="middle" x="287" y="-892.8" font-family="Arial" font-size="14.00" fill="#000000">system </text>
|
||||
<text text-anchor="middle" x="287" y="-877.8" font-family="Arial" font-size="14.00" fill="#000000">: System</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust3" class="cluster"><title>cluster_system_membus</title>
|
||||
<g id="a_clust3"><a xlink:title="clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 point_of_coherency=true point_of_unification=true power_model= response_latency=2 snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false width=16">
|
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<path fill="#6f798c" stroke="#000000" d="M317,-155C317,-155 441,-155 441,-155 447,-155 453,-161 453,-167 453,-167 453,-234 453,-234 453,-240 447,-246 441,-246 441,-246 317,-246 317,-246 311,-246 305,-240 305,-234 305,-234 305,-167 305,-167 305,-161 311,-155 317,-155"/>
|
||||
<text text-anchor="middle" x="379" y="-230.8" font-family="Arial" font-size="14.00" fill="#000000">membus </text>
|
||||
<text text-anchor="middle" x="379" y="-215.8" font-family="Arial" font-size="14.00" fill="#000000">: SystemXBar</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust5" class="cluster"><title>cluster_system_external_memory</title>
|
||||
<g id="a_clust5"><a xlink:title="addr_ranges=0:536870911:0:0:0:0 clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 port_data=transactor port_type=tlm_slave power_model=">
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<path fill="#bab6ae" stroke="#000000" d="M362,-24C362,-24 468,-24 468,-24 474,-24 480,-30 480,-36 480,-36 480,-103 480,-103 480,-109 474,-115 468,-115 468,-115 362,-115 362,-115 356,-115 350,-109 350,-103 350,-103 350,-36 350,-36 350,-30 356,-24 362,-24"/>
|
||||
<text text-anchor="middle" x="415" y="-99.8" font-family="Arial" font-size="14.00" fill="#000000">external_memory </text>
|
||||
<text text-anchor="middle" x="415" y="-84.8" font-family="Arial" font-size="14.00" fill="#000000">: ExternalSlave</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust6" class="cluster"><title>cluster_system_tol2bus</title>
|
||||
<g id="a_clust6"><a xlink:title="clk_domain=system.cpu_clk_domain default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 point_of_coherency=false point_of_unification=true power_model= response_latency=1 snoop_filter=system.tol2bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false width=32">
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<path fill="#6f798c" stroke="#000000" d="M351,-417C351,-417 475,-417 475,-417 481,-417 487,-423 487,-429 487,-429 487,-496 487,-496 487,-502 481,-508 475,-508 475,-508 351,-508 351,-508 345,-508 339,-502 339,-496 339,-496 339,-429 339,-429 339,-423 345,-417 351,-417"/>
|
||||
<text text-anchor="middle" x="413" y="-492.8" font-family="Arial" font-size="14.00" fill="#000000">tol2bus </text>
|
||||
<text text-anchor="middle" x="413" y="-477.8" font-family="Arial" font-size="14.00" fill="#000000">: L2XBar</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust11" class="cluster"><title>cluster_system_l2</title>
|
||||
<g id="a_clust11"><a xlink:title="addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 mshrs=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= prefetch_on_access=false prefetcher=Null replacement_policy=system.l2.replacement_policy response_latency=20 sequential_access=false size=2097152 system=system tag_latency=20 tags=system.l2.tags tgts_per_mshr=12 warmup_percentage=0 write_buffers=8 writeback_clean=false">
|
||||
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|
||||
<text text-anchor="middle" x="454" y="-361.8" font-family="Arial" font-size="14.00" fill="#000000">l2 </text>
|
||||
<text text-anchor="middle" x="454" y="-346.8" font-family="Arial" font-size="14.00" fill="#000000">: L2Cache</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust17" class="cluster"><title>cluster_system_cpu</title>
|
||||
<g id="a_clust17"><a xlink:title="branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_gating_on_idle=false power_model= profile=0 progress_interval=0 pwr_gating_latency=300 simpoint_start_insts= socket_id=0 switched_out=false syscallRetryLatency=10000 system=system tracer=system.cpu.tracer wait_for_remote_gdb=false workload=system.cpu.workload">
|
||||
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|
||||
<text text-anchor="middle" x="287" y="-846.8" font-family="Arial" font-size="14.00" fill="#000000">cpu </text>
|
||||
<text text-anchor="middle" x="287" y="-831.8" font-family="Arial" font-size="14.00" fill="#000000">: TimingSimpleCPU</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust19" class="cluster"><title>cluster_system_cpu_dtb</title>
|
||||
<g id="a_clust19"><a xlink:title="eventq_index=0 is_stage2=false size=64 sys=system walker=system.cpu.dtb.walker">
|
||||
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|
||||
<text text-anchor="middle" x="318" y="-800.8" font-family="Arial" font-size="14.00" fill="#000000">dtb </text>
|
||||
<text text-anchor="middle" x="318" y="-785.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTLB</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust20" class="cluster"><title>cluster_system_cpu_dtb_walker</title>
|
||||
<g id="a_clust20"><a xlink:title="clk_domain=system.cpu_clk_domain default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= sys=system">
|
||||
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|
||||
<text text-anchor="middle" x="318" y="-754.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
|
||||
<text text-anchor="middle" x="318" y="-739.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust22" class="cluster"><title>cluster_system_cpu_itb</title>
|
||||
<g id="a_clust22"><a xlink:title="eventq_index=0 is_stage2=false size=64 sys=system walker=system.cpu.itb.walker">
|
||||
<path fill="#bab6ae" stroke="#000000" d="M410,-671C410,-671 530,-671 530,-671 536,-671 542,-677 542,-683 542,-683 542,-804 542,-804 542,-810 536,-816 530,-816 530,-816 410,-816 410,-816 404,-816 398,-810 398,-804 398,-804 398,-683 398,-683 398,-677 404,-671 410,-671"/>
|
||||
<text text-anchor="middle" x="470" y="-800.8" font-family="Arial" font-size="14.00" fill="#000000">itb </text>
|
||||
<text text-anchor="middle" x="470" y="-785.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTLB</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust23" class="cluster"><title>cluster_system_cpu_itb_walker</title>
|
||||
<g id="a_clust23"><a xlink:title="clk_domain=system.cpu_clk_domain default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= sys=system">
|
||||
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|
||||
<text text-anchor="middle" x="470" y="-754.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
|
||||
<text text-anchor="middle" x="470" y="-739.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust30" class="cluster"><title>cluster_system_cpu_icache</title>
|
||||
<g id="a_clust30"><a xlink:title="addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 is_read_only=true max_miss_count=0 mshrs=4 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= prefetch_on_access=false prefetcher=Null replacement_policy=system.cpu.icache.replacement_policy response_latency=2 sequential_access=false size=32768 system=system tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 warmup_percentage=0 write_buffers=8 writeback_clean=true">
|
||||
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|
||||
<text text-anchor="middle" x="328" y="-623.8" font-family="Arial" font-size="14.00" fill="#000000">icache </text>
|
||||
<text text-anchor="middle" x="328" y="-608.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_ICache</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust33" class="cluster"><title>cluster_system_cpu_dcache</title>
|
||||
<g id="a_clust33"><a xlink:title="addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 mshrs=4 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= prefetch_on_access=false prefetcher=Null replacement_policy=system.cpu.dcache.replacement_policy response_latency=2 sequential_access=false size=65536 system=system tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 warmup_percentage=0 write_buffers=8 writeback_clean=false">
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|
||||
<text text-anchor="middle" x="128" y="-623.8" font-family="Arial" font-size="14.00" fill="#000000">dcache </text>
|
||||
<text text-anchor="middle" x="128" y="-608.8" font-family="Arial" font-size="14.00" fill="#000000">: L1_DCache</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<!-- system_system_port -->
|
||||
<g id="node1" class="node"><title>system_system_port</title>
|
||||
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|
||||
<text text-anchor="middle" x="300" y="-308.8" font-family="Arial" font-size="14.00" fill="#000000">system_port</text>
|
||||
</g>
|
||||
<!-- system_membus_slave -->
|
||||
<g id="node3" class="node"><title>system_membus_slave</title>
|
||||
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|
||||
<text text-anchor="middle" x="340" y="-177.8" font-family="Arial" font-size="14.00" fill="#000000">slave</text>
|
||||
</g>
|
||||
<!-- system_system_port->system_membus_slave -->
|
||||
<g id="edge1" class="edge"><title>system_system_port->system_membus_slave</title>
|
||||
<path fill="none" stroke="black" d="M305.312,-294.37C312.036,-272.685 323.697,-235.078 331.625,-209.51"/>
|
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<polygon fill="black" stroke="black" points="335.048,-210.289 334.666,-199.701 328.362,-208.216 335.048,-210.289"/>
|
||||
</g>
|
||||
<!-- system_membus_master -->
|
||||
<g id="node2" class="node"><title>system_membus_master</title>
|
||||
<path fill="#586070" stroke="#000000" d="M397,-163.5C397,-163.5 433,-163.5 433,-163.5 439,-163.5 445,-169.5 445,-175.5 445,-175.5 445,-187.5 445,-187.5 445,-193.5 439,-199.5 433,-199.5 433,-199.5 397,-199.5 397,-199.5 391,-199.5 385,-193.5 385,-187.5 385,-187.5 385,-175.5 385,-175.5 385,-169.5 391,-163.5 397,-163.5"/>
|
||||
<text text-anchor="middle" x="415" y="-177.8" font-family="Arial" font-size="14.00" fill="#000000">master</text>
|
||||
</g>
|
||||
<!-- system_external_memory_port -->
|
||||
<g id="node4" class="node"><title>system_external_memory_port</title>
|
||||
<path fill="#94918b" stroke="#000000" d="M400,-32.5C400,-32.5 430,-32.5 430,-32.5 436,-32.5 442,-38.5 442,-44.5 442,-44.5 442,-56.5 442,-56.5 442,-62.5 436,-68.5 430,-68.5 430,-68.5 400,-68.5 400,-68.5 394,-68.5 388,-62.5 388,-56.5 388,-56.5 388,-44.5 388,-44.5 388,-38.5 394,-32.5 400,-32.5"/>
|
||||
<text text-anchor="middle" x="415" y="-46.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
|
||||
</g>
|
||||
<!-- system_membus_master->system_external_memory_port -->
|
||||
<g id="edge2" class="edge"><title>system_membus_master->system_external_memory_port</title>
|
||||
<path fill="none" stroke="black" d="M415,-163.37C415,-141.781 415,-104.412 415,-78.852"/>
|
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<polygon fill="black" stroke="black" points="418.5,-78.701 415,-68.7011 411.5,-78.7011 418.5,-78.701"/>
|
||||
</g>
|
||||
<!-- system_tol2bus_master -->
|
||||
<g id="node5" class="node"><title>system_tol2bus_master</title>
|
||||
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|
||||
<text text-anchor="middle" x="449" y="-439.8" font-family="Arial" font-size="14.00" fill="#000000">master</text>
|
||||
</g>
|
||||
<!-- system_l2_cpu_side -->
|
||||
<g id="node8" class="node"><title>system_l2_cpu_side</title>
|
||||
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|
||||
<text text-anchor="middle" x="403" y="-308.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
|
||||
</g>
|
||||
<!-- system_tol2bus_master->system_l2_cpu_side -->
|
||||
<g id="edge3" class="edge"><title>system_tol2bus_master->system_l2_cpu_side</title>
|
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<path fill="none" stroke="black" d="M442.892,-425.37C435.124,-403.588 421.63,-365.744 412.51,-340.17"/>
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<polygon fill="black" stroke="black" points="415.789,-338.945 409.134,-330.701 409.196,-341.296 415.789,-338.945"/>
|
||||
</g>
|
||||
<!-- system_tol2bus_slave -->
|
||||
<g id="node6" class="node"><title>system_tol2bus_slave</title>
|
||||
<path fill="#586070" stroke="#000000" d="M359,-425.5C359,-425.5 389,-425.5 389,-425.5 395,-425.5 401,-431.5 401,-437.5 401,-437.5 401,-449.5 401,-449.5 401,-455.5 395,-461.5 389,-461.5 389,-461.5 359,-461.5 359,-461.5 353,-461.5 347,-455.5 347,-449.5 347,-449.5 347,-437.5 347,-437.5 347,-431.5 353,-425.5 359,-425.5"/>
|
||||
<text text-anchor="middle" x="374" y="-439.8" font-family="Arial" font-size="14.00" fill="#000000">slave</text>
|
||||
</g>
|
||||
<!-- system_l2_mem_side -->
|
||||
<g id="node7" class="node"><title>system_l2_mem_side</title>
|
||||
<path fill="#94918b" stroke="#000000" d="M470,-294.5C470,-294.5 530,-294.5 530,-294.5 536,-294.5 542,-300.5 542,-306.5 542,-306.5 542,-318.5 542,-318.5 542,-324.5 536,-330.5 530,-330.5 530,-330.5 470,-330.5 470,-330.5 464,-330.5 458,-324.5 458,-318.5 458,-318.5 458,-306.5 458,-306.5 458,-300.5 464,-294.5 470,-294.5"/>
|
||||
<text text-anchor="middle" x="500" y="-308.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
|
||||
</g>
|
||||
<!-- system_l2_mem_side->system_membus_slave -->
|
||||
<g id="edge4" class="edge"><title>system_l2_mem_side->system_membus_slave</title>
|
||||
<path fill="none" stroke="black" d="M466.462,-294.374C430.995,-276.175 379.636,-249.529 376,-246 365.309,-235.623 356.845,-221.384 350.817,-209.019"/>
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<polygon fill="black" stroke="black" points="353.856,-207.248 346.509,-199.614 347.491,-210.163 353.856,-207.248"/>
|
||||
</g>
|
||||
<!-- system_cpu_icache_port -->
|
||||
<g id="node9" class="node"><title>system_cpu_icache_port</title>
|
||||
<path fill="#959ead" stroke="#000000" d="M158.5,-687.5C158.5,-687.5 225.5,-687.5 225.5,-687.5 231.5,-687.5 237.5,-693.5 237.5,-699.5 237.5,-699.5 237.5,-711.5 237.5,-711.5 237.5,-717.5 231.5,-723.5 225.5,-723.5 225.5,-723.5 158.5,-723.5 158.5,-723.5 152.5,-723.5 146.5,-717.5 146.5,-711.5 146.5,-711.5 146.5,-699.5 146.5,-699.5 146.5,-693.5 152.5,-687.5 158.5,-687.5"/>
|
||||
<text text-anchor="middle" x="192" y="-701.8" font-family="Arial" font-size="14.00" fill="#000000">icache_port</text>
|
||||
</g>
|
||||
<!-- system_cpu_icache_cpu_side -->
|
||||
<g id="node14" class="node"><title>system_cpu_icache_cpu_side</title>
|
||||
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|
||||
<text text-anchor="middle" x="277" y="-570.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
|
||||
</g>
|
||||
<!-- system_cpu_icache_port->system_cpu_icache_cpu_side -->
|
||||
<g id="edge5" class="edge"><title>system_cpu_icache_port->system_cpu_icache_cpu_side</title>
|
||||
<path fill="none" stroke="black" d="M203.287,-687.37C217.83,-665.299 243.24,-626.736 260.093,-601.158"/>
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<polygon fill="black" stroke="black" points="263.086,-602.977 265.666,-592.701 257.241,-599.126 263.086,-602.977"/>
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||||
</g>
|
||||
<!-- system_cpu_dcache_port -->
|
||||
<g id="node10" class="node"><title>system_cpu_dcache_port</title>
|
||||
<path fill="#959ead" stroke="#000000" d="M44,-687.5C44,-687.5 116,-687.5 116,-687.5 122,-687.5 128,-693.5 128,-699.5 128,-699.5 128,-711.5 128,-711.5 128,-717.5 122,-723.5 116,-723.5 116,-723.5 44,-723.5 44,-723.5 38,-723.5 32,-717.5 32,-711.5 32,-711.5 32,-699.5 32,-699.5 32,-693.5 38,-687.5 44,-687.5"/>
|
||||
<text text-anchor="middle" x="80" y="-701.8" font-family="Arial" font-size="14.00" fill="#000000">dcache_port</text>
|
||||
</g>
|
||||
<!-- system_cpu_dcache_cpu_side -->
|
||||
<g id="node16" class="node"><title>system_cpu_dcache_cpu_side</title>
|
||||
<path fill="#94918b" stroke="#000000" d="M51.5,-556.5C51.5,-556.5 102.5,-556.5 102.5,-556.5 108.5,-556.5 114.5,-562.5 114.5,-568.5 114.5,-568.5 114.5,-580.5 114.5,-580.5 114.5,-586.5 108.5,-592.5 102.5,-592.5 102.5,-592.5 51.5,-592.5 51.5,-592.5 45.5,-592.5 39.5,-586.5 39.5,-580.5 39.5,-580.5 39.5,-568.5 39.5,-568.5 39.5,-562.5 45.5,-556.5 51.5,-556.5"/>
|
||||
<text text-anchor="middle" x="77" y="-570.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
|
||||
</g>
|
||||
<!-- system_cpu_dcache_port->system_cpu_dcache_cpu_side -->
|
||||
<g id="edge6" class="edge"><title>system_cpu_dcache_port->system_cpu_dcache_cpu_side</title>
|
||||
<path fill="none" stroke="black" d="M79.6016,-687.37C79.0996,-665.781 78.2305,-628.412 77.6361,-602.852"/>
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<polygon fill="black" stroke="black" points="81.1317,-602.617 77.4,-592.701 74.1336,-602.78 81.1317,-602.617"/>
|
||||
</g>
|
||||
<!-- system_cpu_dtb_walker_port -->
|
||||
<g id="node11" class="node"><title>system_cpu_dtb_walker_port</title>
|
||||
<path fill="#7f7c77" stroke="#000000" d="M332,-687.5C332,-687.5 362,-687.5 362,-687.5 368,-687.5 374,-693.5 374,-699.5 374,-699.5 374,-711.5 374,-711.5 374,-717.5 368,-723.5 362,-723.5 362,-723.5 332,-723.5 332,-723.5 326,-723.5 320,-717.5 320,-711.5 320,-711.5 320,-699.5 320,-699.5 320,-693.5 326,-687.5 332,-687.5"/>
|
||||
<text text-anchor="middle" x="347" y="-701.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
|
||||
</g>
|
||||
<!-- system_cpu_dtb_walker_port->system_tol2bus_slave -->
|
||||
<g id="edge7" class="edge"><title>system_cpu_dtb_walker_port->system_tol2bus_slave</title>
|
||||
<path fill="none" stroke="black" d="M372.891,-687.286C394.271,-672.443 422.04,-651.485 428,-639 446.956,-599.293 439.197,-582.551 428,-540 427.873,-539.519 404.902,-498.972 388.965,-470.873"/>
|
||||
<polygon fill="black" stroke="black" points="391.851,-468.867 383.873,-461.896 385.763,-472.321 391.851,-468.867"/>
|
||||
</g>
|
||||
<!-- system_cpu_itb_walker_port -->
|
||||
<g id="node12" class="node"><title>system_cpu_itb_walker_port</title>
|
||||
<path fill="#7f7c77" stroke="#000000" d="M440,-687.5C440,-687.5 470,-687.5 470,-687.5 476,-687.5 482,-693.5 482,-699.5 482,-699.5 482,-711.5 482,-711.5 482,-717.5 476,-723.5 470,-723.5 470,-723.5 440,-723.5 440,-723.5 434,-723.5 428,-717.5 428,-711.5 428,-711.5 428,-699.5 428,-699.5 428,-693.5 434,-687.5 440,-687.5"/>
|
||||
<text text-anchor="middle" x="455" y="-701.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
|
||||
</g>
|
||||
<!-- system_cpu_itb_walker_port->system_tol2bus_slave -->
|
||||
<g id="edge8" class="edge"><title>system_cpu_itb_walker_port->system_tol2bus_slave</title>
|
||||
<path fill="none" stroke="black" d="M456.757,-687.277C459.189,-656.32 461.061,-589.855 439,-540 431.233,-522.448 421.246,-523.554 410,-508 401.505,-496.25 393.412,-482.319 387.059,-470.503"/>
|
||||
<polygon fill="black" stroke="black" points="390.112,-468.788 382.363,-461.563 383.915,-472.044 390.112,-468.788"/>
|
||||
</g>
|
||||
<!-- system_cpu_icache_mem_side -->
|
||||
<g id="node13" class="node"><title>system_cpu_icache_mem_side</title>
|
||||
<path fill="#94918b" stroke="#000000" d="M344,-556.5C344,-556.5 404,-556.5 404,-556.5 410,-556.5 416,-562.5 416,-568.5 416,-568.5 416,-580.5 416,-580.5 416,-586.5 410,-592.5 404,-592.5 404,-592.5 344,-592.5 344,-592.5 338,-592.5 332,-586.5 332,-580.5 332,-580.5 332,-568.5 332,-568.5 332,-562.5 338,-556.5 344,-556.5"/>
|
||||
<text text-anchor="middle" x="374" y="-570.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
|
||||
</g>
|
||||
<!-- system_cpu_icache_mem_side->system_tol2bus_slave -->
|
||||
<g id="edge9" class="edge"><title>system_cpu_icache_mem_side->system_tol2bus_slave</title>
|
||||
<path fill="none" stroke="black" d="M374,-556.37C374,-534.781 374,-497.412 374,-471.852"/>
|
||||
<polygon fill="black" stroke="black" points="377.5,-471.701 374,-461.701 370.5,-471.701 377.5,-471.701"/>
|
||||
</g>
|
||||
<!-- system_cpu_dcache_mem_side -->
|
||||
<g id="node15" class="node"><title>system_cpu_dcache_mem_side</title>
|
||||
<path fill="#94918b" stroke="#000000" d="M144,-556.5C144,-556.5 204,-556.5 204,-556.5 210,-556.5 216,-562.5 216,-568.5 216,-568.5 216,-580.5 216,-580.5 216,-586.5 210,-592.5 204,-592.5 204,-592.5 144,-592.5 144,-592.5 138,-592.5 132,-586.5 132,-580.5 132,-580.5 132,-568.5 132,-568.5 132,-562.5 138,-556.5 144,-556.5"/>
|
||||
<text text-anchor="middle" x="174" y="-570.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
|
||||
</g>
|
||||
<!-- system_cpu_dcache_mem_side->system_tol2bus_slave -->
|
||||
<g id="edge10" class="edge"><title>system_cpu_dcache_mem_side->system_tol2bus_slave</title>
|
||||
<path fill="none" stroke="black" d="M200.558,-556.37C236.122,-533.432 299.303,-492.68 338.799,-467.205"/>
|
||||
<polygon fill="black" stroke="black" points="340.825,-470.063 347.332,-461.701 337.031,-464.18 340.825,-470.063"/>
|
||||
</g>
|
||||
</g>
|
||||
</svg>
|
||||
|
Before Width: | Height: | Size: 28 KiB |
@@ -1,5 +1,4 @@
|
||||
# -*- coding: utf-8 -*-
|
||||
# Copyright (c) 2016, University of Kaiserslautern
|
||||
# Copyright (c) 2020, Technische Universität Kaiserslautern
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
@@ -29,42 +28,47 @@
|
||||
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Éder F. Zulian
|
||||
#
|
||||
# Authors:
|
||||
# Lukas Steiner
|
||||
|
||||
import xml.etree.ElementTree as ET
|
||||
cmake_minimum_required(VERSION 3.10)
|
||||
|
||||
set(GEM5_ARCH ARM) # ARM, X86, ALPHA
|
||||
set(GEM5_VARIANT opt) # opt, fast
|
||||
|
||||
class MCConfig(object):
|
||||
""" Memory Controller Configuration Class
|
||||
# Configuration:
|
||||
set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
|
||||
set(DCMAKE_SH="CMAKE_SH-NOTFOUND")
|
||||
|
||||
The format used in memory specification XML files differs from the
|
||||
format used in memory controller configuration XML files. Each class
|
||||
uses the proper format when searching for elements.
|
||||
"""
|
||||
def getValue(self, id):
|
||||
return self.xmlMCConfig.findall(id)[0].attrib['value']
|
||||
find_library(GEM5_LIBRARY gem5_${GEM5_VARIANT} PATH $ENV{GEM5}/build/${GEM5_ARCH}/)
|
||||
|
||||
def getIntValue(self, id):
|
||||
return int(self.getValue(id))
|
||||
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/../library/src/simulation/DRAMSysRecordable.cpp)
|
||||
add_definitions(-DRECORDING)
|
||||
endif()
|
||||
|
||||
def __init__(self, xmlfile):
|
||||
self.xmlMCConfig = ET.parse(xmlfile)
|
||||
add_executable(DRAMSys_gem5
|
||||
main.cpp
|
||||
$ENV{GEM5}/util/systemc/sc_logger.cc
|
||||
$ENV{GEM5}/util/systemc/sc_module.cc
|
||||
$ENV{GEM5}/util/systemc/stats.cc
|
||||
$ENV{GEM5}/util/tlm/src/sc_master_port.cc
|
||||
$ENV{GEM5}/util/tlm/src/sc_slave_port.cc
|
||||
$ENV{GEM5}/util/tlm/src/slave_transactor.cc
|
||||
$ENV{GEM5}/util/tlm/src/sc_ext.cc
|
||||
$ENV{GEM5}/util/tlm/src/sc_mm.cc
|
||||
$ENV{GEM5}/util/tlm/src/sim_control.cc
|
||||
)
|
||||
|
||||
target_include_directories(DRAMSys_gem5
|
||||
PRIVATE $ENV{GEM5}/build/ARM/
|
||||
PRIVATE $ENV{GEM5}/util/tlm/examples/slave_port/
|
||||
PRIVATE $ENV{GEM5}/util/tlm/examples/common/
|
||||
PRIVATE $ENV{GEM5}/util/tlm/src/
|
||||
PRIVATE $ENV{GEM5}/util/systemc/
|
||||
PRIVATE ../library/src/simulation/
|
||||
)
|
||||
|
||||
class MemSpec(object):
|
||||
""" Memory Specification Class
|
||||
|
||||
The format used in memory specification XML files differs from the
|
||||
format used in memory configuration XML files. Each class uses the
|
||||
proper format when searching for elements.
|
||||
"""
|
||||
def getValue(self, id):
|
||||
return self.xmlMemSpec.findall(".//parameter[@id='{0}']".
|
||||
format(id))[0].attrib['value']
|
||||
|
||||
def getIntValue(self, id):
|
||||
return int(self.getValue(id))
|
||||
|
||||
def __init__(self, xmlfile):
|
||||
self.xmlMemSpec = ET.parse(xmlfile)
|
||||
target_link_libraries(DRAMSys_gem5
|
||||
PRIVATE DRAMSysLibrary
|
||||
PRIVATE ${GEM5_LIBRARY}
|
||||
)
|
||||
44
DRAMSys/gem5/README.md
Normal file
44
DRAMSys/gem5/README.md
Normal file
@@ -0,0 +1,44 @@
|
||||
## DRAMSys with gem5
|
||||
|
||||
Install gem5 by following the instructions in the [gem5 documentation](https://www.gem5.org/documentation/general_docs/building). In order to allow a coupling without running into problems we recommend to use **commit a470ef5**. Optionally, use the scripts from [gem5.TnT](https://github.com/tukl-msd/gem5.TnT) to install gem5, build it, get some benchmark programs and learn more about gem5.
|
||||
|
||||
In order to understand the SystemC coupling with gem5 it is recommended to read the documentation in the gem5 repository *util/tlm/README* and [1].
|
||||
|
||||
The main steps for building gem5 and libgem5 follow:
|
||||
|
||||
```bash
|
||||
$ cd gem5
|
||||
$ scons build/ARM/gem5.opt
|
||||
$ scons --with-cxx-config --without-python --without-tcmalloc build/ARM/libgem5_opt.so
|
||||
```
|
||||
|
||||
In order to use gem5 with DRAMSys export the `GEM5` environment variable (gem5 root directory) and add the path of the library to `LD_LIBRARY_PATH`, then rerun CMake and rebuild the DRAMSys project.
|
||||
|
||||
### DRAMSys with gem5 ARM SE mode
|
||||
|
||||
All essential files for a functional example are provided. Execute a hello world application:
|
||||
|
||||
```bash
|
||||
$ cd DRAMSys/build/gem5
|
||||
$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/hello-ARM/config.ini 1
|
||||
```
|
||||
|
||||
A **Hello world!** message should be printed to the standard output.
|
||||
|
||||
### DRAMSys with gem5 X86 SE mode
|
||||
|
||||
Make sure you have built *gem5/build/X86/libgem5_opt.so*. Add the path of the library to `LD_LIBRARY_PATH` and remove the path of the ARM library.
|
||||
|
||||
Change the architecture in the [CMake file](DRAMSys/gem5/CMakeLists.txt) to *X86*, rerun CMake and rebuild the project. Test with a hello world application for X86:
|
||||
|
||||
```bash
|
||||
$ cd DRAMSys/build/gem5
|
||||
$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/hello-X86/config.ini 1
|
||||
```
|
||||
|
||||
A **Hello world!** message should be printed to the standard output.
|
||||
|
||||
## References
|
||||
|
||||
[1] System Simulation with gem5 and SystemC: The Keystone for Full Interoperability
|
||||
C. Menard, M. Jung, J. Castrillon, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2017, Samos Island, Greece.
|
||||
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@@ -1,796 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu0 cpu1 cpu_clk_domain cpu_voltage_domain dvfs_handler membus1 membus2 physmem tlm1 tlm2 voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kernel_extras=
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:536870911:0:0:0:0
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus1.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
type=TraceCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=0
|
||||
dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu0.dstage2_mmu
|
||||
dtb=system.cpu0.dtb
|
||||
enableEarlyExit=false
|
||||
eventq_index=0
|
||||
freqMultiplier=1.0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
|
||||
interrupts=system.cpu0.interrupts
|
||||
isa=system.cpu0.isa
|
||||
istage2_mmu=system.cpu0.istage2_mmu
|
||||
itb=system.cpu0.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_gating_on_idle=false
|
||||
power_model=
|
||||
profile=0
|
||||
progressMsgInterval=0
|
||||
progress_interval=0
|
||||
pwr_gating_latency=300
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
|
||||
sizeROB=40
|
||||
sizeStoreBuffer=16
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
wait_for_remote_gdb=false
|
||||
workload=
|
||||
dcache_port=system.cpu0.dcache.cpu_side
|
||||
icache_port=system.cpu0.icache.cpu_side
|
||||
|
||||
[system.cpu0.dcache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu0.dcache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu0.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.membus1.slave[2]
|
||||
|
||||
[system.cpu0.dcache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.dcache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu0.dcache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu0.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu0.dtb
|
||||
|
||||
[system.cpu0.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu0.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu0.dtb.walker
|
||||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu0.icache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu0.icache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu0.icache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.membus1.slave[1]
|
||||
|
||||
[system.cpu0.icache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.icache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu0.icache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu0.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
impdef_nop=false
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
vecRegRenameMode=Full
|
||||
|
||||
[system.cpu0.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu0.itb
|
||||
|
||||
[system.cpu0.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu0.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu0.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu0.itb.walker
|
||||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1]
|
||||
type=TraceCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=1
|
||||
dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu1.dstage2_mmu
|
||||
dtb=system.cpu1.dtb
|
||||
enableEarlyExit=false
|
||||
eventq_index=0
|
||||
freqMultiplier=1.0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
|
||||
interrupts=system.cpu1.interrupts
|
||||
isa=system.cpu1.isa
|
||||
istage2_mmu=system.cpu1.istage2_mmu
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_gating_on_idle=false
|
||||
power_model=
|
||||
profile=0
|
||||
progressMsgInterval=0
|
||||
progress_interval=0
|
||||
pwr_gating_latency=300
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
|
||||
sizeROB=40
|
||||
sizeStoreBuffer=16
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
wait_for_remote_gdb=false
|
||||
workload=
|
||||
dcache_port=system.cpu1.dcache.cpu_side
|
||||
icache_port=system.cpu1.icache.cpu_side
|
||||
|
||||
[system.cpu1.dcache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu1.dcache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu1.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.membus2.slave[1]
|
||||
|
||||
[system.cpu1.dcache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1.dcache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu1.dcache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu1.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.dtb
|
||||
|
||||
[system.cpu1.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu1.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu1.dtb.walker
|
||||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu1.icache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu1.icache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu1.icache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.membus2.slave[0]
|
||||
|
||||
[system.cpu1.icache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1.icache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu1.icache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
impdef_nop=false
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
vecRegRenameMode=Full
|
||||
|
||||
[system.cpu1.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.itb
|
||||
|
||||
[system.cpu1.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu1.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu1.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu1.itb.walker
|
||||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus1]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus1.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm1.port
|
||||
slave=system.system_port system.cpu0.icache.mem_side system.cpu0.dcache.mem_side
|
||||
|
||||
[system.membus1.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.membus2]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus2.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm2.port
|
||||
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
|
||||
|
||||
[system.membus2.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tlm1]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:268435455:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor1
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus1.master[0]
|
||||
|
||||
[system.tlm2]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:268435455:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor2
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus2.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@@ -1,448 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler membus physmem tlm voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kernel_extras=
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:536870911:0:0:0:0
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TraceCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=0
|
||||
dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.random.data.gz
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
enableEarlyExit=false
|
||||
eventq_index=0
|
||||
freqMultiplier=1.0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_gating_on_idle=false
|
||||
power_model=
|
||||
profile=0
|
||||
progressMsgInterval=0
|
||||
progress_interval=0
|
||||
pwr_gating_latency=300
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
|
||||
sizeROB=40
|
||||
sizeStoreBuffer=16
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
wait_for_remote_gdb=false
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.cpu.dcache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.icache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
impdef_nop=false
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
vecRegRenameMode=Full
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm.port
|
||||
slave=system.system_port system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tlm]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:536870911:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
Binary file not shown.
@@ -1,534 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kernel_extras=
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:1073741823:0:0:0:0
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TraceCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=0
|
||||
dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
enableEarlyExit=false
|
||||
eventq_index=0
|
||||
freqMultiplier=1.0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_gating_on_idle=false
|
||||
power_model=
|
||||
profile=0
|
||||
progressMsgInterval=0
|
||||
progress_interval=0
|
||||
pwr_gating_latency=300
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
|
||||
sizeROB=40
|
||||
sizeStoreBuffer=16
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
wait_for_remote_gdb=false
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.tol2bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.tol2bus.slave[0]
|
||||
|
||||
[system.cpu.icache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
impdef_nop=false
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
vecRegRenameMode=Full
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.l2cache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.tol2bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2cache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.l2cache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
tag_latency=20
|
||||
warmup_percentage=0
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm.port
|
||||
slave=system.system_port system.l2cache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tlm]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:4294967295:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.tol2bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=1
|
||||
snoop_filter=system.tol2bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.tol2bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
@@ -1,448 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler membus physmem tlm voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kernel_extras=
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:536870911:0:0:0:0
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TraceCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=0
|
||||
dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.random.data.gz
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
enableEarlyExit=false
|
||||
eventq_index=0
|
||||
freqMultiplier=1.0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_gating_on_idle=false
|
||||
power_model=
|
||||
profile=0
|
||||
progressMsgInterval=0
|
||||
progress_interval=0
|
||||
pwr_gating_latency=300
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
|
||||
sizeROB=40
|
||||
sizeStoreBuffer=16
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
wait_for_remote_gdb=false
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.cpu.dcache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.icache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
impdef_nop=false
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
vecRegRenameMode=Full
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm.port
|
||||
slave=system.system_port system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tlm]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:536870911:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
@@ -1,534 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kernel_extras=
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:1073741823:0:0:0:0
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TraceCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=0
|
||||
dataTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/HPCG-47MB-simpoints-1B/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.data.itrc.gz
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
enableEarlyExit=false
|
||||
eventq_index=0
|
||||
freqMultiplier=1.0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
instTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/HPCG-47MB-simpoints-1B/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.inst.ptrc.gz
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_gating_on_idle=false
|
||||
power_model=
|
||||
profile=0
|
||||
progressMsgInterval=0
|
||||
progress_interval=0
|
||||
pwr_gating_latency=300
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
|
||||
sizeROB=40
|
||||
sizeStoreBuffer=16
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
wait_for_remote_gdb=false
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.tol2bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.tol2bus.slave[0]
|
||||
|
||||
[system.cpu.icache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
impdef_nop=false
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
vecRegRenameMode=Full
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.l2cache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.tol2bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2cache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.l2cache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
tag_latency=20
|
||||
warmup_percentage=0
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm.port
|
||||
slave=system.system_port system.l2cache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tlm]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:4294967295:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.tol2bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=1
|
||||
snoop_filter=system.tol2bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.tol2bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
@@ -1,534 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kernel_extras=
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:1073741823:0:0:0:0
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TraceCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=0
|
||||
dataTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/Pathfinder-medsmall1-simpoints-1B-1sim/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.data.itrc.gz
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
enableEarlyExit=false
|
||||
eventq_index=0
|
||||
freqMultiplier=1.0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
instTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/Pathfinder-medsmall1-simpoints-1B-1sim/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.inst.ptrc.gz
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_gating_on_idle=false
|
||||
power_model=
|
||||
profile=0
|
||||
progressMsgInterval=0
|
||||
progress_interval=0
|
||||
pwr_gating_latency=300
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
|
||||
sizeROB=40
|
||||
sizeStoreBuffer=16
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
wait_for_remote_gdb=false
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.tol2bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.tol2bus.slave[0]
|
||||
|
||||
[system.cpu.icache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
impdef_nop=false
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
vecRegRenameMode=Full
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.l2cache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.tol2bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2cache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.l2cache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
tag_latency=20
|
||||
warmup_percentage=0
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm.port
|
||||
slave=system.system_port system.l2cache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tlm]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:4294967295:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.tol2bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=1
|
||||
snoop_filter=system.tol2bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.tol2bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
@@ -1,534 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kernel_extras=
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:1073741823:0:0:0:0
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TraceCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=0
|
||||
dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
enableEarlyExit=false
|
||||
eventq_index=0
|
||||
freqMultiplier=1.0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_gating_on_idle=false
|
||||
power_model=
|
||||
profile=0
|
||||
progressMsgInterval=0
|
||||
progress_interval=0
|
||||
pwr_gating_latency=300
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
|
||||
sizeROB=40
|
||||
sizeStoreBuffer=16
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
wait_for_remote_gdb=false
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.tol2bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.tol2bus.slave[0]
|
||||
|
||||
[system.cpu.icache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
impdef_nop=false
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
vecRegRenameMode=Full
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.l2cache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.tol2bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2cache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.l2cache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
tag_latency=20
|
||||
warmup_percentage=0
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm.port
|
||||
slave=system.system_port system.l2cache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tlm]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:4294967295:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.tol2bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=1
|
||||
snoop_filter=system.tol2bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.tol2bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
@@ -1,534 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kernel_extras=
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:1073741823:0:0:0:0
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TraceCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=0
|
||||
dataTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-dgemm-simpoints-1B/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.data.itrc.gz
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
enableEarlyExit=false
|
||||
eventq_index=0
|
||||
freqMultiplier=1.0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
instTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-dgemm-simpoints-1B/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.inst.ptrc.gz
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_gating_on_idle=false
|
||||
power_model=
|
||||
profile=0
|
||||
progressMsgInterval=0
|
||||
progress_interval=0
|
||||
pwr_gating_latency=300
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
|
||||
sizeROB=40
|
||||
sizeStoreBuffer=16
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
wait_for_remote_gdb=false
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.tol2bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.tol2bus.slave[0]
|
||||
|
||||
[system.cpu.icache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
impdef_nop=false
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
vecRegRenameMode=Full
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.l2cache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.tol2bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2cache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.l2cache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
tag_latency=20
|
||||
warmup_percentage=0
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm.port
|
||||
slave=system.system_port system.l2cache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tlm]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:4294967295:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.tol2bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=1
|
||||
snoop_filter=system.tol2bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.tol2bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
@@ -1,534 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kernel_extras=
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:1073741823:0:0:0:0
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TraceCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=0
|
||||
dataTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-fft/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.data.itrc.gz
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
enableEarlyExit=false
|
||||
eventq_index=0
|
||||
freqMultiplier=1.0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
instTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-fft/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.inst.ptrc.gz
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_gating_on_idle=false
|
||||
power_model=
|
||||
profile=0
|
||||
progressMsgInterval=0
|
||||
progress_interval=0
|
||||
pwr_gating_latency=300
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
|
||||
sizeROB=40
|
||||
sizeStoreBuffer=16
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
wait_for_remote_gdb=false
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.tol2bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.tol2bus.slave[0]
|
||||
|
||||
[system.cpu.icache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
impdef_nop=false
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
vecRegRenameMode=Full
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.l2cache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.tol2bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2cache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.l2cache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
tag_latency=20
|
||||
warmup_percentage=0
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm.port
|
||||
slave=system.system_port system.l2cache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tlm]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:4294967295:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.tol2bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=1
|
||||
snoop_filter=system.tol2bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.tol2bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
@@ -1,534 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kernel_extras=
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:1073741823:0:0:0:0
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TraceCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=0
|
||||
dataTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-gups/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.data.itrc.gz
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
enableEarlyExit=false
|
||||
eventq_index=0
|
||||
freqMultiplier=1.0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
instTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-gups/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.inst.ptrc.gz
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_gating_on_idle=false
|
||||
power_model=
|
||||
profile=0
|
||||
progressMsgInterval=0
|
||||
progress_interval=0
|
||||
pwr_gating_latency=300
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
|
||||
sizeROB=40
|
||||
sizeStoreBuffer=16
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
wait_for_remote_gdb=false
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.tol2bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.tol2bus.slave[0]
|
||||
|
||||
[system.cpu.icache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
impdef_nop=false
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
vecRegRenameMode=Full
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.l2cache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.tol2bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2cache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.l2cache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
tag_latency=20
|
||||
warmup_percentage=0
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm.port
|
||||
slave=system.system_port system.l2cache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tlm]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:4294967295:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.tol2bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=1
|
||||
snoop_filter=system.tol2bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.tol2bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
@@ -1,534 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kernel_extras=
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:1073741823:0:0:0:0
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TraceCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=0
|
||||
dataTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-linpack-simpoints-1B/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.data.itrc.gz
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
enableEarlyExit=false
|
||||
eventq_index=0
|
||||
freqMultiplier=1.0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
instTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-linpack-simpoints-1B/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.inst.ptrc.gz
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_gating_on_idle=false
|
||||
power_model=
|
||||
profile=0
|
||||
progressMsgInterval=0
|
||||
progress_interval=0
|
||||
pwr_gating_latency=300
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
|
||||
sizeROB=40
|
||||
sizeStoreBuffer=16
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
wait_for_remote_gdb=false
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.tol2bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.tol2bus.slave[0]
|
||||
|
||||
[system.cpu.icache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
impdef_nop=false
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
vecRegRenameMode=Full
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.l2cache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.tol2bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2cache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.l2cache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.l2cache.replacement_policy
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
tag_latency=20
|
||||
warmup_percentage=0
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm.port
|
||||
slave=system.system_port system.l2cache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tlm]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:4294967295:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.tol2bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=1
|
||||
snoop_filter=system.tol2bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.tol2bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
@@ -1,126 +0,0 @@
|
||||
# Copyright (c) 2016, University of Kaiserslautern
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
#
|
||||
# 3. Neither the name of the copyright holder nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Matthias Jung
|
||||
|
||||
import m5
|
||||
import optparse
|
||||
|
||||
from m5.objects import *
|
||||
from m5.util import addToPath, fatal
|
||||
|
||||
addToPath('../../../configs/common/')
|
||||
|
||||
from Caches import *
|
||||
|
||||
# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
|
||||
# and an external TLM port for SystemC co-simulation.
|
||||
#
|
||||
# We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
|
||||
#
|
||||
# Base System Architecture:
|
||||
#
|
||||
# +-----------+ ^
|
||||
# +-------------+ | eTraceCPU | |
|
||||
# | System Port | +-----+-----+ |
|
||||
# +------+------+ | $D1 | $I1 | |
|
||||
# | +--+--+--+--+ |
|
||||
# | | | | gem5 World
|
||||
# | | | | (see this file)
|
||||
# | | | |
|
||||
# +------v------------v-----v--+ |
|
||||
# | Membus | v
|
||||
# +----------------+-----------+ External Port (see sc_port.*)
|
||||
# | ^
|
||||
# +---v---+ | TLM World
|
||||
# | TLM | | (see sc_target.*)
|
||||
# +-------+ v
|
||||
#
|
||||
#
|
||||
# Create a system with a Crossbar and an Elastic Trace Player as CPU:
|
||||
|
||||
# Setup System:
|
||||
system = System(cpu=TraceCPU(cpu_id=0),
|
||||
mem_mode='timing',
|
||||
mem_ranges = [AddrRange('512MB')],
|
||||
cache_line_size = 64)
|
||||
|
||||
# Create a top-level voltage domain:
|
||||
system.voltage_domain = VoltageDomain()
|
||||
|
||||
# Create a source clock for the system. This is used as the clock period for
|
||||
# xbar and memory:
|
||||
system.clk_domain = SrcClockDomain(clock = '1GHz',
|
||||
voltage_domain = system.voltage_domain)
|
||||
|
||||
system.cpu.createThreads()
|
||||
|
||||
# Create a CPU voltage domain:
|
||||
system.cpu_voltage_domain = VoltageDomain()
|
||||
|
||||
# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
|
||||
# is actually used only by the caches connected to the CPU:
|
||||
system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
|
||||
voltage_domain = system.cpu_voltage_domain)
|
||||
|
||||
# Setup CPU and its L1 caches:
|
||||
system.cpu.createInterruptController()
|
||||
system.cpu.icache = L1_ICache(size="32kB")
|
||||
system.cpu.dcache = L1_DCache(size="32kB")
|
||||
system.cpu.icache.cpu_side = system.cpu.icache_port
|
||||
system.cpu.dcache.cpu_side = system.cpu.dcache_port
|
||||
|
||||
# XXX: Assign input trace files to the eTraceCPU (you have to set this path
|
||||
# properly before running gem5):
|
||||
system.cpu.instTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz"
|
||||
system.cpu.dataTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz"
|
||||
|
||||
# Setting up L1 BUS:
|
||||
system.membus = IOXBar(width = 16)
|
||||
system.physmem = SimpleMemory() # This must be instantiated, even if not needed
|
||||
|
||||
# Create a external TLM port:
|
||||
system.tlm = ExternalSlave()
|
||||
system.tlm.addr_ranges = [AddrRange('512MB')]
|
||||
system.tlm.port_type = "tlm_slave"
|
||||
system.tlm.port_data = "transactor"
|
||||
|
||||
# Connect everything:
|
||||
system.membus = SystemXBar()
|
||||
system.system_port = system.membus.slave
|
||||
system.cpu.icache.mem_side = system.membus.slave
|
||||
system.cpu.dcache.mem_side = system.membus.slave
|
||||
system.membus.master = system.tlm.port
|
||||
|
||||
# Start the simulation:
|
||||
root = Root(full_system = False, system = system)
|
||||
root.system.mem_mode = 'timing'
|
||||
m5.instantiate()
|
||||
m5.simulate() #Simulation time specified later on commandline
|
||||
@@ -1,145 +0,0 @@
|
||||
# Copyright (c) 2016, University of Kaiserslautern
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
#
|
||||
# 3. Neither the name of the copyright holder nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Matthias Jung
|
||||
|
||||
import m5
|
||||
import optparse
|
||||
|
||||
from m5.objects import *
|
||||
from m5.util import addToPath, fatal
|
||||
|
||||
addToPath('../../../configs/common/')
|
||||
|
||||
from Caches import *
|
||||
|
||||
# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
|
||||
# and an external TLM port for SystemC co-simulation.
|
||||
#
|
||||
# We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
|
||||
#
|
||||
# Base System Architecture:
|
||||
#
|
||||
# +--------+ +-----------+ +-----------+ ^
|
||||
# | System | | eTraceCPU | | eTraceCPU | |
|
||||
# | Port | +-----+-----+ +-----+-----+ |
|
||||
# +----+---+ | $D1 | $I1 | | $D1 | $I1 | |
|
||||
# | +--+--+--+--+ +--+--+--+--+ |
|
||||
# | | | | | | gem5 World
|
||||
# | | | | | | (see this file)
|
||||
# | | | | | |
|
||||
# +----v--------v-----v--------v-----v-+ |
|
||||
# | Membus | v
|
||||
# +----------------+-------------------+ External Port (see sc_port.*)
|
||||
# | ^
|
||||
# +---v---+ | TLM World
|
||||
# | TLM | | (see sc_target.*)
|
||||
# +-------+ v
|
||||
#
|
||||
#
|
||||
# Create a system with a Crossbar and Elastic Trace Player CPUs:
|
||||
|
||||
# Setup System:
|
||||
system = System(cpu=[TraceCPU(cpu_id=i) for i in xrange(2)],
|
||||
mem_mode='timing',
|
||||
mem_ranges = [AddrRange('512MB')],
|
||||
cache_line_size = 64)
|
||||
|
||||
# Create a top-level voltage domain:
|
||||
system.voltage_domain = VoltageDomain()
|
||||
|
||||
# Create a source clock for the system. This is used as the clock period for
|
||||
# xbar and memory:
|
||||
system.clk_domain = SrcClockDomain(clock = '1GHz',
|
||||
voltage_domain = system.voltage_domain)
|
||||
|
||||
# Create a CPU voltage domain:
|
||||
system.cpu_voltage_domain = VoltageDomain()
|
||||
|
||||
# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
|
||||
# is actually used only by the caches connected to the CPU:
|
||||
system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
|
||||
voltage_domain = system.cpu_voltage_domain)
|
||||
|
||||
# Setup CPUs and their L1 caches:
|
||||
system.cpu[0].createInterruptController()
|
||||
system.cpu[0].icache = L1_ICache(size="32kB")
|
||||
system.cpu[0].dcache = L1_DCache(size="32kB")
|
||||
system.cpu[0].icache.cpu_side = system.cpu[0].icache_port
|
||||
system.cpu[0].dcache.cpu_side = system.cpu[0].dcache_port
|
||||
system.cpu[0].createThreads()
|
||||
|
||||
system.cpu[1].createInterruptController()
|
||||
system.cpu[1].icache = L1_ICache(size="32kB")
|
||||
system.cpu[1].dcache = L1_DCache(size="32kB")
|
||||
system.cpu[1].icache.cpu_side = system.cpu[1].icache_port
|
||||
system.cpu[1].dcache.cpu_side = system.cpu[1].dcache_port
|
||||
system.cpu[1].createThreads()
|
||||
|
||||
# XXX: Assign input trace files to the eTraceCPU (you have to set this path
|
||||
# properly before running gem5):
|
||||
system.cpu[0].instTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz"
|
||||
system.cpu[0].dataTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz"
|
||||
system.cpu[1].instTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz"
|
||||
system.cpu[1].dataTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz"
|
||||
|
||||
# Setting up memory BUS:
|
||||
system.physmem = SimpleMemory() # This must be instantiated, even if not needed
|
||||
|
||||
# Create a external TLM port:
|
||||
system.tlm1 = ExternalSlave()
|
||||
system.tlm1.addr_ranges = [AddrRange('256MB')]
|
||||
system.tlm1.port_type = "tlm_slave"
|
||||
system.tlm1.port_data = "transactor1"
|
||||
|
||||
system.tlm2 = ExternalSlave()
|
||||
system.tlm2.addr_ranges = [AddrRange('256MB')]
|
||||
system.tlm2.port_type = "tlm_slave"
|
||||
system.tlm2.port_data = "transactor2"
|
||||
|
||||
# Build Helpting Busses:
|
||||
system.membus1 = SystemXBar()
|
||||
system.membus2 = SystemXBar()
|
||||
|
||||
# Connect everything:
|
||||
system.system_port = system.membus1.slave
|
||||
system.cpu[0].icache.mem_side = system.membus1.slave
|
||||
system.cpu[0].dcache.mem_side = system.membus1.slave
|
||||
system.cpu[1].icache.mem_side = system.membus2.slave
|
||||
system.cpu[1].dcache.mem_side = system.membus2.slave
|
||||
system.membus1.master = system.tlm1.port
|
||||
system.membus2.master = system.tlm2.port
|
||||
|
||||
|
||||
# Start the simulation:
|
||||
root = Root(full_system = False, system = system)
|
||||
root.system.mem_mode = 'timing'
|
||||
m5.instantiate()
|
||||
m5.simulate() #Simulation time specified later on commandline
|
||||
@@ -1,135 +0,0 @@
|
||||
# Copyright (c) 2016, University of Kaiserslautern
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
#
|
||||
# 3. Neither the name of the copyright holder nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Matthias Jung
|
||||
|
||||
import m5
|
||||
import optparse
|
||||
|
||||
from m5.objects import *
|
||||
from m5.util import addToPath, fatal
|
||||
|
||||
addToPath('../../../configs/common/')
|
||||
|
||||
from Caches import *
|
||||
|
||||
# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
|
||||
# and an external TLM port for SystemC co-simulation.
|
||||
#
|
||||
# We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
|
||||
#
|
||||
# Base System Architecture:
|
||||
#
|
||||
# +-----------+ ^
|
||||
# +-------------+ | eTraceCPU | |
|
||||
# | System Port | +-----+-----+ |
|
||||
# +------+------+ | $D1 | $I1 | |
|
||||
# | +--+--+--+--+ |
|
||||
# | | | | gem5 World (see this file)
|
||||
# | +--v-----v--+ |
|
||||
# | | toL2Bus | |
|
||||
# | +-----+-----+ |
|
||||
# | | |
|
||||
# | +-----v-----+ |
|
||||
# | | L2 | |
|
||||
# | +-----+-----+ |
|
||||
# | | |
|
||||
# +------v---------------v-----+ |
|
||||
# | Membus | v
|
||||
# +----------------+-----------+ External Port (see sc_port.*)
|
||||
# | ^
|
||||
# +---v---+ | TLM World
|
||||
# | TLM | | (see sc_target.*)
|
||||
# +-------+ v
|
||||
#
|
||||
#
|
||||
# Create a system with a Crossbar and an Elastic Trace Player as CPU:
|
||||
|
||||
# Setup System:
|
||||
system = System(cpu=TraceCPU(cpu_id=0),
|
||||
mem_mode='timing',
|
||||
mem_ranges = [AddrRange('1024MB')],
|
||||
cache_line_size = 64)
|
||||
|
||||
# Create a top-level voltage domain:
|
||||
system.voltage_domain = VoltageDomain()
|
||||
|
||||
# Create a source clock for the system. This is used as the clock period for
|
||||
# xbar and memory:
|
||||
system.clk_domain = SrcClockDomain(clock = '1GHz',
|
||||
voltage_domain = system.voltage_domain)
|
||||
|
||||
system.cpu.createThreads()
|
||||
|
||||
# Create a CPU voltage domain:
|
||||
system.cpu_voltage_domain = VoltageDomain()
|
||||
|
||||
# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
|
||||
# is actually used only by the caches connected to the CPU:
|
||||
system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
|
||||
voltage_domain = system.cpu_voltage_domain)
|
||||
|
||||
# Setup CPU and its L1 caches:
|
||||
system.cpu.createInterruptController()
|
||||
system.cpu.icache = L1_ICache(size="32kB")
|
||||
system.cpu.dcache = L1_DCache(size="32kB")
|
||||
system.cpu.icache.cpu_side = system.cpu.icache_port
|
||||
system.cpu.dcache.cpu_side = system.cpu.dcache_port
|
||||
|
||||
# XXX: Assign input trace files to the eTraceCPU (you have to set this path
|
||||
# properly before running gem5):
|
||||
system.cpu.instTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz"
|
||||
system.cpu.dataTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz"
|
||||
|
||||
# Setting up L1 BUS:
|
||||
system.tol2bus = L2XBar()
|
||||
system.l2cache = L2Cache(size="1MB")
|
||||
system.physmem = SimpleMemory() # This must be instantiated, even if not needed
|
||||
|
||||
# Create a external TLM port:
|
||||
system.tlm = ExternalSlave()
|
||||
system.tlm.addr_ranges = [AddrRange('4096MB')]
|
||||
system.tlm.port_type = "tlm_slave"
|
||||
system.tlm.port_data = "transactor"
|
||||
|
||||
# Connect everything:
|
||||
system.membus = SystemXBar()
|
||||
system.system_port = system.membus.slave
|
||||
system.cpu.icache.mem_side = system.tol2bus.slave
|
||||
system.cpu.dcache.mem_side = system.tol2bus.slave
|
||||
system.tol2bus.master = system.l2cache.cpu_side
|
||||
system.l2cache.mem_side = system.membus.slave
|
||||
system.membus.master = system.tlm.port
|
||||
|
||||
# Start the simulation:
|
||||
root = Root(full_system = False, system = system)
|
||||
root.system.mem_mode = 'timing'
|
||||
m5.instantiate()
|
||||
m5.simulate()
|
||||
@@ -1,13 +0,0 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 11 2018 11:41:41
|
||||
gem5 started Nov 8 2018 17:18:25
|
||||
gem5 executing on botanix, pid 6721
|
||||
command line: build/ARM/gem5.opt -d se_output_2018.11.08-17.18.24/almabench configs/example/arm/starter_se.py --cpu=hpi --num-cores=1 --mem-channels=1 --tlm-memory=transactor /home/eder/gem5_tnt/benchmarks/test-suite/SingleSource/Benchmarks/CoyoteBench/almabench
|
||||
|
||||
info: Standard input is not a terminal, disabling listeners.
|
||||
info: 1. command and arguments: ['/home/eder/gem5_tnt/benchmarks/test-suite/SingleSource/Benchmarks/CoyoteBench/almabench']
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
fatal: Can't find port handler type 'tlm_slave'
|
||||
Memory Usage: 285396 KBytes
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@@ -1,301 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN"
|
||||
"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
|
||||
<!-- Generated by graphviz version 2.38.0 (20140413.2041)
|
||||
-->
|
||||
<!-- Title: G Pages: 1 -->
|
||||
<svg width="984pt" height="1016pt"
|
||||
viewBox="0.00 0.00 984.00 1016.00" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
|
||||
<g id="graph0" class="graph" transform="scale(1 1) rotate(0) translate(4 1012)">
|
||||
<title>G</title>
|
||||
<polygon fill="white" stroke="none" points="-4,4 -4,-1012 980,-1012 980,4 -4,4"/>
|
||||
<g id="clust1" class="cluster"><title>cluster_root</title>
|
||||
<g id="a_clust1"><a xlink:title="eventq_index=0 full_system=false sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000">
|
||||
<path fill="#bab6ae" stroke="#000000" d="M20,-8C20,-8 956,-8 956,-8 962,-8 968,-14 968,-20 968,-20 968,-988 968,-988 968,-994 962,-1000 956,-1000 956,-1000 20,-1000 20,-1000 14,-1000 8,-994 8,-988 8,-988 8,-20 8,-20 8,-14 14,-8 20,-8"/>
|
||||
<text text-anchor="middle" x="488" y="-984.8" font-family="Arial" font-size="14.00" fill="#000000">root </text>
|
||||
<text text-anchor="middle" x="488" y="-969.8" font-family="Arial" font-size="14.00" fill="#000000">: Root</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust2" class="cluster"><title>cluster_system</title>
|
||||
<g id="a_clust2"><a xlink:title="boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 kernel= kernel_addr_check=false kernel_extras= load_addr_mask=18446744073709551615 load_offset=0 mem_mode=timing mem_ranges=0:2147483647:0:0:0:0 memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= readfile= symbolfile= thermal_components= thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1">
|
||||
<path fill="#e4e7eb" stroke="#000000" d="M28,-16C28,-16 948,-16 948,-16 954,-16 960,-22 960,-28 960,-28 960,-942 960,-942 960,-948 954,-954 948,-954 948,-954 28,-954 28,-954 22,-954 16,-948 16,-942 16,-942 16,-28 16,-28 16,-22 22,-16 28,-16"/>
|
||||
<text text-anchor="middle" x="488" y="-938.8" font-family="Arial" font-size="14.00" fill="#000000">system </text>
|
||||
<text text-anchor="middle" x="488" y="-923.8" font-family="Arial" font-size="14.00" fill="#000000">: SimpleSeSystem</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust3" class="cluster"><title>cluster_system_membus</title>
|
||||
<g id="a_clust3"><a xlink:title="clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 point_of_coherency=true point_of_unification=true power_model= response_latency=2 snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false width=16">
|
||||
<path fill="#6f798c" stroke="#000000" d="M247,-155C247,-155 371,-155 371,-155 377,-155 383,-161 383,-167 383,-167 383,-234 383,-234 383,-240 377,-246 371,-246 371,-246 247,-246 247,-246 241,-246 235,-240 235,-234 235,-234 235,-167 235,-167 235,-161 241,-155 247,-155"/>
|
||||
<text text-anchor="middle" x="309" y="-230.8" font-family="Arial" font-size="14.00" fill="#000000">membus </text>
|
||||
<text text-anchor="middle" x="309" y="-215.8" font-family="Arial" font-size="14.00" fill="#000000">: SystemXBar</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust8" class="cluster"><title>cluster_system_cpu_cluster</title>
|
||||
<g id="a_clust8"><a xlink:title="eventq_index=0 thermal_domain=Null">
|
||||
<path fill="#bab6ae" stroke="#000000" d="M140,-278C140,-278 940,-278 940,-278 946,-278 952,-284 952,-290 952,-290 952,-896 952,-896 952,-902 946,-908 940,-908 940,-908 140,-908 140,-908 134,-908 128,-902 128,-896 128,-896 128,-290 128,-290 128,-284 134,-278 140,-278"/>
|
||||
<text text-anchor="middle" x="540" y="-892.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_cluster </text>
|
||||
<text text-anchor="middle" x="540" y="-877.8" font-family="Arial" font-size="14.00" fill="#000000">: CpuCluster</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust9" class="cluster"><title>cluster_system_cpu_cluster_toL2Bus</title>
|
||||
<g id="a_clust9"><a xlink:title="clk_domain=system.cpu_cluster.clk_domain default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 point_of_coherency=false point_of_unification=true power_model= response_latency=1 snoop_filter=system.cpu_cluster.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false width=64">
|
||||
<path fill="#6f798c" stroke="#000000" d="M463,-417C463,-417 587,-417 587,-417 593,-417 599,-423 599,-429 599,-429 599,-496 599,-496 599,-502 593,-508 587,-508 587,-508 463,-508 463,-508 457,-508 451,-502 451,-496 451,-496 451,-429 451,-429 451,-423 457,-417 463,-417"/>
|
||||
<text text-anchor="middle" x="525" y="-492.8" font-family="Arial" font-size="14.00" fill="#000000">toL2Bus </text>
|
||||
<text text-anchor="middle" x="525" y="-477.8" font-family="Arial" font-size="14.00" fill="#000000">: L2XBar</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust12" class="cluster"><title>cluster_system_cpu_cluster_l2</title>
|
||||
<g id="a_clust12"><a xlink:title="addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_cluster.clk_domain clusivity=mostly_incl data_latency=13 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 mshrs=4 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= prefetch_on_access=false prefetcher=Null replacement_policy=system.cpu_cluster.l2.replacement_policy response_latency=5 sequential_access=false size=1048576 system=system tag_latency=13 tags=system.cpu_cluster.l2.tags tgts_per_mshr=8 warmup_percentage=0 write_buffers=16 writeback_clean=false">
|
||||
<path fill="#9f9c95" stroke="#000000" d="M338,-286C338,-286 506,-286 506,-286 512,-286 518,-292 518,-298 518,-298 518,-365 518,-365 518,-371 512,-377 506,-377 506,-377 338,-377 338,-377 332,-377 326,-371 326,-365 326,-365 326,-298 326,-298 326,-292 332,-286 338,-286"/>
|
||||
<text text-anchor="middle" x="422" y="-361.8" font-family="Arial" font-size="14.00" fill="#000000">l2 </text>
|
||||
<text text-anchor="middle" x="422" y="-346.8" font-family="Arial" font-size="14.00" fill="#000000">: HPI_L2</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust16" class="cluster"><title>cluster_system_cpu_cluster_cpus</title>
|
||||
<g id="a_clust16"><a xlink:title="branchPred=system.cpu_cluster.cpus.branchPred checker=Null clk_domain=system.cpu_cluster.clk_domain cpu_id=0 decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dstage2_mmu=system.cpu_cluster.cpus.dstage2_mmu dtb=system.cpu_cluster.cpus.dtb enableIdling=true eventq_index=0 executeAllowEarlyMemoryIssue=true executeBranchDelay=1 executeCommitLimit=2 executeCycleInput=true executeFuncUnits=system.cpu_cluster.cpus.executeFuncUnits executeInputBufferSize=7 executeInputWidth=2 executeIssueLimit=2 executeLSQMaxStoreBufferStoresPerCycle=2 executeLSQRequestsQueueSize=1 executeLSQStoreBufferSize=5 executeLSQTransfersQueueSize=2 executeMaxAccessesInMemory=2 executeMemoryCommitLimit=1 executeMemoryIssueLimit=1 executeMemoryWidth=0 executeSetTraceTimeOnCommit=true executeSetTraceTimeOnIssue=false fetch1FetchLimit=1 fetch1LineSnapWidth=0 fetch1LineWidth=0 fetch1ToFetch2BackwardDelay=1 fetch1ToFetch2ForwardDelay=1 fetch2CycleInput=true fetch2InputBufferSize=2 fetch2ToDecodeForwardDelay=1 function_trace=false function_trace_start=0 interrupts=system.cpu_cluster.cpus.interrupts isa=system.cpu_cluster.cpus.isa istage2_mmu=system.cpu_cluster.cpus.istage2_mmu itb=system.cpu_cluster.cpus.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_gating_on_idle=false power_model= profile=0 progress_interval=0 pwr_gating_latency=300 simpoint_start_insts= socket_id=0 switched_out=false syscallRetryLatency=10000 system=system threadPolicy=RoundRobin tracer=system.cpu_cluster.cpus.tracer wait_for_remote_gdb=false workload=system.cpu_cluster.cpus.workload">
|
||||
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|
||||
<text text-anchor="middle" x="540" y="-846.8" font-family="Arial" font-size="14.00" fill="#000000">cpus </text>
|
||||
<text text-anchor="middle" x="540" y="-831.8" font-family="Arial" font-size="14.00" fill="#000000">: HPI</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust17" class="cluster"><title>cluster_system_cpu_cluster_cpus_dtb_walker_cache</title>
|
||||
<g id="a_clust17"><a xlink:title="addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_cluster.clk_domain clusivity=mostly_incl data_latency=4 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 mshrs=6 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= prefetch_on_access=false prefetcher=Null replacement_policy=system.cpu_cluster.cpus.dtb_walker_cache.replacement_policy response_latency=4 sequential_access=false size=1024 system=system tag_latency=4 tags=system.cpu_cluster.cpus.dtb_walker_cache.tags tgts_per_mshr=8 warmup_percentage=0 write_buffers=16 writeback_clean=false">
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||||
<text text-anchor="middle" x="840" y="-623.8" font-family="Arial" font-size="14.00" fill="#000000">dtb_walker_cache </text>
|
||||
<text text-anchor="middle" x="840" y="-608.8" font-family="Arial" font-size="14.00" fill="#000000">: HPI_WalkCache</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust20" class="cluster"><title>cluster_system_cpu_cluster_cpus_icache</title>
|
||||
<g id="a_clust20"><a xlink:title="addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_cluster.clk_domain clusivity=mostly_incl data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 mshrs=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= prefetch_on_access=false prefetcher=Null replacement_policy=system.cpu_cluster.cpus.icache.replacement_policy response_latency=1 sequential_access=false size=32768 system=system tag_latency=1 tags=system.cpu_cluster.cpus.icache.tags tgts_per_mshr=8 warmup_percentage=0 write_buffers=8 writeback_clean=false">
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||||
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|
||||
<text text-anchor="middle" x="440" y="-623.8" font-family="Arial" font-size="14.00" fill="#000000">icache </text>
|
||||
<text text-anchor="middle" x="440" y="-608.8" font-family="Arial" font-size="14.00" fill="#000000">: HPI_ICache</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust23" class="cluster"><title>cluster_system_cpu_cluster_cpus_dtb</title>
|
||||
<g id="a_clust23"><a xlink:title="eventq_index=0 is_stage2=false size=256 sys=system walker=system.cpu_cluster.cpus.dtb.walker">
|
||||
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|
||||
<text text-anchor="middle" x="794" y="-800.8" font-family="Arial" font-size="14.00" fill="#000000">dtb </text>
|
||||
<text text-anchor="middle" x="794" y="-785.8" font-family="Arial" font-size="14.00" fill="#000000">: HPI_DTB</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust24" class="cluster"><title>cluster_system_cpu_cluster_cpus_dtb_walker</title>
|
||||
<g id="a_clust24"><a xlink:title="clk_domain=system.cpu_cluster.clk_domain default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= sys=system">
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||||
<text text-anchor="middle" x="794" y="-754.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
|
||||
<text text-anchor="middle" x="794" y="-739.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust26" class="cluster"><title>cluster_system_cpu_cluster_cpus_itb_walker_cache</title>
|
||||
<g id="a_clust26"><a xlink:title="addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_cluster.clk_domain clusivity=mostly_incl data_latency=4 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 mshrs=6 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= prefetch_on_access=false prefetcher=Null replacement_policy=system.cpu_cluster.cpus.itb_walker_cache.replacement_policy response_latency=4 sequential_access=false size=1024 system=system tag_latency=4 tags=system.cpu_cluster.cpus.itb_walker_cache.tags tgts_per_mshr=8 warmup_percentage=0 write_buffers=16 writeback_clean=false">
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<text text-anchor="middle" x="640" y="-623.8" font-family="Arial" font-size="14.00" fill="#000000">itb_walker_cache </text>
|
||||
<text text-anchor="middle" x="640" y="-608.8" font-family="Arial" font-size="14.00" fill="#000000">: HPI_WalkCache</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust29" class="cluster"><title>cluster_system_cpu_cluster_cpus_itb</title>
|
||||
<g id="a_clust29"><a xlink:title="eventq_index=0 is_stage2=false size=256 sys=system walker=system.cpu_cluster.cpus.itb.walker">
|
||||
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<text text-anchor="middle" x="589" y="-800.8" font-family="Arial" font-size="14.00" fill="#000000">itb </text>
|
||||
<text text-anchor="middle" x="589" y="-785.8" font-family="Arial" font-size="14.00" fill="#000000">: HPI_ITB</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust30" class="cluster"><title>cluster_system_cpu_cluster_cpus_itb_walker</title>
|
||||
<g id="a_clust30"><a xlink:title="clk_domain=system.cpu_cluster.clk_domain default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= sys=system">
|
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<text text-anchor="middle" x="589" y="-754.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
|
||||
<text text-anchor="middle" x="589" y="-739.8" font-family="Arial" font-size="14.00" fill="#000000">: ArmTableWalker</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust38" class="cluster"><title>cluster_system_cpu_cluster_cpus_dcache</title>
|
||||
<g id="a_clust38"><a xlink:title="addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_cluster.clk_domain clusivity=mostly_incl data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 mshrs=4 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= prefetch_on_access=false prefetcher=system.cpu_cluster.cpus.dcache.prefetcher replacement_policy=system.cpu_cluster.cpus.dcache.replacement_policy response_latency=1 sequential_access=false size=32768 system=system tag_latency=1 tags=system.cpu_cluster.cpus.dcache.tags tgts_per_mshr=8 warmup_percentage=0 write_buffers=4 writeback_clean=false">
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<text text-anchor="middle" x="240" y="-623.8" font-family="Arial" font-size="14.00" fill="#000000">dcache </text>
|
||||
<text text-anchor="middle" x="240" y="-608.8" font-family="Arial" font-size="14.00" fill="#000000">: HPI_DCache</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust557" class="cluster"><title>cluster_system_external_memory</title>
|
||||
<g id="a_clust557"><a xlink:title="addr_ranges=0:2147483647:0:0:0:0 clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 port_data=transactor port_type=tlm_slave power_model=">
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|
||||
<text text-anchor="middle" x="345" y="-99.8" font-family="Arial" font-size="14.00" fill="#000000">external_memory </text>
|
||||
<text text-anchor="middle" x="345" y="-84.8" font-family="Arial" font-size="14.00" fill="#000000">: ExternalSlave</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<!-- system_system_port -->
|
||||
<g id="node1" class="node"><title>system_system_port</title>
|
||||
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|
||||
<text text-anchor="middle" x="72" y="-308.8" font-family="Arial" font-size="14.00" fill="#000000">system_port</text>
|
||||
</g>
|
||||
<!-- system_membus_slave -->
|
||||
<g id="node3" class="node"><title>system_membus_slave</title>
|
||||
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|
||||
<text text-anchor="middle" x="270" y="-177.8" font-family="Arial" font-size="14.00" fill="#000000">slave</text>
|
||||
</g>
|
||||
<!-- system_system_port->system_membus_slave -->
|
||||
<g id="edge1" class="edge"><title>system_system_port->system_membus_slave</title>
|
||||
<path fill="none" stroke="black" d="M98.2929,-294.37C133.5,-271.432 196.05,-230.68 235.151,-205.205"/>
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<polygon fill="black" stroke="black" points="237.13,-208.092 243.598,-199.701 233.309,-202.227 237.13,-208.092"/>
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||||
</g>
|
||||
<!-- system_membus_master -->
|
||||
<g id="node2" class="node"><title>system_membus_master</title>
|
||||
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|
||||
<text text-anchor="middle" x="345" y="-177.8" font-family="Arial" font-size="14.00" fill="#000000">master</text>
|
||||
</g>
|
||||
<!-- system_external_memory_port -->
|
||||
<g id="node20" class="node"><title>system_external_memory_port</title>
|
||||
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|
||||
<text text-anchor="middle" x="345" y="-46.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
|
||||
</g>
|
||||
<!-- system_membus_master->system_external_memory_port -->
|
||||
<g id="edge2" class="edge"><title>system_membus_master->system_external_memory_port</title>
|
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<path fill="none" stroke="black" d="M345,-163.37C345,-141.781 345,-104.412 345,-78.852"/>
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</g>
|
||||
<!-- system_cpu_cluster_toL2Bus_master -->
|
||||
<g id="node4" class="node"><title>system_cpu_cluster_toL2Bus_master</title>
|
||||
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|
||||
<text text-anchor="middle" x="561" y="-439.8" font-family="Arial" font-size="14.00" fill="#000000">master</text>
|
||||
</g>
|
||||
<!-- system_cpu_cluster_l2_cpu_side -->
|
||||
<g id="node7" class="node"><title>system_cpu_cluster_l2_cpu_side</title>
|
||||
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|
||||
<text text-anchor="middle" x="371" y="-308.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
|
||||
</g>
|
||||
<!-- system_cpu_cluster_toL2Bus_master->system_cpu_cluster_l2_cpu_side -->
|
||||
<g id="edge3" class="edge"><title>system_cpu_cluster_toL2Bus_master->system_cpu_cluster_l2_cpu_side</title>
|
||||
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||||
</g>
|
||||
<!-- system_cpu_cluster_toL2Bus_slave -->
|
||||
<g id="node5" class="node"><title>system_cpu_cluster_toL2Bus_slave</title>
|
||||
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|
||||
<text text-anchor="middle" x="486" y="-439.8" font-family="Arial" font-size="14.00" fill="#000000">slave</text>
|
||||
</g>
|
||||
<!-- system_cpu_cluster_l2_mem_side -->
|
||||
<g id="node6" class="node"><title>system_cpu_cluster_l2_mem_side</title>
|
||||
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|
||||
<text text-anchor="middle" x="468" y="-308.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
|
||||
</g>
|
||||
<!-- system_cpu_cluster_l2_mem_side->system_membus_slave -->
|
||||
<g id="edge4" class="edge"><title>system_cpu_cluster_l2_mem_side->system_membus_slave</title>
|
||||
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</g>
|
||||
<!-- system_cpu_cluster_cpus_icache_port -->
|
||||
<g id="node8" class="node"><title>system_cpu_cluster_cpus_icache_port</title>
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<text text-anchor="middle" x="389" y="-701.8" font-family="Arial" font-size="14.00" fill="#000000">icache_port</text>
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</g>
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<!-- system_cpu_cluster_cpus_icache_cpu_side -->
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<g id="node13" class="node"><title>system_cpu_cluster_cpus_icache_cpu_side</title>
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</g>
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<!-- system_cpu_cluster_cpus_icache_port->system_cpu_cluster_cpus_icache_cpu_side -->
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<g id="edge5" class="edge"><title>system_cpu_cluster_cpus_icache_port->system_cpu_cluster_cpus_icache_cpu_side</title>
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<g id="node9" class="node"><title>system_cpu_cluster_cpus_dcache_port</title>
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<text text-anchor="middle" x="192" y="-701.8" font-family="Arial" font-size="14.00" fill="#000000">dcache_port</text>
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</g>
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<!-- system_cpu_cluster_cpus_dcache_cpu_side -->
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<g id="node19" class="node"><title>system_cpu_cluster_cpus_dcache_cpu_side</title>
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<text text-anchor="middle" x="189" y="-570.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
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</g>
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<!-- system_cpu_cluster_cpus_dcache_port->system_cpu_cluster_cpus_dcache_cpu_side -->
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<g id="node10" class="node"><title>system_cpu_cluster_cpus_dtb_walker_cache_mem_side</title>
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<text text-anchor="middle" x="886" y="-570.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
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</g>
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<!-- system_cpu_cluster_cpus_dtb_walker_cache_mem_side->system_cpu_cluster_toL2Bus_slave -->
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<g id="edge7" class="edge"><title>system_cpu_cluster_cpus_dtb_walker_cache_mem_side->system_cpu_cluster_toL2Bus_slave</title>
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</g>
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<!-- system_cpu_cluster_cpus_dtb_walker_cache_cpu_side -->
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<g id="node11" class="node"><title>system_cpu_cluster_cpus_dtb_walker_cache_cpu_side</title>
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<g id="node12" class="node"><title>system_cpu_cluster_cpus_icache_mem_side</title>
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</g>
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<!-- system_cpu_cluster_cpus_icache_mem_side->system_cpu_cluster_toL2Bus_slave -->
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<g id="edge8" class="edge"><title>system_cpu_cluster_cpus_icache_mem_side->system_cpu_cluster_toL2Bus_slave</title>
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<!-- system_cpu_cluster_cpus_dtb_walker_port -->
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<g id="node14" class="node"><title>system_cpu_cluster_cpus_dtb_walker_port</title>
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<text text-anchor="middle" x="789" y="-701.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
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</g>
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<!-- system_cpu_cluster_cpus_dtb_walker_port->system_cpu_cluster_cpus_dtb_walker_cache_cpu_side -->
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<g id="edge9" class="edge"><title>system_cpu_cluster_cpus_dtb_walker_port->system_cpu_cluster_cpus_dtb_walker_cache_cpu_side</title>
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</g>
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<!-- system_cpu_cluster_cpus_itb_walker_cache_mem_side -->
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<g id="node15" class="node"><title>system_cpu_cluster_cpus_itb_walker_cache_mem_side</title>
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<text text-anchor="middle" x="686" y="-570.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
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</g>
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<!-- system_cpu_cluster_cpus_itb_walker_cache_mem_side->system_cpu_cluster_toL2Bus_slave -->
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<g id="edge10" class="edge"><title>system_cpu_cluster_cpus_itb_walker_cache_mem_side->system_cpu_cluster_toL2Bus_slave</title>
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<g id="node16" class="node"><title>system_cpu_cluster_cpus_itb_walker_cache_cpu_side</title>
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</g>
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<!-- system_cpu_cluster_cpus_itb_walker_port -->
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<g id="node17" class="node"><title>system_cpu_cluster_cpus_itb_walker_port</title>
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<text text-anchor="middle" x="589" y="-701.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
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</g>
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<!-- system_cpu_cluster_cpus_itb_walker_port->system_cpu_cluster_cpus_itb_walker_cache_cpu_side -->
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<g id="edge11" class="edge"><title>system_cpu_cluster_cpus_itb_walker_port->system_cpu_cluster_cpus_itb_walker_cache_cpu_side</title>
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<g id="node18" class="node"><title>system_cpu_cluster_cpus_dcache_mem_side</title>
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<!-- system_cpu_cluster_cpus_dcache_mem_side->system_cpu_cluster_toL2Bus_slave -->
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<g id="edge12" class="edge"><title>system_cpu_cluster_cpus_dcache_mem_side->system_cpu_cluster_toL2Bus_slave</title>
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</svg>
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|
Before Width: | Height: | Size: 37 KiB |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -355,7 +355,7 @@ eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=../../DRAMSys/gem5/gem5_se/hello
|
||||
cmd=../../DRAMSys/gem5/gem5_se/hello-ARM/hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
@@ -363,7 +363,7 @@ env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=../../DRAMSys/gem5/gem5_se/hello
|
||||
executable=../../DRAMSys/gem5/gem5_se/hello-ARM/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
0
DRAMSys/gem5/gem5_se/hello → DRAMSys/gem5/gem5_se/hello-ARM/hello
Executable file → Normal file
0
DRAMSys/gem5/gem5_se/hello → DRAMSys/gem5/gem5_se/hello-ARM/hello
Executable file → Normal file
@@ -170,7 +170,7 @@ eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=../../DRAMSys/gem5/gem5_se/hello-x86/hello
|
||||
cmd=../../DRAMSys/gem5/gem5_se/hello-X86/hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
@@ -178,7 +178,7 @@ env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=../../DRAMSys/gem5/gem5_se/hello-x86/hello
|
||||
executable=../../DRAMSys/gem5/gem5_se/hello-X86/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
@@ -1,275 +0,0 @@
|
||||
digraph G {
|
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ranksep="1.3";
|
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subgraph cluster_root {
|
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color="#000000";
|
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fillcolor="#bab6ae";
|
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fontcolor="#000000";
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fontname=Arial;
|
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fontsize=14;
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label="root \n: Root";
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shape=Mrecord;
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style="rounded, filled";
|
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tooltip="eventq_index=0 full_system=false sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000";
|
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subgraph cluster_system {
|
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color="#000000";
|
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fillcolor="#e4e7eb";
|
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fontcolor="#000000";
|
||||
fontname=Arial;
|
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fontsize=14;
|
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label="system \n: System";
|
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shape=Mrecord;
|
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style="rounded, filled";
|
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tooltip="boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 kernel= kernel_addr_check=false kernel_extras= kvm_vm=Null load_addr_mask=18446744073709551615 load_offset=0 mem_mode=timing mem_ranges=0:536870911:0:0:0:0 memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= readfile= symbolfile= thermal_components= thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1";
|
||||
system_system_port [color="#000000", fillcolor="#b6b8bc", fontcolor="#000000", fontname=Arial, fontsize=14, label=system_port, shape=Mrecord, style="rounded, filled"];
|
||||
subgraph cluster_system_membus {
|
||||
color="#000000";
|
||||
fillcolor="#6f798c";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="membus \n: SystemXBar";
|
||||
shape=Mrecord;
|
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style="rounded, filled";
|
||||
tooltip="clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 point_of_coherency=true point_of_unification=true power_model= response_latency=2 snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false width=16";
|
||||
system_membus_master [color="#000000", fillcolor="#586070", fontcolor="#000000", fontname=Arial, fontsize=14, label=master, shape=Mrecord, style="rounded, filled"];
|
||||
system_membus_slave [color="#000000", fillcolor="#586070", fontcolor="#000000", fontname=Arial, fontsize=14, label=slave, shape=Mrecord, style="rounded, filled"];
|
||||
subgraph cluster_system_membus_snoop_filter {
|
||||
color="#000000";
|
||||
fillcolor="#bab6ae";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="snoop_filter \n: SnoopFilter";
|
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shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="eventq_index=0 lookup_latency=1 max_capacity=8388608 system=system";
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
subgraph cluster_system_external_memory {
|
||||
color="#000000";
|
||||
fillcolor="#bab6ae";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="external_memory \n: ExternalSlave";
|
||||
shape=Mrecord;
|
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style="rounded, filled";
|
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tooltip="addr_ranges=0:536870911:0:0:0:0 clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 port_data=transactor port_type=tlm_slave power_model=";
|
||||
system_external_memory_port [color="#000000", fillcolor="#94918b", fontcolor="#000000", fontname=Arial, fontsize=14, label=port, shape=Mrecord, style="rounded, filled"];
|
||||
}
|
||||
|
||||
subgraph cluster_system_voltage_domain {
|
||||
color="#000000";
|
||||
fillcolor="#bab6ae";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="voltage_domain \n: VoltageDomain";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="eventq_index=0 voltage=1.0";
|
||||
}
|
||||
|
||||
subgraph cluster_system_physmem {
|
||||
color="#000000";
|
||||
fillcolor="#5e5958";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="physmem \n: SimpleMemory";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true kvm_map=true latency=30000 latency_var=0 null=false p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= range=0:134217727:0:0:0:0";
|
||||
}
|
||||
|
||||
subgraph cluster_system_clk_domain {
|
||||
color="#000000";
|
||||
fillcolor="#bab6ae";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="clk_domain \n: SrcClockDomain";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="clock=1000 domain_id=-1 eventq_index=0 init_perf_level=0 voltage_domain=system.voltage_domain";
|
||||
}
|
||||
|
||||
subgraph cluster_system_cpu_voltage_domain {
|
||||
color="#000000";
|
||||
fillcolor="#bab6ae";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="cpu_voltage_domain \n: VoltageDomain";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="eventq_index=0 voltage=1.0";
|
||||
}
|
||||
|
||||
subgraph cluster_system_dvfs_handler {
|
||||
color="#000000";
|
||||
fillcolor="#bab6ae";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="dvfs_handler \n: DVFSHandler";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="domains= enable=false eventq_index=0 sys_clk_domain=system.clk_domain transition_latency=100000000";
|
||||
}
|
||||
|
||||
subgraph cluster_system_cpu_clk_domain {
|
||||
color="#000000";
|
||||
fillcolor="#bab6ae";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="cpu_clk_domain \n: SrcClockDomain";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="clock=500 domain_id=-1 eventq_index=0 init_perf_level=0 voltage_domain=system.cpu_voltage_domain";
|
||||
}
|
||||
|
||||
subgraph cluster_system_cpu {
|
||||
color="#000000";
|
||||
fillcolor="#bbc6d9";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="cpu \n: TimingSimpleCPU";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_gating_on_idle=false power_model= profile=0 progress_interval=0 pwr_gating_latency=300 simpoint_start_insts= socket_id=0 switched_out=false syscallRetryLatency=10000 system=system tracer=system.cpu.tracer wait_for_remote_gdb=false workload=system.cpu.workload";
|
||||
system_cpu_icache_port [color="#000000", fillcolor="#959ead", fontcolor="#000000", fontname=Arial, fontsize=14, label=icache_port, shape=Mrecord, style="rounded, filled"];
|
||||
system_cpu_dcache_port [color="#000000", fillcolor="#959ead", fontcolor="#000000", fontname=Arial, fontsize=14, label=dcache_port, shape=Mrecord, style="rounded, filled"];
|
||||
subgraph cluster_system_cpu_workload {
|
||||
color="#000000";
|
||||
fillcolor="#bab6ae";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="workload \n: Process";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="cmd=tests/test-progs/hello/bin/x86/linux/hello cwd=/media/disk2/gem5_tnt/gem5 drivers= egid=100 env= errout=cerr euid=100 eventq_index=0 executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false maxStackSize=67108864 output=cout pgid=100 pid=100 ppid=0 simpoint=0 system=system uid=100 useArchPT=false";
|
||||
}
|
||||
|
||||
subgraph cluster_system_cpu_apic_clk_domain {
|
||||
color="#000000";
|
||||
fillcolor="#bab6ae";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="apic_clk_domain \n: DerivedClockDomain";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="clk_divider=16 clk_domain=system.cpu_clk_domain eventq_index=0";
|
||||
}
|
||||
|
||||
subgraph cluster_system_cpu_dtb {
|
||||
color="#000000";
|
||||
fillcolor="#bab6ae";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="dtb \n: X86TLB";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="eventq_index=0 size=64 walker=system.cpu.dtb.walker";
|
||||
subgraph cluster_system_cpu_dtb_walker {
|
||||
color="#000000";
|
||||
fillcolor="#9f9c95";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="walker \n: X86PagetableWalker";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="clk_domain=system.cpu_clk_domain default_p_state=UNDEFINED eventq_index=0 num_squash_per_cycle=4 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= system=system";
|
||||
system_cpu_dtb_walker_port [color="#000000", fillcolor="#7f7c77", fontcolor="#000000", fontname=Arial, fontsize=14, label=port, shape=Mrecord, style="rounded, filled"];
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
subgraph cluster_system_cpu_interrupts {
|
||||
color="#000000";
|
||||
fillcolor="#c7a793";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="interrupts \n: X86LocalApic";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="clk_domain=system.cpu.apic_clk_domain default_p_state=UNDEFINED eventq_index=0 int_latency=1000 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 pio_addr=2305843009213693952 pio_latency=100000 power_model= system=system";
|
||||
system_cpu_interrupts_int_slave [color="#000000", fillcolor="#9f8575", fontcolor="#000000", fontname=Arial, fontsize=14, label=int_slave, shape=Mrecord, style="rounded, filled"];
|
||||
system_cpu_interrupts_int_master [color="#000000", fillcolor="#9f8575", fontcolor="#000000", fontname=Arial, fontsize=14, label=int_master, shape=Mrecord, style="rounded, filled"];
|
||||
system_cpu_interrupts_pio [color="#000000", fillcolor="#9f8575", fontcolor="#000000", fontname=Arial, fontsize=14, label=pio, shape=Mrecord, style="rounded, filled"];
|
||||
}
|
||||
|
||||
subgraph cluster_system_cpu_itb {
|
||||
color="#000000";
|
||||
fillcolor="#bab6ae";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="itb \n: X86TLB";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="eventq_index=0 size=64 walker=system.cpu.itb.walker";
|
||||
subgraph cluster_system_cpu_itb_walker {
|
||||
color="#000000";
|
||||
fillcolor="#9f9c95";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="walker \n: X86PagetableWalker";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="clk_domain=system.cpu_clk_domain default_p_state=UNDEFINED eventq_index=0 num_squash_per_cycle=4 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= system=system";
|
||||
system_cpu_itb_walker_port [color="#000000", fillcolor="#7f7c77", fontcolor="#000000", fontname=Arial, fontsize=14, label=port, shape=Mrecord, style="rounded, filled"];
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
subgraph cluster_system_cpu_isa {
|
||||
color="#000000";
|
||||
fillcolor="#bab6ae";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="isa \n: X86ISA";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="eventq_index=0";
|
||||
}
|
||||
|
||||
subgraph cluster_system_cpu_tracer {
|
||||
color="#000000";
|
||||
fillcolor="#bab6ae";
|
||||
fontcolor="#000000";
|
||||
fontname=Arial;
|
||||
fontsize=14;
|
||||
label="tracer \n: ExeTracer";
|
||||
shape=Mrecord;
|
||||
style="rounded, filled";
|
||||
tooltip="eventq_index=0";
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
system_system_port -> system_membus_slave;
|
||||
system_membus_master -> system_cpu_interrupts_pio;
|
||||
system_membus_master -> system_cpu_interrupts_int_slave;
|
||||
system_membus_master -> system_external_memory_port;
|
||||
system_cpu_icache_port -> system_membus_slave;
|
||||
system_cpu_dcache_port -> system_membus_slave;
|
||||
system_cpu_dtb_walker_port -> system_membus_slave;
|
||||
system_cpu_interrupts_int_master -> system_membus_slave;
|
||||
system_cpu_itb_walker_port -> system_membus_slave;
|
||||
}
|
||||
Binary file not shown.
@@ -1,193 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN"
|
||||
"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
|
||||
<!-- Generated by graphviz version 2.38.0 (20140413.2041)
|
||||
-->
|
||||
<!-- Title: G Pages: 1 -->
|
||||
<svg width="1007pt" height="577pt"
|
||||
viewBox="0.00 0.00 1007.00 577.00" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
|
||||
<g id="graph0" class="graph" transform="scale(1 1) rotate(0) translate(4 573)">
|
||||
<title>G</title>
|
||||
<polygon fill="white" stroke="none" points="-4,4 -4,-573 1003,-573 1003,4 -4,4"/>
|
||||
<g id="clust1" class="cluster"><title>cluster_root</title>
|
||||
<g id="a_clust1"><a xlink:title="eventq_index=0 full_system=false sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000">
|
||||
<path fill="#bab6ae" stroke="#000000" d="M20,-8C20,-8 979,-8 979,-8 985,-8 991,-14 991,-20 991,-20 991,-549 991,-549 991,-555 985,-561 979,-561 979,-561 20,-561 20,-561 14,-561 8,-555 8,-549 8,-549 8,-20 8,-20 8,-14 14,-8 20,-8"/>
|
||||
<text text-anchor="middle" x="499.5" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">root </text>
|
||||
<text text-anchor="middle" x="499.5" y="-530.8" font-family="Arial" font-size="14.00" fill="#000000">: Root</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust2" class="cluster"><title>cluster_system</title>
|
||||
<g id="a_clust2"><a xlink:title="boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 kernel= kernel_addr_check=false kernel_extras= kvm_vm=Null load_addr_mask=18446744073709551615 load_offset=0 mem_mode=timing mem_ranges=0:536870911:0:0:0:0 memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= readfile= symbolfile= thermal_components= thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1">
|
||||
<path fill="#e4e7eb" stroke="#000000" d="M28,-16C28,-16 971,-16 971,-16 977,-16 983,-22 983,-28 983,-28 983,-503 983,-503 983,-509 977,-515 971,-515 971,-515 28,-515 28,-515 22,-515 16,-509 16,-503 16,-503 16,-28 16,-28 16,-22 22,-16 28,-16"/>
|
||||
<text text-anchor="middle" x="499.5" y="-499.8" font-family="Arial" font-size="14.00" fill="#000000">system </text>
|
||||
<text text-anchor="middle" x="499.5" y="-484.8" font-family="Arial" font-size="14.00" fill="#000000">: System</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust3" class="cluster"><title>cluster_system_membus</title>
|
||||
<g id="a_clust3"><a xlink:title="clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 point_of_coherency=true point_of_unification=true power_model= response_latency=2 snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false width=16">
|
||||
<path fill="#6f798c" stroke="#000000" d="M493,-155C493,-155 617,-155 617,-155 623,-155 629,-161 629,-167 629,-167 629,-234 629,-234 629,-240 623,-246 617,-246 617,-246 493,-246 493,-246 487,-246 481,-240 481,-234 481,-234 481,-167 481,-167 481,-161 487,-155 493,-155"/>
|
||||
<text text-anchor="middle" x="555" y="-230.8" font-family="Arial" font-size="14.00" fill="#000000">membus </text>
|
||||
<text text-anchor="middle" x="555" y="-215.8" font-family="Arial" font-size="14.00" fill="#000000">: SystemXBar</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust5" class="cluster"><title>cluster_system_external_memory</title>
|
||||
<g id="a_clust5"><a xlink:title="addr_ranges=0:536870911:0:0:0:0 clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 port_data=transactor port_type=tlm_slave power_model=">
|
||||
<path fill="#bab6ae" stroke="#000000" d="M538,-24C538,-24 644,-24 644,-24 650,-24 656,-30 656,-36 656,-36 656,-103 656,-103 656,-109 650,-115 644,-115 644,-115 538,-115 538,-115 532,-115 526,-109 526,-103 526,-103 526,-36 526,-36 526,-30 532,-24 538,-24"/>
|
||||
<text text-anchor="middle" x="591" y="-99.8" font-family="Arial" font-size="14.00" fill="#000000">external_memory </text>
|
||||
<text text-anchor="middle" x="591" y="-84.8" font-family="Arial" font-size="14.00" fill="#000000">: ExternalSlave</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust12" class="cluster"><title>cluster_system_cpu</title>
|
||||
<g id="a_clust12"><a xlink:title="branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_gating_on_idle=false power_model= profile=0 progress_interval=0 pwr_gating_latency=300 simpoint_start_insts= socket_id=0 switched_out=false syscallRetryLatency=10000 system=system tracer=system.cpu.tracer wait_for_remote_gdb=false workload=system.cpu.workload">
|
||||
<path fill="#bbc6d9" stroke="#000000" d="M141,-270C141,-270 963,-270 963,-270 969,-270 975,-276 975,-282 975,-282 975,-457 975,-457 975,-463 969,-469 963,-469 963,-469 141,-469 141,-469 135,-469 129,-463 129,-457 129,-457 129,-282 129,-282 129,-276 135,-270 141,-270"/>
|
||||
<text text-anchor="middle" x="552" y="-453.8" font-family="Arial" font-size="14.00" fill="#000000">cpu </text>
|
||||
<text text-anchor="middle" x="552" y="-438.8" font-family="Arial" font-size="14.00" fill="#000000">: TimingSimpleCPU</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust15" class="cluster"><title>cluster_system_cpu_dtb</title>
|
||||
<g id="a_clust15"><a xlink:title="eventq_index=0 size=64 walker=system.cpu.dtb.walker">
|
||||
<path fill="#bab6ae" stroke="#000000" d="M535,-278C535,-278 685,-278 685,-278 691,-278 697,-284 697,-290 697,-290 697,-411 697,-411 697,-417 691,-423 685,-423 685,-423 535,-423 535,-423 529,-423 523,-417 523,-411 523,-411 523,-290 523,-290 523,-284 529,-278 535,-278"/>
|
||||
<text text-anchor="middle" x="610" y="-407.8" font-family="Arial" font-size="14.00" fill="#000000">dtb </text>
|
||||
<text text-anchor="middle" x="610" y="-392.8" font-family="Arial" font-size="14.00" fill="#000000">: X86TLB</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust16" class="cluster"><title>cluster_system_cpu_dtb_walker</title>
|
||||
<g id="a_clust16"><a xlink:title="clk_domain=system.cpu_clk_domain default_p_state=UNDEFINED eventq_index=0 num_squash_per_cycle=4 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= system=system">
|
||||
<path fill="#9f9c95" stroke="#000000" d="M543,-286C543,-286 677,-286 677,-286 683,-286 689,-292 689,-298 689,-298 689,-365 689,-365 689,-371 683,-377 677,-377 677,-377 543,-377 543,-377 537,-377 531,-371 531,-365 531,-365 531,-298 531,-298 531,-292 537,-286 543,-286"/>
|
||||
<text text-anchor="middle" x="610" y="-361.8" font-family="Arial" font-size="14.00" fill="#000000">walker </text>
|
||||
<text text-anchor="middle" x="610" y="-346.8" font-family="Arial" font-size="14.00" fill="#000000">: X86PagetableWalker</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust17" class="cluster"><title>cluster_system_cpu_interrupts</title>
|
||||
<g id="a_clust17"><a xlink:title="clk_domain=system.cpu.apic_clk_domain default_p_state=UNDEFINED eventq_index=0 int_latency=1000 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 pio_addr=2305843009213693952 pio_latency=100000 power_model= system=system">
|
||||
<path fill="#c7a793" stroke="#000000" d="M717,-286C717,-286 955,-286 955,-286 961,-286 967,-292 967,-298 967,-298 967,-365 967,-365 967,-371 961,-377 955,-377 955,-377 717,-377 717,-377 711,-377 705,-371 705,-365 705,-365 705,-298 705,-298 705,-292 711,-286 717,-286"/>
|
||||
<text text-anchor="middle" x="836" y="-361.8" font-family="Arial" font-size="14.00" fill="#000000">interrupts </text>
|
||||
<text text-anchor="middle" x="836" y="-346.8" font-family="Arial" font-size="14.00" fill="#000000">: X86LocalApic</text>
|
||||
</a>
|
||||
</g>
|
||||
</g>
|
||||
<g id="clust18" class="cluster"><title>cluster_system_cpu_itb</title>
|
||||
<g id="a_clust18"><a xlink:title="eventq_index=0 size=64 walker=system.cpu.itb.walker">
|
||||
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Before Width: | Height: | Size: 20 KiB |
@@ -1,397 +0,0 @@
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{
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|
||||
"kvm_map": true,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"power_model": [],
|
||||
"latency_var": 0,
|
||||
"bandwidth": "73.000000",
|
||||
"conf_table_reported": true,
|
||||
"cxx_class": "SimpleMemory",
|
||||
"p_state_clk_gate_max": 1000000000000,
|
||||
"path": "system.physmem",
|
||||
"null": false,
|
||||
"type": "SimpleMemory",
|
||||
"in_addr_map": true
|
||||
},
|
||||
"power_model": [],
|
||||
"work_cpus_ckpt_count": 0,
|
||||
"thermal_components": [],
|
||||
"path": "system",
|
||||
"cpu_clk_domain": {
|
||||
"name": "cpu_clk_domain",
|
||||
"clock": [
|
||||
500
|
||||
],
|
||||
"init_perf_level": 0,
|
||||
"voltage_domain": "system.cpu_voltage_domain",
|
||||
"eventq_index": 0,
|
||||
"cxx_class": "SrcClockDomain",
|
||||
"path": "system.cpu_clk_domain",
|
||||
"type": "SrcClockDomain",
|
||||
"domain_id": -1
|
||||
},
|
||||
"work_end_ckpt_count": 0,
|
||||
"mem_mode": "timing",
|
||||
"name": "system",
|
||||
"init_param": 0,
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"kernel_extras": [],
|
||||
"load_addr_mask": 18446744073709551615,
|
||||
"cpu": [
|
||||
{
|
||||
"do_statistics_insts": true,
|
||||
"numThreads": 1,
|
||||
"itb": {
|
||||
"name": "itb",
|
||||
"eventq_index": 0,
|
||||
"cxx_class": "X86ISA::TLB",
|
||||
"walker": {
|
||||
"name": "walker",
|
||||
"p_state_clk_gate_min": 1000,
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"cxx_class": "X86ISA::Walker",
|
||||
"clk_domain": "system.cpu_clk_domain",
|
||||
"power_model": [],
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 1000000000000,
|
||||
"path": "system.cpu.itb.walker",
|
||||
"type": "X86PagetableWalker",
|
||||
"port": {
|
||||
"peer": "system.membus.slave[3]",
|
||||
"role": "MASTER"
|
||||
},
|
||||
"num_squash_per_cycle": 4
|
||||
},
|
||||
"path": "system.cpu.itb",
|
||||
"type": "X86TLB",
|
||||
"size": 64
|
||||
},
|
||||
"power_gating_on_idle": false,
|
||||
"function_trace": false,
|
||||
"do_checkpoint_insts": true,
|
||||
"cxx_class": "TimingSimpleCPU",
|
||||
"max_loads_all_threads": 0,
|
||||
"system": "system",
|
||||
"apic_clk_domain": {
|
||||
"name": "apic_clk_domain",
|
||||
"clk_domain": "system.cpu_clk_domain",
|
||||
"eventq_index": 0,
|
||||
"cxx_class": "DerivedClockDomain",
|
||||
"path": "system.cpu.apic_clk_domain",
|
||||
"type": "DerivedClockDomain",
|
||||
"clk_divider": 16
|
||||
},
|
||||
"clk_domain": "system.cpu_clk_domain",
|
||||
"function_trace_start": 0,
|
||||
"cpu_id": 0,
|
||||
"checker": null,
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 1000000000000,
|
||||
"do_quiesce": true,
|
||||
"type": "TimingSimpleCPU",
|
||||
"profile": 0,
|
||||
"icache_port": {
|
||||
"peer": "system.membus.slave[1]",
|
||||
"role": "MASTER"
|
||||
},
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"p_state_clk_gate_min": 1000,
|
||||
"syscallRetryLatency": 10000,
|
||||
"interrupts": [
|
||||
{
|
||||
"int_master": {
|
||||
"peer": "system.membus.slave[5]",
|
||||
"role": "MASTER"
|
||||
},
|
||||
"name": "interrupts",
|
||||
"p_state_clk_gate_min": 1000,
|
||||
"pio": {
|
||||
"peer": "system.membus.master[0]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"int_slave": {
|
||||
"peer": "system.membus.master[1]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"cxx_class": "X86ISA::Interrupts",
|
||||
"pio_latency": 100000,
|
||||
"clk_domain": "system.cpu.apic_clk_domain",
|
||||
"power_model": [],
|
||||
"system": "system",
|
||||
"int_latency": 1000,
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 1000000000000,
|
||||
"path": "system.cpu.interrupts",
|
||||
"pio_addr": 2305843009213693952,
|
||||
"type": "X86LocalApic"
|
||||
}
|
||||
],
|
||||
"dcache_port": {
|
||||
"peer": "system.membus.slave[2]",
|
||||
"role": "MASTER"
|
||||
},
|
||||
"socket_id": 0,
|
||||
"power_model": [],
|
||||
"max_insts_all_threads": 0,
|
||||
"path": "system.cpu",
|
||||
"pwr_gating_latency": 300,
|
||||
"max_loads_any_thread": 0,
|
||||
"switched_out": false,
|
||||
"workload": [
|
||||
{
|
||||
"uid": 100,
|
||||
"pid": 100,
|
||||
"kvmInSE": false,
|
||||
"cxx_class": "Process",
|
||||
"executable": "tests/test-progs/hello/bin/x86/linux/hello",
|
||||
"drivers": [],
|
||||
"system": "system",
|
||||
"gid": 100,
|
||||
"eventq_index": 0,
|
||||
"env": [],
|
||||
"maxStackSize": 67108864,
|
||||
"ppid": 0,
|
||||
"type": "Process",
|
||||
"cwd": "/media/disk2/gem5_tnt/gem5",
|
||||
"pgid": 100,
|
||||
"simpoint": 0,
|
||||
"euid": 100,
|
||||
"input": "cin",
|
||||
"path": "system.cpu.workload",
|
||||
"name": "workload",
|
||||
"cmd": [
|
||||
"tests/test-progs/hello/bin/x86/linux/hello"
|
||||
],
|
||||
"errout": "cerr",
|
||||
"useArchPT": false,
|
||||
"egid": 100,
|
||||
"output": "cout"
|
||||
}
|
||||
],
|
||||
"name": "cpu",
|
||||
"wait_for_remote_gdb": false,
|
||||
"dtb": {
|
||||
"name": "dtb",
|
||||
"eventq_index": 0,
|
||||
"cxx_class": "X86ISA::TLB",
|
||||
"walker": {
|
||||
"name": "walker",
|
||||
"p_state_clk_gate_min": 1000,
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"cxx_class": "X86ISA::Walker",
|
||||
"clk_domain": "system.cpu_clk_domain",
|
||||
"power_model": [],
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 1000000000000,
|
||||
"path": "system.cpu.dtb.walker",
|
||||
"type": "X86PagetableWalker",
|
||||
"port": {
|
||||
"peer": "system.membus.slave[4]",
|
||||
"role": "MASTER"
|
||||
},
|
||||
"num_squash_per_cycle": 4
|
||||
},
|
||||
"path": "system.cpu.dtb",
|
||||
"type": "X86TLB",
|
||||
"size": 64
|
||||
},
|
||||
"simpoint_start_insts": [],
|
||||
"max_insts_any_thread": 0,
|
||||
"progress_interval": 0,
|
||||
"branchPred": null,
|
||||
"isa": [
|
||||
{
|
||||
"eventq_index": 0,
|
||||
"path": "system.cpu.isa",
|
||||
"type": "X86ISA",
|
||||
"name": "isa",
|
||||
"cxx_class": "X86ISA::ISA"
|
||||
}
|
||||
],
|
||||
"tracer": {
|
||||
"eventq_index": 0,
|
||||
"path": "system.cpu.tracer",
|
||||
"type": "ExeTracer",
|
||||
"name": "tracer",
|
||||
"cxx_class": "Trace::ExeTracer"
|
||||
}
|
||||
}
|
||||
],
|
||||
"multi_thread": false,
|
||||
"cpu_voltage_domain": {
|
||||
"name": "cpu_voltage_domain",
|
||||
"eventq_index": 0,
|
||||
"voltage": [
|
||||
1.0
|
||||
],
|
||||
"cxx_class": "VoltageDomain",
|
||||
"path": "system.cpu_voltage_domain",
|
||||
"type": "VoltageDomain"
|
||||
},
|
||||
"num_work_ids": 16,
|
||||
"work_item_id": -1,
|
||||
"exit_on_work_items": false
|
||||
},
|
||||
"time_sync_period": 100000000000,
|
||||
"eventq_index": 0,
|
||||
"time_sync_spin_threshold": 100000000,
|
||||
"cxx_class": "Root",
|
||||
"path": "root",
|
||||
"time_sync_enable": false,
|
||||
"type": "Root",
|
||||
"full_system": false
|
||||
}
|
||||
@@ -1,105 +0,0 @@
|
||||
#! /bin/bash
|
||||
|
||||
# Copyright (c) 2018, University of Kaiserslautern
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
#
|
||||
# 3. Neither the name of the copyright holder nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Author: Éder F. Zulian
|
||||
|
||||
simfiles="
|
||||
ddr3-gem5-se.xml
|
||||
"
|
||||
|
||||
bins="
|
||||
8_cores
|
||||
Bubblesort
|
||||
chomp
|
||||
exptree
|
||||
FloatMM
|
||||
IntMM
|
||||
misr
|
||||
Oscar
|
||||
Perm
|
||||
Puzzle
|
||||
Queens
|
||||
Quicksort
|
||||
RealMM
|
||||
Towers
|
||||
Treesort
|
||||
"
|
||||
|
||||
DIR="$(cd "$(dirname "$0")" && pwd)"
|
||||
basedir="$DIR/../../.."
|
||||
sfpath="../../DRAMSys/library/resources/simulations"
|
||||
elf="DRAMSys_gem5"
|
||||
|
||||
if [[ -z "${GEM5}" ]]; then
|
||||
echo "GEM5 environment variable is undefined"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
proj_build() {
|
||||
if [[ $(hostname -s) =~ ^head[0-9]+$ ]] || [[ $(hostname -s) =~ ^node[0-9]+$ ]]; then
|
||||
# Elwetritsch cluster - heads or nodes
|
||||
module load qt/latest
|
||||
#module load anaconda3/latest
|
||||
fi
|
||||
cd $basedir
|
||||
rm -rf build
|
||||
mkdir -p build
|
||||
cd build
|
||||
qmake ../DRAMSys/DRAMSys.pro
|
||||
nprocs=$(cat /proc/cpuinfo | grep processor | wc -l)
|
||||
make -j$nprocs
|
||||
}
|
||||
|
||||
proj_build
|
||||
|
||||
cd $basedir/build/gem5
|
||||
if [ ! -f ${elf} ]; then
|
||||
echo "${elf} could not be found"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
for s in $simfiles; do
|
||||
sf="${sfpath}/${s}"
|
||||
sfn="${s%.*}"
|
||||
ext="${s##*.}"
|
||||
for bin in $bins; do
|
||||
`sed -i s/id=\".*\"/id=\"${sfn}_${bin}\"/g $sf`
|
||||
simulation="${sfpath}/${sfn}_${bin}.${ext}"
|
||||
cp $sf $simulation
|
||||
logfile=${sfn}_${bin}.log
|
||||
# LD_PRELOAD=/usr/lib/libtcmalloc.so ./${elf} ${simulation} ../../DRAMSys/gem5/gem5_se/${bin}/config.ini 1 > ${logfile} 2>&1 &
|
||||
date >> ${logfile}
|
||||
time ./${elf} ${simulation} ../../DRAMSys/gem5/gem5_se/${bin}/config.ini 1 >> ${logfile} 2>&1
|
||||
date >> ${logfile}
|
||||
done
|
||||
done
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2015, University of Kaiserslautern
|
||||
* Copyright (c) 2015, Technische Universität Kaiserslautern
|
||||
* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
|
||||
* All rights reserved.
|
||||
*
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
# Copyright (c) 2020, Fraunhofer IESE
|
||||
# Copyright (c) 2020, Technische Universität Kaiserslautern
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
@@ -28,53 +28,72 @@
|
||||
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Author: Matthias Jung
|
||||
# Authors:
|
||||
# Matthias Jung
|
||||
# Lukas Steiner
|
||||
|
||||
cmake_minimum_required(VERSION 3.10)
|
||||
|
||||
# Project Name
|
||||
project(DRAMSysLibrary)
|
||||
|
||||
# Add DRAMPower:
|
||||
add_subdirectory(src/common/third_party/DRAMPower)
|
||||
|
||||
# Add SystemC:
|
||||
set(BUILD_SHARED_LIBS OFF CACHE BOOL "Build Shared Libs")
|
||||
add_subdirectory(src/common/third_party/systemc)
|
||||
|
||||
# Configuration:
|
||||
set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
|
||||
set(DCMAKE_SH="CMAKE_SH-NOTFOUND")
|
||||
|
||||
include_directories(
|
||||
src/common
|
||||
src/common/third_party/DRAMPower/src
|
||||
src/configuration
|
||||
src/configuration/memspec
|
||||
src/controller
|
||||
src/controller/checker
|
||||
src/controller/cmdmux
|
||||
src/controller/powerdown
|
||||
src/controller/refresh
|
||||
src/controller/respqueue
|
||||
src/controller/scheduler
|
||||
src/error
|
||||
src/error/ECC
|
||||
src/simulation
|
||||
src/simulation/dram
|
||||
)
|
||||
if(DEFINED ENV{COVERAGE})
|
||||
if($ENV{COVERAGE} STREQUAL "true")
|
||||
message("---- Coverage check enabled")
|
||||
set(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage")
|
||||
set(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov")
|
||||
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}")
|
||||
set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}")
|
||||
endif()
|
||||
endif()
|
||||
|
||||
# Add DRAMPower:
|
||||
add_subdirectory(src/common/third_party/DRAMPower)
|
||||
|
||||
# Add nlohmann:
|
||||
add_subdirectory(src/common/third_party/nlohmann)
|
||||
|
||||
# Add SystemC:
|
||||
if(DEFINED ENV{SYSTEMC_HOME})
|
||||
find_library(SYSTEMC_LIBRARY
|
||||
NAMES systemc SnpsVP
|
||||
PATHS $ENV{SYSTEMC_HOME}/lib-$ENV{SYSTEMC_TARGET_ARCH}/ $ENV{SYSTEMC_HOME}/lib-linux64/ $ENV{SYSTEMC_HOME}/libso-$ENV{COWARE_CXX_COMPILER}/
|
||||
)
|
||||
message("---- Building with external SystemC located in $ENV{SYSTEMC_HOME}")
|
||||
else()
|
||||
set(BUILD_SHARED_LIBS OFF CACHE BOOL "Build Shared Libs")
|
||||
add_subdirectory(src/common/third_party/systemc)
|
||||
set(SYSTEMC_LIBRARY systemc)
|
||||
message("---- Building with SystemC submodule")
|
||||
endif()
|
||||
|
||||
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/common/third_party/sqlite-amalgamation)
|
||||
message("---- Database recording included")
|
||||
# Add sqlite3 Dependency:
|
||||
set(BUILD_ENABLE_RTREE ON CACHE BOOL "Enable R-Tree Feature")
|
||||
set(BUILD_ENABLE_RTREE ON)
|
||||
add_subdirectory(src/common/third_party/sqlite-amalgamation)
|
||||
|
||||
set(RECORDING_SOURCES
|
||||
src/common/TlmRecorder.cpp
|
||||
src/controller/ControllerRecordable.cpp
|
||||
src/simulation/DRAMSysRecordable.cpp
|
||||
src/simulation/dram/DramRecordable.cpp
|
||||
)
|
||||
endif()
|
||||
|
||||
add_library(DRAMSysLibrary
|
||||
src/common/AddressDecoder.cpp
|
||||
src/common/DebugManager.cpp
|
||||
src/common/dramExtensions.cpp
|
||||
src/common/tlm2_base_protocol_checker.h
|
||||
src/common/TlmRecorder.cpp
|
||||
src/common/utils.cpp
|
||||
src/common/third_party/tinyxml2/tinyxml2.cpp
|
||||
|
||||
src/configuration/Configuration.cpp
|
||||
src/configuration/ConfigurationLoader.cpp
|
||||
src/configuration/TemperatureSimConfig.h
|
||||
|
||||
src/configuration/memspec/MemSpec.cpp
|
||||
@@ -92,7 +111,6 @@ add_library(DRAMSysLibrary
|
||||
src/controller/Command.cpp
|
||||
src/controller/ControllerIF.h
|
||||
src/controller/Controller.cpp
|
||||
src/controller/ControllerRecordable.cpp
|
||||
|
||||
src/controller/checker/CheckerIF.h
|
||||
src/controller/checker/CheckerDDR3.cpp
|
||||
@@ -137,19 +155,10 @@ add_library(DRAMSysLibrary
|
||||
|
||||
src/simulation/Arbiter.cpp
|
||||
src/simulation/DRAMSys.cpp
|
||||
src/simulation/ExampleInitiator.h
|
||||
src/simulation/MemoryManager.cpp
|
||||
src/simulation/ReorderBuffer.h
|
||||
src/simulation/Setup.cpp
|
||||
src/simulation/StlPlayer.h
|
||||
src/simulation/TemperatureController.cpp
|
||||
src/simulation/TraceGenerator.h
|
||||
src/simulation/TracePlayer.cpp
|
||||
src/simulation/TracePlayerListener.h
|
||||
src/simulation/TraceSetup.cpp
|
||||
|
||||
src/simulation/dram/Dram.cpp
|
||||
src/simulation/dram/DramRecordable.cpp
|
||||
src/simulation/dram/DramDDR3.cpp
|
||||
src/simulation/dram/DramDDR4.cpp
|
||||
src/simulation/dram/DramLPDDR4.cpp
|
||||
@@ -159,16 +168,147 @@ add_library(DRAMSysLibrary
|
||||
src/simulation/dram/DramGDDR5X.cpp
|
||||
src/simulation/dram/DramGDDR6.cpp
|
||||
src/simulation/dram/DramHBM2.cpp
|
||||
|
||||
${RECORDING_SOURCES}
|
||||
|
||||
|
||||
# Simulation Config Files
|
||||
resources/simulations/ddr3-example.json
|
||||
resources/simulations/ddr3-example2.json
|
||||
resources/simulations/ddr3-gem5-se.json
|
||||
resources/simulations/ddr4-example.json
|
||||
resources/simulations/hbm2-example.json
|
||||
resources/simulations/lpddr4-example.json
|
||||
resources/simulations/ranktest.json
|
||||
resources/simulations/wideio-example.json
|
||||
resources/simulations/wideio-thermal.json
|
||||
|
||||
# Address Mapping Config Files
|
||||
resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json
|
||||
resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json
|
||||
resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json
|
||||
resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json
|
||||
resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json
|
||||
resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json
|
||||
resources/configs/amconfigs/am_ddr3_x16_brc.json
|
||||
resources/configs/amconfigs/am_ddr3_x16_rbc.json
|
||||
resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json
|
||||
resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json
|
||||
resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.json
|
||||
resources/configs/amconfigs/am_ranktest.json
|
||||
resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json
|
||||
resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json
|
||||
resources/configs/amconfigs/am_wideio_4x1Gb_brc.json
|
||||
resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json
|
||||
resources/configs/amconfigs/am_wideio_4x256Mb_brc.json
|
||||
resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json
|
||||
resources/configs/amconfigs/am_wideio_4x2Gb_brc.json
|
||||
resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json
|
||||
resources/configs/amconfigs/am_wideio_4x4Gb_brc.json
|
||||
resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json
|
||||
resources/configs/amconfigs/am_wideio_4x512Mb_brc.json
|
||||
resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json
|
||||
|
||||
# Memory Controller Config Files
|
||||
resources/configs/mcconfigs/fifo.json
|
||||
resources/configs/mcconfigs/fifoStrict.json
|
||||
resources/configs/mcconfigs/fr_fcfs_grp.json
|
||||
resources/configs/mcconfigs/fr_fcfs.json
|
||||
|
||||
# Memspec Config Files
|
||||
resources/configs/memspecs/HBM2.json
|
||||
resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json
|
||||
resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json
|
||||
resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json
|
||||
resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json
|
||||
resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json
|
||||
resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json
|
||||
resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json
|
||||
resources/configs/memspecs/memspec_ranktest.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json
|
||||
resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json
|
||||
resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json
|
||||
resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json
|
||||
resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json
|
||||
resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json
|
||||
resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json
|
||||
resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json
|
||||
resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json
|
||||
resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json
|
||||
resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json
|
||||
resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json
|
||||
resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json
|
||||
resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json
|
||||
resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json
|
||||
resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json
|
||||
|
||||
# Simulator Config Files
|
||||
resources/configs/simulator/ddr3_ecc.json
|
||||
resources/configs/simulator/ddr3.json
|
||||
resources/configs/simulator/ddr3_gem5_se.json
|
||||
resources/configs/simulator/ddr4.json
|
||||
resources/configs/simulator/hbm2.json
|
||||
resources/configs/simulator/lpddr4.json
|
||||
resources/configs/simulator/wideio.json
|
||||
resources/configs/simulator/wideio_thermal.json
|
||||
|
||||
# Thermal Simulation Config Files
|
||||
resources/configs/thermalsim/config.json
|
||||
resources/configs/thermalsim/powerInfo.json
|
||||
)
|
||||
|
||||
if(DEFINED ENV{LIBTHREED_ICE_HOME})
|
||||
message("---- Thermal simulation available")
|
||||
add_definitions(-DTHERMALSIM)
|
||||
target_include_directories(DRAMSysLibrary
|
||||
PRIVATE $ENV{LIBTHREED_ICE_HOME}/include/
|
||||
)
|
||||
find_library(3DICE_LIBRARY NAMES threed-ice-2.2.4 PATHS $ENV{LIBTHREED_ICE_HOME}/lib/)
|
||||
target_link_libraries(DRAMSysLibrary
|
||||
PRIVATE ${3DICE_LIBRARY}
|
||||
)
|
||||
endif()
|
||||
|
||||
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/common/third_party/sqlite-amalgamation)
|
||||
target_include_directories(DRAMSysLibrary
|
||||
PRIVATE src/common/third_party/sqlite-amalgamation/
|
||||
)
|
||||
target_link_libraries(DRAMSysLibrary
|
||||
PRIVATE sqlite3::sqlite3
|
||||
)
|
||||
endif()
|
||||
|
||||
# Build:
|
||||
target_include_directories(DRAMSysLibrary
|
||||
PUBLIC src/common/third_party/DRAMPower/src
|
||||
PUBLIC src/common/third_party/sqlite-amalgamation/
|
||||
)
|
||||
target_link_libraries(DRAMSysLibrary
|
||||
SystemC::systemc
|
||||
sqlite3::sqlite3
|
||||
DRAMPower
|
||||
PUBLIC src/common/third_party/DRAMPower/src/
|
||||
PUBLIC $ENV{SYSTEMC_HOME}/include/
|
||||
PUBLIC $ENV{SYSTEMC_HOME}/include/tlm/
|
||||
)
|
||||
|
||||
target_link_libraries(DRAMSysLibrary
|
||||
PUBLIC ${SYSTEMC_LIBRARY}
|
||||
PRIVATE DRAMPower
|
||||
)
|
||||
|
||||
14
DRAMSys/library/resources/configs/mcconfigs/fifo.json
Normal file
14
DRAMSys/library/resources/configs/mcconfigs/fifo.json
Normal file
@@ -0,0 +1,14 @@
|
||||
{
|
||||
"mcconfig": {
|
||||
"PagePolicy": "Open",
|
||||
"Scheduler": "Fifo",
|
||||
"RequestBufferSize": 8,
|
||||
"CmdMux": "Oldest",
|
||||
"RespQueue": "Fifo",
|
||||
"RefreshPolicy": "Rankwise",
|
||||
"RefreshMaxPostponed": 8,
|
||||
"RefreshMaxPulledin": 8,
|
||||
"PowerDownPolicy": "NoPowerDown",
|
||||
"PowerDownTimeout": 100
|
||||
}
|
||||
}
|
||||
14
DRAMSys/library/resources/configs/mcconfigs/fifoStrict.json
Normal file
14
DRAMSys/library/resources/configs/mcconfigs/fifoStrict.json
Normal file
@@ -0,0 +1,14 @@
|
||||
{
|
||||
"mcconfig": {
|
||||
"PagePolicy": "Open",
|
||||
"Scheduler": "Fifo",
|
||||
"RequestBufferSize": 8,
|
||||
"CmdMux": "Strict",
|
||||
"RespQueue": "Fifo",
|
||||
"RefreshPolicy": "Rankwise",
|
||||
"RefreshMaxPostponed": 8,
|
||||
"RefreshMaxPulledin": 8,
|
||||
"PowerDownPolicy": "NoPowerDown",
|
||||
"PowerDownTimeout": 100
|
||||
}
|
||||
}
|
||||
14
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json
Normal file
14
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json
Normal file
@@ -0,0 +1,14 @@
|
||||
{
|
||||
"mcconfig": {
|
||||
"PagePolicy": "Open",
|
||||
"Scheduler": "FrFcfs",
|
||||
"RequestBufferSize": 8,
|
||||
"CmdMux": "Oldest",
|
||||
"RespQueue": "Fifo",
|
||||
"RefreshPolicy": "Rankwise",
|
||||
"RefreshMaxPostponed": 8,
|
||||
"RefreshMaxPulledin": 8,
|
||||
"PowerDownPolicy": "NoPowerDown",
|
||||
"PowerDownTimeout": 100
|
||||
}
|
||||
}
|
||||
14
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.json
Normal file
14
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.json
Normal file
@@ -0,0 +1,14 @@
|
||||
{
|
||||
"mcconfig": {
|
||||
"PagePolicy": "Open",
|
||||
"Scheduler": "FrFcfsGrp",
|
||||
"RequestBufferSize": 8,
|
||||
"CmdMux": "Oldest",
|
||||
"RespQueue": "Fifo",
|
||||
"RefreshPolicy": "Rankwise",
|
||||
"RefreshMaxPostponed": 8,
|
||||
"RefreshMaxPulledin": 8,
|
||||
"PowerDownPolicy": "NoPowerDown",
|
||||
"PowerDownTimeout": 100
|
||||
}
|
||||
}
|
||||
47
DRAMSys/library/resources/configs/memspecs/HBM2.json
Normal file
47
DRAMSys/library/resources/configs/memspecs/HBM2.json
Normal file
@@ -0,0 +1,47 @@
|
||||
{
|
||||
"memspec": {
|
||||
"memarchitecturespec": {
|
||||
"burstLength": 4,
|
||||
"dataRate": 2,
|
||||
"nbrOfBankGroups": 4,
|
||||
"nbrOfBanks": 16,
|
||||
"nbrOfColumns": 128,
|
||||
"nbrOfRanks": 2,
|
||||
"nbrOfRows": 32768,
|
||||
"width": 64,
|
||||
"nbrOfChannels": 1
|
||||
},
|
||||
"memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder",
|
||||
"memoryType": "HBM2",
|
||||
"memtimingspec": {
|
||||
"CCDL": 3,
|
||||
"CCDS": 2,
|
||||
"CKE": 8,
|
||||
"DQSCK": 1,
|
||||
"FAW": 16,
|
||||
"PL": 0,
|
||||
"RAS": 28,
|
||||
"RC": 42,
|
||||
"RCDRD": 12,
|
||||
"RCDWR": 6,
|
||||
"REFI": 3900,
|
||||
"REFISB": 244,
|
||||
"RFC": 220,
|
||||
"RFCSB": 96,
|
||||
"RL": 17,
|
||||
"RP": 14,
|
||||
"RRDL": 6,
|
||||
"RRDS": 4,
|
||||
"RREFD": 8,
|
||||
"RTP": 5,
|
||||
"RTW": 18,
|
||||
"WL": 7,
|
||||
"WR": 14,
|
||||
"WTRL": 9,
|
||||
"WTRS": 4,
|
||||
"XP": 8,
|
||||
"XS": 216,
|
||||
"clkMhz": 1000
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,66 @@
|
||||
{
|
||||
"memspec": {
|
||||
"memarchitecturespec": {
|
||||
"burstLength": 4,
|
||||
"dataRate": 1,
|
||||
"nbrOfBanks": 4,
|
||||
"nbrOfColumns": 128,
|
||||
"nbrOfRanks": 1,
|
||||
"nbrOfRows": 4096,
|
||||
"width": 128,
|
||||
"nbrOfChannels": 4
|
||||
},
|
||||
"memoryId": "JEDEC_256Mb_WIDEIO_SDR-200_128bit",
|
||||
"memoryType": "WIDEIO_SDR",
|
||||
"mempowerspec": {
|
||||
"idd0": 5.88,
|
||||
"idd02": 21.18,
|
||||
"idd2n": 0.13,
|
||||
"idd2n2": 4.04,
|
||||
"idd2p0": 0.05,
|
||||
"idd2p02": 0.17,
|
||||
"idd2p1": 0.05,
|
||||
"idd2p12": 0.17,
|
||||
"idd3n": 0.52,
|
||||
"idd3n2": 6.55,
|
||||
"idd3p0": 0.25,
|
||||
"idd3p02": 1.49,
|
||||
"idd3p1": 0.25,
|
||||
"idd3p12": 1.49,
|
||||
"idd4r": 1.41,
|
||||
"idd4r2": 85.73,
|
||||
"idd4w": 1.42,
|
||||
"idd4w2": 60.79,
|
||||
"idd5": 14.43,
|
||||
"idd52": 48.17,
|
||||
"idd6": 0.07,
|
||||
"idd62": 0.27,
|
||||
"vdd": 1.8,
|
||||
"vdd2": 1.2
|
||||
},
|
||||
"memtimingspec": {
|
||||
"AC": 1,
|
||||
"CCD_R": 2,
|
||||
"CCD_W": 1,
|
||||
"CKE": 3,
|
||||
"CKESR": 3,
|
||||
"DQSCK": 1,
|
||||
"RAS": 9,
|
||||
"RC": 12,
|
||||
"RCD": 4,
|
||||
"REFI": 3120,
|
||||
"RFC": 18,
|
||||
"RL": 3,
|
||||
"RP": 4,
|
||||
"RRD": 2,
|
||||
"TAW": 10,
|
||||
"WL": 1,
|
||||
"WR": 3,
|
||||
"WTR": 3,
|
||||
"XP": 2,
|
||||
"XSR": 20,
|
||||
"RTRS": 1,
|
||||
"clkMhz": 200
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,66 @@
|
||||
{
|
||||
"memspec": {
|
||||
"memarchitecturespec": {
|
||||
"burstLength": 4,
|
||||
"dataRate": 1,
|
||||
"nbrOfBanks": 4,
|
||||
"nbrOfColumns": 128,
|
||||
"nbrOfRanks": 1,
|
||||
"nbrOfRows": 4096,
|
||||
"width": 128,
|
||||
"nbrOfChannels": 4
|
||||
},
|
||||
"memoryId": "JEDEC_256Mb_WIDEIO_SDR-266_128bit",
|
||||
"memoryType": "WIDEIO_SDR",
|
||||
"mempowerspec": {
|
||||
"idd0": 6.06,
|
||||
"idd02": 21.82,
|
||||
"idd2n": 0.16,
|
||||
"idd2n2": 4.76,
|
||||
"idd2p0": 0.05,
|
||||
"idd2p02": 0.17,
|
||||
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||||
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@@ -0,0 +1,71 @@
|
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@@ -0,0 +1,71 @@
|
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{
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||||
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@@ -0,0 +1,43 @@
|
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{
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@@ -0,0 +1,43 @@
|
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{
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@@ -0,0 +1,100 @@
|
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{
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|
||||
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||||
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||||
}
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||||
@@ -0,0 +1,57 @@
|
||||
{
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
@@ -0,0 +1,57 @@
|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
@@ -0,0 +1,61 @@
|
||||
{
|
||||
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|
||||
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|
||||
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|
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||||
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||||
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@@ -0,0 +1,61 @@
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@@ -0,0 +1,61 @@
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{
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}
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@@ -0,0 +1,61 @@
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{
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@@ -0,0 +1,61 @@
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{
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@@ -0,0 +1,61 @@
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{
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}
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@@ -0,0 +1,61 @@
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{
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}
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@@ -0,0 +1,61 @@
|
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{
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}
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@@ -0,0 +1,61 @@
|
||||
{
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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||||
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||||
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|
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|
||||
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|
||||
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|
||||
@@ -0,0 +1,61 @@
|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
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|
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}
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||||
}
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||||
@@ -0,0 +1,61 @@
|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
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||||
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|
||||
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|
||||
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||||
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|
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}
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}
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}
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||||
@@ -0,0 +1,61 @@
|
||||
{
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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}
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}
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@@ -0,0 +1,61 @@
|
||||
{
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}
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@@ -0,0 +1,61 @@
|
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{
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}
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@@ -0,0 +1,61 @@
|
||||
{
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||||
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|
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|
||||
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||||
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|
||||
}
|
||||
@@ -0,0 +1,61 @@
|
||||
{
|
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
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|
||||
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|
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}
|
||||
}
|
||||
@@ -0,0 +1,61 @@
|
||||
{
|
||||
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|
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|
||||
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|
||||
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|
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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@@ -0,0 +1,61 @@
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}
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@@ -0,0 +1,61 @@
|
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{
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}
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@@ -0,0 +1,61 @@
|
||||
{
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}
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@@ -0,0 +1,61 @@
|
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{
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}
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@@ -0,0 +1,61 @@
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{
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}
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@@ -0,0 +1,61 @@
|
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{
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}
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@@ -0,0 +1,61 @@
|
||||
{
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}
|
||||
@@ -0,0 +1,61 @@
|
||||
{
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|
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|
||||
}
|
||||
@@ -0,0 +1,61 @@
|
||||
{
|
||||
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||||
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@@ -0,0 +1,55 @@
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@@ -0,0 +1,55 @@
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}
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@@ -0,0 +1,68 @@
|
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{
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}
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@@ -0,0 +1,68 @@
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{
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@@ -0,0 +1,69 @@
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@@ -0,0 +1,69 @@
|
||||
{
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|
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|
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|
||||
}
|
||||
@@ -0,0 +1,68 @@
|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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||||
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|
||||
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|
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||||
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||||
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||||
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|
||||
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||||
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|
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
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"XPDLL": 6,
|
||||
"XS": 94,
|
||||
"XSDLL": 94,
|
||||
"clkMhz": 667
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,68 @@
|
||||
{
|
||||
"memspec": {
|
||||
"memarchitecturespec": {
|
||||
"burstLength": 8,
|
||||
"dataRate": 2,
|
||||
"nbrOfBanks": 8,
|
||||
"nbrOfColumns": 1024,
|
||||
"nbrOfRanks": 1,
|
||||
"nbrOfRows": 16384,
|
||||
"width": 32,
|
||||
"nbrOfChannels": 1
|
||||
},
|
||||
"memoryId": "MICRON_4Gb_LPDDR3-1600_32bit_A",
|
||||
"memoryType": "LPDDR3",
|
||||
"mempowerspec": {
|
||||
"idd0": 15.0,
|
||||
"idd02": 80.0,
|
||||
"idd2n": 2.0,
|
||||
"idd2n2": 38.0,
|
||||
"idd2p0": 0.6,
|
||||
"idd2p02": 0.87,
|
||||
"idd2p1": 0.6,
|
||||
"idd2p12": 0.87,
|
||||
"idd3n": 2.0,
|
||||
"idd3n2": 45.0,
|
||||
"idd3p0": 1.2,
|
||||
"idd3p02": 8.15,
|
||||
"idd3p1": 1.2,
|
||||
"idd3p12": 8.15,
|
||||
"idd4r": 5.0,
|
||||
"idd4r2": 260.0,
|
||||
"idd4w": 10.0,
|
||||
"idd4w2": 284.0,
|
||||
"idd5": 40.0,
|
||||
"idd52": 160.0,
|
||||
"idd6": 1.0,
|
||||
"idd62": 3.27,
|
||||
"vdd": 1.8,
|
||||
"vdd2": 1.2
|
||||
},
|
||||
"memtimingspec": {
|
||||
"AL": 0,
|
||||
"CCD": 4,
|
||||
"CKE": 6,
|
||||
"CKESR": 12,
|
||||
"CL": 12,
|
||||
"DQSCK": 2,
|
||||
"FAW": 40,
|
||||
"RAS": 36,
|
||||
"RC": 48,
|
||||
"RCD": 15,
|
||||
"REFI": 3120,
|
||||
"RFC": 104,
|
||||
"RL": 12,
|
||||
"RP": 15,
|
||||
"RRD": 8,
|
||||
"RTP": 8,
|
||||
"WL": 9,
|
||||
"WR": 12,
|
||||
"WTR": 8,
|
||||
"XP": 6,
|
||||
"XPDLL": 6,
|
||||
"XS": 112,
|
||||
"XSDLL": 112,
|
||||
"clkMhz": 800
|
||||
}
|
||||
}
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user