Merge branch 'revert-322bc3b4' into 'master'
Revert "Merge branch 'opensource_splitting' into 'master'" See merge request ems/astdm/dram.sys!252
This commit is contained in:
Lukas Steiner
@@ -19,8 +19,8 @@ build:
|
||||
- rm -rf build
|
||||
- mkdir -p build
|
||||
- cd build
|
||||
- cmake ../DRAMSys
|
||||
- make -j16
|
||||
- qmake ../DRAMSys/DRAMSys.pro
|
||||
- make -j4
|
||||
- find . -name "*.o" -type f -delete
|
||||
- rm -rf ${CI_PROJECT_DIR}/coverage
|
||||
- mkdir -p ${CI_PROJECT_DIR}/coverage
|
||||
|
||||
6
.gitmodules
vendored
6
.gitmodules
vendored
@@ -1,3 +1,6 @@
|
||||
[submodule "DRAMSys/library/src/common/third_party/tinyxml2"]
|
||||
path = DRAMSys/library/src/common/third_party/tinyxml2
|
||||
url = https://github.com/leethomason/tinyxml2.git
|
||||
[submodule "DRAMSys/library/src/common/third_party/DRAMPower"]
|
||||
path = DRAMSys/library/src/common/third_party/DRAMPower
|
||||
url = https://github.com/tukl-msd/DRAMPower.git
|
||||
@@ -11,6 +14,3 @@
|
||||
[submodule "DRAMSys/library/src/common/third_party/sqlite-amalgamation"]
|
||||
path = DRAMSys/library/src/common/third_party/sqlite-amalgamation
|
||||
url = https://github.com/azadkuh/sqlite-amalgamation.git
|
||||
[submodule "DRAMSys/library/src/common/third_party/nlohmann"]
|
||||
path = DRAMSys/library/src/common/third_party/nlohmann
|
||||
url = https://github.com/nlohmann/json
|
||||
|
||||
@@ -39,18 +39,22 @@ project(DRAMSys)
|
||||
set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
|
||||
set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows")
|
||||
|
||||
# Add sqlite3 Dependency:
|
||||
set(BUILD_ENABLE_RTREE ON CACHE BOOL "Enable R-Tree Feature")
|
||||
set(BUILD_ENABLE_RTREE ON)
|
||||
add_subdirectory(library/src/common/third_party/sqlite-amalgamation)
|
||||
|
||||
# Add DRAMSysLibrary:
|
||||
add_subdirectory(library)
|
||||
|
||||
# Add TraceAnalyzer:
|
||||
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/library/src/simulation/DRAMSysRecordable.cpp)
|
||||
add_subdirectory(traceAnalyzer)
|
||||
endif()
|
||||
add_subdirectory(traceAnalyzer)
|
||||
|
||||
# Add DRAMSysSimulator:
|
||||
add_subdirectory(simulator)
|
||||
# Build:
|
||||
add_executable(DRAMSys simulator/main.cpp)
|
||||
target_include_directories(DRAMSys
|
||||
PUBLIC library/src/simulation/
|
||||
PUBLIC library/src/common/third_party/sqlite-amalgamation/
|
||||
)
|
||||
target_link_libraries(DRAMSys sqlite3::sqlite3 systemc DRAMSysLibrary)
|
||||
|
||||
# Add DRAMSysgem5
|
||||
if(DEFINED ENV{GEM5})
|
||||
add_subdirectory(gem5)
|
||||
endif()
|
||||
|
||||
BIN
DRAMSys/docs/Timings.ods
Normal file
BIN
DRAMSys/docs/Timings.ods
Normal file
Binary file not shown.
@@ -1,73 +0,0 @@
|
||||
# Copyright (c) 2020, Technische Universität Kaiserslautern
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
#
|
||||
# 3. Neither the name of the copyright holder nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Author: Lukas Steiner
|
||||
|
||||
cmake_minimum_required(VERSION 3.10)
|
||||
|
||||
set(GEM5_ARCH ARM) # ARM, X86, ALPHA
|
||||
set(GEM5_VARIANT opt) # opt, fast
|
||||
|
||||
# Configuration:
|
||||
set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
|
||||
set(DCMAKE_SH="CMAKE_SH-NOTFOUND")
|
||||
|
||||
find_library(GEM5_LIBRARY gem5_${GEM5_VARIANT} PATH $ENV{GEM5}/build/${GEM5_ARCH}/)
|
||||
|
||||
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/../library/src/simulation/DRAMSysRecordable.cpp)
|
||||
add_definitions(-DRECORDING)
|
||||
endif()
|
||||
|
||||
add_executable(DRAMSys_gem5
|
||||
main.cpp
|
||||
$ENV{GEM5}/util/systemc/sc_logger.cc
|
||||
$ENV{GEM5}/util/systemc/sc_module.cc
|
||||
$ENV{GEM5}/util/systemc/stats.cc
|
||||
$ENV{GEM5}/util/tlm/src/sc_master_port.cc
|
||||
$ENV{GEM5}/util/tlm/src/sc_slave_port.cc
|
||||
$ENV{GEM5}/util/tlm/src/slave_transactor.cc
|
||||
$ENV{GEM5}/util/tlm/src/sc_ext.cc
|
||||
$ENV{GEM5}/util/tlm/src/sc_mm.cc
|
||||
$ENV{GEM5}/util/tlm/src/sim_control.cc
|
||||
)
|
||||
|
||||
target_include_directories(DRAMSys_gem5
|
||||
PRIVATE $ENV{GEM5}/build/ARM/
|
||||
PRIVATE $ENV{GEM5}/util/tlm/examples/slave_port/
|
||||
PRIVATE $ENV{GEM5}/util/tlm/examples/common/
|
||||
PRIVATE $ENV{GEM5}/util/tlm/src/
|
||||
PRIVATE $ENV{GEM5}/util/systemc/
|
||||
PRIVATE ../library/src/simulation/
|
||||
)
|
||||
|
||||
target_link_libraries(DRAMSys_gem5
|
||||
PRIVATE DRAMSysLibrary
|
||||
PRIVATE ${GEM5_LIBRARY}
|
||||
)
|
||||
4
DRAMSys/gem5/configs/configs.pri
Normal file
4
DRAMSys/gem5/configs/configs.pri
Normal file
@@ -0,0 +1,4 @@
|
||||
|
||||
DISTFILES += dualElasticTraceReplay.ini
|
||||
DISTFILES += nvdimmp.ini
|
||||
DISTFILES += singleElasticTraceReplay.ini
|
||||
167
DRAMSys/gem5/gem5.pro
Normal file
167
DRAMSys/gem5/gem5.pro
Normal file
@@ -0,0 +1,167 @@
|
||||
TARGET = DRAMSys_gem5
|
||||
TEMPLATE = app
|
||||
CONFIG += console
|
||||
CONFIG -= app_bundle
|
||||
CONFIG -= qt
|
||||
|
||||
# gem5 parameters:
|
||||
gem5_arch = 'ARM'
|
||||
gem5_variant = 'opt'
|
||||
gem5_root = $$(GEM5)
|
||||
|
||||
systemc_home = $$(SYSTEMC_HOME)
|
||||
isEmpty(systemc_home) {
|
||||
systemc_home = /opt/systemc
|
||||
}
|
||||
message(SystemC home is $${systemc_home})
|
||||
|
||||
systemc_target_arch = $$(SYSTEMC_TARGET_ARCH)
|
||||
isEmpty(systemc_target_arch) {
|
||||
systemc_target_arch = linux64
|
||||
}
|
||||
|
||||
message(SystemC target architecture is $${systemc_target_arch})
|
||||
|
||||
unix:!macx {
|
||||
message(Building on a GNU/Linux)
|
||||
QMAKE_RPATHDIR += $${systemc_home}/lib-$${systemc_target_arch}
|
||||
QMAKE_RPATHDIR += $${gem5_root}/build/$${gem5_arch}
|
||||
message(Linker options QMAKE_RPATHDIR is $${QMAKE_RPATHDIR})
|
||||
}
|
||||
|
||||
DEFINES += TIXML_USE_STL
|
||||
DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES
|
||||
DEFINES += DRAMSYS_GEM5
|
||||
|
||||
dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK)
|
||||
isEmpty(dramsys_disable_coverage_check) {
|
||||
coverage_check = true
|
||||
message(Coverage check ENABLED)
|
||||
} else {
|
||||
coverage_check = false
|
||||
message(Coverage check DISABLED)
|
||||
}
|
||||
|
||||
unix:!macx {
|
||||
QMAKE_CXXFLAGS += -std=c++11 -O0 -g
|
||||
$$eval(coverage_check) {
|
||||
QMAKE_CXXFLAGS += -fprofile-arcs -ftest-coverage -fPIC -O0
|
||||
QMAKE_LFLAGS += -lgcov --coverage
|
||||
}
|
||||
}
|
||||
|
||||
macx: {
|
||||
CONFIG += c++11
|
||||
QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ -O0 -g
|
||||
$$eval(coverage_check) {
|
||||
QMAKE_CXXFLAGS += --coverage
|
||||
QMAKE_LFLAGS += --coverage
|
||||
}
|
||||
}
|
||||
|
||||
INCLUDEPATH += ../library/src/simulation/
|
||||
INCLUDEPATH += $${systemc_home}/include
|
||||
INCLUDEPATH += ../library/src/common/third_party/DRAMPower/src
|
||||
INCLUDEPATH += ../library/src/common/third_party/DRAMPower/src/libdrampower
|
||||
INCLUDEPATH += $${gem5_root}/build/$${gem5_arch}/
|
||||
INCLUDEPATH += $${gem5_root}/util/tlm/examples/slave_port
|
||||
INCLUDEPATH += $${gem5_root}/util/tlm/examples/common
|
||||
INCLUDEPATH += $${gem5_root}/util/tlm/src/
|
||||
INCLUDEPATH += $${gem5_root}/util/systemc
|
||||
|
||||
LIBS += -L$${systemc_home}/lib-$${systemc_target_arch} -lsystemc
|
||||
LIBS += ../library/libDRAMSys.a
|
||||
LIBS += ../../DRAMSys/library/src/common/third_party/DRAMPower/src/libdrampower.a
|
||||
LIBS += -lsqlite3
|
||||
LIBS += -L$${gem5_root}/build/$${gem5_arch} -lgem5_$${gem5_variant}
|
||||
|
||||
SOURCES += $${gem5_root}/util/systemc/sc_gem5_control.cc
|
||||
SOURCES += $${gem5_root}/util/systemc/sc_logger.cc
|
||||
SOURCES += $${gem5_root}/util/systemc/sc_module.cc
|
||||
SOURCES += $${gem5_root}/util/systemc/stats.cc
|
||||
SOURCES += $${gem5_root}/util/tlm/examples/common/cli_parser.cc
|
||||
SOURCES += $${gem5_root}/util/tlm/examples/common/report_handler.cc
|
||||
SOURCES += $${gem5_root}/util/tlm/src/master_transactor.cc
|
||||
SOURCES += $${gem5_root}/util/tlm/src/sc_master_port.cc
|
||||
SOURCES += $${gem5_root}/util/tlm/src/sc_slave_port.cc
|
||||
SOURCES += $${gem5_root}/util/tlm/src/slave_transactor.cc
|
||||
SOURCES += $${gem5_root}/util/tlm/src/sc_ext.cc
|
||||
SOURCES += $${gem5_root}/util/tlm/src/sc_mm.cc
|
||||
SOURCES += $${gem5_root}/util/tlm/src/sim_control.cc
|
||||
|
||||
SOURCES += main.cpp
|
||||
|
||||
DISTFILES += ../DRAMSys.astylerc
|
||||
|
||||
DISTFILES += etrace_single/config.ini
|
||||
DISTFILES += etrace_single_L2/HPCG-47MB/config.ini
|
||||
DISTFILES += etrace_single_L2/Pathfinder/config.ini
|
||||
DISTFILES += etrace_single_L2/hpcc-linpack/config.ini
|
||||
DISTFILES += etrace_single_L2/hpcc-fft/config.ini
|
||||
DISTFILES += etrace_single_L2/config.ini
|
||||
DISTFILES += etrace_single_L2/hpcc-dgemm/config.ini
|
||||
DISTFILES += etrace_single_L2/hpcc-gups/config.ini
|
||||
DISTFILES += configs/singleElasticTraceReplayWithL2.ini
|
||||
DISTFILES += configs/nvdimmp.ini
|
||||
DISTFILES += configs/hello.ini
|
||||
DISTFILES += configs/dualElasticTraceReplay.ini
|
||||
DISTFILES += configs/singleElasticTraceReplay.ini
|
||||
DISTFILES += configs/boot_linux.ini
|
||||
DISTFILES += gem5_fs/stream/config.ini
|
||||
DISTFILES += gem5_fs/stream/stream_1_cores.rcS
|
||||
DISTFILES += gem5_fs/parsec/simmedium/fluidanimate/fluidanimate_simmedium_2.rcS
|
||||
DISTFILES += gem5_fs/parsec/simmedium/fluidanimate/config.ini
|
||||
DISTFILES += gem5_fs/parsec/simmedium/ferret/config.ini
|
||||
DISTFILES += gem5_fs/parsec/simmedium/ferret/ferret_simmedium_2.rcS
|
||||
DISTFILES += gem5_fs/parsec/simmedium/blackscholes/blackscholes_simmedium_2.rcS
|
||||
DISTFILES += gem5_fs/parsec/simmedium/blackscholes/config.ini
|
||||
DISTFILES += gem5_fs/parsec/simlarge/streamcluster/config.ini
|
||||
DISTFILES += gem5_fs/parsec/simlarge/streamcluster/streamcluster_simlarge_2.rcS
|
||||
DISTFILES += gem5_fs/parsec/simsmall/fluidanimate/fluidanimate_simsmall_2.rcS
|
||||
DISTFILES += gem5_fs/parsec/simsmall/fluidanimate/config.ini
|
||||
DISTFILES += gem5_fs/parsec/simsmall/bodytrack/bodytrack_simsmall_2.rcS
|
||||
DISTFILES += gem5_fs/parsec/simsmall/bodytrack/config.ini
|
||||
DISTFILES += gem5_fs/parsec/simsmall/ferret/config.ini
|
||||
DISTFILES += gem5_fs/parsec/simsmall/ferret/ferret_simsmall_2.rcS
|
||||
DISTFILES += gem5_fs/parsec/simsmall/blackscholes/config.ini
|
||||
DISTFILES += gem5_fs/parsec/simsmall/blackscholes/blackscholes_simsmall_2.rcS
|
||||
DISTFILES += gem5_fs/parsec/simdev/fluidanimate/config.ini
|
||||
DISTFILES += gem5_fs/parsec/simdev/fluidanimate/fluidanimate_simdev_2.rcS
|
||||
DISTFILES += gem5_fs/parsec/simdev/blackscholes/blackscholes_simdev_2.rcS
|
||||
DISTFILES += gem5_fs/parsec/simdev/blackscholes/config.ini
|
||||
DISTFILES += examples/tlm_elastic_slave.py
|
||||
DISTFILES += examples/tlm_elastic_slave_mc_direct.py
|
||||
DISTFILES += examples/tlm_elastic_slave_with_l2.py
|
||||
DISTFILES += gem5_se/almabench/config.ini
|
||||
DISTFILES += gem5_se/fldry/config.ini
|
||||
DISTFILES += gem5_se/Queens/config.ini
|
||||
DISTFILES += gem5_se/chomp/config.ini
|
||||
DISTFILES += gem5_se/l1_cache/Queens/config.ini
|
||||
DISTFILES += gem5_se/l1_cache/chomp/config.ini
|
||||
DISTFILES += gem5_se/l1_cache/Puzzle/config.ini
|
||||
DISTFILES += gem5_se/l1_cache/RealMM/config.ini
|
||||
DISTFILES += gem5_se/l1_cache/Perm/config.ini
|
||||
DISTFILES += gem5_se/l1_cache/Treesort/config.ini
|
||||
DISTFILES += gem5_se/l1_cache/Bubblesort/config.ini
|
||||
DISTFILES += gem5_se/l1_cache/misr/config.ini
|
||||
DISTFILES += gem5_se/l1_cache/exptree/config.ini
|
||||
DISTFILES += gem5_se/l1_cache/Quicksort/config.ini
|
||||
DISTFILES += gem5_se/l1_cache/IntMM/config.ini
|
||||
DISTFILES += gem5_se/l1_cache/Oscar/config.ini
|
||||
DISTFILES += gem5_se/l1_cache/FloatMM/config.ini
|
||||
DISTFILES += gem5_se/l1_cache/Towers/config.ini
|
||||
DISTFILES += gem5_se/run.sh
|
||||
DISTFILES += gem5_se/Puzzle/config.ini
|
||||
DISTFILES += gem5_se/RealMM/config.ini
|
||||
DISTFILES += gem5_se/Perm/config.ini
|
||||
DISTFILES += gem5_se/Treesort/config.ini
|
||||
DISTFILES += gem5_se/Bubblesort/config.ini
|
||||
DISTFILES += gem5_se/misr/config.ini
|
||||
DISTFILES += gem5_se/lpbench/config.ini
|
||||
DISTFILES += gem5_se/8_cores/config.ini
|
||||
DISTFILES += gem5_se/exptree/config.ini
|
||||
DISTFILES += gem5_se/Quicksort/config.ini
|
||||
DISTFILES += gem5_se/IntMM/config.ini
|
||||
DISTFILES += gem5_se/Oscar/config.ini
|
||||
DISTFILES += gem5_se/FloatMM/config.ini
|
||||
DISTFILES += gem5_se/Towers/config.ini
|
||||
@@ -41,29 +41,24 @@
|
||||
#include <string>
|
||||
#include <cstdlib>
|
||||
|
||||
#include "DRAMSys.h"
|
||||
#include "TraceSetup.h"
|
||||
|
||||
#include "report_handler.hh"
|
||||
#include "sc_target.hh"
|
||||
#include "sim_control.hh"
|
||||
#include "slave_transactor.hh"
|
||||
#include "stats.hh"
|
||||
|
||||
#include "DRAMSys.h"
|
||||
using namespace std;
|
||||
|
||||
#ifdef RECORDING
|
||||
#include "DRAMSysRecordable.h"
|
||||
#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
|
||||
using json = nlohmann::json;
|
||||
#endif
|
||||
|
||||
using namespace tlm;
|
||||
|
||||
class Gem5SimControlDRAMsys : public Gem5SystemC::Gem5SimControl
|
||||
class Gem5SimControlDRAMsys: public Gem5SystemC::Gem5SimControl
|
||||
{
|
||||
public:
|
||||
Gem5SimControlDRAMsys(std::string configFile) :
|
||||
Gem5SimControlDRAMsys(string configFile) :
|
||||
Gem5SystemC::Gem5SimControl("gem5", configFile, 0, "MemoryAccess")
|
||||
{}
|
||||
{
|
||||
}
|
||||
|
||||
void afterSimulate()
|
||||
{
|
||||
@@ -72,8 +67,7 @@ public:
|
||||
};
|
||||
|
||||
|
||||
class AddressOffset : sc_module
|
||||
{
|
||||
struct AddressOffset: sc_module {
|
||||
private:
|
||||
unsigned long long int offset;
|
||||
|
||||
@@ -91,7 +85,7 @@ public:
|
||||
}
|
||||
|
||||
//Forward Interface
|
||||
tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase,
|
||||
tlm::tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase,
|
||||
sc_time &delay)
|
||||
{
|
||||
//std::cout << "NB "<< this->name() <<": " << trans.get_address() << " -" << offset;
|
||||
@@ -100,7 +94,7 @@ public:
|
||||
return i_socket->nb_transport_fw(trans, phase, delay);
|
||||
}
|
||||
|
||||
unsigned int transport_dbg(tlm_generic_payload &trans)
|
||||
unsigned int transport_dbg(tlm::tlm_generic_payload &trans)
|
||||
{
|
||||
// adjust address offset:
|
||||
//std::cout << "Debug "<< this->name() <<": " << trans.get_address() << " -" << offset;
|
||||
@@ -109,7 +103,7 @@ public:
|
||||
return i_socket->transport_dbg(trans);
|
||||
}
|
||||
|
||||
void b_transport(tlm_generic_payload &trans, sc_time &delay)
|
||||
void b_transport(tlm::tlm_generic_payload &trans, sc_time &delay)
|
||||
{
|
||||
// adjust address offset:
|
||||
//std::cout << "B "<< this->name() <<": " << trans.get_address() << " -" << offset;
|
||||
@@ -119,7 +113,7 @@ public:
|
||||
}
|
||||
|
||||
//Backward Interface
|
||||
tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase,
|
||||
tlm::tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase,
|
||||
sc_time &delay)
|
||||
{
|
||||
//trans.set_address(trans.get_address()+offset);
|
||||
@@ -128,7 +122,7 @@ public:
|
||||
|
||||
};
|
||||
|
||||
std::string pathOfFile(std::string file)
|
||||
string pathOfFile(string file)
|
||||
{
|
||||
return file.substr(0, file.find_last_of('/'));
|
||||
}
|
||||
@@ -137,9 +131,9 @@ int sc_main(int argc, char **argv)
|
||||
{
|
||||
SC_REPORT_INFO("sc_main", "Simulation Setup");
|
||||
|
||||
std::string simulationJson;
|
||||
std::string gem5ConfigFile;
|
||||
std::string resources;
|
||||
string SimulationXML;
|
||||
string gem5ConfigFile;
|
||||
string resources;
|
||||
unsigned int numTransactors;
|
||||
Gem5SystemC::Gem5SlaveTransactor *t;
|
||||
std::vector<Gem5SystemC::Gem5SlaveTransactor *> transactors;
|
||||
@@ -147,28 +141,18 @@ int sc_main(int argc, char **argv)
|
||||
if (argc == 4) {
|
||||
// Get path of resources:
|
||||
resources = pathOfFile(argv[0])
|
||||
+ std::string("/../../DRAMSys/library/resources/");
|
||||
+ string("/../../DRAMSys/library/resources/");
|
||||
|
||||
simulationJson = argv[1];
|
||||
SimulationXML = argv[1];
|
||||
gem5ConfigFile = argv[2];
|
||||
numTransactors = std::stoul(argv[3]);
|
||||
numTransactors = atoi(argv[3]);
|
||||
|
||||
} else {
|
||||
SC_REPORT_FATAL("sc_main", "Please provide configuration files and number of ports");
|
||||
}
|
||||
|
||||
// Instantiate DRAMSys:
|
||||
DRAMSys *dramSys;
|
||||
#ifdef RECORDING
|
||||
json simulationdoc = parseJSON(simulationJson);
|
||||
json simulatordoc = parseJSON(resources + "configs/simulator/"
|
||||
+ std::string(simulationdoc["simulation"]["simconfig"]));
|
||||
|
||||
if (simulatordoc["simconfig"]["DatabaseRecording"])
|
||||
dramSys = new DRAMSysRecordable("DRAMSys", simulationJson, resources);
|
||||
else
|
||||
#endif
|
||||
dramSys = new DRAMSys("DRAMSys", simulationJson, resources);
|
||||
DRAMSys dramSys("DRAMSys", SimulationXML, resources);
|
||||
|
||||
// Instantiate gem5:
|
||||
Gem5SimControlDRAMsys sim_control(gem5ConfigFile);
|
||||
@@ -179,7 +163,7 @@ int sc_main(int argc, char **argv)
|
||||
// Names generated here must match port names used by the gem5 config file, e.g., config.ini
|
||||
if (numTransactors == 1) {
|
||||
t = new Gem5SystemC::Gem5SlaveTransactor("transactor", "transactor");
|
||||
t->socket.bind(dramSys->tSocket);
|
||||
t->socket.bind(dramSys.tSocket);
|
||||
t->sim_control.bind(sim_control);
|
||||
transactors.push_back(t);
|
||||
} else {
|
||||
@@ -189,7 +173,7 @@ int sc_main(int argc, char **argv)
|
||||
std::string name = "transactor" + std::to_string(index);
|
||||
std::string portName = "transactor" + std::to_string(index);
|
||||
t = new Gem5SystemC::Gem5SlaveTransactor(name.c_str(), portName.c_str());
|
||||
t->socket.bind(dramSys->tSocket);
|
||||
t->socket.bind(dramSys.tSocket);
|
||||
t->sim_control.bind(sim_control);
|
||||
transactors.push_back(t);
|
||||
}
|
||||
@@ -205,9 +189,9 @@ int sc_main(int argc, char **argv)
|
||||
AddressOffset dramOffset("dramOffset", (2147483648 - 67108863)); //+67108863);
|
||||
|
||||
dramInterface.socket.bind(dramOffset.t_socket);
|
||||
dramOffset.i_socket.bind(dramSys->tSocket); // ID0
|
||||
dramOffset.i_socket.bind(dramSys.tSocket); // ID0
|
||||
nvmInterface.socket.bind(nvmOffset.t_socket);
|
||||
nvmOffset.i_socket.bind(dramSys->tSocket);
|
||||
nvmOffset.i_socket.bind(dramSys.tSocket);
|
||||
|
||||
dramInterface.sim_control.bind(sim_control);
|
||||
nvmInterface.sim_control.bind(sim_control);
|
||||
@@ -223,10 +207,9 @@ int sc_main(int argc, char **argv)
|
||||
sc_core::sc_stop();
|
||||
}
|
||||
|
||||
for (auto t : transactors)
|
||||
for (auto t : transactors) {
|
||||
delete t;
|
||||
|
||||
delete dramSys;
|
||||
}
|
||||
|
||||
SC_REPORT_INFO("sc_main", "End of Simulation");
|
||||
|
||||
|
||||
@@ -35,52 +35,46 @@ cmake_minimum_required(VERSION 3.10)
|
||||
# Project Name
|
||||
project(DRAMSysLibrary)
|
||||
|
||||
# Add DRAMPower:
|
||||
add_subdirectory(src/common/third_party/DRAMPower)
|
||||
|
||||
# Add SystemC:
|
||||
set(BUILD_SHARED_LIBS OFF CACHE BOOL "Build Shared Libs")
|
||||
add_subdirectory(src/common/third_party/systemc)
|
||||
|
||||
# Configuration:
|
||||
set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
|
||||
set(DCMAKE_SH="CMAKE_SH-NOTFOUND")
|
||||
|
||||
# Add DRAMPower:
|
||||
add_subdirectory(src/common/third_party/DRAMPower)
|
||||
|
||||
# Add nlohmann:
|
||||
add_subdirectory(src/common/third_party/nlohmann)
|
||||
|
||||
# Add SystemC:
|
||||
if(DEFINED ENV{SYSTEMC_HOME})
|
||||
find_library(SYSTEMC_LIBRARY
|
||||
NAMES systemc SnpsVP
|
||||
PATHS $ENV{SYSTEMC_HOME}/lib-$ENV{SYSTEMC_TARGET_ARCH}/ $ENV{SYSTEMC_HOME}/lib-linux64/ $ENV{SYSTEMC_HOME}/libso-$ENV{COWARE_CXX_COMPILER}/
|
||||
)
|
||||
message("-- Building with external SystemC located in $ENV{SYSTEMC_HOME}")
|
||||
else()
|
||||
set(BUILD_SHARED_LIBS OFF CACHE BOOL "Build Shared Libs")
|
||||
add_subdirectory(src/common/third_party/systemc)
|
||||
set(SYSTEMC_LIBRARY systemc)
|
||||
message("-- Building with SystemC submodule")
|
||||
endif()
|
||||
|
||||
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/simulation/DRAMSysRecordable.cpp)
|
||||
# Add sqlite3 Dependency:
|
||||
set(BUILD_ENABLE_RTREE ON CACHE BOOL "Enable R-Tree Feature")
|
||||
set(BUILD_ENABLE_RTREE ON)
|
||||
add_subdirectory(src/common/third_party/sqlite-amalgamation)
|
||||
|
||||
set(RECORDING_SOURCES
|
||||
src/common/TlmRecorder.cpp
|
||||
src/controller/ControllerRecordable.cpp
|
||||
src/simulation/DRAMSysRecordable.cpp
|
||||
src/simulation/dram/DramRecordable.cpp
|
||||
)
|
||||
endif()
|
||||
include_directories(
|
||||
src/common
|
||||
src/common/third_party/DRAMPower/src
|
||||
src/configuration
|
||||
src/configuration/memspec
|
||||
src/controller
|
||||
src/controller/checker
|
||||
src/controller/cmdmux
|
||||
src/controller/powerdown
|
||||
src/controller/refresh
|
||||
src/controller/respqueue
|
||||
src/controller/scheduler
|
||||
src/error
|
||||
src/error/ECC
|
||||
src/simulation
|
||||
src/simulation/dram
|
||||
)
|
||||
|
||||
add_library(DRAMSysLibrary
|
||||
src/common/AddressDecoder.cpp
|
||||
src/common/DebugManager.cpp
|
||||
src/common/dramExtensions.cpp
|
||||
src/common/tlm2_base_protocol_checker.h
|
||||
src/common/TlmRecorder.cpp
|
||||
src/common/utils.cpp
|
||||
src/common/third_party/tinyxml2/tinyxml2.cpp
|
||||
|
||||
src/configuration/Configuration.cpp
|
||||
src/configuration/ConfigurationLoader.cpp
|
||||
src/configuration/TemperatureSimConfig.h
|
||||
|
||||
src/configuration/memspec/MemSpec.cpp
|
||||
@@ -98,6 +92,7 @@ add_library(DRAMSysLibrary
|
||||
src/controller/Command.cpp
|
||||
src/controller/ControllerIF.h
|
||||
src/controller/Controller.cpp
|
||||
src/controller/ControllerRecordable.cpp
|
||||
|
||||
src/controller/checker/CheckerIF.h
|
||||
src/controller/checker/CheckerDDR3.cpp
|
||||
@@ -142,10 +137,19 @@ add_library(DRAMSysLibrary
|
||||
|
||||
src/simulation/Arbiter.cpp
|
||||
src/simulation/DRAMSys.cpp
|
||||
src/simulation/ExampleInitiator.h
|
||||
src/simulation/MemoryManager.cpp
|
||||
src/simulation/ReorderBuffer.h
|
||||
src/simulation/Setup.cpp
|
||||
src/simulation/StlPlayer.h
|
||||
src/simulation/TemperatureController.cpp
|
||||
src/simulation/TraceGenerator.h
|
||||
src/simulation/TracePlayer.cpp
|
||||
src/simulation/TracePlayerListener.h
|
||||
src/simulation/TraceSetup.cpp
|
||||
|
||||
src/simulation/dram/Dram.cpp
|
||||
src/simulation/dram/DramRecordable.cpp
|
||||
src/simulation/dram/DramDDR3.cpp
|
||||
src/simulation/dram/DramDDR4.cpp
|
||||
src/simulation/dram/DramLPDDR4.cpp
|
||||
@@ -155,159 +159,16 @@ add_library(DRAMSysLibrary
|
||||
src/simulation/dram/DramGDDR5X.cpp
|
||||
src/simulation/dram/DramGDDR6.cpp
|
||||
src/simulation/dram/DramHBM2.cpp
|
||||
|
||||
${RECORDING_SOURCES}
|
||||
|
||||
|
||||
# Simulation Config Files
|
||||
resources/simulations/ddr3-boot-linux.json
|
||||
resources/simulations/ddr3-ecc.json
|
||||
resources/simulations/ddr3-example2.json
|
||||
resources/simulations/ddr3-example.json
|
||||
resources/simulations/ddr3-gem5-se.json
|
||||
resources/simulations/ddr3_postpone_ref_test.json
|
||||
resources/simulations/ddr3-single-device.json
|
||||
resources/simulations/ddr4-example.json
|
||||
resources/simulations/hbm2-example.json
|
||||
resources/simulations/lpddr4-example.json
|
||||
resources/simulations/ranktest.json
|
||||
resources/simulations/wideio-example.json
|
||||
|
||||
# Address Mapping Config Files
|
||||
resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.json
|
||||
resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json
|
||||
resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json
|
||||
resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json
|
||||
resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json
|
||||
resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json
|
||||
resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json
|
||||
resources/configs/amconfigs/am_ddr3_x16_brc.json
|
||||
resources/configs/amconfigs/am_ddr3_x16_rbc.json
|
||||
resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json
|
||||
resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json
|
||||
resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.json
|
||||
resources/configs/amconfigs/am_ranktest.json
|
||||
resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json
|
||||
resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json
|
||||
resources/configs/amconfigs/am_wideio_4x1Gb_brc.json
|
||||
resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json
|
||||
resources/configs/amconfigs/am_wideio_4x256Mb_brc.json
|
||||
resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json
|
||||
resources/configs/amconfigs/am_wideio_4x2Gb_brc.json
|
||||
resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json
|
||||
resources/configs/amconfigs/am_wideio_4x4Gb_brc.json
|
||||
resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json
|
||||
resources/configs/amconfigs/am_wideio_4x512Mb_brc.json
|
||||
resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json
|
||||
|
||||
# Memory Controller Config Files
|
||||
resources/configs/mcconfigs/fifo.json
|
||||
resources/configs/mcconfigs/fifoStrict.json
|
||||
resources/configs/mcconfigs/fr_fcfs_grp.json
|
||||
resources/configs/mcconfigs/fr_fcfs.json
|
||||
|
||||
# Memspec Config Files
|
||||
resources/configs/memspecs/HBM2.json
|
||||
resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json
|
||||
resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json
|
||||
resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json
|
||||
resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json
|
||||
resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json
|
||||
resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json
|
||||
resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json
|
||||
resources/configs/memspecs/memspec_ranktest.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json
|
||||
resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json
|
||||
resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json
|
||||
resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json
|
||||
resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json
|
||||
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json
|
||||
resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json
|
||||
resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json
|
||||
resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json
|
||||
resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json
|
||||
resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json
|
||||
resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json
|
||||
resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json
|
||||
resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json
|
||||
resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json
|
||||
resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json
|
||||
resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json
|
||||
resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json
|
||||
|
||||
# Simulator Config Files
|
||||
resources/configs/simulator/ddr3_boot_linux.json
|
||||
resources/configs/simulator/ddr3_ecc.json
|
||||
resources/configs/simulator/ddr3.json
|
||||
resources/configs/simulator/ddr3_gem5_se.json
|
||||
resources/configs/simulator/ddr3-single-device.json
|
||||
resources/configs/simulator/ddr4.json
|
||||
resources/configs/simulator/hbm2.json
|
||||
resources/configs/simulator/lpddr4.json
|
||||
resources/configs/simulator/wideio.json
|
||||
|
||||
# Thermal Simulation Config Files
|
||||
resources/configs/thermalsim/config.json
|
||||
|
||||
# Trace Files
|
||||
resources/traces/test_ecc.stl
|
||||
resources/traces/ddr3_example.stl
|
||||
resources/traces/ddr3_single_dev_example.stl
|
||||
resources/traces/ddr3_postpone_ref_test_1.stl
|
||||
resources/traces/ranktest.stl
|
||||
resources/traces/chstone-adpcm_32.stl
|
||||
)
|
||||
|
||||
if(DEFINED ENV{LIBTHREED_ICE_HOME} AND DEFINED ENV{LIBSUPERLU_HOME})
|
||||
message("-- 3D-ICE and SuperLU available")
|
||||
add_definitions(-DTHERMALSIM)
|
||||
target_include_directories(DRAMSysLibrary
|
||||
PRIVATE $ENV{LIBTHREED_ICE_HOME}/include/
|
||||
)
|
||||
find_library(3DICE_LIBRARY NAMES threed-ice-2.2.4 PATHS $ENV{LIBTHREED_ICE_HOME}/lib/)
|
||||
target_link_libraries(DRAMSysLibrary
|
||||
PRIVATE ${3DICE_LIBRARY}
|
||||
)
|
||||
endif()
|
||||
|
||||
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/simulation/DRAMSysRecordable.cpp)
|
||||
target_include_directories(DRAMSysLibrary
|
||||
PRIVATE src/common/third_party/sqlite-amalgamation/
|
||||
)
|
||||
target_link_libraries(DRAMSysLibrary
|
||||
PRIVATE sqlite3::sqlite3
|
||||
)
|
||||
endif()
|
||||
|
||||
# Build:
|
||||
target_include_directories(DRAMSysLibrary
|
||||
PUBLIC src/common/third_party/DRAMPower/src/
|
||||
PUBLIC $ENV{SYSTEMC_HOME}/include/
|
||||
PUBLIC $ENV{SYSTEMC_HOME}/include/tlm/
|
||||
PUBLIC src/common/third_party/DRAMPower/src
|
||||
PUBLIC src/common/third_party/sqlite-amalgamation/
|
||||
)
|
||||
target_link_libraries(DRAMSysLibrary
|
||||
SystemC::systemc
|
||||
sqlite3::sqlite3
|
||||
DRAMPower
|
||||
)
|
||||
|
||||
target_link_libraries(DRAMSysLibrary
|
||||
PUBLIC ${SYSTEMC_LIBRARY}
|
||||
PRIVATE DRAMPower
|
||||
)
|
||||
|
||||
6
DRAMSys/library/resources/configs/amconfigs/am_ddr3.xml
Executable file
6
DRAMSys/library/resources/configs/amconfigs/am_ddr3.xml
Executable file
@@ -0,0 +1,6 @@
|
||||
<addressmapping>
|
||||
<bank from="27" to="29" />
|
||||
<row from="13" to="26" />
|
||||
<column from="3" to="12" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
@@ -1,37 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
24,
|
||||
25,
|
||||
26
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9
|
||||
],
|
||||
"ROW_BIT": [
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,21 @@
|
||||
<!--
|
||||
DDR3-SDRAM 1Gbit x8 (single device, e.g. Micron MT41J128M8) with Page Size: 1KB
|
||||
|
||||
Addressing:
|
||||
|
||||
Row addressing: 16K (A[13:0]) -> 14 bits
|
||||
Bank addressing: 8 (BA[2:0]) -> 3 bits
|
||||
Column addressing: 1K (A[9:0] -> 10 bits
|
||||
|
||||
2 2 2 | 2 2 2 2 1 1 1 1 1 1 1 1 1 1 |
|
||||
6 5 4 | 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | 9 8 7 6 5 4 3 2 1 0 |
|
||||
B B B | R R R R R R R R R R R R R R | C C C C C C C C C C |
|
||||
|
||||
-->
|
||||
|
||||
<addressmapping>
|
||||
<bank from="24" to="26" />
|
||||
<row from="10" to="23" />
|
||||
<column from="0" to="9" />
|
||||
</addressmapping>
|
||||
|
||||
@@ -1,43 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
28,
|
||||
29,
|
||||
30
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12
|
||||
],
|
||||
"ROW_BIT": [
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,34 @@
|
||||
<!--
|
||||
DDR3L Unbuffered SODIMM Information:
|
||||
|
||||
Part Number: M471B5674QH0-YH9/K0
|
||||
Density: 2GB
|
||||
Organization: 256Mx64
|
||||
Component Composition: 256Mx16(K4B4G1646Q-HY##)*4
|
||||
Number of Rank: 1
|
||||
|
||||
Device mounted: K4B4G1646Q-HYK0
|
||||
Original fck is 800 MHz (DDR3-1600). Adapted to fck 533 MHz (DDR-1066).
|
||||
Deepak provided most of the timing and current values. For the ones not provided datasheet values were used.
|
||||
|
||||
|
||||
2GB x64 DIMM with: 4 * 4Gb x16 devices (K4B4G1646Q-HYK0) with Page Size: 2KB
|
||||
|
||||
DIMM Characteristics:
|
||||
Byte Offset (Y): 8 [0:2] (8-byte-wide memory module, i.e., 64-bit-wide data bus) -> 3 bit
|
||||
Cols (C): 1K [3:12] (A0 - A9) -> 10 bit
|
||||
Rows (R): 32K [13:27] (A0 - A14) -> 15 bit
|
||||
Bank (B): 8 [28:30] (BA0 - BA2) -> 3 bit
|
||||
|
||||
3 2 2 | 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
|
||||
0 9 8 | 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
|
||||
B B B | R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
|
||||
-->
|
||||
|
||||
<addressmapping>
|
||||
<bank from="28" to="30" />
|
||||
<row from="13" to="27" />
|
||||
<column from="3" to="12" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
|
||||
@@ -1,43 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
13,
|
||||
14,
|
||||
15
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12
|
||||
],
|
||||
"ROW_BIT": [
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
29,
|
||||
30
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,34 @@
|
||||
<!--
|
||||
DDR3L Unbuffered SODIMM Information:
|
||||
|
||||
Part Number: M471B5674QH0-YH9/K0
|
||||
Density: 2GB
|
||||
Organization: 256Mx64
|
||||
Component Composition: 256Mx16(K4B4G1646Q-HY##)*4
|
||||
Number of Rank: 1
|
||||
|
||||
Device mounted: K4B4G1646Q-HYK0
|
||||
Original fck is 800 MHz (DDR3-1600). Adapted to fck 533 MHz (DDR-1066).
|
||||
Deepak provided most of the timing and current values. For the ones not provided datasheet values were used.
|
||||
|
||||
|
||||
2GB x64 DIMM with: 4 * 4Gb x16 devices (K4B4G1646Q-HYK0) with Page Size: 2KB
|
||||
|
||||
DIMM Characteristics:
|
||||
Byte Offset (Y): 8 [0:2] (8-byte-wide memory module, i.e., 64-bit-wide data bus) -> 3 bit
|
||||
Cols (C): 1K [3:12] (A0 - A9) -> 10 bit
|
||||
Bank (B): 8 [13:15] (BA0 - BA2) -> 3 bit
|
||||
Rows (R): 32K [16:30] (A0 - A14) -> 15 bit
|
||||
|
||||
3 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1 | 1 1 1
|
||||
0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 | 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
|
||||
R R R R R R R R R R R R R R R | B B B | C C C C C C C C C C | Y Y Y
|
||||
-->
|
||||
|
||||
<addressmapping>
|
||||
<row from="16" to="30" />
|
||||
<bank from="13" to="15" />
|
||||
<column from="3" to="12" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
|
||||
@@ -1,42 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
27,
|
||||
28,
|
||||
29
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12
|
||||
],
|
||||
"ROW_BIT": [
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,24 @@
|
||||
<!--
|
||||
DDR3 Example:
|
||||
1GB x64 DIMM with: 8 * 1 Gb x8 Devices (e.g. Micron MT41J128M8) with Page Size: 1KB
|
||||
|
||||
Device Characteristics:
|
||||
|
||||
Rows: 16 K [13:0] -> 14 bit
|
||||
Bank: 8 [2:0] -> 3 bit
|
||||
Cols: 1 K [9:0] -> 10 bit
|
||||
|
||||
Due to the DIMM we have a Byte Offset Y
|
||||
|
||||
2 2 2 | 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
|
||||
9 8 7 | 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
|
||||
B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
|
||||
-->
|
||||
|
||||
<addressmapping>
|
||||
<bank from="27" to="29" />
|
||||
<row from="13" to="26" />
|
||||
<column from="3" to="12" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
|
||||
@@ -1,42 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
13,
|
||||
14,
|
||||
15
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12
|
||||
],
|
||||
"ROW_BIT": [
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
29
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,24 @@
|
||||
<!--
|
||||
DDR3 Example:
|
||||
1GB x64 DIMM with: 8 * 1 Gb x8 Devices (e.g. Micron MT41J128M8) with Page Size: 1KB
|
||||
|
||||
Device Characteristics:
|
||||
|
||||
Rows: 16 K [13:0] -> 14 bit
|
||||
Bank: 8 [2:0] -> 3 bit
|
||||
Cols: 1 K [9:0] -> 10 bit
|
||||
|
||||
Due to the DIMM we have a Byte Offset Y
|
||||
|
||||
2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1 | 1 1 1
|
||||
9 8 7 6 5 4 3 2 1 0 9 8 7 6 | 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
|
||||
R R R R R R R R R R R R R R | B B B | C C C C C C C C C C | Y Y Y
|
||||
-->
|
||||
|
||||
<addressmapping>
|
||||
<row from="16" to="29" />
|
||||
<bank from="13" to="15" />
|
||||
<column from="3" to="12" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
|
||||
@@ -1,43 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
28,
|
||||
29,
|
||||
30
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12
|
||||
],
|
||||
"ROW_BIT": [
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,24 @@
|
||||
<!--
|
||||
DDR3 Example:
|
||||
2GB x64 DIMM with: 8 * 2 Gb x8 Devices (e.g. Micron MT41J256M8) with Page Size: 1KB
|
||||
|
||||
Device Characteristics:
|
||||
|
||||
Rows: 32 K [14:0] -> 15 bit
|
||||
Bank: 8 [2:0] -> 3 bit
|
||||
Cols: 1 K [9:0] -> 10 bit
|
||||
|
||||
Due to the DIMM we have a Byte Offset Y
|
||||
|
||||
3 2 2 | 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
|
||||
0 9 8 | 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
|
||||
B B B | R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
|
||||
-->
|
||||
|
||||
<addressmapping>
|
||||
<bank from="28" to="30" />
|
||||
<row from="13" to="27" />
|
||||
<column from="3" to="12" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
|
||||
@@ -1,43 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
13,
|
||||
14,
|
||||
15
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12
|
||||
],
|
||||
"ROW_BIT": [
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
29,
|
||||
30
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,24 @@
|
||||
<!--
|
||||
DDR3 Example:
|
||||
2GB x64 DIMM with: 8 * 2 Gb x8 Devices (e.g. Micron MT41J256M8) with Page Size: 1KB
|
||||
|
||||
Device Characteristics:
|
||||
|
||||
Rows: 32 K [14:0] -> 15 bit
|
||||
Bank: 8 [2:0] -> 3 bit
|
||||
Cols: 1 K [9:0] -> 10 bit
|
||||
|
||||
Due to the DIMM we have a Byte Offset Y
|
||||
|
||||
3 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1 | 1 1 1
|
||||
0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 | 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
|
||||
R R R R R R R R R R R R R R R | B B B | C C C C C C C C C C | Y Y Y
|
||||
-->
|
||||
|
||||
<addressmapping>
|
||||
<row from="16" to="30" />
|
||||
<bank from="13" to="15" />
|
||||
<column from="3" to="12" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
|
||||
@@ -1,41 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
26,
|
||||
27,
|
||||
28
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12
|
||||
],
|
||||
"ROW_BIT": [
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<bank from="26" to="28" />
|
||||
<row from="13" to="25" />
|
||||
<column from="3" to="12" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
|
||||
@@ -1,41 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
13,
|
||||
14,
|
||||
15
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12
|
||||
],
|
||||
"ROW_BIT": [
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<row from="16" to="28" />
|
||||
<bank from="13" to="15" />
|
||||
<column from="3" to="12" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
|
||||
16
DRAMSys/library/resources/configs/amconfigs/am_ddr4.xml
Executable file
16
DRAMSys/library/resources/configs/amconfigs/am_ddr4.xml
Executable file
@@ -0,0 +1,16 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
|
||||
<!-- highest bank parallelism - high hits -->
|
||||
<dramconfig>
|
||||
<addressmap length="32">
|
||||
<row from="19" to="31" />
|
||||
<column from="9" to="18" />
|
||||
<bank from="5" to="8" />
|
||||
</addressmap>
|
||||
</dramconfig>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,46 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANKGROUP_BIT":[
|
||||
28,
|
||||
29
|
||||
],
|
||||
"BANK_BIT": [
|
||||
30,
|
||||
31
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12
|
||||
],
|
||||
"ROW_BIT": [
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<bankgroup from="30" to="31" />
|
||||
<bank from="28" to="29" />
|
||||
<row from="13" to="27" />
|
||||
<column from="3" to="12" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
@@ -1,46 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"RANK_BIT":[
|
||||
29
|
||||
],
|
||||
"BANKGROUP_BIT":[
|
||||
27,
|
||||
28
|
||||
],
|
||||
"BANK_BIT": [
|
||||
25,
|
||||
26
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9
|
||||
],
|
||||
"ROW_BIT": [
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,9 @@
|
||||
<addressmapping>
|
||||
<!--channel from="30" to="32" /-->
|
||||
<rank from="29" to="29" /> <!-- 2 pseudo channels -->
|
||||
<bankgroup from="27" to="28" />
|
||||
<bank from="25" to="26" />
|
||||
<row from="10" to="24" />
|
||||
<column from="3" to="9" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<!-- should have highest hit rate, since a (row, bank) bank pair changes infrequently -->
|
||||
<dramconfig>
|
||||
<addressmap length="32">
|
||||
<row from="19" to="31" />
|
||||
<bank from="15" to="18" />
|
||||
<column from="5" to="14" />
|
||||
</addressmap>
|
||||
</dramconfig>
|
||||
10
DRAMSys/library/resources/configs/amconfigs/am_highPara.xml
Executable file
10
DRAMSys/library/resources/configs/amconfigs/am_highPara.xml
Executable file
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<!-- should have high bank parallelism with good row hit rate, since bank bits have the
|
||||
highest entropy and row bits the lowest -->
|
||||
<dramconfig>
|
||||
<addressmap length="32">
|
||||
<row from="19" to="31" />
|
||||
<column from="9" to="18" />
|
||||
<bank from="5" to="8" />
|
||||
</addressmap>
|
||||
</dramconfig>
|
||||
10
DRAMSys/library/resources/configs/amconfigs/am_lowHits.xml
Executable file
10
DRAMSys/library/resources/configs/amconfigs/am_lowHits.xml
Executable file
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
|
||||
<!-- should have high bank parallelism with a low hit rate -->
|
||||
<dramconfig>
|
||||
<addressmap length="32">
|
||||
<column from="24" to="31" />
|
||||
<row from="9" to="23" />
|
||||
<bank from="5" to="8" />
|
||||
</addressmap>
|
||||
</dramconfig>
|
||||
12
DRAMSys/library/resources/configs/amconfigs/am_lowPara.xml
Executable file
12
DRAMSys/library/resources/configs/amconfigs/am_lowPara.xml
Executable file
@@ -0,0 +1,12 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
|
||||
<!-- should have low bank parallelism and a high hit rate -->
|
||||
<dramconfig>
|
||||
<addressmap length="32">
|
||||
<bank from="30" to="31" />
|
||||
<row from="15" to="29" />
|
||||
<column from="5" to="14" />
|
||||
</addressmap>
|
||||
</dramconfig>
|
||||
|
||||
|
||||
@@ -1,42 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
27,
|
||||
28,
|
||||
29
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10
|
||||
],
|
||||
"ROW_BIT": [
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,6 @@
|
||||
<addressmapping>
|
||||
<bank from="27" to="29" />
|
||||
<row from="11" to="26" />
|
||||
<column from="1" to="10" />
|
||||
<bytes from="0" to="0" />
|
||||
</addressmapping>
|
||||
@@ -0,0 +1,6 @@
|
||||
<addressmapping>
|
||||
<row from="14" to="29" />
|
||||
<bank from="11" to="13" />
|
||||
<column from="1" to="10" />
|
||||
<bytes from="0" to="0" />
|
||||
</addressmapping>
|
||||
@@ -1,46 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"RANK_BIT":[
|
||||
30,
|
||||
31
|
||||
],
|
||||
"BANK_BIT": [
|
||||
27,
|
||||
28,
|
||||
29
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12
|
||||
],
|
||||
"ROW_BIT": [
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26
|
||||
]
|
||||
}
|
||||
}
|
||||
25
DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml
Normal file
25
DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml
Normal file
@@ -0,0 +1,25 @@
|
||||
<!--
|
||||
DDR3 Example:
|
||||
1GB x64 DIMM with: 8 * 1 Gb x8 Devices (e.g. Micron MT41J128M8) with Page Size: 1KB
|
||||
|
||||
Device Characteristics:
|
||||
|
||||
Rows: 16 K [13:0] -> 14 bit
|
||||
Bank: 8 [2:0] -> 3 bit
|
||||
Cols: 1 K [9:0] -> 10 bit
|
||||
|
||||
Due to the DIMM we have a Byte Offset Y
|
||||
|
||||
2 2 2 | 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
|
||||
9 8 7 | 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
|
||||
B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
|
||||
-->
|
||||
|
||||
<addressmapping>
|
||||
<rank from="30" to="31" />
|
||||
<bank from="27" to="29" />
|
||||
<row from="13" to="26" />
|
||||
<column from="3" to="12" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
|
||||
22
DRAMSys/library/resources/configs/amconfigs/am_wideio.xml
Executable file
22
DRAMSys/library/resources/configs/amconfigs/am_wideio.xml
Executable file
@@ -0,0 +1,22 @@
|
||||
<!-- Row Bank Column -->
|
||||
|
||||
<addressmapping>
|
||||
<channel from="27" to="28" />
|
||||
<row from="14" to="26" />
|
||||
<bank from="11" to="13" />
|
||||
<column from="4" to="10" />
|
||||
<bytes from="0" to="3" />
|
||||
</addressmapping>
|
||||
|
||||
<!-- Bank Row Column -->
|
||||
|
||||
<!--
|
||||
<addressmapping>
|
||||
<channel from="27" to="28" />
|
||||
<bank from="24" to="26" />
|
||||
<row from="11" to="23" />
|
||||
<column from="4" to="10" />
|
||||
<bytes from="0" to="3" />
|
||||
</addressmapping>
|
||||
-->
|
||||
|
||||
@@ -1,44 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
25,
|
||||
26,
|
||||
27
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
"CHANNEL_BIT": [
|
||||
28,
|
||||
29
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11
|
||||
],
|
||||
"ROW_BIT": [
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
<!-- Bank Row Column -->
|
||||
|
||||
<addressmapping>
|
||||
<channel from="28" to="29" />
|
||||
<bank from="25" to="27" />
|
||||
<row from="12" to="24" />
|
||||
<column from="3" to="11" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
|
||||
<!-- Bank Row Column -->
|
||||
@@ -1,44 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
12,
|
||||
13,
|
||||
14
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
"CHANNEL_BIT": [
|
||||
28,
|
||||
29
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11
|
||||
],
|
||||
"ROW_BIT": [
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
<!-- Row Bank Column -->
|
||||
|
||||
<addressmapping>
|
||||
<channel from="28" to="29" />
|
||||
<row from="15" to="27" />
|
||||
<bank from="12" to="14" />
|
||||
<column from="3" to="11" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
|
||||
<!-- Bank Row Column -->
|
||||
27
DRAMSys/library/resources/configs/amconfigs/am_wideioFourBanks.xml
Executable file
27
DRAMSys/library/resources/configs/amconfigs/am_wideioFourBanks.xml
Executable file
@@ -0,0 +1,27 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<!--
|
||||
<dramconfig>
|
||||
<addressmap length="29">
|
||||
<channel from="27" to="28" />
|
||||
<bank from="24" to="26" />
|
||||
<row from="11" to="23" />
|
||||
<colum from="4" to="10" />
|
||||
<bytes from="0" to="3" />
|
||||
</addressmap>
|
||||
</dramconfig>
|
||||
-->
|
||||
<dramconfig>
|
||||
<addressmap length="29">
|
||||
<channel from="27" to="28" />
|
||||
<row from="13" to="26" />
|
||||
<bank from="11" to="12" />
|
||||
<column from="4" to="10" />
|
||||
<bytes from="0" to="3" />
|
||||
<!-- <channel from="27" to="28" />
|
||||
<row from="14" to="26" />
|
||||
<bytes from="10" to="13" />
|
||||
<colum from="3" to="9" />
|
||||
<bank from="0" to="2" /> -->
|
||||
|
||||
</addressmap>
|
||||
</dramconfig>
|
||||
@@ -1,43 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
25,
|
||||
26
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3
|
||||
],
|
||||
"CHANNEL_BIT": [
|
||||
27,
|
||||
28
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10
|
||||
],
|
||||
"ROW_BIT": [
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<channel from="27" to="28" />
|
||||
<bank from="25" to="26" />
|
||||
<row from="11" to="24" />
|
||||
<column from="4" to="10" />
|
||||
<bytes from="0" to="3" />
|
||||
</addressmapping>
|
||||
@@ -1,43 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
11,
|
||||
12
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3
|
||||
],
|
||||
"CHANNEL_BIT": [
|
||||
27,
|
||||
28
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10
|
||||
],
|
||||
"ROW_BIT": [
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<channel from="27" to="28" />
|
||||
<row from="13" to="26" />
|
||||
<bank from="11" to="12" />
|
||||
<column from="4" to="10" />
|
||||
<bytes from="0" to="3" />
|
||||
</addressmapping>
|
||||
@@ -1,41 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
23,
|
||||
24
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3
|
||||
],
|
||||
"CHANNEL_BIT": [
|
||||
25,
|
||||
26
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10
|
||||
],
|
||||
"ROW_BIT": [
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<channel from="25" to="26" />
|
||||
<bank from="23" to="24" />
|
||||
<row from="11" to="22" />
|
||||
<column from="4" to="10" />
|
||||
<bytes from="0" to="3" />
|
||||
</addressmapping>
|
||||
@@ -1,41 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
11,
|
||||
12
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3
|
||||
],
|
||||
"CHANNEL_BIT": [
|
||||
25,
|
||||
26
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10
|
||||
],
|
||||
"ROW_BIT": [
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<channel from="25" to="26" />
|
||||
<row from="13" to="24" />
|
||||
<bank from="11" to="12" />
|
||||
<column from="4" to="10" />
|
||||
<bytes from="0" to="3" />
|
||||
</addressmapping>
|
||||
@@ -1,44 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
26,
|
||||
27
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3
|
||||
],
|
||||
"CHANNEL_BIT": [
|
||||
28,
|
||||
29
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10
|
||||
],
|
||||
"ROW_BIT": [
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<channel from="28" to="29" />
|
||||
<bank from="26" to="27" />
|
||||
<row from="11" to="25" />
|
||||
<column from="4" to="10" />
|
||||
<bytes from="0" to="3" />
|
||||
</addressmapping>
|
||||
@@ -1,44 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
11,
|
||||
12
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3
|
||||
],
|
||||
"CHANNEL_BIT": [
|
||||
28,
|
||||
29
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10
|
||||
],
|
||||
"ROW_BIT": [
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<channel from="28" to="29" />
|
||||
<row from="13" to="27" />
|
||||
<bank from="11" to="12" />
|
||||
<column from="4" to="10" />
|
||||
<bytes from="0" to="3" />
|
||||
</addressmapping>
|
||||
@@ -1,45 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
27,
|
||||
28
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3
|
||||
],
|
||||
"CHANNEL_BIT": [
|
||||
29,
|
||||
30
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11
|
||||
],
|
||||
"ROW_BIT": [
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<channel from="29" to="30" />
|
||||
<bank from="27" to="28" />
|
||||
<row from="12" to="26" />
|
||||
<column from="4" to="11" />
|
||||
<bytes from="0" to="3" />
|
||||
</addressmapping>
|
||||
@@ -1,45 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
12,
|
||||
13
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3
|
||||
],
|
||||
"CHANNEL_BIT": [
|
||||
29,
|
||||
30
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11
|
||||
],
|
||||
"ROW_BIT": [
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<channel from="29" to="30" />
|
||||
<row from="14" to="28" />
|
||||
<bank from="12" to="13" />
|
||||
<column from="4" to="11" />
|
||||
<bytes from="0" to="3" />
|
||||
</addressmapping>
|
||||
@@ -1,42 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
24,
|
||||
25
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3
|
||||
],
|
||||
"CHANNEL_BIT": [
|
||||
26,
|
||||
27
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10
|
||||
],
|
||||
"ROW_BIT": [
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<channel from="26" to="27" />
|
||||
<bank from="24" to="25" />
|
||||
<row from="11" to="23" />
|
||||
<column from="4" to="10" />
|
||||
<bytes from="0" to="3" />
|
||||
</addressmapping>
|
||||
@@ -1,42 +0,0 @@
|
||||
{
|
||||
"CONGEN": {
|
||||
"BANK_BIT": [
|
||||
11,
|
||||
12
|
||||
],
|
||||
"BYTE_BIT": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3
|
||||
],
|
||||
"CHANNEL_BIT": [
|
||||
26,
|
||||
27
|
||||
],
|
||||
"COLUMN_BIT": [
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10
|
||||
],
|
||||
"ROW_BIT": [
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<channel from="26" to="27" />
|
||||
<row from="13" to="25" />
|
||||
<bank from="11" to="12" />
|
||||
<column from="4" to="10" />
|
||||
<bytes from="0" to="3" />
|
||||
</addressmapping>
|
||||
@@ -0,0 +1,36 @@
|
||||
<?xml version="1.0" ?>
|
||||
<CONGEN>
|
||||
<SOLUTION ID="0">
|
||||
<XOR FIRST="13" SECOND="16"/>
|
||||
<BYTE_BIT>0</BYTE_BIT>
|
||||
<BYTE_BIT>1</BYTE_BIT>
|
||||
<BYTE_BIT>2</BYTE_BIT>
|
||||
<COLUMN_BIT>3</COLUMN_BIT>
|
||||
<COLUMN_BIT>4</COLUMN_BIT>
|
||||
<COLUMN_BIT>5</COLUMN_BIT>
|
||||
<COLUMN_BIT>6</COLUMN_BIT>
|
||||
<COLUMN_BIT>7</COLUMN_BIT>
|
||||
<COLUMN_BIT>8</COLUMN_BIT>
|
||||
<COLUMN_BIT>9</COLUMN_BIT>
|
||||
<COLUMN_BIT>10</COLUMN_BIT>
|
||||
<COLUMN_BIT>11</COLUMN_BIT>
|
||||
<COLUMN_BIT>12</COLUMN_BIT>
|
||||
<BANK_BIT>13</BANK_BIT>
|
||||
<BANK_BIT>14</BANK_BIT>
|
||||
<BANK_BIT>15</BANK_BIT>
|
||||
<ROW_BIT>16</ROW_BIT>
|
||||
<ROW_BIT>17</ROW_BIT>
|
||||
<ROW_BIT>18</ROW_BIT>
|
||||
<ROW_BIT>19</ROW_BIT>
|
||||
<ROW_BIT>20</ROW_BIT>
|
||||
<ROW_BIT>21</ROW_BIT>
|
||||
<ROW_BIT>22</ROW_BIT>
|
||||
<ROW_BIT>23</ROW_BIT>
|
||||
<ROW_BIT>24</ROW_BIT>
|
||||
<ROW_BIT>25</ROW_BIT>
|
||||
<ROW_BIT>26</ROW_BIT>
|
||||
<ROW_BIT>27</ROW_BIT>
|
||||
<ROW_BIT>28</ROW_BIT>
|
||||
<ROW_BIT>29</ROW_BIT>
|
||||
</SOLUTION>
|
||||
</CONGEN>
|
||||
@@ -0,0 +1,19 @@
|
||||
<!--
|
||||
DIMM Characteristics:
|
||||
Bank (B): 8 [30:32] (BA0 - BA2) -> 3 bit
|
||||
Rows (R): 128K [13:29] (A0 - A16) -> 17 bit
|
||||
Cols (C): 1K [3:12] (A0 - A9) -> 10 bit
|
||||
Byte Offset (Y): 8 [0:2] (8-byte-wide memory module, i.e., 64-bit-wide data bus) -> 3 bit
|
||||
|
||||
3 3 3 | 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
|
||||
2 1 0 | 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
|
||||
B B B | R R R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
|
||||
-->
|
||||
|
||||
<addressmapping>
|
||||
<bank from="30" to="32" />
|
||||
<row from="13" to="29" />
|
||||
<column from="3" to="12" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
|
||||
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<row from="16" to="32" />
|
||||
<bank from="13" to="15" />
|
||||
<column from="3" to="12" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
|
||||
7
DRAMSys/library/resources/configs/amconfigs/rgram.xml
Normal file
7
DRAMSys/library/resources/configs/amconfigs/rgram.xml
Normal file
@@ -0,0 +1,7 @@
|
||||
<addressmapping>
|
||||
<bank from="30" to="32" />
|
||||
<row from="13" to="29" />
|
||||
<column from="3" to="12" />
|
||||
<bytes from="0" to="2" />
|
||||
</addressmapping>
|
||||
|
||||
@@ -1,15 +0,0 @@
|
||||
{
|
||||
"mcconfig": {
|
||||
"PagePolicy": "Open",
|
||||
"Scheduler": "Fifo",
|
||||
"RequestBufferSize": 8,
|
||||
"CmdMux": "Oldest",
|
||||
"RespQueue": "Fifo",
|
||||
"RefreshPolicy": "Rankwise",
|
||||
"RefreshMode": 1,
|
||||
"RefreshMaxPostponed": 8,
|
||||
"RefreshMaxPulledin": 8,
|
||||
"PowerDownPolicy": "NoPowerDown",
|
||||
"PowerDownTimeout": 100
|
||||
}
|
||||
}
|
||||
20
DRAMSys/library/resources/configs/mcconfigs/fifo.xml
Normal file
20
DRAMSys/library/resources/configs/mcconfigs/fifo.xml
Normal file
@@ -0,0 +1,20 @@
|
||||
<mcconfig>
|
||||
<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
|
||||
<PagePolicy value="Open" />
|
||||
<!-- Fifo, FrFcfs, FrFcfsGrp -->
|
||||
<Scheduler value="Fifo" />
|
||||
<RequestBufferSize value="8" />
|
||||
<!-- Oldest, Strict -->
|
||||
<CmdMux value="Strict" />
|
||||
<!-- Fifo, Reorder -->
|
||||
<RespQueue value="Fifo" />
|
||||
<!-- NoRefresh, Rankwise, Bankwise -->
|
||||
<RefreshPolicy value="Rankwise" />
|
||||
<!-- 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
|
||||
<RefreshMode value="1" />
|
||||
<RefreshMaxPostponed value="8"/>
|
||||
<RefreshMaxPulledin value="8"/>
|
||||
<!-- NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
|
||||
<PowerDownPolicy value="NoPowerDown" />
|
||||
<PowerDownTimeout value="100" />
|
||||
</mcconfig>
|
||||
@@ -1,15 +0,0 @@
|
||||
{
|
||||
"mcconfig": {
|
||||
"PagePolicy": "Open",
|
||||
"Scheduler": "Fifo",
|
||||
"RequestBufferSize": 8,
|
||||
"CmdMux": "Strict",
|
||||
"RespQueue": "Fifo",
|
||||
"RefreshPolicy": "Rankwise",
|
||||
"RefreshMode": 1,
|
||||
"RefreshMaxPostponed": 8,
|
||||
"RefreshMaxPulledin": 8,
|
||||
"PowerDownPolicy": "NoPowerDown",
|
||||
"PowerDownTimeout": 100
|
||||
}
|
||||
}
|
||||
@@ -1,15 +0,0 @@
|
||||
{
|
||||
"mcconfig": {
|
||||
"PagePolicy": "Open",
|
||||
"Scheduler": "FrFcfs",
|
||||
"RequestBufferSize": 8,
|
||||
"CmdMux": "Oldest",
|
||||
"RespQueue": "Fifo",
|
||||
"RefreshPolicy": "Rankwise",
|
||||
"RefreshMode": 1,
|
||||
"RefreshMaxPostponed": 8,
|
||||
"RefreshMaxPulledin": 8,
|
||||
"PowerDownPolicy": "NoPowerDown",
|
||||
"PowerDownTimeout": 100
|
||||
}
|
||||
}
|
||||
20
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml
Normal file
20
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml
Normal file
@@ -0,0 +1,20 @@
|
||||
<mcconfig>
|
||||
<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
|
||||
<PagePolicy value="Open" />
|
||||
<!-- Fifo, FrFcfs, FrFcfsGrp -->
|
||||
<Scheduler value="FrFcfs" />
|
||||
<RequestBufferSize value="8" />
|
||||
<!-- Oldest, Strict -->
|
||||
<CmdMux value="Oldest" />
|
||||
<!-- Fifo, Reorder -->
|
||||
<RespQueue value="Fifo" />
|
||||
<!-- NoRefresh, Rankwise, Bankwise -->
|
||||
<RefreshPolicy value="Rankwise" />
|
||||
<!-- 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
|
||||
<RefreshMode value="1" />
|
||||
<RefreshMaxPostponed value="8"/>
|
||||
<RefreshMaxPulledin value="8"/>
|
||||
<!-- NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
|
||||
<PowerDownPolicy value="NoPowerDown" />
|
||||
<PowerDownTimeout value="100" />
|
||||
</mcconfig>
|
||||
@@ -1,15 +0,0 @@
|
||||
{
|
||||
"mcconfig": {
|
||||
"PagePolicy": "Open",
|
||||
"Scheduler": "FrFcfsGrp",
|
||||
"RequestBufferSize": 8,
|
||||
"CmdMux": "Oldest",
|
||||
"RespQueue": "Fifo",
|
||||
"RefreshPolicy": "Rankwise",
|
||||
"RefreshMode": 1,
|
||||
"RefreshMaxPostponed": 8,
|
||||
"RefreshMaxPulledin": 8,
|
||||
"PowerDownPolicy": "NoPowerDown",
|
||||
"PowerDownTimeout": 100
|
||||
}
|
||||
}
|
||||
20
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml
Normal file
20
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml
Normal file
@@ -0,0 +1,20 @@
|
||||
<mcconfig>
|
||||
<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
|
||||
<PagePolicy value="Open" />
|
||||
<!-- Fifo, FrFcfs, FrFcfsGrp -->
|
||||
<Scheduler value="FrFcfsGrp" />
|
||||
<RequestBufferSize value="8" />
|
||||
<!-- Oldest, Strict -->
|
||||
<CmdMux value="Oldest" />
|
||||
<!-- Fifo, Reorder -->
|
||||
<RespQueue value="Fifo" />
|
||||
<!-- NoRefresh, Rankwise, Bankwise -->
|
||||
<RefreshPolicy value="Rankwise" />
|
||||
<!-- 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
|
||||
<RefreshMode value="1" />
|
||||
<RefreshMaxPostponed value="8"/>
|
||||
<RefreshMaxPulledin value="8"/>
|
||||
<!-- NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
|
||||
<PowerDownPolicy value="NoPowerDown" />
|
||||
<PowerDownTimeout value="100" />
|
||||
</mcconfig>
|
||||
61
DRAMSys/library/resources/configs/memspecs/DDR4.xml
Normal file
61
DRAMSys/library/resources/configs/memspecs/DDR4.xml
Normal file
@@ -0,0 +1,61 @@
|
||||
<!DOCTYPE memspec SYSTEM "memspec.dtd">
|
||||
<memspec>
|
||||
<parameter id="memoryId" type="string" value="MICRON_4Gb_DDR4-2400_8bit_A" />
|
||||
<parameter id="memoryType" type="string" value="DDR4" />
|
||||
<memarchitecturespec>
|
||||
<parameter id="width" type="uint" value="8" />
|
||||
<parameter id="nbrOfBankGroups" type="uint" value="4" />
|
||||
<parameter id="nbrOfBanks" type="uint" value="16" />
|
||||
<parameter id="nbrOfRanks" type="uint" value="1" />
|
||||
<parameter id="nbrOfColumns" type="uint" value="1024" />
|
||||
<parameter id="nbrOfRows" type="uint" value="32768" />
|
||||
<parameter id="dataRate" type="uint" value="2" />
|
||||
<parameter id="burstLength" type="uint" value="8" />
|
||||
</memarchitecturespec>
|
||||
<memtimingspec>
|
||||
<parameter id="clkMhz" type="double" value="1200" />
|
||||
<parameter id="REFI" type="uint" value="4680" />
|
||||
<parameter id="RFC" type="uint" value="313" />
|
||||
<parameter id="RL" type="uint" value="16" />
|
||||
<parameter id="WL" type="uint" value="16" />
|
||||
<parameter id="CL" type="uint" value="16" />
|
||||
<parameter id="AL" type="uint" value="0" />
|
||||
<parameter id="RP" type="uint" value="16" />
|
||||
<parameter id="RAS" type="uint" value="39" />
|
||||
<parameter id="RCD" type="uint" value="16" />
|
||||
<parameter id="RC" type="uint" value="55" />
|
||||
<parameter id="FAW" type="uint" value="26" />
|
||||
<parameter id="RTP" type="uint" value="12" />
|
||||
<parameter id="WR" type="uint" value="18" />
|
||||
<parameter id="RRD_S" type="uint" value="4" />
|
||||
<parameter id="RRD_L" type="uint" value="6" />
|
||||
<parameter id="CCD_S" type="uint" value="4" />
|
||||
<parameter id="CCD_L" type="uint" value="6" />
|
||||
<parameter id="WTR_S" type="uint" value="3" />
|
||||
<parameter id="WTR_L" type="uint" value="9" />
|
||||
<parameter id="DQSCK" type="uint" value="2" />
|
||||
<parameter id="XP" type="uint" value="8" />
|
||||
<parameter id="XPDLL" type="uint" value="325" />
|
||||
<parameter id="XS" type="uint" value="324" />
|
||||
<parameter id="XSDLL" type="uint" value="512" />
|
||||
<parameter id="CKE" type="uint" value="6" />
|
||||
<parameter id="CKESR" type="uint" value="7" />
|
||||
</memtimingspec>
|
||||
<mempowerspec>
|
||||
<parameter id="idd0" type="double" value="60.75" />
|
||||
<parameter id="idd02" type="double" value="4.05" />
|
||||
<parameter id="idd2p0" type="double" value="17.0" />
|
||||
<parameter id="idd2p1" type="double" value="17.0" />
|
||||
<parameter id="idd2n" type="double" value="38.25" />
|
||||
<parameter id="idd3p0" type="double" value="22.5" />
|
||||
<parameter id="idd3p1" type="double" value="22.5" />
|
||||
<parameter id="idd3n" type="double" value="44.0" />
|
||||
<parameter id="idd4r" type="double" value="184.5" />
|
||||
<parameter id="idd4w" type="double" value="168.75" />
|
||||
<parameter id="idd5" type="double" value="118.0" />
|
||||
<parameter id="idd6" type="double" value="20.25" />
|
||||
<parameter id="idd62" type="double" value="2.6" />
|
||||
<parameter id="vdd" type="double" value="1.2" />
|
||||
<parameter id="vdd2" type="double" value="2.5" />
|
||||
</mempowerspec>
|
||||
</memspec>
|
||||
@@ -1,46 +0,0 @@
|
||||
{
|
||||
"memspec": {
|
||||
"memarchitecturespec": {
|
||||
"burstLength": 4,
|
||||
"dataRate": 2,
|
||||
"nbrOfBankGroups": 4,
|
||||
"nbrOfBanks": 16,
|
||||
"nbrOfColumns": 128,
|
||||
"nbrOfRanks": 2,
|
||||
"nbrOfRows": 32768,
|
||||
"width": 64
|
||||
},
|
||||
"memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder",
|
||||
"memoryType": "HBM2",
|
||||
"memtimingspec": {
|
||||
"CCDL": 3,
|
||||
"CCDS": 2,
|
||||
"CKE": 8,
|
||||
"DQSCK": 1,
|
||||
"FAW": 16,
|
||||
"PL": 0,
|
||||
"RAS": 28,
|
||||
"RC": 42,
|
||||
"RCDRD": 12,
|
||||
"RCDWR": 6,
|
||||
"REFI": 3900,
|
||||
"REFISB": 244,
|
||||
"RFC": 220,
|
||||
"RFCSB": 96,
|
||||
"RL": 17,
|
||||
"RP": 14,
|
||||
"RRDL": 6,
|
||||
"RRDS": 4,
|
||||
"RREFD": 8,
|
||||
"RTP": 5,
|
||||
"RTW": 18,
|
||||
"WL": 7,
|
||||
"WR": 14,
|
||||
"WTRL": 9,
|
||||
"WTRS": 4,
|
||||
"XP": 8,
|
||||
"XS": 216,
|
||||
"clkMhz": 1000
|
||||
}
|
||||
}
|
||||
}
|
||||
49
DRAMSys/library/resources/configs/memspecs/HBM2.xml
Normal file
49
DRAMSys/library/resources/configs/memspecs/HBM2.xml
Normal file
@@ -0,0 +1,49 @@
|
||||
<!DOCTYPE memspec SYSTEM "memspec.dtd">
|
||||
<!--8GiB, 8 channels, 1GiB per channel-->
|
||||
<memspec>
|
||||
<parameter id="memoryId" type="string" value="https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder" />
|
||||
<parameter id="memoryType" type="string" value="HBM2" />
|
||||
<memarchitecturespec>
|
||||
<parameter id="width" type="uint" value="64" />
|
||||
<parameter id="nbrOfBanks" type="uint" value="16" />
|
||||
<parameter id="nbrOfBankGroups" type="uint" value="4" />
|
||||
<parameter id="nbrOfRanks" type="uint" value="2" />
|
||||
<parameter id="nbrOfColumns" type="uint" value="128" />
|
||||
<parameter id="nbrOfRows" type="uint" value="32768" />
|
||||
<parameter id="dataRate" type="uint" value="2" />
|
||||
<parameter id="burstLength" type="uint" value="4" />
|
||||
</memarchitecturespec>
|
||||
<memtimingspec>
|
||||
<parameter id="clkMhz" type="double" value="1000" />
|
||||
<parameter id="DQSCK" type="uint" value="1" />
|
||||
<parameter id="RC" type="uint" value="42" />
|
||||
<parameter id="RAS" type="uint" value="28" />
|
||||
<parameter id="RCDRD" type="uint" value="12" />
|
||||
<parameter id="RCDWR" type="uint" value="6" />
|
||||
<parameter id="RRDL" type="uint" value="6" />
|
||||
<parameter id="RRDS" type="uint" value="4" />
|
||||
<parameter id="FAW" type="uint" value="16" />
|
||||
<parameter id="RTP" type="uint" value="5" />
|
||||
<parameter id="RP" type="uint" value="14" />
|
||||
<parameter id="RL" type="uint" value="17" />
|
||||
<parameter id="WL" type="uint" value="7" />
|
||||
<parameter id="PL" type="uint" value="0" />
|
||||
<parameter id="WR" type="uint" value="14" />
|
||||
<parameter id="CCDL" type="uint" value="3" />
|
||||
<parameter id="CCDS" type="uint" value="2" />
|
||||
<parameter id="WTRL" type="uint" value="9" />
|
||||
<parameter id="WTRS" type="uint" value="4" />
|
||||
<parameter id="RTW" type="uint" value="18" />
|
||||
<parameter id="XP" type="uint" value="8" />
|
||||
<parameter id="CKE" type="uint" value="8" />
|
||||
<parameter id="XS" type="uint" value="216" />
|
||||
<parameter id="RFC" type="uint" value="220" />
|
||||
<parameter id="RFCSB" type="uint" value="96" />
|
||||
<parameter id="RREFD" type="uint" value="8" />
|
||||
<parameter id="REFI" type="uint" value="3900" />
|
||||
<parameter id="REFISB" type="uint" value="244" />
|
||||
</memtimingspec>
|
||||
<mempowerspec>
|
||||
<!-- to be completed -->
|
||||
</mempowerspec>
|
||||
</memspec>
|
||||
@@ -1,65 +0,0 @@
|
||||
{
|
||||
"memspec": {
|
||||
"memarchitecturespec": {
|
||||
"burstLength": 4,
|
||||
"dataRate": 1,
|
||||
"nbrOfBanks": 4,
|
||||
"nbrOfColumns": 128,
|
||||
"nbrOfRanks": 1,
|
||||
"nbrOfRows": 4096,
|
||||
"width": 128
|
||||
},
|
||||
"memoryId": "JEDEC_256Mb_WIDEIO_SDR-200_128bit",
|
||||
"memoryType": "WIDEIO_SDR",
|
||||
"mempowerspec": {
|
||||
"idd0": 5.88,
|
||||
"idd02": 21.18,
|
||||
"idd2n": 0.13,
|
||||
"idd2n2": 4.04,
|
||||
"idd2p0": 0.05,
|
||||
"idd2p02": 0.17,
|
||||
"idd2p1": 0.05,
|
||||
"idd2p12": 0.17,
|
||||
"idd3n": 0.52,
|
||||
"idd3n2": 6.55,
|
||||
"idd3p0": 0.25,
|
||||
"idd3p02": 1.49,
|
||||
"idd3p1": 0.25,
|
||||
"idd3p12": 1.49,
|
||||
"idd4r": 1.41,
|
||||
"idd4r2": 85.73,
|
||||
"idd4w": 1.42,
|
||||
"idd4w2": 60.79,
|
||||
"idd5": 14.43,
|
||||
"idd52": 48.17,
|
||||
"idd6": 0.07,
|
||||
"idd62": 0.27,
|
||||
"vdd": 1.8,
|
||||
"vdd2": 1.2
|
||||
},
|
||||
"memtimingspec": {
|
||||
"AC": 1,
|
||||
"CCD_R": 2,
|
||||
"CCD_W": 1,
|
||||
"CKE": 3,
|
||||
"CKESR": 3,
|
||||
"DQSCK": 1,
|
||||
"RAS": 9,
|
||||
"RC": 12,
|
||||
"RCD": 4,
|
||||
"REFI": 3120,
|
||||
"RFC": 18,
|
||||
"RL": 3,
|
||||
"RP": 4,
|
||||
"RRD": 2,
|
||||
"TAW": 10,
|
||||
"WL": 1,
|
||||
"WR": 3,
|
||||
"WTR": 3,
|
||||
"XP": 2,
|
||||
"XSR": 20,
|
||||
"RTRS": 1,
|
||||
"clkMhz": 200
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,64 @@
|
||||
<!DOCTYPE memspec SYSTEM "memspec.dtd">
|
||||
<!--BL 2/4, REFM 1/0.5/0.25-->
|
||||
<memspec>
|
||||
<parameter id="memoryId" type="string" value="JEDEC_256Mb_WIDEIO_SDR-200_128bit" />
|
||||
<parameter id="memoryType" type="string" value="WIDEIO_SDR" />
|
||||
<memarchitecturespec>
|
||||
<parameter id="width" type="uint" value="128" />
|
||||
<parameter id="nbrOfBanks" type="uint" value="4" />
|
||||
<parameter id="nbrOfRanks" type="uint" value="1" />
|
||||
<parameter id="nbrOfColumns" type="uint" value="128" />
|
||||
<parameter id="nbrOfRows" type="uint" value="4096" />
|
||||
<parameter id="dataRate" type="uint" value="1" />
|
||||
<parameter id="burstLength" type="uint" value="4" />
|
||||
</memarchitecturespec>
|
||||
<memtimingspec>
|
||||
<parameter id="clkMhz" type="double" value="200" />
|
||||
<parameter id="RC" type="uint" value="12" />
|
||||
<parameter id="RCD" type="uint" value="4" />
|
||||
<parameter id="RL" type="uint" value="3" />
|
||||
<parameter id="RP" type="uint" value="4" />
|
||||
<parameter id="RFC" type="uint" value="18" />
|
||||
<parameter id="RAS" type="uint" value="9" />
|
||||
<parameter id="WL" type="uint" value="1" />
|
||||
<parameter id="DQSCK" type="uint" value="1" />
|
||||
<parameter id="AC" type="uint" value="1" />
|
||||
<parameter id="WR" type="uint" value="3" />
|
||||
<parameter id="XP" type="uint" value="2" />
|
||||
<parameter id="XS" type="uint" value="20" />
|
||||
<parameter id="REFI" type="uint" value="3120" />
|
||||
<parameter id="TAW" type="uint" value="10" />
|
||||
<parameter id="RRD" type="uint" value="2" />
|
||||
<parameter id="CCD_R" type="uint" value="2" />
|
||||
<parameter id="CCD_W" type="uint" value="1" />
|
||||
<parameter id="WTR" type="uint" value="3" />
|
||||
<parameter id="CKE" type="uint" value="3" />
|
||||
<parameter id="CKESR" type="uint" value="3" />
|
||||
</memtimingspec>
|
||||
<mempowerspec>
|
||||
<parameter id="idd0" type="double" value="5.88" />
|
||||
<parameter id="idd02" type="double" value="21.18" />
|
||||
<parameter id="idd2p0" type="double" value="0.05" />
|
||||
<parameter id="idd2p02" type="double" value="0.17" />
|
||||
<parameter id="idd2p1" type="double" value="0.05" />
|
||||
<parameter id="idd2p12" type="double" value="0.17" />
|
||||
<parameter id="idd2n" type="double" value="0.13" />
|
||||
<parameter id="idd2n2" type="double" value="4.04" />
|
||||
<parameter id="idd3p0" type="double" value="0.25" />
|
||||
<parameter id="idd3p02" type="double" value="1.49" />
|
||||
<parameter id="idd3p1" type="double" value="0.25" />
|
||||
<parameter id="idd3p12" type="double" value="1.49" />
|
||||
<parameter id="idd3n" type="double" value="0.52" />
|
||||
<parameter id="idd3n2" type="double" value="6.55" />
|
||||
<parameter id="idd4r" type="double" value="1.41" />
|
||||
<parameter id="idd4r2" type="double" value="85.73" />
|
||||
<parameter id="idd4w" type="double" value="1.42" />
|
||||
<parameter id="idd4w2" type="double" value="60.79" />
|
||||
<parameter id="idd5" type="double" value="14.43" />
|
||||
<parameter id="idd52" type="double" value="48.17" />
|
||||
<parameter id="idd6" type="double" value="0.07" />
|
||||
<parameter id="idd62" type="double" value="0.27" />
|
||||
<parameter id="vdd" type="double" value="1.8" />
|
||||
<parameter id="vdd2" type="double" value="1.2" />
|
||||
</mempowerspec>
|
||||
</memspec>
|
||||
@@ -1,65 +0,0 @@
|
||||
{
|
||||
"memspec": {
|
||||
"memarchitecturespec": {
|
||||
"burstLength": 4,
|
||||
"dataRate": 1,
|
||||
"nbrOfBanks": 4,
|
||||
"nbrOfColumns": 128,
|
||||
"nbrOfRanks": 1,
|
||||
"nbrOfRows": 4096,
|
||||
"width": 128
|
||||
},
|
||||
"memoryId": "JEDEC_256Mb_WIDEIO_SDR-266_128bit",
|
||||
"memoryType": "WIDEIO_SDR",
|
||||
"mempowerspec": {
|
||||
"idd0": 6.06,
|
||||
"idd02": 21.82,
|
||||
"idd2n": 0.16,
|
||||
"idd2n2": 4.76,
|
||||
"idd2p0": 0.05,
|
||||
"idd2p02": 0.17,
|
||||
"idd2p1": 0.05,
|
||||
"idd2p12": 0.17,
|
||||
"idd3n": 0.58,
|
||||
"idd3n2": 7.24,
|
||||
"idd3p0": 0.25,
|
||||
"idd3p02": 1.49,
|
||||
"idd3p1": 0.25,
|
||||
"idd3p12": 1.49,
|
||||
"idd4r": 1.82,
|
||||
"idd4r2": 111.22,
|
||||
"idd4w": 1.82,
|
||||
"idd4w2": 78.0,
|
||||
"idd5": 14.48,
|
||||
"idd52": 48.34,
|
||||
"idd6": 0.07,
|
||||
"idd62": 0.27,
|
||||
"vdd": 1.8,
|
||||
"vdd2": 1.2
|
||||
},
|
||||
"memtimingspec": {
|
||||
"AC": 1,
|
||||
"CCD_R": 2,
|
||||
"CCD_W": 1,
|
||||
"CKE": 3,
|
||||
"CKESR": 4,
|
||||
"DQSCK": 1,
|
||||
"RAS": 12,
|
||||
"RC": 16,
|
||||
"RCD": 5,
|
||||
"REFI": 4160,
|
||||
"RFC": 24,
|
||||
"RL": 3,
|
||||
"RP": 5,
|
||||
"RRD": 3,
|
||||
"TAW": 14,
|
||||
"WL": 1,
|
||||
"WR": 4,
|
||||
"WTR": 4,
|
||||
"XP": 3,
|
||||
"XSR": 27,
|
||||
"RTRS": 1,
|
||||
"clkMhz": 266
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,64 @@
|
||||
<!DOCTYPE memspec SYSTEM "memspec.dtd">
|
||||
<!--BL 2/4, REFM 1/0.5/0.25-->
|
||||
<memspec>
|
||||
<parameter id="memoryId" type="string" value="JEDEC_256Mb_WIDEIO_SDR-266_128bit" />
|
||||
<parameter id="memoryType" type="string" value="WIDEIO_SDR" />
|
||||
<memarchitecturespec>
|
||||
<parameter id="width" type="uint" value="128" />
|
||||
<parameter id="nbrOfBanks" type="uint" value="4" />
|
||||
<parameter id="nbrOfRanks" type="uint" value="1" />
|
||||
<parameter id="nbrOfColumns" type="uint" value="128" />
|
||||
<parameter id="nbrOfRows" type="uint" value="4096" />
|
||||
<parameter id="dataRate" type="uint" value="1" />
|
||||
<parameter id="burstLength" type="uint" value="4" />
|
||||
</memarchitecturespec>
|
||||
<memtimingspec>
|
||||
<parameter id="clkMhz" type="double" value="266" />
|
||||
<parameter id="RC" type="uint" value="16" />
|
||||
<parameter id="RCD" type="uint" value="5" />
|
||||
<parameter id="RL" type="uint" value="3" />
|
||||
<parameter id="RP" type="uint" value="5" />
|
||||
<parameter id="RFC" type="uint" value="24" />
|
||||
<parameter id="RAS" type="uint" value="12" />
|
||||
<parameter id="WL" type="uint" value="1" />
|
||||
<parameter id="DQSCK" type="uint" value="1" />
|
||||
<parameter id="AC" type="uint" value="1" />
|
||||
<parameter id="WR" type="uint" value="4" />
|
||||
<parameter id="XP" type="uint" value="3" />
|
||||
<parameter id="XS" type="uint" value="27" />
|
||||
<parameter id="REFI" type="uint" value="4160" />
|
||||
<parameter id="TAW" type="uint" value="14" />
|
||||
<parameter id="RRD" type="uint" value="3" />
|
||||
<parameter id="CCD_R" type="uint" value="2" />
|
||||
<parameter id="CCD_W" type="uint" value="1" />
|
||||
<parameter id="WTR" type="uint" value="4" />
|
||||
<parameter id="CKE" type="uint" value="3" />
|
||||
<parameter id="CKESR" type="uint" value="4" />
|
||||
</memtimingspec>
|
||||
<mempowerspec>
|
||||
<parameter id="idd0" type="double" value="6.06" />
|
||||
<parameter id="idd02" type="double" value="21.82" />
|
||||
<parameter id="idd2p0" type="double" value="0.05" />
|
||||
<parameter id="idd2p02" type="double" value="0.17" />
|
||||
<parameter id="idd2p1" type="double" value="0.05" />
|
||||
<parameter id="idd2p12" type="double" value="0.17" />
|
||||
<parameter id="idd2n" type="double" value="0.16" />
|
||||
<parameter id="idd2n2" type="double" value="4.76" />
|
||||
<parameter id="idd3p0" type="double" value="0.25" />
|
||||
<parameter id="idd3p02" type="double" value="1.49" />
|
||||
<parameter id="idd3p1" type="double" value="0.25" />
|
||||
<parameter id="idd3p12" type="double" value="1.49" />
|
||||
<parameter id="idd3n" type="double" value="0.58" />
|
||||
<parameter id="idd3n2" type="double" value="7.24" />
|
||||
<parameter id="idd4r" type="double" value="1.82" />
|
||||
<parameter id="idd4r2" type="double" value="111.22" />
|
||||
<parameter id="idd4w" type="double" value="1.82" />
|
||||
<parameter id="idd4w2" type="double" value="78.0" />
|
||||
<parameter id="idd5" type="double" value="14.48" />
|
||||
<parameter id="idd52" type="double" value="48.34" />
|
||||
<parameter id="idd6" type="double" value="0.07" />
|
||||
<parameter id="idd62" type="double" value="0.27" />
|
||||
<parameter id="vdd" type="double" value="1.8" />
|
||||
<parameter id="vdd2" type="double" value="1.2" />
|
||||
</mempowerspec>
|
||||
</memspec>
|
||||
@@ -0,0 +1 @@
|
||||
../../../src/common/third_party/DRAMPower/memspecs/JEDEC_256Mb_WIDEIO_SDR-200_128bit.xml
|
||||
@@ -0,0 +1 @@
|
||||
../../../src/common/third_party/DRAMPower/memspecs/JEDEC_256Mb_WIDEIO_SDR-266_128bit.xml
|
||||
@@ -1,68 +0,0 @@
|
||||
{
|
||||
"memspec": {
|
||||
"memarchitecturespec": {
|
||||
"burstLength": 8,
|
||||
"dataRate": 2,
|
||||
"nbrOfBankGroups": 4,
|
||||
"nbrOfBanks": 16,
|
||||
"nbrOfColumns": 1024,
|
||||
"nbrOfRanks": 1,
|
||||
"nbrOfRows": 32768,
|
||||
"width": 8
|
||||
},
|
||||
"memoryId": "MICRON_4Gb_DDR4-1866_8bit_A",
|
||||
"memoryType": "DDR4",
|
||||
"mempowerspec": {
|
||||
"idd0": 56.25,
|
||||
"idd02": 4.05,
|
||||
"idd2n": 33.75,
|
||||
"idd2p0": 17.0,
|
||||
"idd2p1": 17.0,
|
||||
"idd3n": 39.5,
|
||||
"idd3p0": 22.5,
|
||||
"idd3p1": 22.5,
|
||||
"idd4r": 157.5,
|
||||
"idd4w": 135.0,
|
||||
"idd5": 118.0,
|
||||
"idd6": 20.25,
|
||||
"idd62": 2.6,
|
||||
"vdd": 1.2,
|
||||
"vdd2": 2.5
|
||||
},
|
||||
"memtimingspec": {
|
||||
"AL": 0,
|
||||
"CCD_L": 5,
|
||||
"CCD_S": 4,
|
||||
"CKE": 6,
|
||||
"CKESR": 7,
|
||||
"CL": 13,
|
||||
"DQSCK": 2,
|
||||
"FAW": 22,
|
||||
"RAS": 32,
|
||||
"RC": 45,
|
||||
"RCD": 13,
|
||||
"REFI": 7280,
|
||||
"RFC": 243,
|
||||
"RFC2": 150,
|
||||
"RFC4": 103,
|
||||
"RL": 13,
|
||||
"RP": 13,
|
||||
"RRD_L": 5,
|
||||
"RRD_S": 4,
|
||||
"RTP": 8,
|
||||
"WL": 12,
|
||||
"WR": 14,
|
||||
"WTR_L": 7,
|
||||
"WTR_S": 3,
|
||||
"XP": 8,
|
||||
"XPDLL": 255,
|
||||
"XS": 252,
|
||||
"XSDLL": 512,
|
||||
"ACTPDEN": 1,
|
||||
"PRPDEN": 1,
|
||||
"REFPDEN": 1,
|
||||
"RTRS": 1,
|
||||
"clkMhz": 933
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,64 @@
|
||||
<!DOCTYPE memspec SYSTEM "memspec.dtd">
|
||||
<memspec>
|
||||
|
||||
<parameter id="memoryId" type="string" value="MICRON_4Gb_DDR4-1866_8bit_A" />
|
||||
<parameter id="memoryType" type="string" value="DDR4" />
|
||||
<memarchitecturespec>
|
||||
<parameter id="width" type="uint" value="8" />
|
||||
<parameter id="nbrOfBankGroups" type="uint" value="4" />
|
||||
<parameter id="nbrOfBanks" type="uint" value="16" />
|
||||
<parameter id="nbrOfRanks" type="uint" value="1" />
|
||||
<parameter id="nbrOfColumns" type="uint" value="1024" />
|
||||
<parameter id="nbrOfRows" type="uint" value="32768" />
|
||||
<parameter id="dataRate" type="uint" value="2" />
|
||||
<parameter id="burstLength" type="uint" value="8" />
|
||||
</memarchitecturespec>
|
||||
<memtimingspec>
|
||||
<parameter id="clkMhz" type="double" value="933" />
|
||||
<parameter id="REFI" type="uint" value="7280" />
|
||||
<parameter id="RFC" type="uint" value="243" />
|
||||
<parameter id="RFC2" type="uint" value="150" />
|
||||
<parameter id="RFC4" type="uint" value="103" />
|
||||
<parameter id="RL" type="uint" value="13" />
|
||||
<parameter id="WL" type="uint" value="12" />
|
||||
<parameter id="CL" type="uint" value="13" />
|
||||
<parameter id="AL" type="uint" value="0" />
|
||||
<parameter id="RP" type="uint" value="13" />
|
||||
<parameter id="RAS" type="uint" value="32" />
|
||||
<parameter id="RCD" type="uint" value="13" />
|
||||
<parameter id="RC" type="uint" value="45" />
|
||||
<parameter id="FAW" type="uint" value="22" />
|
||||
<parameter id="RTP" type="uint" value="8" />
|
||||
<parameter id="WR" type="uint" value="14" />
|
||||
<parameter id="RRD_S" type="uint" value="4" />
|
||||
<parameter id="RRD_L" type="uint" value="5" />
|
||||
<parameter id="CCD_S" type="uint" value="4" />
|
||||
<parameter id="CCD_L" type="uint" value="5" />
|
||||
<parameter id="WTR_S" type="uint" value="3" />
|
||||
<parameter id="WTR_L" type="uint" value="7" />
|
||||
<parameter id="DQSCK" type="uint" value="2" />
|
||||
<parameter id="XP" type="uint" value="8" />
|
||||
<parameter id="XPDLL" type="uint" value="255" />
|
||||
<parameter id="XS" type="uint" value="252" />
|
||||
<parameter id="XSDLL" type="uint" value="512" />
|
||||
<parameter id="CKE" type="uint" value="6" />
|
||||
<parameter id="CKESR" type="uint" value="7" />
|
||||
</memtimingspec>
|
||||
<mempowerspec>
|
||||
<parameter id="idd0" type="double" value="56.25" />
|
||||
<parameter id="idd02" type="double" value="4.05" />
|
||||
<parameter id="idd2p0" type="double" value="17.0" />
|
||||
<parameter id="idd2p1" type="double" value="17.0" />
|
||||
<parameter id="idd2n" type="double" value="33.75" />
|
||||
<parameter id="idd3p0" type="double" value="22.5" />
|
||||
<parameter id="idd3p1" type="double" value="22.5" />
|
||||
<parameter id="idd3n" type="double" value="39.5" />
|
||||
<parameter id="idd4r" type="double" value="157.5" />
|
||||
<parameter id="idd4w" type="double" value="135.0" />
|
||||
<parameter id="idd5" type="double" value="118.0" />
|
||||
<parameter id="idd6" type="double" value="20.25" />
|
||||
<parameter id="idd62" type="double" value="2.6" />
|
||||
<parameter id="vdd" type="double" value="1.2" />
|
||||
<parameter id="vdd2" type="double" value="2.5" />
|
||||
</mempowerspec>
|
||||
</memspec>
|
||||
@@ -1,68 +0,0 @@
|
||||
{
|
||||
"memspec": {
|
||||
"memarchitecturespec": {
|
||||
"burstLength": 8,
|
||||
"dataRate": 2,
|
||||
"nbrOfBankGroups": 4,
|
||||
"nbrOfBanks": 16,
|
||||
"nbrOfColumns": 1024,
|
||||
"nbrOfRanks": 1,
|
||||
"nbrOfRows": 32768,
|
||||
"width": 8
|
||||
},
|
||||
"memoryId": "MICRON_4Gb_DDR4-2400_8bit_A",
|
||||
"memoryType": "DDR4",
|
||||
"mempowerspec": {
|
||||
"idd0": 60.75,
|
||||
"idd02": 4.05,
|
||||
"idd2n": 38.25,
|
||||
"idd2p0": 17.0,
|
||||
"idd2p1": 17.0,
|
||||
"idd3n": 44.0,
|
||||
"idd3p0": 22.5,
|
||||
"idd3p1": 22.5,
|
||||
"idd4r": 184.5,
|
||||
"idd4w": 168.75,
|
||||
"idd5": 118.0,
|
||||
"idd6": 20.25,
|
||||
"idd62": 2.6,
|
||||
"vdd": 1.2,
|
||||
"vdd2": 2.5
|
||||
},
|
||||
"memtimingspec": {
|
||||
"AL": 0,
|
||||
"CCD_L": 6,
|
||||
"CCD_S": 4,
|
||||
"CKE": 6,
|
||||
"CKESR": 7,
|
||||
"CL": 16,
|
||||
"DQSCK": 2,
|
||||
"FAW": 26,
|
||||
"RAS": 39,
|
||||
"RC": 55,
|
||||
"RCD": 16,
|
||||
"REFI": 9360,
|
||||
"RFC": 312,
|
||||
"RFC2": 192,
|
||||
"RFC4": 132,
|
||||
"RL": 16,
|
||||
"RP": 16,
|
||||
"RRD_L": 6,
|
||||
"RRD_S": 4,
|
||||
"RTP": 12,
|
||||
"WL": 16,
|
||||
"WR": 18,
|
||||
"WTR_L": 9,
|
||||
"WTR_S": 3,
|
||||
"XP": 8,
|
||||
"XPDLL": 325,
|
||||
"XS": 324,
|
||||
"XSDLL": 512,
|
||||
"ACTPDEN": 2,
|
||||
"PRPDEN": 2,
|
||||
"REFPDEN": 2,
|
||||
"RTRS": 1,
|
||||
"clkMhz": 1200
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,64 @@
|
||||
<!DOCTYPE memspec SYSTEM "memspec.dtd">
|
||||
<memspec>
|
||||
|
||||
<parameter id="memoryId" type="string" value="MICRON_4Gb_DDR4-2400_8bit_A" />
|
||||
<parameter id="memoryType" type="string" value="DDR4" />
|
||||
<memarchitecturespec>
|
||||
<parameter id="width" type="uint" value="8" />
|
||||
<parameter id="nbrOfBankGroups" type="uint" value="4" />
|
||||
<parameter id="nbrOfBanks" type="uint" value="16" />
|
||||
<parameter id="nbrOfRanks" type="uint" value="1" />
|
||||
<parameter id="nbrOfColumns" type="uint" value="1024" />
|
||||
<parameter id="nbrOfRows" type="uint" value="32768" />
|
||||
<parameter id="dataRate" type="uint" value="2" />
|
||||
<parameter id="burstLength" type="uint" value="8" />
|
||||
</memarchitecturespec>
|
||||
<memtimingspec>
|
||||
<parameter id="clkMhz" type="double" value="1200" />
|
||||
<parameter id="REFI" type="uint" value="9360" />
|
||||
<parameter id="RFC" type="uint" value="312" />
|
||||
<parameter id="RFC2" type="uint" value="192" />
|
||||
<parameter id="RFC4" type="uint" value="132" />
|
||||
<parameter id="RL" type="uint" value="16" />
|
||||
<parameter id="WL" type="uint" value="16" />
|
||||
<parameter id="CL" type="uint" value="16" />
|
||||
<parameter id="AL" type="uint" value="0" />
|
||||
<parameter id="RP" type="uint" value="16" />
|
||||
<parameter id="RAS" type="uint" value="39" />
|
||||
<parameter id="RCD" type="uint" value="16" />
|
||||
<parameter id="RC" type="uint" value="55" />
|
||||
<parameter id="FAW" type="uint" value="26" />
|
||||
<parameter id="RTP" type="uint" value="12" />
|
||||
<parameter id="WR" type="uint" value="18" />
|
||||
<parameter id="RRD_S" type="uint" value="4" />
|
||||
<parameter id="RRD_L" type="uint" value="6" />
|
||||
<parameter id="CCD_S" type="uint" value="4" />
|
||||
<parameter id="CCD_L" type="uint" value="6" />
|
||||
<parameter id="WTR_S" type="uint" value="3" />
|
||||
<parameter id="WTR_L" type="uint" value="9" />
|
||||
<parameter id="DQSCK" type="uint" value="2" />
|
||||
<parameter id="XP" type="uint" value="8" />
|
||||
<parameter id="XPDLL" type="uint" value="325" />
|
||||
<parameter id="XS" type="uint" value="324" />
|
||||
<parameter id="XSDLL" type="uint" value="512" />
|
||||
<parameter id="CKE" type="uint" value="6" />
|
||||
<parameter id="CKESR" type="uint" value="7" />
|
||||
</memtimingspec>
|
||||
<mempowerspec>
|
||||
<parameter id="idd0" type="double" value="60.75" />
|
||||
<parameter id="idd02" type="double" value="4.05" />
|
||||
<parameter id="idd2p0" type="double" value="17.0" />
|
||||
<parameter id="idd2p1" type="double" value="17.0" />
|
||||
<parameter id="idd2n" type="double" value="38.25" />
|
||||
<parameter id="idd3p0" type="double" value="22.5" />
|
||||
<parameter id="idd3p1" type="double" value="22.5" />
|
||||
<parameter id="idd3n" type="double" value="44.0" />
|
||||
<parameter id="idd4r" type="double" value="184.5" />
|
||||
<parameter id="idd4w" type="double" value="168.75" />
|
||||
<parameter id="idd5" type="double" value="118.0" />
|
||||
<parameter id="idd6" type="double" value="20.25" />
|
||||
<parameter id="idd62" type="double" value="2.6" />
|
||||
<parameter id="vdd" type="double" value="1.2" />
|
||||
<parameter id="vdd2" type="double" value="2.5" />
|
||||
</mempowerspec>
|
||||
</memspec>
|
||||
@@ -1,42 +0,0 @@
|
||||
{
|
||||
"memspec": {
|
||||
"memarchitecturespec": {
|
||||
"burstLength": 4,
|
||||
"dataRate": 2,
|
||||
"nbrOfBanks": 8,
|
||||
"nbrOfColumns": 512,
|
||||
"nbrOfRanks": 1,
|
||||
"nbrOfRows": 8192,
|
||||
"width": 64
|
||||
},
|
||||
"memoryId": "JEDEC_4x64_2Gb_WIDEIO2-400_64bit",
|
||||
"memoryType": "WIDEIO2",
|
||||
"memtimingspec": {
|
||||
"CCD": 2,
|
||||
"CKE": 3,
|
||||
"CKESR": 6,
|
||||
"FAW": 24,
|
||||
"RAS": 17,
|
||||
"RCAB": 26,
|
||||
"RCD": 8,
|
||||
"RCPB": 24,
|
||||
"REFI": 1560,
|
||||
"REFIPB": 195,
|
||||
"REFM": 1,
|
||||
"RFCAB": 72,
|
||||
"RFCPB": 36,
|
||||
"RL": 7,
|
||||
"RPAB": 9,
|
||||
"RPPB": 8,
|
||||
"RRD": 4,
|
||||
"RTP": 3,
|
||||
"WL": 5,
|
||||
"WR": 8,
|
||||
"WTR": 4,
|
||||
"XP": 3,
|
||||
"XSR": 76,
|
||||
"RTRS": 1,
|
||||
"clkMhz": 400
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,43 @@
|
||||
<!DOCTYPE memspec SYSTEM "memspec.dtd">
|
||||
<!--BL 4/8, DBI disabled/enabled, REFM 0.25/0.5/1/2/4-->
|
||||
<memspec>
|
||||
<parameter id="memoryId" type="string" value="JEDEC_4x64_2Gb_WIDEIO2-400_64bit" />
|
||||
<parameter id="memoryType" type="string" value="WIDEIO2" />
|
||||
<memarchitecturespec>
|
||||
<parameter id="width" type="uint" value="64" />
|
||||
<parameter id="nbrOfBanks" type="uint" value="8" />
|
||||
<parameter id="nbrOfRanks" type="uint" value="1" />
|
||||
<parameter id="nbrOfColumns" type="uint" value="512" />
|
||||
<parameter id="nbrOfRows" type="uint" value="8192" />
|
||||
<parameter id="dataRate" type="uint" value="2" />
|
||||
<parameter id="burstLength" type="uint" value="4" />
|
||||
</memarchitecturespec>
|
||||
<memtimingspec>
|
||||
<parameter id="clkMhz" type="double" value="400" />
|
||||
<parameter id="RCD" type="uint" value="8" />
|
||||
<parameter id="RPPB" type="uint" value="8" />
|
||||
<parameter id="RPAB" type="uint" value="9" />
|
||||
<parameter id="RAS" type="uint" value="17" />
|
||||
<parameter id="RCPB" type="uint" value="24" />
|
||||
<parameter id="RCAB" type="uint" value="26" />
|
||||
<parameter id="WTR" type="uint" value="4" />
|
||||
<parameter id="RRD" type="uint" value="4" />
|
||||
<parameter id="FAW" type="uint" value="24" />
|
||||
<parameter id="CKE" type="uint" value="3" />
|
||||
<parameter id="REFM" type="uint" value="1" />
|
||||
<parameter id="REFI" type="uint" value="1560" />
|
||||
<parameter id="RFCAB" type="uint" value="72" />
|
||||
<parameter id="RFCPB" type="uint" value="36" />
|
||||
<parameter id="CKESR" type="uint" value="6" />
|
||||
<parameter id="XS" type="uint" value="76" />
|
||||
<parameter id="XP" type="uint" value="3" />
|
||||
<parameter id="RL" type="uint" value="7" />
|
||||
<parameter id="WL" type="uint" value="5" />
|
||||
<parameter id="WR" type="uint" value="8" />
|
||||
<parameter id="RTP" type="uint" value="3" />
|
||||
<parameter id="CCD" type="uint" value="2" />
|
||||
</memtimingspec>
|
||||
<mempowerspec>
|
||||
<!-- to be completed -->
|
||||
</mempowerspec>
|
||||
</memspec>
|
||||
@@ -1,42 +0,0 @@
|
||||
{
|
||||
"memspec": {
|
||||
"memarchitecturespec": {
|
||||
"burstLength": 4,
|
||||
"dataRate": 2,
|
||||
"nbrOfBanks": 8,
|
||||
"nbrOfColumns": 512,
|
||||
"nbrOfRanks": 1,
|
||||
"nbrOfRows": 8192,
|
||||
"width": 64
|
||||
},
|
||||
"memoryId": "JEDEC_4x64_2Gb_WIDEIO2-533_64bit",
|
||||
"memoryType": "WIDEIO2",
|
||||
"memtimingspec": {
|
||||
"CCD": 2,
|
||||
"CKE": 3,
|
||||
"CKESR": 8,
|
||||
"FAW": 32,
|
||||
"RAS": 23,
|
||||
"RCAB": 34,
|
||||
"RCD": 10,
|
||||
"RCPB": 32,
|
||||
"REFI": 2080,
|
||||
"REFIPB": 260,
|
||||
"REFM": 1,
|
||||
"RFCAB": 96,
|
||||
"RFCPB": 48,
|
||||
"RL": 9,
|
||||
"RPAB": 12,
|
||||
"RPPB": 10,
|
||||
"RRD": 6,
|
||||
"RTP": 4,
|
||||
"WL": 7,
|
||||
"WR": 11,
|
||||
"WTR": 6,
|
||||
"XP": 4,
|
||||
"XSR": 102,
|
||||
"RTRS": 1,
|
||||
"clkMhz": 533
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,43 @@
|
||||
<!DOCTYPE memspec SYSTEM "memspec.dtd">
|
||||
<!--BL 4/8, DBI disabled/enabled, REFM 0.25/0.5/1/2/4-->
|
||||
<memspec>
|
||||
<parameter id="memoryId" type="string" value="JEDEC_4x64_2Gb_WIDEIO2-533_64bit" />
|
||||
<parameter id="memoryType" type="string" value="WIDEIO2" />
|
||||
<memarchitecturespec>
|
||||
<parameter id="width" type="uint" value="64" />
|
||||
<parameter id="nbrOfBanks" type="uint" value="8" />
|
||||
<parameter id="nbrOfRanks" type="uint" value="1" />
|
||||
<parameter id="nbrOfColumns" type="uint" value="512" />
|
||||
<parameter id="nbrOfRows" type="uint" value="8192" />
|
||||
<parameter id="dataRate" type="uint" value="2" />
|
||||
<parameter id="burstLength" type="uint" value="4" />
|
||||
</memarchitecturespec>
|
||||
<memtimingspec>
|
||||
<parameter id="clkMhz" type="double" value="533" />
|
||||
<parameter id="RCD" type="uint" value="10" />
|
||||
<parameter id="RPPB" type="uint" value="10" />
|
||||
<parameter id="RPAB" type="uint" value="12" />
|
||||
<parameter id="RAS" type="uint" value="23" />
|
||||
<parameter id="RCPB" type="uint" value="32" />
|
||||
<parameter id="RCAB" type="uint" value="34" />
|
||||
<parameter id="WTR" type="uint" value="6" />
|
||||
<parameter id="RRD" type="uint" value="6" />
|
||||
<parameter id="FAW" type="uint" value="32" />
|
||||
<parameter id="CKE" type="uint" value="3" />
|
||||
<parameter id="REFM" type="uint" value="1" />
|
||||
<parameter id="REFI" type="uint" value="2078" />
|
||||
<parameter id="RFCAB" type="uint" value="96" />
|
||||
<parameter id="RFCPB" type="uint" value="48" />
|
||||
<parameter id="CKESR" type="uint" value="8" />
|
||||
<parameter id="XS" type="uint" value="102" />
|
||||
<parameter id="XP" type="uint" value="4" />
|
||||
<parameter id="RL" type="uint" value="9" />
|
||||
<parameter id="WL" type="uint" value="7" />
|
||||
<parameter id="WR" type="uint" value="11" />
|
||||
<parameter id="RTP" type="uint" value="4" />
|
||||
<parameter id="CCD" type="uint" value="2" />
|
||||
</memtimingspec>
|
||||
<mempowerspec>
|
||||
<!-- to be completed -->
|
||||
</mempowerspec>
|
||||
</memspec>
|
||||
@@ -1,96 +0,0 @@
|
||||
{
|
||||
"memspec": {
|
||||
"memarchitecturespec": {
|
||||
"burstLength": 16,
|
||||
"dataRate": 2,
|
||||
"nbrOfBanks": 8,
|
||||
"nbrOfColumns": 1024,
|
||||
"nbrOfRanks": 1,
|
||||
"nbrOfRows": 65536,
|
||||
"width": 16
|
||||
},
|
||||
"memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit",
|
||||
"memoryType": "LPDDR4",
|
||||
"mempowerspec": {
|
||||
"idd0": 3.5,
|
||||
"idd02": 45.0,
|
||||
"idd0ql": 0.75,
|
||||
"idd2n": 2.0,
|
||||
"idd2n2": 27.0,
|
||||
"idd2nQ": 0.75,
|
||||
"idd2ns": 2.0,
|
||||
"idd2ns2": 23.0,
|
||||
"idd2nsq": 0.75,
|
||||
"idd2p": 1.2,
|
||||
"idd2p2": 3.0,
|
||||
"idd2pQ": 0.75,
|
||||
"idd2ps": 1.2,
|
||||
"idd2ps2": 3.0,
|
||||
"idd2psq": 0.75,
|
||||
"idd3n": 2.25,
|
||||
"idd3n2": 30.0,
|
||||
"idd3nQ": 0.75,
|
||||
"idd3ns": 2.25,
|
||||
"idd3ns2": 30.0,
|
||||
"idd3nsq": 0.75,
|
||||
"idd3p": 1.2,
|
||||
"idd3p2": 9.0,
|
||||
"idd3pQ": 0.75,
|
||||
"idd3ps": 1.2,
|
||||
"idd3ps2": 9.0,
|
||||
"idd3psq": 0.75,
|
||||
"idd4r": 2.25,
|
||||
"idd4r2": 275.0,
|
||||
"idd4rq": 150.0,
|
||||
"idd4w": 2.25,
|
||||
"idd4w2": 210.0,
|
||||
"idd4wq": 55.0,
|
||||
"idd5": 10.0,
|
||||
"idd52": 90.0,
|
||||
"idd5ab": 2.5,
|
||||
"idd5ab2": 30.0,
|
||||
"idd5abq": 0.75,
|
||||
"idd5b": 2.5,
|
||||
"idd5b2": 30.0,
|
||||
"idd5bq": 0.75,
|
||||
"idd5q": 0.75,
|
||||
"idd6": 0.3,
|
||||
"idd62": 0.5,
|
||||
"idd6q": 0.1,
|
||||
"vdd": 1.8,
|
||||
"vdd2": 1.1,
|
||||
"vddq": 1.1
|
||||
},
|
||||
"memtimingspec": {
|
||||
"CCD": 8,
|
||||
"CKE": 12,
|
||||
"CMDCKE": 3,
|
||||
"DQS2DQ": 2,
|
||||
"DQSCK": 6,
|
||||
"DQSS": 1,
|
||||
"ESCKE": 3,
|
||||
"FAW": 64,
|
||||
"PPD": 4,
|
||||
"RAS": 68,
|
||||
"RCD": 29,
|
||||
"REFI": 6246,
|
||||
"REFIPB": 780,
|
||||
"RFCAB": 448,
|
||||
"RFCPB": 224,
|
||||
"RL": 28,
|
||||
"RPAB": 34,
|
||||
"RPPB": 29,
|
||||
"RPST": 0,
|
||||
"RRD": 16,
|
||||
"RTP": 12,
|
||||
"SR": 24,
|
||||
"WL": 14,
|
||||
"WPRE": 2,
|
||||
"WR": 29,
|
||||
"WTR": 16,
|
||||
"XP": 12,
|
||||
"XSR": 460,
|
||||
"clkMhz": 1600
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,50 @@
|
||||
<!DOCTYPE memspec SYSTEM "memspec.dtd">
|
||||
<!--Single channel device with 8Gb, Set A WL-->
|
||||
<memspec>
|
||||
<parameter id="memoryId" type="string" value="JEDEC_8Gb_LPDDR4-3200_16bit" />
|
||||
<parameter id="memoryType" type="string" value="LPDDR4" />
|
||||
<memarchitecturespec>
|
||||
<parameter id="width" type="uint" value="16" />
|
||||
<parameter id="nbrOfBanks" type="uint" value="8" />
|
||||
<parameter id="nbrOfRanks" type="uint" value="1" />
|
||||
<parameter id="nbrOfRows" type="uint" value="65536" />
|
||||
<parameter id="nbrOfColumns" type="uint" value="1024" />
|
||||
<parameter id="dataRate" type="uint" value="2" />
|
||||
<parameter id="burstLength" type="uint" value="16" />
|
||||
</memarchitecturespec>
|
||||
<memtimingspec>
|
||||
<parameter id="clkMhz" type="double" value="1600" />
|
||||
<parameter id="REFI" type="uint" value="6246" />
|
||||
<parameter id="REFIPB" type="uint" value="780" />
|
||||
<parameter id="RFCAB" type="uint" value="448" />
|
||||
<parameter id="RFCPB" type="uint" value="224" />
|
||||
<parameter id="RPAB" type="uint" value="34" />
|
||||
<parameter id="RPPB" type="uint" value="29" />
|
||||
<parameter id="PPD" type="uint" value="4" />
|
||||
<parameter id="RAS" type="uint" value="68" />
|
||||
<parameter id="RCD" type="uint" value="29" />
|
||||
<parameter id="FAW" type="uint" value="64" />
|
||||
<parameter id="RRD" type="uint" value="16" />
|
||||
<parameter id="CCD" type="uint" value="8" />
|
||||
<parameter id="RL" type="uint" value="28" />
|
||||
<parameter id="RPST" type="uint" value="0" />
|
||||
<parameter id="DQSCK" type="uint" value="6" />
|
||||
<parameter id="RTP" type="uint" value="12" />
|
||||
<parameter id="WL" type="uint" value="14" />
|
||||
<parameter id="DQSS" type="uint" value="1" />
|
||||
<parameter id="DQS2DQ" type="uint" value="2" />
|
||||
<!--parameter id="nWR" type="uint" value="30" /-->
|
||||
<parameter id="WR" type="uint" value="29" />
|
||||
<parameter id="WPRE" type="uint" value="2" />
|
||||
<parameter id="WTR" type="uint" value="16" />
|
||||
<parameter id="XP" type="uint" value="12" />
|
||||
<parameter id="SR" type="uint" value="24" />
|
||||
<parameter id="XSR" type="uint" value="460" />
|
||||
<parameter id="ESCKE" type="uint" value="3" />
|
||||
<parameter id="CKE" type="uint" value="12" />
|
||||
<parameter id="CMDCKE" type="uint" value="3" />
|
||||
</memtimingspec>
|
||||
<mempowerspec>
|
||||
<!-- to be completed -->
|
||||
</mempowerspec>
|
||||
</memspec>
|
||||
@@ -1,55 +0,0 @@
|
||||
{
|
||||
"memspec": {
|
||||
"memarchitecturespec": {
|
||||
"burstLength": 8,
|
||||
"dataRate": 2,
|
||||
"nbrOfBanks": 8,
|
||||
"nbrOfColumns": 1024,
|
||||
"nbrOfRanks": 1,
|
||||
"nbrOfRows": 8192,
|
||||
"width": 16
|
||||
},
|
||||
"memoryId": "MICRON_1Gb_DDR2-1066_16bit_H",
|
||||
"memoryType": "DDR2",
|
||||
"mempowerspec": {
|
||||
"idd0": 90.0,
|
||||
"idd2n": 36.0,
|
||||
"idd2p0": 7.0,
|
||||
"idd2p1": 7.0,
|
||||
"idd3n": 42.0,
|
||||
"idd3p0": 10.0,
|
||||
"idd3p1": 23.0,
|
||||
"idd4r": 180.0,
|
||||
"idd4w": 185.0,
|
||||
"idd5": 160.0,
|
||||
"idd6": 7.0,
|
||||
"vdd": 1.8
|
||||
},
|
||||
"memtimingspec": {
|
||||
"AL": 0,
|
||||
"CCD": 2,
|
||||
"CKE": 3,
|
||||
"CKESR": 4,
|
||||
"CL": 7,
|
||||
"DQSCK": 0,
|
||||
"FAW": 24,
|
||||
"RAS": 24,
|
||||
"RC": 31,
|
||||
"RCD": 7,
|
||||
"REFI": 3120,
|
||||
"RFC": 68,
|
||||
"RL": 7,
|
||||
"RP": 7,
|
||||
"RRD": 6,
|
||||
"RTP": 4,
|
||||
"WL": 6,
|
||||
"WR": 8,
|
||||
"WTR": 4,
|
||||
"XP": 3,
|
||||
"XPDLL": 10,
|
||||
"XS": 74,
|
||||
"XSDLL": 200,
|
||||
"clkMhz": 533
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1 @@
|
||||
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.xml
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user