From 6383a1fce566aa66afcdcdecd4853f206e8e8c4a Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 5 Jun 2020 16:26:29 +0200 Subject: [PATCH] Revert "Merge branch 'opensource_splitting' into 'master'" This reverts merge request !251 --- .gitlab-ci.yml | 4 +- .gitmodules | 6 +- DRAMSys/CMakeLists.txt | 22 +- DRAMSys/docs/Timings.ods | Bin 0 -> 13502 bytes DRAMSys/gem5/CMakeLists.txt | 73 - DRAMSys/gem5/configs/configs.pri | 4 + DRAMSys/gem5/gem5.pro | 167 + DRAMSys/gem5/main.cpp | 71 +- DRAMSys/library/CMakeLists.txt | 227 +- .../resources/configs/amconfigs/am_ddr3.xml | 6 + .../amconfigs/am_ddr3_1Gbx8_p1KB_brc.json | 37 - .../amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml | 21 + .../am_ddr3_4x4Gbx16_dimm_p2KB_brc.json | 43 - .../am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml | 34 + .../am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json | 43 - .../am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml | 34 + .../am_ddr3_8x1Gbx8_dimm_p1KB_brc.json | 42 - .../am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml | 24 + .../am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json | 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DRAMSys/library/resources/configs/simulator/lpddr4.xml create mode 100644 DRAMSys/library/resources/configs/simulator/orgr.xml create mode 100644 DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml create mode 100644 DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml create mode 100644 DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml create mode 100644 DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml create mode 100644 DRAMSys/library/resources/configs/simulator/orgr_ddr4.xml create mode 100644 DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.xml create mode 100644 DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.xml create mode 100644 DRAMSys/library/resources/configs/simulator/rgrsimcfg.xml create mode 100644 DRAMSys/library/resources/configs/simulator/sms.xml delete mode 100644 DRAMSys/library/resources/configs/simulator/wideio.json create mode 100644 DRAMSys/library/resources/configs/simulator/wideio.xml delete mode 100644 DRAMSys/library/resources/configs/simulator/wideio_ecc.json create mode 100644 DRAMSys/library/resources/configs/simulator/wideio_ecc.xml delete mode 100644 DRAMSys/library/resources/configs/simulator/wideio_thermal.json create mode 100644 DRAMSys/library/resources/configs/simulator/wideio_thermal.xml delete mode 100644 DRAMSys/library/resources/configs/thermalsim/config.json create mode 100644 DRAMSys/library/resources/configs/thermalsim/config.xml delete mode 100644 DRAMSys/library/resources/configs/thermalsim/powerInfo.json create mode 100644 DRAMSys/library/resources/configs/thermalsim/powerInfo.xml create mode 100644 DRAMSys/library/resources/resources.pri delete mode 100644 DRAMSys/library/resources/simulations/ddr3-boot-linux.json create mode 100644 DRAMSys/library/resources/simulations/ddr3-boot-linux.xml delete mode 100644 DRAMSys/library/resources/simulations/ddr3-ecc.json create mode 100644 DRAMSys/library/resources/simulations/ddr3-ecc.xml delete mode 100644 DRAMSys/library/resources/simulations/ddr3-example.json create mode 100644 DRAMSys/library/resources/simulations/ddr3-example.xml delete mode 100644 DRAMSys/library/resources/simulations/ddr3-example2.json create mode 100644 DRAMSys/library/resources/simulations/ddr3-example2.xml delete mode 100644 DRAMSys/library/resources/simulations/ddr3-gem5-se.json create mode 100644 DRAMSys/library/resources/simulations/ddr3-gem5-se.xml delete mode 100644 DRAMSys/library/resources/simulations/ddr3-single-device.json create mode 100644 DRAMSys/library/resources/simulations/ddr3-single-device.xml delete mode 100644 DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.json create mode 100644 DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.xml delete mode 100644 DRAMSys/library/resources/simulations/ddr4-example.json create mode 100644 DRAMSys/library/resources/simulations/ddr4-example.xml delete mode 100644 DRAMSys/library/resources/simulations/hbm2-example.json create mode 100644 DRAMSys/library/resources/simulations/hbm2-example.xml delete mode 100644 DRAMSys/library/resources/simulations/lpddr4-example.json create mode 100644 DRAMSys/library/resources/simulations/lpddr4-example.xml delete mode 100644 DRAMSys/library/resources/simulations/ranktest.json create mode 100644 DRAMSys/library/resources/simulations/ranktest.xml create mode 100644 DRAMSys/library/resources/simulations/rgrsim-gem5-fs.xml create mode 100644 DRAMSys/library/resources/simulations/rgrsim-gem5-se.xml create mode 100644 DRAMSys/library/resources/simulations/rgrsim.xml create mode 100644 DRAMSys/library/resources/simulations/sms-example.xml create mode 100644 DRAMSys/library/resources/simulations/wideio-ecc.xml delete mode 100644 DRAMSys/library/resources/simulations/wideio-example.json create mode 100644 DRAMSys/library/resources/simulations/wideio-example.xml delete mode 100644 DRAMSys/library/resources/simulations/wideio-thermal.json create mode 100755 DRAMSys/library/resources/traces/prettyTest delete mode 160000 DRAMSys/library/src/common/third_party/nlohmann create mode 160000 DRAMSys/library/src/common/third_party/tinyxml2 create mode 100644 DRAMSys/library/src/configuration/ConfigurationLoader.cpp create mode 100644 DRAMSys/library/src/configuration/ConfigurationLoader.h delete mode 100644 DRAMSys/library/src/simulation/DRAMSysRecordable.cpp rename DRAMSys/{simulator => library/src/simulation}/ExampleInitiator.h (97%) rename DRAMSys/{simulator => library/src/simulation}/MemoryManager.cpp (97%) rename DRAMSys/{simulator => library/src/simulation}/MemoryManager.h (100%) create mode 100644 DRAMSys/library/src/simulation/Setup.cpp rename DRAMSys/library/src/simulation/{DRAMSysRecordable.h => Setup.h} (64%) rename DRAMSys/{simulator => library/src/simulation}/StlPlayer.h (100%) rename DRAMSys/{simulator => library/src/simulation}/TraceGenerator.h (100%) rename DRAMSys/{simulator => library/src/simulation}/TracePlayer.cpp (100%) rename DRAMSys/{simulator => library/src/simulation}/TracePlayer.h (97%) rename DRAMSys/{simulator => library/src/simulation}/TracePlayerListener.h (100%) rename DRAMSys/{simulator => library/src/simulation}/TraceSetup.cpp (52%) rename DRAMSys/{simulator => library/src/simulation}/TraceSetup.h (98%) create mode 100755 DRAMSys/pct/buildDRAMSys.sh delete mode 100644 DRAMSys/simulator/CMakeLists.txt rename DRAMSys/traceAnalyzer/presentation/{tracescroller.cpp => pornotracescroller.cpp} (91%) rename DRAMSys/traceAnalyzer/presentation/{tracescroller.h => pornotracescroller.h} (93%) create mode 100644 DRAMSys/traceAnalyzer/scripts/scripts.pri create mode 100644 DRAMSys/unitTests/googleTest.pri create mode 100644 DRAMSys/unitTests/unitTests.pro diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 9011e4ab..700ec923 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -19,8 +19,8 @@ build: - rm -rf build - mkdir -p build - cd build - - cmake ../DRAMSys - - make -j16 + - qmake ../DRAMSys/DRAMSys.pro + - make -j4 - find . -name "*.o" -type f -delete - rm -rf ${CI_PROJECT_DIR}/coverage - mkdir -p ${CI_PROJECT_DIR}/coverage diff --git a/.gitmodules b/.gitmodules index 8456cd1e..13b67848 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ +[submodule "DRAMSys/library/src/common/third_party/tinyxml2"] + path = DRAMSys/library/src/common/third_party/tinyxml2 + url = https://github.com/leethomason/tinyxml2.git [submodule "DRAMSys/library/src/common/third_party/DRAMPower"] path = DRAMSys/library/src/common/third_party/DRAMPower url = https://github.com/tukl-msd/DRAMPower.git @@ -11,6 +14,3 @@ [submodule "DRAMSys/library/src/common/third_party/sqlite-amalgamation"] path = DRAMSys/library/src/common/third_party/sqlite-amalgamation url = https://github.com/azadkuh/sqlite-amalgamation.git -[submodule "DRAMSys/library/src/common/third_party/nlohmann"] - path = DRAMSys/library/src/common/third_party/nlohmann - url = https://github.com/nlohmann/json diff --git a/DRAMSys/CMakeLists.txt b/DRAMSys/CMakeLists.txt index 6a50c48c..9ce35df7 100644 --- a/DRAMSys/CMakeLists.txt +++ b/DRAMSys/CMakeLists.txt @@ -39,18 +39,22 @@ project(DRAMSys) set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows") +# Add sqlite3 Dependency: +set(BUILD_ENABLE_RTREE ON CACHE BOOL "Enable R-Tree Feature") +set(BUILD_ENABLE_RTREE ON) +add_subdirectory(library/src/common/third_party/sqlite-amalgamation) + # Add DRAMSysLibrary: add_subdirectory(library) # Add TraceAnalyzer: -if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/library/src/simulation/DRAMSysRecordable.cpp) - add_subdirectory(traceAnalyzer) -endif() +add_subdirectory(traceAnalyzer) -# Add DRAMSysSimulator: -add_subdirectory(simulator) +# Build: +add_executable(DRAMSys simulator/main.cpp) +target_include_directories(DRAMSys + PUBLIC library/src/simulation/ + PUBLIC library/src/common/third_party/sqlite-amalgamation/ +) +target_link_libraries(DRAMSys sqlite3::sqlite3 systemc DRAMSysLibrary) -# Add DRAMSysgem5 -if(DEFINED ENV{GEM5}) - add_subdirectory(gem5) -endif() diff --git a/DRAMSys/docs/Timings.ods b/DRAMSys/docs/Timings.ods new file mode 100644 index 0000000000000000000000000000000000000000..e3e6139b543a909eba7a96736d27c8852c6a0a90 GIT binary patch literal 13502 zcma)j1z2S{5-v3E4o#ztH16*1?(XjH?(XhR)401sV6?($%EXLokr&ih{7dv0=0 zQn@FoRPtAnk`@C3Mg{-?2LNy~4CW6oX9=YQ008*BJ{|#Bm{=ItyI33OSX-N$=;_#- zSXojzTIy3;>DZarQCe9WSn6BpIanB2+EdzD+ZyQT+Zh`e*h~LMnQv@#)yH1}06wpe zFMzzUgN3f8j)}P)mHnSlN^47_5NSyv7|3ssA6Z~Tg!yGZ!T)%;h| z$+lUA2Kl4&L|KyN27wsHq4u=Ladf?r@T!Cq7o*no@gTbW^!s#|@#m3`i*5XwlgdXh z?>oFUE^fm8$_#N(d$kok+bx^R*IVZ>!URsS-v}#nXHrd(&iWVi=gWGz`5o4pfV0qJn^(}cfNJ${;ycBt7npd(-r-jq$d(Ypz9(!WEl8(w7 zt@Y03r{XSBroYIw!)2VZQX8x%l~v%l!gQk)SY|e8_eZ?2K5jd1hy@|+U#}~Rh9^#L?JMsC> z6WjUS`6&xHBskak3#`c^0sfHiR0$?ILR*($UNz!`vWWrF$?#AmyUp7b&OVSQi}mqV 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#include "sc_target.hh" #include "sim_control.hh" #include "slave_transactor.hh" #include "stats.hh" -#include "DRAMSys.h" +using namespace std; -#ifdef RECORDING -#include "DRAMSysRecordable.h" -#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp" - -using json = nlohmann::json; -#endif - -using namespace tlm; - -class Gem5SimControlDRAMsys : public Gem5SystemC::Gem5SimControl +class Gem5SimControlDRAMsys: public Gem5SystemC::Gem5SimControl { public: - Gem5SimControlDRAMsys(std::string configFile) : + Gem5SimControlDRAMsys(string configFile) : Gem5SystemC::Gem5SimControl("gem5", configFile, 0, "MemoryAccess") - {} + { + } void afterSimulate() { @@ -72,8 +67,7 @@ public: }; -class AddressOffset : sc_module -{ +struct AddressOffset: sc_module { private: unsigned long long int offset; @@ -91,7 +85,7 @@ public: } //Forward Interface - tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, + tlm::tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { //std::cout << "NB "<< this->name() <<": " << trans.get_address() << " -" << offset; @@ -100,7 +94,7 @@ public: return i_socket->nb_transport_fw(trans, phase, delay); } - unsigned int transport_dbg(tlm_generic_payload &trans) + unsigned int transport_dbg(tlm::tlm_generic_payload &trans) { // adjust address offset: //std::cout << "Debug "<< this->name() <<": " << trans.get_address() << " -" << offset; @@ -109,7 +103,7 @@ public: return i_socket->transport_dbg(trans); } - void b_transport(tlm_generic_payload &trans, sc_time &delay) + void b_transport(tlm::tlm_generic_payload &trans, sc_time &delay) { // adjust address offset: //std::cout << "B "<< this->name() <<": " << trans.get_address() << " -" << offset; @@ -119,7 +113,7 @@ public: } //Backward Interface - tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, + tlm::tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { //trans.set_address(trans.get_address()+offset); @@ -128,7 +122,7 @@ public: }; -std::string pathOfFile(std::string file) +string pathOfFile(string file) { return file.substr(0, file.find_last_of('/')); } @@ -137,9 +131,9 @@ int sc_main(int argc, char **argv) { SC_REPORT_INFO("sc_main", "Simulation Setup"); - std::string simulationJson; - std::string gem5ConfigFile; - std::string resources; + string SimulationXML; + string gem5ConfigFile; + string resources; unsigned int numTransactors; Gem5SystemC::Gem5SlaveTransactor *t; std::vector transactors; @@ -147,28 +141,18 @@ int sc_main(int argc, char **argv) if (argc == 4) { // Get path of resources: resources = pathOfFile(argv[0]) - + std::string("/../../DRAMSys/library/resources/"); + + string("/../../DRAMSys/library/resources/"); - simulationJson = argv[1]; + SimulationXML = argv[1]; gem5ConfigFile = argv[2]; - numTransactors = std::stoul(argv[3]); + numTransactors = atoi(argv[3]); } else { SC_REPORT_FATAL("sc_main", "Please provide configuration files and number of ports"); } // Instantiate DRAMSys: - DRAMSys *dramSys; -#ifdef RECORDING - json simulationdoc = parseJSON(simulationJson); - json simulatordoc = parseJSON(resources + "configs/simulator/" - + std::string(simulationdoc["simulation"]["simconfig"])); - - if (simulatordoc["simconfig"]["DatabaseRecording"]) - dramSys = new DRAMSysRecordable("DRAMSys", simulationJson, resources); - else -#endif - dramSys = new DRAMSys("DRAMSys", simulationJson, resources); + DRAMSys dramSys("DRAMSys", SimulationXML, resources); // Instantiate gem5: Gem5SimControlDRAMsys sim_control(gem5ConfigFile); @@ -179,7 +163,7 @@ int sc_main(int argc, char **argv) // Names generated here must match port names used by the gem5 config file, e.g., config.ini if (numTransactors == 1) { t = new Gem5SystemC::Gem5SlaveTransactor("transactor", "transactor"); - t->socket.bind(dramSys->tSocket); + t->socket.bind(dramSys.tSocket); t->sim_control.bind(sim_control); transactors.push_back(t); } else { @@ -189,7 +173,7 @@ int sc_main(int argc, char **argv) std::string name = "transactor" + std::to_string(index); std::string portName = "transactor" + std::to_string(index); t = new Gem5SystemC::Gem5SlaveTransactor(name.c_str(), portName.c_str()); - t->socket.bind(dramSys->tSocket); + t->socket.bind(dramSys.tSocket); t->sim_control.bind(sim_control); transactors.push_back(t); } @@ -205,9 +189,9 @@ int sc_main(int argc, char **argv) AddressOffset dramOffset("dramOffset", (2147483648 - 67108863)); //+67108863); dramInterface.socket.bind(dramOffset.t_socket); - dramOffset.i_socket.bind(dramSys->tSocket); // ID0 + dramOffset.i_socket.bind(dramSys.tSocket); // ID0 nvmInterface.socket.bind(nvmOffset.t_socket); - nvmOffset.i_socket.bind(dramSys->tSocket); + nvmOffset.i_socket.bind(dramSys.tSocket); dramInterface.sim_control.bind(sim_control); nvmInterface.sim_control.bind(sim_control); @@ -223,10 +207,9 @@ int sc_main(int argc, char **argv) sc_core::sc_stop(); } - for (auto t : transactors) + for (auto t : transactors) { delete t; - - delete dramSys; + } SC_REPORT_INFO("sc_main", "End of Simulation"); diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index 0b828857..0bfbbd1e 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -35,52 +35,46 @@ cmake_minimum_required(VERSION 3.10) # Project Name project(DRAMSysLibrary) +# Add DRAMPower: +add_subdirectory(src/common/third_party/DRAMPower) + +# Add SystemC: +set(BUILD_SHARED_LIBS OFF CACHE BOOL "Build Shared Libs") +add_subdirectory(src/common/third_party/systemc) + # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH="CMAKE_SH-NOTFOUND") -# Add DRAMPower: -add_subdirectory(src/common/third_party/DRAMPower) - -# Add nlohmann: -add_subdirectory(src/common/third_party/nlohmann) - -# Add SystemC: -if(DEFINED ENV{SYSTEMC_HOME}) - find_library(SYSTEMC_LIBRARY - NAMES systemc SnpsVP - PATHS $ENV{SYSTEMC_HOME}/lib-$ENV{SYSTEMC_TARGET_ARCH}/ $ENV{SYSTEMC_HOME}/lib-linux64/ $ENV{SYSTEMC_HOME}/libso-$ENV{COWARE_CXX_COMPILER}/ - ) - message("-- Building with external SystemC located in $ENV{SYSTEMC_HOME}") -else() - set(BUILD_SHARED_LIBS OFF CACHE BOOL "Build Shared Libs") - add_subdirectory(src/common/third_party/systemc) - set(SYSTEMC_LIBRARY systemc) - message("-- Building with SystemC submodule") -endif() - -if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/simulation/DRAMSysRecordable.cpp) - # Add sqlite3 Dependency: - set(BUILD_ENABLE_RTREE ON CACHE BOOL "Enable R-Tree Feature") - set(BUILD_ENABLE_RTREE ON) - add_subdirectory(src/common/third_party/sqlite-amalgamation) - - set(RECORDING_SOURCES - src/common/TlmRecorder.cpp - src/controller/ControllerRecordable.cpp - src/simulation/DRAMSysRecordable.cpp - src/simulation/dram/DramRecordable.cpp - ) -endif() +include_directories( + src/common + src/common/third_party/DRAMPower/src + src/configuration + src/configuration/memspec + src/controller + src/controller/checker + src/controller/cmdmux + src/controller/powerdown + src/controller/refresh + src/controller/respqueue + src/controller/scheduler + src/error + src/error/ECC + src/simulation + src/simulation/dram +) add_library(DRAMSysLibrary src/common/AddressDecoder.cpp src/common/DebugManager.cpp src/common/dramExtensions.cpp src/common/tlm2_base_protocol_checker.h + src/common/TlmRecorder.cpp src/common/utils.cpp + src/common/third_party/tinyxml2/tinyxml2.cpp src/configuration/Configuration.cpp + src/configuration/ConfigurationLoader.cpp src/configuration/TemperatureSimConfig.h src/configuration/memspec/MemSpec.cpp @@ -98,6 +92,7 @@ add_library(DRAMSysLibrary src/controller/Command.cpp src/controller/ControllerIF.h src/controller/Controller.cpp + src/controller/ControllerRecordable.cpp src/controller/checker/CheckerIF.h src/controller/checker/CheckerDDR3.cpp @@ -142,10 +137,19 @@ add_library(DRAMSysLibrary src/simulation/Arbiter.cpp src/simulation/DRAMSys.cpp + src/simulation/ExampleInitiator.h + src/simulation/MemoryManager.cpp src/simulation/ReorderBuffer.h + src/simulation/Setup.cpp + src/simulation/StlPlayer.h src/simulation/TemperatureController.cpp + src/simulation/TraceGenerator.h + src/simulation/TracePlayer.cpp + src/simulation/TracePlayerListener.h + src/simulation/TraceSetup.cpp src/simulation/dram/Dram.cpp + src/simulation/dram/DramRecordable.cpp src/simulation/dram/DramDDR3.cpp src/simulation/dram/DramDDR4.cpp src/simulation/dram/DramLPDDR4.cpp @@ -155,159 +159,16 @@ add_library(DRAMSysLibrary src/simulation/dram/DramGDDR5X.cpp src/simulation/dram/DramGDDR6.cpp src/simulation/dram/DramHBM2.cpp - - ${RECORDING_SOURCES} - - - # Simulation Config Files - resources/simulations/ddr3-boot-linux.json - resources/simulations/ddr3-ecc.json - resources/simulations/ddr3-example2.json - resources/simulations/ddr3-example.json - resources/simulations/ddr3-gem5-se.json - resources/simulations/ddr3_postpone_ref_test.json - resources/simulations/ddr3-single-device.json - resources/simulations/ddr4-example.json - resources/simulations/hbm2-example.json - resources/simulations/lpddr4-example.json - resources/simulations/ranktest.json - resources/simulations/wideio-example.json - - # Address Mapping Config Files - resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.json - resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json - resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json - resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json - resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json - resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json - resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json - resources/configs/amconfigs/am_ddr3_x16_brc.json - resources/configs/amconfigs/am_ddr3_x16_rbc.json - resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json - resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json - resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.json - resources/configs/amconfigs/am_ranktest.json - resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json - resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json - resources/configs/amconfigs/am_wideio_4x1Gb_brc.json - resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json - resources/configs/amconfigs/am_wideio_4x256Mb_brc.json - resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json - resources/configs/amconfigs/am_wideio_4x2Gb_brc.json - resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json - resources/configs/amconfigs/am_wideio_4x4Gb_brc.json - resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json - resources/configs/amconfigs/am_wideio_4x512Mb_brc.json - resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json - - # Memory Controller Config Files - resources/configs/mcconfigs/fifo.json - resources/configs/mcconfigs/fifoStrict.json - resources/configs/mcconfigs/fr_fcfs_grp.json - resources/configs/mcconfigs/fr_fcfs.json - - # Memspec Config Files - resources/configs/memspecs/HBM2.json - resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json - resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json - resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json - resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json - resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json - resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json - resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json - resources/configs/memspecs/memspec_ranktest.json - resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json - resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json - resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json - resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json - resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json - resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json - resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json - resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json - resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json - resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json - resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json - resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json - resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json - resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json - resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json - resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json - resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json - resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json - - # Simulator Config Files - resources/configs/simulator/ddr3_boot_linux.json - resources/configs/simulator/ddr3_ecc.json - resources/configs/simulator/ddr3.json - resources/configs/simulator/ddr3_gem5_se.json - resources/configs/simulator/ddr3-single-device.json - resources/configs/simulator/ddr4.json - resources/configs/simulator/hbm2.json - resources/configs/simulator/lpddr4.json - resources/configs/simulator/wideio.json - - # Thermal Simulation Config Files - resources/configs/thermalsim/config.json - - # Trace Files - resources/traces/test_ecc.stl - resources/traces/ddr3_example.stl - resources/traces/ddr3_single_dev_example.stl - resources/traces/ddr3_postpone_ref_test_1.stl - resources/traces/ranktest.stl - resources/traces/chstone-adpcm_32.stl ) -if(DEFINED ENV{LIBTHREED_ICE_HOME} AND DEFINED ENV{LIBSUPERLU_HOME}) - message("-- 3D-ICE and SuperLU available") - add_definitions(-DTHERMALSIM) - target_include_directories(DRAMSysLibrary - PRIVATE $ENV{LIBTHREED_ICE_HOME}/include/ - ) - find_library(3DICE_LIBRARY NAMES threed-ice-2.2.4 PATHS $ENV{LIBTHREED_ICE_HOME}/lib/) - target_link_libraries(DRAMSysLibrary - PRIVATE ${3DICE_LIBRARY} - ) -endif() - -if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/simulation/DRAMSysRecordable.cpp) - target_include_directories(DRAMSysLibrary - PRIVATE src/common/third_party/sqlite-amalgamation/ - ) - target_link_libraries(DRAMSysLibrary - PRIVATE sqlite3::sqlite3 - ) -endif() - # Build: target_include_directories(DRAMSysLibrary - PUBLIC src/common/third_party/DRAMPower/src/ - PUBLIC $ENV{SYSTEMC_HOME}/include/ - PUBLIC $ENV{SYSTEMC_HOME}/include/tlm/ + PUBLIC src/common/third_party/DRAMPower/src + PUBLIC src/common/third_party/sqlite-amalgamation/ +) +target_link_libraries(DRAMSysLibrary + SystemC::systemc + sqlite3::sqlite3 + DRAMPower ) -target_link_libraries(DRAMSysLibrary - PUBLIC ${SYSTEMC_LIBRARY} - PRIVATE DRAMPower -) diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3.xml new file mode 100755 index 00000000..8d73c4c5 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3.xml @@ -0,0 +1,6 @@ + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.json b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.json deleted file mode 100644 index 7554bac8..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.json +++ /dev/null @@ -1,37 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 24, - 25, - 26 - ], - "COLUMN_BIT": [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9 - ], - "ROW_BIT": [ - 10, - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml new file mode 100644 index 00000000..7b392322 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml @@ -0,0 +1,21 @@ + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json deleted file mode 100644 index 3999c105..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json +++ /dev/null @@ -1,43 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 28, - 29, - 30 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12 - ], - "ROW_BIT": [ - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml new file mode 100644 index 00000000..886385fe --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml @@ -0,0 +1,34 @@ + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json deleted file mode 100644 index d1bcfe70..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json +++ /dev/null @@ -1,43 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 13, - 14, - 15 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12 - ], - "ROW_BIT": [ - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28, - 29, - 30 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml new file mode 100644 index 00000000..48f2962a --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml @@ -0,0 +1,34 @@ + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json deleted file mode 100644 index 13ee107d..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json +++ /dev/null @@ -1,42 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 27, - 28, - 29 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12 - ], - "ROW_BIT": [ - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml new file mode 100644 index 00000000..5500c9ae --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml @@ -0,0 +1,24 @@ + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json deleted file mode 100644 index 81ac8ef6..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json +++ /dev/null @@ -1,42 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 13, - 14, - 15 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12 - ], - "ROW_BIT": [ - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28, - 29 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml new file mode 100644 index 00000000..fb4d44ed --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml @@ -0,0 +1,24 @@ + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json deleted file mode 100644 index 3999c105..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json +++ /dev/null @@ -1,43 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 28, - 29, - 30 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12 - ], - "ROW_BIT": [ - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.xml new file mode 100644 index 00000000..0106b60d --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.xml @@ -0,0 +1,24 @@ + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json deleted file mode 100644 index d1bcfe70..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json +++ /dev/null @@ -1,43 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 13, - 14, - 15 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12 - ], - "ROW_BIT": [ - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28, - 29, - 30 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.xml new file mode 100644 index 00000000..c87cdd44 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.xml @@ -0,0 +1,24 @@ + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.json b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.json deleted file mode 100644 index dbd6a2d2..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.json +++ /dev/null @@ -1,41 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 26, - 27, - 28 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12 - ], - "ROW_BIT": [ - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.xml new file mode 100644 index 00000000..66341554 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.json b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.json deleted file mode 100644 index e7cbcd22..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.json +++ /dev/null @@ -1,41 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 13, - 14, - 15 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12 - ], - "ROW_BIT": [ - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.xml new file mode 100644 index 00000000..cb042a68 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr4.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr4.xml new file mode 100755 index 00000000..a53b0970 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr4.xml @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json b/DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json deleted file mode 100644 index 7b9f8340..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json +++ /dev/null @@ -1,46 +0,0 @@ -{ - "CONGEN": { - "BANKGROUP_BIT":[ - 28, - 29 - ], - "BANK_BIT": [ - 30, - 31 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12 - ], - "ROW_BIT": [ - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.xml new file mode 100644 index 00000000..83fa9e4c --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.xml @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json b/DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json deleted file mode 100644 index b151bd03..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json +++ /dev/null @@ -1,46 +0,0 @@ -{ - "CONGEN": { - "RANK_BIT":[ - 29 - ], - "BANKGROUP_BIT":[ - 27, - 28 - ], - "BANK_BIT": [ - 25, - 26 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9 - ], - "ROW_BIT": [ - 10, - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.xml new file mode 100644 index 00000000..24cf9469 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.xml @@ -0,0 +1,9 @@ + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_highHits.xml b/DRAMSys/library/resources/configs/amconfigs/am_highHits.xml new file mode 100644 index 00000000..a58f41db --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_highHits.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_highPara.xml b/DRAMSys/library/resources/configs/amconfigs/am_highPara.xml new file mode 100755 index 00000000..da617801 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_highPara.xml @@ -0,0 +1,10 @@ + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_lowHits.xml b/DRAMSys/library/resources/configs/amconfigs/am_lowHits.xml new file mode 100755 index 00000000..4e61ed44 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_lowHits.xml @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_lowPara.xml b/DRAMSys/library/resources/configs/amconfigs/am_lowPara.xml new file mode 100755 index 00000000..c73ccdd4 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_lowPara.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.json b/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.json deleted file mode 100644 index e9b3ac9f..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.json +++ /dev/null @@ -1,42 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 27, - 28, - 29 - ], - "BYTE_BIT": [ - 0 - ], - "COLUMN_BIT": [ - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10 - ], - "ROW_BIT": [ - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.xml new file mode 100644 index 00000000..4844bbf4 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.xml @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_rbc.xml new file mode 100644 index 00000000..c4ae7d76 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_rbc.xml @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ranktest.json b/DRAMSys/library/resources/configs/amconfigs/am_ranktest.json deleted file mode 100644 index 720b214e..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_ranktest.json +++ /dev/null @@ -1,46 +0,0 @@ -{ - "CONGEN": { - "RANK_BIT":[ - 30, - 31 - ], - "BANK_BIT": [ - 27, - 28, - 29 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12 - ], - "ROW_BIT": [ - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml b/DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml new file mode 100644 index 00000000..e0a858fe --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml @@ -0,0 +1,25 @@ + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio.xml new file mode 100755 index 00000000..1af39e8d --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio.xml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json deleted file mode 100644 index 512b8090..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json +++ /dev/null @@ -1,44 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 25, - 26, - 27 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "CHANNEL_BIT": [ - 28, - 29 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11 - ], - "ROW_BIT": [ - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml new file mode 100644 index 00000000..63c29bfc --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json deleted file mode 100644 index 58bc5ce4..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json +++ /dev/null @@ -1,44 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 12, - 13, - 14 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "CHANNEL_BIT": [ - 28, - 29 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11 - ], - "ROW_BIT": [ - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml new file mode 100644 index 00000000..fc952eba --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideioFourBanks.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideioFourBanks.xml new file mode 100755 index 00000000..6c575c0f --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideioFourBanks.xml @@ -0,0 +1,27 @@ + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.json b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.json deleted file mode 100644 index 7f51385c..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.json +++ /dev/null @@ -1,43 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 25, - 26 - ], - "BYTE_BIT": [ - 0, - 1, - 2, - 3 - ], - "CHANNEL_BIT": [ - 27, - 28 - ], - "COLUMN_BIT": [ - 4, - 5, - 6, - 7, - 8, - 9, - 10 - ], - "ROW_BIT": [ - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.xml new file mode 100644 index 00000000..ffce3d26 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json deleted file mode 100644 index cbe47587..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json +++ /dev/null @@ -1,43 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 11, - 12 - ], - "BYTE_BIT": [ - 0, - 1, - 2, - 3 - ], - "CHANNEL_BIT": [ - 27, - 28 - ], - "COLUMN_BIT": [ - 4, - 5, - 6, - 7, - 8, - 9, - 10 - ], - "ROW_BIT": [ - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.xml new file mode 100644 index 00000000..cbed2266 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.json b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.json deleted file mode 100644 index 52d665e5..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.json +++ /dev/null @@ -1,41 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 23, - 24 - ], - "BYTE_BIT": [ - 0, - 1, - 2, - 3 - ], - "CHANNEL_BIT": [ - 25, - 26 - ], - "COLUMN_BIT": [ - 4, - 5, - 6, - 7, - 8, - 9, - 10 - ], - "ROW_BIT": [ - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.xml new file mode 100644 index 00000000..71f71bc8 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.xml @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json deleted file mode 100644 index fc5f8b2a..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json +++ /dev/null @@ -1,41 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 11, - 12 - ], - "BYTE_BIT": [ - 0, - 1, - 2, - 3 - ], - "CHANNEL_BIT": [ - 25, - 26 - ], - "COLUMN_BIT": [ - 4, - 5, - 6, - 7, - 8, - 9, - 10 - ], - "ROW_BIT": [ - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.xml new file mode 100644 index 00000000..49e1a0ba --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.xml @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.json b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.json deleted file mode 100644 index 3040e90a..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.json +++ /dev/null @@ -1,44 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 26, - 27 - ], - "BYTE_BIT": [ - 0, - 1, - 2, - 3 - ], - "CHANNEL_BIT": [ - 28, - 29 - ], - "COLUMN_BIT": [ - 4, - 5, - 6, - 7, - 8, - 9, - 10 - ], - "ROW_BIT": [ - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.xml new file mode 100644 index 00000000..bbf25e41 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json deleted file mode 100644 index 76a9de62..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json +++ /dev/null @@ -1,44 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 11, - 12 - ], - "BYTE_BIT": [ - 0, - 1, - 2, - 3 - ], - "CHANNEL_BIT": [ - 28, - 29 - ], - "COLUMN_BIT": [ - 4, - 5, - 6, - 7, - 8, - 9, - 10 - ], - "ROW_BIT": [ - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.xml new file mode 100644 index 00000000..cd213a33 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.xml @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.json b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.json deleted file mode 100644 index 8c16b58c..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.json +++ /dev/null @@ -1,45 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 27, - 28 - ], - "BYTE_BIT": [ - 0, - 1, - 2, - 3 - ], - "CHANNEL_BIT": [ - 29, - 30 - ], - "COLUMN_BIT": [ - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11 - ], - "ROW_BIT": [ - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.xml new file mode 100644 index 00000000..b330b0cd --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json deleted file mode 100644 index e8d1b1e8..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json +++ /dev/null @@ -1,45 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 12, - 13 - ], - "BYTE_BIT": [ - 0, - 1, - 2, - 3 - ], - "CHANNEL_BIT": [ - 29, - 30 - ], - "COLUMN_BIT": [ - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11 - ], - "ROW_BIT": [ - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.xml new file mode 100644 index 00000000..7973505e --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.json b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.json deleted file mode 100644 index 18ab6414..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.json +++ /dev/null @@ -1,42 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 24, - 25 - ], - "BYTE_BIT": [ - 0, - 1, - 2, - 3 - ], - "CHANNEL_BIT": [ - 26, - 27 - ], - "COLUMN_BIT": [ - 4, - 5, - 6, - 7, - 8, - 9, - 10 - ], - "ROW_BIT": [ - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.xml new file mode 100644 index 00000000..b6de91b9 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json deleted file mode 100644 index 62578383..00000000 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json +++ /dev/null @@ -1,42 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 11, - 12 - ], - "BYTE_BIT": [ - 0, - 1, - 2, - 3 - ], - "CHANNEL_BIT": [ - 26, - 27 - ], - "COLUMN_BIT": [ - 4, - 5, - 6, - 7, - 8, - 9, - 10 - ], - "ROW_BIT": [ - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25 - ] - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.xml new file mode 100644 index 00000000..52235bd4 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.xml @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/congen_extended.xml b/DRAMSys/library/resources/configs/amconfigs/congen_extended.xml new file mode 100644 index 00000000..42617f4a --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/congen_extended.xml @@ -0,0 +1,36 @@ + + + + + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + 22 + 23 + 24 + 25 + 26 + 27 + 28 + 29 + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/orgr_ddr4_4x16Gbx16_dimm_p2KB_brc.xml b/DRAMSys/library/resources/configs/amconfigs/orgr_ddr4_4x16Gbx16_dimm_p2KB_brc.xml new file mode 100644 index 00000000..a4d04ebe --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/orgr_ddr4_4x16Gbx16_dimm_p2KB_brc.xml @@ -0,0 +1,19 @@ + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/rgram-rbc.xml b/DRAMSys/library/resources/configs/amconfigs/rgram-rbc.xml new file mode 100644 index 00000000..c616ec0c --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/rgram-rbc.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/DRAMSys/library/resources/configs/amconfigs/rgram.xml b/DRAMSys/library/resources/configs/amconfigs/rgram.xml new file mode 100644 index 00000000..82e8bea2 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/rgram.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifo.json b/DRAMSys/library/resources/configs/mcconfigs/fifo.json deleted file mode 100644 index ead81d04..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/fifo.json +++ /dev/null @@ -1,15 +0,0 @@ -{ - "mcconfig": { - "PagePolicy": "Open", - "Scheduler": "Fifo", - "RequestBufferSize": 8, - "CmdMux": "Oldest", - "RespQueue": "Fifo", - "RefreshPolicy": "Rankwise", - "RefreshMode": 1, - "RefreshMaxPostponed": 8, - "RefreshMaxPulledin": 8, - "PowerDownPolicy": "NoPowerDown", - "PowerDownTimeout": 100 - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifo.xml b/DRAMSys/library/resources/configs/mcconfigs/fifo.xml new file mode 100644 index 00000000..629ad725 --- /dev/null +++ b/DRAMSys/library/resources/configs/mcconfigs/fifo.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.json b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.json deleted file mode 100644 index 79af805d..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.json +++ /dev/null @@ -1,15 +0,0 @@ -{ - "mcconfig": { - "PagePolicy": "Open", - "Scheduler": "Fifo", - "RequestBufferSize": 8, - "CmdMux": "Strict", - "RespQueue": "Fifo", - "RefreshPolicy": "Rankwise", - "RefreshMode": 1, - "RefreshMaxPostponed": 8, - "RefreshMaxPulledin": 8, - "PowerDownPolicy": "NoPowerDown", - "PowerDownTimeout": 100 - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json deleted file mode 100644 index 78ef5aa3..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json +++ /dev/null @@ -1,15 +0,0 @@ -{ - "mcconfig": { - "PagePolicy": "Open", - "Scheduler": "FrFcfs", - "RequestBufferSize": 8, - "CmdMux": "Oldest", - "RespQueue": "Fifo", - "RefreshPolicy": "Rankwise", - "RefreshMode": 1, - "RefreshMaxPostponed": 8, - "RefreshMaxPulledin": 8, - "PowerDownPolicy": "NoPowerDown", - "PowerDownTimeout": 100 - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml new file mode 100644 index 00000000..dada4e70 --- /dev/null +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.json b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.json deleted file mode 100644 index 70553a0f..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.json +++ /dev/null @@ -1,15 +0,0 @@ -{ - "mcconfig": { - "PagePolicy": "Open", - "Scheduler": "FrFcfsGrp", - "RequestBufferSize": 8, - "CmdMux": "Oldest", - "RespQueue": "Fifo", - "RefreshPolicy": "Rankwise", - "RefreshMode": 1, - "RefreshMaxPostponed": 8, - "RefreshMaxPulledin": 8, - "PowerDownPolicy": "NoPowerDown", - "PowerDownTimeout": 100 - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml new file mode 100644 index 00000000..06104618 --- /dev/null +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/DDR4.xml b/DRAMSys/library/resources/configs/memspecs/DDR4.xml new file mode 100644 index 00000000..db03826f --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/DDR4.xml @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/HBM2.json b/DRAMSys/library/resources/configs/memspecs/HBM2.json deleted file mode 100644 index efa8ee9e..00000000 --- a/DRAMSys/library/resources/configs/memspecs/HBM2.json +++ /dev/null @@ -1,46 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 4, - "dataRate": 2, - "nbrOfBankGroups": 4, - "nbrOfBanks": 16, - "nbrOfColumns": 128, - "nbrOfRanks": 2, - "nbrOfRows": 32768, - "width": 64 - }, - "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", - "memoryType": "HBM2", - "memtimingspec": { - "CCDL": 3, - "CCDS": 2, - "CKE": 8, - "DQSCK": 1, - "FAW": 16, - "PL": 0, - "RAS": 28, - "RC": 42, - "RCDRD": 12, - "RCDWR": 6, - "REFI": 3900, - "REFISB": 244, - "RFC": 220, - "RFCSB": 96, - "RL": 17, - "RP": 14, - "RRDL": 6, - "RRDS": 4, - "RREFD": 8, - "RTP": 5, - "RTW": 18, - "WL": 7, - "WR": 14, - "WTRL": 9, - "WTRS": 4, - "XP": 8, - "XS": 216, - "clkMhz": 1000 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/HBM2.xml b/DRAMSys/library/resources/configs/memspecs/HBM2.xml new file mode 100644 index 00000000..9760bfbf --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/HBM2.xml @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json deleted file mode 100644 index 64256e3c..00000000 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json +++ /dev/null @@ -1,65 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 4, - "dataRate": 1, - "nbrOfBanks": 4, - "nbrOfColumns": 128, - "nbrOfRanks": 1, - "nbrOfRows": 4096, - "width": 128 - }, - "memoryId": "JEDEC_256Mb_WIDEIO_SDR-200_128bit", - "memoryType": "WIDEIO_SDR", - "mempowerspec": { - "idd0": 5.88, - "idd02": 21.18, - "idd2n": 0.13, - "idd2n2": 4.04, - "idd2p0": 0.05, - "idd2p02": 0.17, - "idd2p1": 0.05, - "idd2p12": 0.17, - "idd3n": 0.52, - "idd3n2": 6.55, - "idd3p0": 0.25, - "idd3p02": 1.49, - "idd3p1": 0.25, - "idd3p12": 1.49, - "idd4r": 1.41, - "idd4r2": 85.73, - "idd4w": 1.42, - "idd4w2": 60.79, - "idd5": 14.43, - "idd52": 48.17, - "idd6": 0.07, - "idd62": 0.27, - "vdd": 1.8, - "vdd2": 1.2 - }, - "memtimingspec": { - "AC": 1, - "CCD_R": 2, - "CCD_W": 1, - "CKE": 3, - "CKESR": 3, - "DQSCK": 1, - "RAS": 9, - "RC": 12, - "RCD": 4, - "REFI": 3120, - "RFC": 18, - "RL": 3, - "RP": 4, - "RRD": 2, - "TAW": 10, - "WL": 1, - "WR": 3, - "WTR": 3, - "XP": 2, - "XSR": 20, - "RTRS": 1, - "clkMhz": 200 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml new file mode 100644 index 00000000..99fc35e7 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json deleted file mode 100644 index c2d60cd9..00000000 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json +++ /dev/null @@ -1,65 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 4, - "dataRate": 1, - "nbrOfBanks": 4, - "nbrOfColumns": 128, - "nbrOfRanks": 1, - "nbrOfRows": 4096, - "width": 128 - }, - "memoryId": "JEDEC_256Mb_WIDEIO_SDR-266_128bit", - "memoryType": "WIDEIO_SDR", - "mempowerspec": { - "idd0": 6.06, - "idd02": 21.82, - "idd2n": 0.16, - "idd2n2": 4.76, - "idd2p0": 0.05, - "idd2p02": 0.17, - "idd2p1": 0.05, - "idd2p12": 0.17, - "idd3n": 0.58, - "idd3n2": 7.24, - "idd3p0": 0.25, - "idd3p02": 1.49, - "idd3p1": 0.25, - "idd3p12": 1.49, - "idd4r": 1.82, - "idd4r2": 111.22, - "idd4w": 1.82, - "idd4w2": 78.0, - "idd5": 14.48, - "idd52": 48.34, - "idd6": 0.07, - "idd62": 0.27, - "vdd": 1.8, - "vdd2": 1.2 - }, - "memtimingspec": { - "AC": 1, - "CCD_R": 2, - "CCD_W": 1, - "CKE": 3, - "CKESR": 4, - "DQSCK": 1, - "RAS": 12, - "RC": 16, - "RCD": 5, - "REFI": 4160, - "RFC": 24, - "RL": 3, - "RP": 5, - "RRD": 3, - "TAW": 14, - "WL": 1, - "WR": 4, - "WTR": 4, - "XP": 3, - "XSR": 27, - "RTRS": 1, - "clkMhz": 266 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml new file mode 100644 index 00000000..62abc699 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-200_128bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-200_128bit.xml new file mode 120000 index 00000000..c5badd2e --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-200_128bit.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/JEDEC_256Mb_WIDEIO_SDR-200_128bit.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-266_128bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-266_128bit.xml new file mode 120000 index 00000000..96d9d4b9 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-266_128bit.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/JEDEC_256Mb_WIDEIO_SDR-266_128bit.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json deleted file mode 100644 index c7c0e7a0..00000000 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json +++ /dev/null @@ -1,68 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBankGroups": 4, - "nbrOfBanks": 16, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 32768, - "width": 8 - }, - "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", - "memoryType": "DDR4", - "mempowerspec": { - "idd0": 56.25, - "idd02": 4.05, - "idd2n": 33.75, - "idd2p0": 17.0, - "idd2p1": 17.0, - "idd3n": 39.5, - "idd3p0": 22.5, - "idd3p1": 22.5, - "idd4r": 157.5, - "idd4w": 135.0, - "idd5": 118.0, - "idd6": 20.25, - "idd62": 2.6, - "vdd": 1.2, - "vdd2": 2.5 - }, - "memtimingspec": { - "AL": 0, - "CCD_L": 5, - "CCD_S": 4, - "CKE": 6, - "CKESR": 7, - "CL": 13, - "DQSCK": 2, - "FAW": 22, - "RAS": 32, - "RC": 45, - "RCD": 13, - "REFI": 7280, - "RFC": 243, - "RFC2": 150, - "RFC4": 103, - "RL": 13, - "RP": 13, - "RRD_L": 5, - "RRD_S": 4, - "RTP": 8, - "WL": 12, - "WR": 14, - "WTR_L": 7, - "WTR_S": 3, - "XP": 8, - "XPDLL": 255, - "XS": 252, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 933 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.xml new file mode 100644 index 00000000..d4801b92 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.xml @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json deleted file mode 100644 index 51ac9635..00000000 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json +++ /dev/null @@ -1,68 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBankGroups": 4, - "nbrOfBanks": 16, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 32768, - "width": 8 - }, - "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A", - "memoryType": "DDR4", - "mempowerspec": { - "idd0": 60.75, - "idd02": 4.05, - "idd2n": 38.25, - "idd2p0": 17.0, - "idd2p1": 17.0, - "idd3n": 44.0, - "idd3p0": 22.5, - "idd3p1": 22.5, - "idd4r": 184.5, - "idd4w": 168.75, - "idd5": 118.0, - "idd6": 20.25, - "idd62": 2.6, - "vdd": 1.2, - "vdd2": 2.5 - }, - "memtimingspec": { - "AL": 0, - "CCD_L": 6, - "CCD_S": 4, - "CKE": 6, - "CKESR": 7, - "CL": 16, - "DQSCK": 2, - "FAW": 26, - "RAS": 39, - "RC": 55, - "RCD": 16, - "REFI": 9360, - "RFC": 312, - "RFC2": 192, - "RFC4": 132, - "RL": 16, - "RP": 16, - "RRD_L": 6, - "RRD_S": 4, - "RTP": 12, - "WL": 16, - "WR": 18, - "WTR_L": 9, - "WTR_S": 3, - "XP": 8, - "XPDLL": 325, - "XS": 324, - "XSDLL": 512, - "ACTPDEN": 2, - "PRPDEN": 2, - "REFPDEN": 2, - "RTRS": 1, - "clkMhz": 1200 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.xml new file mode 100644 index 00000000..49b10280 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.xml @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json deleted file mode 100644 index 65be78a0..00000000 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json +++ /dev/null @@ -1,42 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 4, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 512, - "nbrOfRanks": 1, - "nbrOfRows": 8192, - "width": 64 - }, - "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-400_64bit", - "memoryType": "WIDEIO2", - "memtimingspec": { - "CCD": 2, - "CKE": 3, - "CKESR": 6, - "FAW": 24, - "RAS": 17, - "RCAB": 26, - "RCD": 8, - "RCPB": 24, - "REFI": 1560, - "REFIPB": 195, - "REFM": 1, - "RFCAB": 72, - "RFCPB": 36, - "RL": 7, - "RPAB": 9, - "RPPB": 8, - "RRD": 4, - "RTP": 3, - "WL": 5, - "WR": 8, - "WTR": 4, - "XP": 3, - "XSR": 76, - "RTRS": 1, - "clkMhz": 400 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml new file mode 100644 index 00000000..d2c14626 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json deleted file mode 100644 index a01fedb0..00000000 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json +++ /dev/null @@ -1,42 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 4, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 512, - "nbrOfRanks": 1, - "nbrOfRows": 8192, - "width": 64 - }, - "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-533_64bit", - "memoryType": "WIDEIO2", - "memtimingspec": { - "CCD": 2, - "CKE": 3, - "CKESR": 8, - "FAW": 32, - "RAS": 23, - "RCAB": 34, - "RCD": 10, - "RCPB": 32, - "REFI": 2080, - "REFIPB": 260, - "REFM": 1, - "RFCAB": 96, - "RFCPB": 48, - "RL": 9, - "RPAB": 12, - "RPPB": 10, - "RRD": 6, - "RTP": 4, - "WL": 7, - "WR": 11, - "WTR": 6, - "XP": 4, - "XSR": 102, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml new file mode 100644 index 00000000..901e0b21 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json deleted file mode 100644 index c41d427f..00000000 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json +++ /dev/null @@ -1,96 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 16, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 65536, - "width": 16 - }, - "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", - "memoryType": "LPDDR4", - "mempowerspec": { - "idd0": 3.5, - "idd02": 45.0, - "idd0ql": 0.75, - "idd2n": 2.0, - "idd2n2": 27.0, - "idd2nQ": 0.75, - "idd2ns": 2.0, - "idd2ns2": 23.0, - "idd2nsq": 0.75, - "idd2p": 1.2, - "idd2p2": 3.0, - "idd2pQ": 0.75, - "idd2ps": 1.2, - "idd2ps2": 3.0, - "idd2psq": 0.75, - "idd3n": 2.25, - "idd3n2": 30.0, - "idd3nQ": 0.75, - "idd3ns": 2.25, - "idd3ns2": 30.0, - "idd3nsq": 0.75, - "idd3p": 1.2, - "idd3p2": 9.0, - "idd3pQ": 0.75, - "idd3ps": 1.2, - "idd3ps2": 9.0, - "idd3psq": 0.75, - "idd4r": 2.25, - "idd4r2": 275.0, - "idd4rq": 150.0, - "idd4w": 2.25, - "idd4w2": 210.0, - "idd4wq": 55.0, - "idd5": 10.0, - "idd52": 90.0, - "idd5ab": 2.5, - "idd5ab2": 30.0, - "idd5abq": 0.75, - "idd5b": 2.5, - "idd5b2": 30.0, - "idd5bq": 0.75, - "idd5q": 0.75, - "idd6": 0.3, - "idd62": 0.5, - "idd6q": 0.1, - "vdd": 1.8, - "vdd2": 1.1, - "vddq": 1.1 - }, - "memtimingspec": { - "CCD": 8, - "CKE": 12, - "CMDCKE": 3, - "DQS2DQ": 2, - "DQSCK": 6, - "DQSS": 1, - "ESCKE": 3, - "FAW": 64, - "PPD": 4, - "RAS": 68, - "RCD": 29, - "REFI": 6246, - "REFIPB": 780, - "RFCAB": 448, - "RFCPB": 224, - "RL": 28, - "RPAB": 34, - "RPPB": 29, - "RPST": 0, - "RRD": 16, - "RTP": 12, - "SR": 24, - "WL": 14, - "WPRE": 2, - "WR": 29, - "WTR": 16, - "XP": 12, - "XSR": 460, - "clkMhz": 1600 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml new file mode 100644 index 00000000..562e1e07 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json deleted file mode 100644 index aaecf874..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json +++ /dev/null @@ -1,55 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 8192, - "width": 16 - }, - "memoryId": "MICRON_1Gb_DDR2-1066_16bit_H", - "memoryType": "DDR2", - "mempowerspec": { - "idd0": 90.0, - "idd2n": 36.0, - "idd2p0": 7.0, - "idd2p1": 7.0, - "idd3n": 42.0, - "idd3p0": 10.0, - "idd3p1": 23.0, - "idd4r": 180.0, - "idd4w": 185.0, - "idd5": 160.0, - "idd6": 7.0, - "vdd": 1.8 - }, - "memtimingspec": { - "AL": 0, - "CCD": 2, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 24, - "RAS": 24, - "RC": 31, - "RCD": 7, - "REFI": 3120, - "RFC": 68, - "RL": 7, - "RP": 7, - "RRD": 6, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 3, - "XPDLL": 10, - "XS": 74, - "XSDLL": 200, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.xml new file mode 120000 index 00000000..bd42018d --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json deleted file mode 100644 index 33f80da5..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json +++ /dev/null @@ -1,55 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 8192, - "width": 16 - }, - "memoryId": "MICRON_1Gb_DDR2-800_16bit_H", - "memoryType": "DDR2", - "mempowerspec": { - "idd0": 80.0, - "idd2n": 30.0, - "idd2p0": 7.0, - "idd2p1": 7.0, - "idd3n": 35.0, - "idd3p0": 10.0, - "idd3p1": 20.0, - "idd4r": 150.0, - "idd4w": 160.0, - "idd5": 150.0, - "idd6": 7.0, - "vdd": 1.8 - }, - "memtimingspec": { - "AL": 0, - "CCD": 2, - "CKE": 3, - "CKESR": 4, - "CL": 5, - "DQSCK": 0, - "FAW": 18, - "RAS": 16, - "RC": 23, - "RCD": 5, - "REFI": 3120, - "RFC": 51, - "RL": 5, - "RP": 5, - "RRD": 4, - "RTP": 3, - "WL": 4, - "WR": 6, - "WTR": 3, - "XP": 2, - "XPDLL": 8, - "XS": 55, - "XSDLL": 200, - "clkMhz": 400 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.xml new file mode 120000 index 00000000..9934a36c --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR2-800_16bit_H.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json deleted file mode 100644 index 467c599b..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 8192, - "width": 16 - }, - "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 75.0, - "idd2n": 35.0, - "idd2p0": 12.0, - "idd2p1": 25.0, - "idd3n": 45.0, - "idd3p0": 30.0, - "idd3p1": 30.0, - "idd4r": 140.0, - "idd4w": 155.0, - "idd5": 160.0, - "idd6": 8.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 27, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 59, - "RL": 7, - "RP": 7, - "RRD": 6, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 64, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.xml new file mode 120000 index 00000000..4a859eb2 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json deleted file mode 100644 index 6ff10023..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 8192, - "width": 16 - }, - "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_2s", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 70.22, - "idd2n": 30.95, - "idd2p0": 9.07, - "idd2p1": 18.9, - "idd3n": 39.0, - "idd3p0": 26.0, - "idd3p1": 26.0, - "idd4r": 128.59, - "idd4w": 144.31, - "idd5": 150.64, - "idd6": 6.02, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 27, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 59, - "RL": 7, - "RP": 7, - "RRD": 6, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 64, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.xml new file mode 120000 index 00000000..d50dbf7f --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json deleted file mode 100644 index 9b4a0ad8..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 8192, - "width": 16 - }, - "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_3s", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 71.81, - "idd2n": 32.3, - "idd2p0": 10.04, - "idd2p1": 20.93, - "idd3n": 41.0, - "idd3p0": 27.33, - "idd3p1": 27.33, - "idd4r": 132.39, - "idd4w": 147.87, - "idd5": 153.76, - "idd6": 6.68, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 27, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 59, - "RL": 7, - "RP": 7, - "RRD": 6, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 64, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.xml new file mode 120000 index 00000000..143cb949 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json deleted file mode 100644 index 9459ab49..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 8192, - "width": 16 - }, - "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_mu", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 67.04, - "idd2n": 28.25, - "idd2p0": 7.12, - "idd2p1": 14.83, - "idd3n": 35.01, - "idd3p0": 23.34, - "idd3p1": 23.34, - "idd4r": 120.98, - "idd4w": 137.19, - "idd5": 144.41, - "idd6": 4.7, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 27, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 59, - "RL": 7, - "RP": 7, - "RRD": 6, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 64, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.xml new file mode 120000 index 00000000..fda8d2f5 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json deleted file mode 100644 index 5dd17ce0..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 8 - }, - "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 60.0, - "idd2n": 35.0, - "idd2p0": 12.0, - "idd2p1": 25.0, - "idd3n": 40.0, - "idd3p0": 30.0, - "idd3p1": 30.0, - "idd4r": 105.0, - "idd4w": 110.0, - "idd5": 160.0, - "idd6": 8.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 20, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 59, - "RL": 7, - "RP": 7, - "RRD": 4, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 64, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml new file mode 120000 index 00000000..4cff3d2b --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json deleted file mode 100644 index 8f7e730b..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 8 - }, - "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_2s", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 56.18, - "idd2n": 30.95, - "idd2p0": 9.07, - "idd2p1": 18.9, - "idd3n": 34.67, - "idd3p0": 26.0, - "idd3p1": 26.0, - "idd4r": 96.88, - "idd4w": 102.0, - "idd5": 150.64, - "idd6": 6.02, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 20, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 59, - "RL": 7, - "RP": 7, - "RRD": 4, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 64, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.xml new file mode 120000 index 00000000..0b9d2c25 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json deleted file mode 100644 index 315c3fce..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 8 - }, - "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_3s", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 57.45, - "idd2n": 32.3, - "idd2p0": 10.04, - "idd2p1": 20.93, - "idd3n": 36.45, - "idd3p0": 27.33, - "idd3p1": 27.33, - "idd4r": 99.59, - "idd4w": 104.67, - "idd5": 153.76, - "idd6": 6.68, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 20, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 59, - "RL": 7, - "RP": 7, - "RRD": 4, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 64, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.xml new file mode 120000 index 00000000..606fc7ac --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json deleted file mode 100644 index ae39db63..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 8 - }, - "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_mu", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 53.63, - "idd2n": 28.25, - "idd2p0": 7.12, - "idd2p1": 14.83, - "idd3n": 31.12, - "idd3p0": 23.34, - "idd3p1": 23.34, - "idd4r": 91.47, - "idd4w": 96.68, - "idd5": 144.41, - "idd6": 4.7, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 20, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 59, - "RL": 7, - "RP": 7, - "RRD": 4, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 64, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.xml new file mode 120000 index 00000000..eafdd763 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json deleted file mode 100644 index 3020b53b..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 8 - }, - "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 70.0, - "idd2n": 45.0, - "idd2p0": 12.0, - "idd2p1": 30.0, - "idd3n": 45.0, - "idd3p0": 35.0, - "idd3p1": 35.0, - "idd4r": 140.0, - "idd4w": 145.0, - "idd5": 170.0, - "idd6": 8.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 10, - "DQSCK": 0, - "FAW": 24, - "RAS": 28, - "RC": 38, - "RCD": 10, - "REFI": 6240, - "RFC": 88, - "RL": 10, - "RP": 10, - "RRD": 5, - "RTP": 6, - "WL": 8, - "WR": 12, - "WTR": 6, - "XP": 6, - "XPDLL": 20, - "XS": 96, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 800 - } - } -} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml new file mode 120000 index 00000000..a45a1f67 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json deleted file mode 100644 index 6867118b..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 8 - }, - "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_2s", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 65.19, - "idd2n": 40.0, - "idd2p0": 9.07, - "idd2p1": 22.68, - "idd3n": 40.07, - "idd3p0": 31.16, - "idd3p1": 31.16, - "idd4r": 127.49, - "idd4w": 130.17, - "idd5": 159.28, - "idd6": 6.02, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 10, - "DQSCK": 0, - "FAW": 24, - "RAS": 28, - "RC": 38, - "RCD": 10, - "REFI": 6240, - "RFC": 88, - "RL": 10, - "RP": 10, - "RRD": 5, - "RTP": 6, - "WL": 8, - "WR": 12, - "WTR": 6, - "XP": 6, - "XPDLL": 20, - "XS": 96, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 800 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.xml new file mode 120000 index 00000000..df3f9d21 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json deleted file mode 100644 index 2988bf90..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 8 - }, - "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_3s", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 66.79, - "idd2n": 41.67, - "idd2p0": 10.04, - "idd2p1": 25.12, - "idd3n": 41.71, - "idd3p0": 32.44, - "idd3p1": 32.44, - "idd4r": 131.66, - "idd4w": 135.11, - "idd5": 162.85, - "idd6": 6.68, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 10, - "DQSCK": 0, - "FAW": 24, - "RAS": 28, - "RC": 38, - "RCD": 10, - "REFI": 6240, - "RFC": 88, - "RL": 10, - "RP": 10, - "RRD": 5, - "RTP": 6, - "WL": 8, - "WR": 12, - "WTR": 6, - "XP": 6, - "XPDLL": 20, - "XS": 96, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 800 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.xml new file mode 120000 index 00000000..b0dca095 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json deleted file mode 100644 index c6dabf1d..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 8 - }, - "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 70.0, - "idd2n": 45.0, - "idd2p0": 12.0, - "idd2p1": 30.0, - "idd3n": 45.0, - "idd3p0": 35.0, - "idd3p1": 35.0, - "idd4r": 140.0, - "idd4w": 145.0, - "idd5": 170.0, - "idd6": 8.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 10, - "DQSCK": 0, - "FAW": 24, - "RAS": 28, - "RC": 38, - "RCD": 10, - "REFI": 300000000, - "RFC": 88, - "RL": 10, - "RP": 10, - "RRD": 5, - "RTP": 6, - "WL": 8, - "WR": 12, - "WTR": 6, - "XP": 6, - "XPDLL": 20, - "XS": 96, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 800 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.xml new file mode 100644 index 00000000..7a94a932 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.xml @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json deleted file mode 100644 index 9aaa2c4c..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 8 - }, - "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_mu", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 61.99, - "idd2n": 36.68, - "idd2p0": 7.12, - "idd2p1": 17.8, - "idd3n": 36.78, - "idd3p0": 28.61, - "idd3p1": 28.61, - "idd4r": 119.16, - "idd4w": 120.28, - "idd5": 152.13, - "idd6": 4.7, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 10, - "DQSCK": 0, - "FAW": 24, - "RAS": 28, - "RC": 38, - "RCD": 10, - "REFI": 6240, - "RFC": 88, - "RL": 10, - "RP": 10, - "RRD": 5, - "RTP": 6, - "WL": 8, - "WR": 12, - "WTR": 6, - "XP": 6, - "XPDLL": 20, - "XS": 96, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 800 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.xml new file mode 120000 index 00000000..6a87f531 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json deleted file mode 100644 index 0aef9bf9..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 8 - }, - "memoryId": "MICRON_1Gb_DDR3-800_8bit_G", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 60.0, - "idd2n": 35.0, - "idd2p0": 12.0, - "idd2p1": 25.0, - "idd3n": 40.0, - "idd3p0": 30.0, - "idd3p1": 30.0, - "idd4r": 105.0, - "idd4w": 110.0, - "idd5": 160.0, - "idd6": 8.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 5, - "DQSCK": 0, - "FAW": 16, - "RAS": 15, - "RC": 20, - "RCD": 5, - "REFI": 3120, - "RFC": 44, - "RL": 5, - "RP": 5, - "RRD": 4, - "RTP": 4, - "WL": 5, - "WR": 6, - "WTR": 4, - "XP": 3, - "XPDLL": 10, - "XS": 48, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 400 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml new file mode 100644 index 00000000..262feb17 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json deleted file mode 100644 index b8cd6ba9..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 2, - "nbrOfRows": 16384, - "width": 64 - }, - "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 720.0, - "idd2n": 400.0, - "idd2p0": 80.0, - "idd2p1": 200.0, - "idd3n": 440.0, - "idd3p0": 240.0, - "idd3p1": 240.0, - "idd4r": 1200.0, - "idd4w": 1200.0, - "idd5": 1760.0, - "idd6": 48.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 20, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 59, - "RL": 7, - "RP": 7, - "RRD": 4, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 64, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.xml new file mode 120000 index 00000000..bb5a1c55 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json deleted file mode 100644 index d19953e5..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 2, - "nbrOfRows": 16384, - "width": 64 - }, - "memoryId": "MICRON_2GB_DDR3-1066_64bit_G_UDIMM", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 432.0, - "idd2n": 315.0, - "idd2p0": 108.0, - "idd2p1": 225.0, - "idd3n": 360.0, - "idd3p0": 270.0, - "idd3p1": 270.0, - "idd4r": 882.0, - "idd4w": 837.0, - "idd5": 1332.0, - "idd6": 90.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 20, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 59, - "RL": 7, - "RP": 7, - "RRD": 4, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 64, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.xml new file mode 120000 index 00000000..0b6ffbe5 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json deleted file mode 100644 index 2b954795..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 2, - "nbrOfRows": 16384, - "width": 64 - }, - "memoryId": "MICRON_2GB_DDR3-1333_64bit_D_SODIMM", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 800.0, - "idd2n": 440.0, - "idd2p0": 80.0, - "idd2p1": 200.0, - "idd3n": 480.0, - "idd3p0": 280.0, - "idd3p1": 280.0, - "idd4r": 1440.0, - "idd4w": 1520.0, - "idd5": 1920.0, - "idd6": 48.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 4, - "CKESR": 5, - "CL": 9, - "DQSCK": 0, - "FAW": 20, - "RAS": 24, - "RC": 33, - "RCD": 9, - "REFI": 5200, - "RFC": 74, - "RL": 9, - "RP": 9, - "RRD": 4, - "RTP": 5, - "WL": 7, - "WR": 10, - "WTR": 5, - "XP": 4, - "XPDLL": 16, - "XS": 80, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 666 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.xml new file mode 120000 index 00000000..04ae55f6 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json deleted file mode 100644 index ef9a59b8..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 2, - "nbrOfRows": 16384, - "width": 64 - }, - "memoryId": "MICRON_2GB_DDR3-1600_64bit_G_UDIMM", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 522.0, - "idd2n": 405.0, - "idd2p0": 108.0, - "idd2p1": 270.0, - "idd3n": 405.0, - "idd3p0": 315.0, - "idd3p1": 315.0, - "idd4r": 1197.0, - "idd4w": 1152.0, - "idd5": 1422.0, - "idd6": 90.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 5, - "CKESR": 5, - "CL": 10, - "DQSCK": 0, - "FAW": 32, - "RAS": 28, - "RC": 38, - "RCD": 10, - "REFI": 4160, - "RFC": 88, - "RL": 10, - "RP": 10, - "RRD": 6, - "RTP": 6, - "WL": 8, - "WR": 12, - "WTR": 6, - "XP": 5, - "XPDLL": 20, - "XS": 96, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 800 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.xml new file mode 120000 index 00000000..c120ca42 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json deleted file mode 100644 index f135a2e6..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 32768, - "width": 8 - }, - "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 75.0, - "idd2n": 32.0, - "idd2p0": 12.0, - "idd2p1": 25.0, - "idd3n": 35.0, - "idd3p0": 30.0, - "idd3p1": 30.0, - "idd4r": 140.0, - "idd4w": 145.0, - "idd5": 190.0, - "idd6": 12.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 20, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 86, - "RL": 7, - "RP": 7, - "RRD": 4, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 92, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.xml new file mode 120000 index 00000000..7d00687f --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json deleted file mode 100644 index 0cd99819..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 32768, - "width": 8 - }, - "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_2s", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 70.08, - "idd2n": 27.52, - "idd2p0": 8.78, - "idd2p1": 18.29, - "idd3n": 30.6, - "idd3p0": 26.23, - "idd3p1": 26.23, - "idd4r": 128.07, - "idd4w": 131.42, - "idd5": 178.56, - "idd6": 8.41, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 20, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 86, - "RL": 7, - "RP": 7, - "RRD": 4, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 92, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.xml new file mode 120000 index 00000000..86526b8a --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json deleted file mode 100644 index 647e8938..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 32768, - "width": 8 - }, - "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_3s", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 71.72, - "idd2n": 29.02, - "idd2p0": 9.85, - "idd2p1": 20.53, - "idd3n": 32.06, - "idd3p0": 27.48, - "idd3p1": 27.48, - "idd4r": 132.05, - "idd4w": 135.95, - "idd5": 182.37, - "idd6": 9.6, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 20, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 86, - "RL": 7, - "RP": 7, - "RRD": 4, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 92, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.xml new file mode 120000 index 00000000..d972cad7 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json deleted file mode 100644 index 1273f6e2..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 32768, - "width": 8 - }, - "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_mu", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 66.8, - "idd2n": 24.54, - "idd2p0": 6.63, - "idd2p1": 13.82, - "idd3n": 27.67, - "idd3p0": 23.71, - "idd3p1": 23.71, - "idd4r": 120.13, - "idd4w": 122.38, - "idd5": 170.93, - "idd6": 6.01, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 20, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 86, - "RL": 7, - "RP": 7, - "RRD": 4, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 92, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.xml new file mode 120000 index 00000000..d474794e --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json deleted file mode 100644 index a6a5a43a..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 16 - }, - "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 110.0, - "idd2n": 42.0, - "idd2p0": 12.0, - "idd2p1": 40.0, - "idd3n": 45.0, - "idd3p0": 45.0, - "idd3p1": 45.0, - "idd4r": 270.0, - "idd4w": 280.0, - "idd5": 215.0, - "idd6": 12.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 10, - "DQSCK": 0, - "FAW": 32, - "RAS": 28, - "RC": 38, - "RCD": 10, - "REFI": 4160, - "RFC": 128, - "RL": 10, - "RP": 10, - "RRD": 6, - "RTP": 6, - "WL": 8, - "WR": 12, - "WTR": 6, - "XP": 5, - "XPDLL": 20, - "XS": 136, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 800 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.xml new file mode 120000 index 00000000..5bc48f1f --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json deleted file mode 100644 index 768b1cae..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 16 - }, - "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_2s", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 102.83, - "idd2n": 36.89, - "idd2p0": 8.77, - "idd2p1": 29.25, - "idd3n": 38.75, - "idd3p0": 38.75, - "idd3p1": 38.75, - "idd4r": 247.34, - "idd4w": 260.04, - "idd5": 202.17, - "idd6": 8.67, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 10, - "DQSCK": 0, - "FAW": 32, - "RAS": 28, - "RC": 38, - "RCD": 10, - "REFI": 4160, - "RFC": 128, - "RL": 10, - "RP": 10, - "RRD": 6, - "RTP": 6, - "WL": 8, - "WR": 12, - "WTR": 6, - "XP": 5, - "XPDLL": 20, - "XS": 136, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 800 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.xml new file mode 120000 index 00000000..bd7a9c66 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json deleted file mode 100644 index a5b3a676..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 16 - }, - "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_3s", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 105.25, - "idd2n": 38.59, - "idd2p0": 9.85, - "idd2p1": 32.83, - "idd3n": 40.83, - "idd3p0": 40.83, - "idd3p1": 40.83, - "idd4r": 254.89, - "idd4w": 266.69, - "idd5": 206.44, - "idd6": 9.78, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 10, - "DQSCK": 0, - "FAW": 32, - "RAS": 28, - "RC": 38, - "RCD": 10, - "REFI": 4160, - "RFC": 128, - "RL": 10, - "RP": 10, - "RRD": 6, - "RTP": 6, - "WL": 8, - "WR": 12, - "WTR": 6, - "XP": 5, - "XPDLL": 20, - "XS": 136, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 800 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.xml new file mode 120000 index 00000000..b87e5dd4 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json deleted file mode 100644 index a6b86516..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 16 - }, - "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_mu", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 98.06, - "idd2n": 33.49, - "idd2p0": 6.62, - "idd2p1": 22.09, - "idd3n": 34.59, - "idd3p0": 34.59, - "idd3p1": 34.59, - "idd4r": 232.24, - "idd4w": 246.74, - "idd5": 193.62, - "idd6": 6.45, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 10, - "DQSCK": 0, - "FAW": 32, - "RAS": 28, - "RC": 38, - "RCD": 10, - "REFI": 4160, - "RFC": 128, - "RL": 10, - "RP": 10, - "RRD": 6, - "RTP": 6, - "WL": 8, - "WR": 12, - "WTR": 6, - "XP": 5, - "XPDLL": 20, - "XS": 136, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 800 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.xml new file mode 120000 index 00000000..09e6194c --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json deleted file mode 100644 index a75ff24b..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 4, - "nbrOfColumns": 2048, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 16 - }, - "memoryId": "MICRON_2Gb_LPDDR-266_16bit_A", - "memoryType": "LPDDR", - "mempowerspec": { - "idd0": 70.0, - "idd2n": 12.0, - "idd2p0": 0.6, - "idd2p1": 0.6, - "idd3n": 16.0, - "idd3p0": 3.6, - "idd3p1": 3.6, - "idd4r": 105.0, - "idd4w": 105.0, - "idd5": 170.0, - "idd6": 1.7, - "vdd": 1.8 - }, - "memtimingspec": { - "AL": 0, - "CCD": 2, - "CKE": 1, - "CKESR": 2, - "CL": 3, - "DQSCK": 1, - "RAS": 6, - "RC": 9, - "RCD": 3, - "REFI": 2080, - "RFC": 10, - "RL": 3, - "RP": 3, - "RRD": 2, - "RTP": 3, - "WL": 3, - "WR": 2, - "WTR": 1, - "XP": 1, - "XPDLL": 1, - "XS": 15, - "XSDLL": 15, - "clkMhz": 133 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.xml new file mode 120000 index 00000000..e03502fd --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json deleted file mode 100644 index 8b17dc3f..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 4, - "nbrOfColumns": 2048, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 16 - }, - "memoryId": "MICRON_2Gb_LPDDR-333_16bit_A", - "memoryType": "LPDDR", - "mempowerspec": { - "idd0": 100.0, - "idd2n": 15.0, - "idd2p0": 0.6, - "idd2p1": 0.6, - "idd3n": 18.0, - "idd3p0": 3.6, - "idd3p1": 3.6, - "idd4r": 115.0, - "idd4w": 115.0, - "idd5": 170.0, - "idd6": 1.7, - "vdd": 1.8 - }, - "memtimingspec": { - "AL": 0, - "CCD": 2, - "CKE": 1, - "CKESR": 2, - "CL": 3, - "DQSCK": 1, - "RAS": 7, - "RC": 10, - "RCD": 3, - "REFI": 2600, - "RFC": 12, - "RL": 3, - "RP": 3, - "RRD": 2, - "RTP": 3, - "WL": 3, - "WR": 3, - "WTR": 1, - "XP": 1, - "XPDLL": 1, - "XS": 19, - "XSDLL": 19, - "clkMhz": 166 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.xml new file mode 120000 index 00000000..a632efe0 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json deleted file mode 100644 index 8aadde0a..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json +++ /dev/null @@ -1,67 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 16 - }, - "memoryId": "MICRON_2Gb_LPDDR2-1066-S4_16bit_A", - "memoryType": "LPDDR2", - "mempowerspec": { - "idd0": 20.0, - "idd02": 71.0, - "idd2n": 1.7, - "idd2n2": 22.0, - "idd2p0": 0.5, - "idd2p02": 1.7, - "idd2p1": 0.5, - "idd2p12": 1.7, - "idd3n": 1.2, - "idd3n2": 30.0, - "idd3p0": 1.2, - "idd3p02": 4.12, - "idd3p1": 1.2, - "idd3p12": 4.12, - "idd4r": 5.0, - "idd4r2": 226.0, - "idd4w": 10.0, - "idd4w2": 208.0, - "idd5": 15.0, - "idd52": 136.0, - "idd6": 1.2, - "idd62": 2.6, - "vdd": 1.8, - "vdd2": 1.2 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 8, - "CL": 8, - "DQSCK": 2, - "FAW": 27, - "RAS": 23, - "RC": 32, - "RCD": 10, - "REFI": 2080, - "RFC": 70, - "RL": 8, - "RP": 10, - "RRD": 6, - "RTP": 4, - "WL": 4, - "WR": 10, - "WTR": 4, - "XP": 4, - "XPDLL": 4, - "XS": 75, - "XSDLL": 75, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.xml new file mode 120000 index 00000000..eaf99658 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json deleted file mode 100644 index ebe11f7a..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json +++ /dev/null @@ -1,67 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 16 - }, - "memoryId": "MICRON_2Gb_LPDDR2-800-S4_16bit_A", - "memoryType": "LPDDR2", - "mempowerspec": { - "idd0": 20.0, - "idd02": 56.0, - "idd2n": 1.7, - "idd2n2": 21.0, - "idd2p0": 0.5, - "idd2p02": 1.7, - "idd2p1": 0.5, - "idd2p12": 1.7, - "idd3n": 1.2, - "idd3n2": 29.0, - "idd3p0": 1.2, - "idd3p02": 4.12, - "idd3p1": 1.2, - "idd3p12": 4.12, - "idd4r": 5.0, - "idd4r2": 216.0, - "idd4w": 10.0, - "idd4w2": 203.0, - "idd5": 15.0, - "idd52": 136.0, - "idd6": 1.2, - "idd62": 2.6, - "vdd": 1.8, - "vdd2": 1.2 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 6, - "CL": 6, - "DQSCK": 1, - "FAW": 20, - "RAS": 17, - "RC": 24, - "RCD": 8, - "REFI": 1560, - "RFC": 52, - "RL": 6, - "RP": 8, - "RRD": 4, - "RTP": 3, - "WL": 3, - "WR": 6, - "WTR": 3, - "XP": 3, - "XPDLL": 3, - "XS": 56, - "XSDLL": 56, - "clkMhz": 400 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.xml new file mode 120000 index 00000000..dd7c6a81 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json deleted file mode 100644 index 11700aaf..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json +++ /dev/null @@ -1,66 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBankGroups": 4, - "nbrOfBanks": 16, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 32768, - "width": 8 - }, - "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", - "memoryType": "DDR4", - "mempowerspec": { - "idd0": 56.25, - "idd02": 4.05, - "idd2n": 33.75, - "idd2p0": 17.0, - "idd2p1": 17.0, - "idd3n": 39.5, - "idd3p0": 22.5, - "idd3p1": 22.5, - "idd4r": 157.5, - "idd4w": 135.0, - "idd5": 118.0, - "idd6": 20.25, - "idd62": 2.6, - "vdd": 1.2, - "vdd2": 2.5 - }, - "memtimingspec": { - "AL": 0, - "CCD_L": 5, - "CCD_S": 4, - "CKE": 6, - "CKESR": 7, - "CL": 13, - "DQSCK": 2, - "FAW": 22, - "RAS": 32, - "RC": 45, - "RCD": 13, - "REFI": 3644, - "RFC": 243, - "RL": 13, - "RP": 13, - "RRD_L": 5, - "RRD_S": 4, - "RTP": 8, - "WL": 12, - "WR": 14, - "WTR_L": 7, - "WTR_S": 3, - "XP": 8, - "XPDLL": 255, - "XS": 252, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 933 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.xml new file mode 120000 index 00000000..9a22397b --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json deleted file mode 100644 index ed4906cd..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json +++ /dev/null @@ -1,66 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBankGroups": 4, - "nbrOfBanks": 16, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 32768, - "width": 8 - }, - "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A", - "memoryType": "DDR4", - "mempowerspec": { - "idd0": 60.75, - "idd02": 4.05, - "idd2n": 38.25, - "idd2p0": 17.0, - "idd2p1": 17.0, - "idd3n": 44.0, - "idd3p0": 22.5, - "idd3p1": 22.5, - "idd4r": 184.5, - "idd4w": 168.75, - "idd5": 118.0, - "idd6": 20.25, - "idd62": 2.6, - "vdd": 1.2, - "vdd2": 2.5 - }, - "memtimingspec": { - "AL": 0, - "CCD_L": 6, - "CCD_S": 4, - "CKE": 6, - "CKESR": 7, - "CL": 16, - "DQSCK": 2, - "FAW": 26, - "RAS": 39, - "RC": 55, - "RCD": 16, - "REFI": 4680, - "RFC": 313, - "RL": 16, - "RP": 16, - "RRD_L": 6, - "RRD_S": 4, - "RTP": 12, - "WL": 16, - "WR": 18, - "WTR_L": 9, - "WTR_S": 3, - "XP": 8, - "XPDLL": 325, - "XS": 324, - "XSDLL": 512, - "ACTPDEN": 2, - "PRPDEN": 2, - "REFPDEN": 2, - "RTRS": 1, - "clkMhz": 1200 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.xml new file mode 120000 index 00000000..1d9a6b9c --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json deleted file mode 100644 index 35e1fe35..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json +++ /dev/null @@ -1,67 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 32 - }, - "memoryId": "MICRON_4Gb_LPDDR3-1333_32bit_A", - "memoryType": "LPDDR3", - "mempowerspec": { - "idd0": 15.0, - "idd02": 78.0, - "idd2n": 2.0, - "idd2n2": 36.0, - "idd2p0": 0.6, - "idd2p02": 0.87, - "idd2p1": 0.6, - "idd2p12": 0.87, - "idd3n": 2.0, - "idd3n2": 38.0, - "idd3p0": 1.2, - "idd3p02": 8.15, - "idd3p1": 1.2, - "idd3p12": 8.15, - "idd4r": 5.0, - "idd4r2": 243.0, - "idd4w": 10.0, - "idd4w2": 265.0, - "idd5": 40.0, - "idd52": 158.0, - "idd6": 1.0, - "idd62": 3.27, - "vdd": 1.8, - "vdd2": 1.2 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 6, - "CKESR": 12, - "CL": 10, - "DQSCK": 2, - "FAW": 40, - "RAS": 30, - "RC": 40, - "RCD": 12, - "REFI": 2600, - "RFC": 87, - "RL": 10, - "RP": 12, - "RRD": 8, - "RTP": 8, - "WL": 8, - "WR": 12, - "WTR": 8, - "XP": 6, - "XPDLL": 6, - "XS": 94, - "XSDLL": 94, - "clkMhz": 667 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.xml new file mode 120000 index 00000000..65ff62d0 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json deleted file mode 100644 index 60d40c43..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json +++ /dev/null @@ -1,67 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 16384, - "width": 32 - }, - "memoryId": "MICRON_4Gb_LPDDR3-1600_32bit_A", - "memoryType": "LPDDR3", - "mempowerspec": { - "idd0": 15.0, - "idd02": 80.0, - "idd2n": 2.0, - "idd2n2": 38.0, - "idd2p0": 0.6, - "idd2p02": 0.87, - "idd2p1": 0.6, - "idd2p12": 0.87, - "idd3n": 2.0, - "idd3n2": 45.0, - "idd3p0": 1.2, - "idd3p02": 8.15, - "idd3p1": 1.2, - "idd3p12": 8.15, - "idd4r": 5.0, - "idd4r2": 260.0, - "idd4w": 10.0, - "idd4w2": 284.0, - "idd5": 40.0, - "idd52": 160.0, - "idd6": 1.0, - "idd62": 3.27, - "vdd": 1.8, - "vdd2": 1.2 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 6, - "CKESR": 12, - "CL": 12, - "DQSCK": 2, - "FAW": 40, - "RAS": 36, - "RC": 48, - "RCD": 15, - "REFI": 3120, - "RFC": 104, - "RL": 12, - "RP": 15, - "RRD": 8, - "RTP": 8, - "WL": 9, - "WR": 12, - "WTR": 8, - "XP": 6, - "XPDLL": 6, - "XS": 112, - "XSDLL": 112, - "clkMhz": 800 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.xml new file mode 120000 index 00000000..0fda05af --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json deleted file mode 100644 index 17638bb1..00000000 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json +++ /dev/null @@ -1,95 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 16, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 49152, - "width": 16 - }, - "memoryId": "MICRON_6Gb_LPDDR3-3200_16bit_A", - "memoryType": "LPDDR4", - "mempowerspec": { - "idd0": 3.5, - "idd02": 45.0, - "idd0ql": 0.75, - "idd2n": 2.0, - "idd2n2": 27.0, - "idd2nQ": 0.75, - "idd2ns": 2.0, - "idd2ns2": 23.0, - "idd2nsq": 0.75, - "idd2p": 1.2, - "idd2p2": 3.0, - "idd2pQ": 0.75, - "idd2ps": 1.2, - "idd2ps2": 3.0, - "idd2psq": 0.75, - "idd3n": 2.25, - "idd3n2": 30.0, - "idd3nQ": 0.75, - "idd3ns": 2.25, - "idd3ns2": 30.0, - "idd3nsq": 0.75, - "idd3p": 1.2, - "idd3p2": 9.0, - "idd3pQ": 0.75, - "idd3ps": 1.2, - "idd3ps2": 9.0, - "idd3psq": 0.75, - "idd4r": 2.25, - "idd4r2": 275.0, - "idd4rq": 150.0, - "idd4w": 2.25, - "idd4w2": 210.0, - "idd4wq": 55.0, - "idd5": 10.0, - "idd52": 90.0, - "idd5ab": 2.5, - "idd5ab2": 30.0, - "idd5abq": 0.75, - "idd5b": 2.5, - "idd5b2": 30.0, - "idd5bq": 0.75, - "idd5q": 0.75, - "idd6": 0.3, - "idd62": 0.5, - "idd6q": 0.1, - "vdd": 1.8, - "vdd2": 1.1, - "vddq": 1.1 - }, - "memtimingspec": { - "AL": 0, - "CCD": 8, - "CCDMW": 32, - "CKE": 12, - "CKESR": 24, - "CL": 12, - "DQSCK": 3, - "ESCKE": 24, - "FAW": 64, - "PPD": 4, - "RAS": 68, - "RC": 97, - "RCD": 29, - "REFIAB": 6246, - "REFIPB": 780, - "RFCAB": 448, - "RFCPB": 224, - "RL": 28, - "RPAB": 34, - "RPPB": 29, - "RRD": 16, - "RTP": 12, - "WL": 14, - "WR": 29, - "WTR": 16, - "XP": 12, - "XS": 458, - "clkMhz": 1600 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.xml new file mode 100644 index 00000000..506e20b7 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.xml @@ -0,0 +1,98 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/MatzesWideIO-short.xml b/DRAMSys/library/resources/configs/memspecs/MatzesWideIO-short.xml new file mode 100644 index 00000000..09e23645 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MatzesWideIO-short.xml @@ -0,0 +1,65 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/MatzesWideIO.xml b/DRAMSys/library/resources/configs/memspecs/MatzesWideIO.xml new file mode 100644 index 00000000..22996aa3 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MatzesWideIO.xml @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json deleted file mode 100644 index 41f5cef2..00000000 --- a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 8192, - "width": 16 - }, - "memoryId": "SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 75.0, - "idd2n": 40.0, - "idd2p0": 10.0, - "idd2p1": 25.0, - "idd3n": 55.0, - "idd3p0": 40.0, - "idd3p1": 40.0, - "idd4r": 180.0, - "idd4w": 190.0, - "idd5": 170.0, - "idd6": 10.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 4, - "CKESR": 5, - "CL": 11, - "DQSCK": 0, - "FAW": 32, - "RAS": 28, - "RC": 39, - "RCD": 11, - "REFI": 6240, - "RFC": 88, - "RL": 11, - "RP": 11, - "RRD": 6, - "RTP": 6, - "WL": 8, - "WR": 12, - "WTR": 6, - "XP": 5, - "XPDLL": 20, - "XS": 96, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 800 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml new file mode 120000 index 00000000..23f3dba5 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml @@ -0,0 +1 @@ +../../../src/common/third_party/DRAMPower/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json deleted file mode 100644 index ca86b2d5..00000000 --- a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfRows": 32768, - "width": 16 - }, - "memoryId": "SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 125.0, - "idd2n": 34.0, - "idd2p0": 16.0, - "idd2p1": 55.0, - "idd3n": 60.0, - "idd3p0": 70.0, - "idd3p1": 70.0, - "idd4r": 412.0, - "idd4w": 402.0, - "idd5": 395.0, - "idd6": 22.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 6, - "CKESR": 5, - "CL": 6, - "DQSCK": 0, - "FAW": 27, - "RAS": 20, - "RC": 27, - "RCD": 8, - "REFI": 4160, - "RFC": 160, - "RL": 6, - "RP": 8, - "RRD": 6, - "RTP": 6, - "WL": 5, - "WR": 8, - "WTR": 6, - "XP": 4, - "XPDLL": 13, - "XS": 64, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.xml b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.xml new file mode 100644 index 00000000..e4c571e3 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.xml @@ -0,0 +1,67 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/memspec.dtd b/DRAMSys/library/resources/configs/memspecs/memspec.dtd new file mode 100644 index 00000000..f94ed9e9 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/memspec.dtd @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json deleted file mode 100644 index 88044fdd..00000000 --- a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 4, - "nbrOfRows": 16384, - "width": 8 - }, - "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 70.0, - "idd2n": 45.0, - "idd2p0": 12.0, - "idd2p1": 30.0, - "idd3n": 45.0, - "idd3p0": 35.0, - "idd3p1": 35.0, - "idd4r": 140.0, - "idd4w": 145.0, - "idd5": 170.0, - "idd6": 8.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 10, - "DQSCK": 0, - "FAW": 24, - "RAS": 28, - "RC": 38, - "RCD": 10, - "REFI": 6240, - "RFC": 88, - "RL": 10, - "RP": 10, - "RRD": 5, - "RTP": 6, - "WL": 8, - "WR": 12, - "WTR": 6, - "XP": 6, - "XPDLL": 20, - "XS": 96, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 800 - } - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml new file mode 100644 index 00000000..b4e43e4d --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4.xml b/DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4.xml new file mode 100644 index 00000000..42105d48 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4.xml @@ -0,0 +1,77 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4_2x.xml b/DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4_2x.xml new file mode 100644 index 00000000..a41e1e57 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4_2x.xml @@ -0,0 +1,77 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4_4x.xml b/DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4_4x.xml new file mode 100644 index 00000000..2b56ba2d --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4_4x.xml @@ -0,0 +1,77 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/rgrspec.xml b/DRAMSys/library/resources/configs/memspecs/rgrspec.xml new file mode 100644 index 00000000..52d20f56 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/rgrspec.xml @@ -0,0 +1,73 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/wideio.xml b/DRAMSys/library/resources/configs/memspecs/wideio.xml new file mode 100644 index 00000000..fbe252d6 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/wideio.xml @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/wideio_less_refresh.xml b/DRAMSys/library/resources/configs/memspecs/wideio_less_refresh.xml new file mode 100644 index 00000000..f8aa3190 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/wideio_less_refresh.xml @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json b/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json deleted file mode 100644 index a1621422..00000000 --- a/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json +++ /dev/null @@ -1,21 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": true, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, - "PowerAnalysis": true, - "SimulationName": "ddr3_single_dev", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr3-single-device.xml b/DRAMSys/library/resources/configs/simulator/ddr3-single-device.xml new file mode 100644 index 00000000..7045a52a --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/ddr3-single-device.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.json b/DRAMSys/library/resources/configs/simulator/ddr3.json deleted file mode 100644 index 4e9faadc..00000000 --- a/DRAMSys/library/resources/configs/simulator/ddr3.json +++ /dev/null @@ -1,21 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, - "PowerAnalysis": false, - "SimulationName": "ddr3", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.xml b/DRAMSys/library/resources/configs/simulator/ddr3.xml new file mode 100644 index 00000000..276dde8e --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/ddr3.xml @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json b/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json deleted file mode 100644 index fd35bdee..00000000 --- a/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json +++ /dev/null @@ -1,21 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 2147483648, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": true, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, - "PowerAnalysis": true, - "SimulationName": "ddr3", - "SimulationProgressBar": true, - "StoreMode": "Store", - "ThermalSimulation": false, - "UseMalloc": true, - "WindowSize": 1000 - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.xml b/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.xml new file mode 100644 index 00000000..da5a47a1 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.xml @@ -0,0 +1,28 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json b/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json deleted file mode 100644 index 2b813f99..00000000 --- a/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json +++ /dev/null @@ -1,21 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Hamming", - "EnableWindowing": true, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, - "PowerAnalysis": true, - "SimulationName": "ddr3", - "SimulationProgressBar": true, - "StoreMode": "ErrorModel", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_ecc.xml b/DRAMSys/library/resources/configs/simulator/ddr3_ecc.xml new file mode 100644 index 00000000..8e976731 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/ddr3_ecc.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json b/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json deleted file mode 100644 index 72ebcf9b..00000000 --- a/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json +++ /dev/null @@ -1,21 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": true, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, - "PowerAnalysis": true, - "SimulationName": "ddr3", - "SimulationProgressBar": true, - "StoreMode": "Store", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.xml b/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.xml new file mode 100644 index 00000000..ee39f175 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.xml @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/ddr4.json b/DRAMSys/library/resources/configs/simulator/ddr4.json deleted file mode 100644 index 8e62e680..00000000 --- a/DRAMSys/library/resources/configs/simulator/ddr4.json +++ /dev/null @@ -1,21 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, - "PowerAnalysis": false, - "SimulationName": "ddr4", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr4.xml b/DRAMSys/library/resources/configs/simulator/ddr4.xml new file mode 100644 index 00000000..8975c326 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/ddr4.xml @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/hbm2.json b/DRAMSys/library/resources/configs/simulator/hbm2.json deleted file mode 100644 index 9589611f..00000000 --- a/DRAMSys/library/resources/configs/simulator/hbm2.json +++ /dev/null @@ -1,21 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, - "PowerAnalysis": false, - "SimulationName": "hbm2", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/hbm2.xml b/DRAMSys/library/resources/configs/simulator/hbm2.xml new file mode 100644 index 00000000..3bf50046 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/hbm2.xml @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/lpddr4.json b/DRAMSys/library/resources/configs/simulator/lpddr4.json deleted file mode 100644 index fd8fe855..00000000 --- a/DRAMSys/library/resources/configs/simulator/lpddr4.json +++ /dev/null @@ -1,21 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, - "PowerAnalysis": false, - "SimulationName": "lpddr4", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/lpddr4.xml b/DRAMSys/library/resources/configs/simulator/lpddr4.xml new file mode 100644 index 00000000..87b02763 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/lpddr4.xml @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/orgr.xml b/DRAMSys/library/resources/configs/simulator/orgr.xml new file mode 100644 index 00000000..0ebb9544 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/orgr.xml @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml b/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml new file mode 100644 index 00000000..d284a045 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml b/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml new file mode 100644 index 00000000..3dd9dc0e --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml b/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml new file mode 100644 index 00000000..784719a1 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml b/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml new file mode 100644 index 00000000..79c60e13 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/orgr_ddr4.xml b/DRAMSys/library/resources/configs/simulator/orgr_ddr4.xml new file mode 100644 index 00000000..866c0403 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/orgr_ddr4.xml @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.xml b/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.xml new file mode 100644 index 00000000..47c6a016 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.xml @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.xml b/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.xml new file mode 100644 index 00000000..215846a6 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.xml @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/rgrsimcfg.xml b/DRAMSys/library/resources/configs/simulator/rgrsimcfg.xml new file mode 100644 index 00000000..569ac4d6 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/rgrsimcfg.xml @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/sms.xml b/DRAMSys/library/resources/configs/simulator/sms.xml new file mode 100644 index 00000000..28887877 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/sms.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/wideio.json b/DRAMSys/library/resources/configs/simulator/wideio.json deleted file mode 100644 index 4a0bd0ee..00000000 --- a/DRAMSys/library/resources/configs/simulator/wideio.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "simconfig": { - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": true, - "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", - "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 4, - "PowerAnalysis": true, - "SimulationName": "wideio", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/wideio.xml b/DRAMSys/library/resources/configs/simulator/wideio.xml new file mode 100644 index 00000000..acd95599 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/wideio.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/wideio_ecc.json b/DRAMSys/library/resources/configs/simulator/wideio_ecc.json deleted file mode 100644 index 216d3623..00000000 --- a/DRAMSys/library/resources/configs/simulator/wideio_ecc.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "simconfig": { - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Hamming", - "EnableWindowing": true, - "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", - "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, - "PowerAnalysis": true, - "SimulationName": "wideio_ecc", - "SimulationProgressBar": true, - "StoreMode": "ErrorModel", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/wideio_ecc.xml b/DRAMSys/library/resources/configs/simulator/wideio_ecc.xml new file mode 100644 index 00000000..ee16313a --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/wideio_ecc.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/wideio_thermal.json b/DRAMSys/library/resources/configs/simulator/wideio_thermal.json deleted file mode 100644 index 6a47ff5b..00000000 --- a/DRAMSys/library/resources/configs/simulator/wideio_thermal.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "simconfig": { - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": true, - "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", - "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 4, - "PowerAnalysis": true, - "SimulationName": "wideio", - "SimulationProgressBar": true, - "StoreMode": "ErrorModel", - "ThermalSimulation": true, - "UseMalloc": false, - "WindowSize": 1000 - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/wideio_thermal.xml b/DRAMSys/library/resources/configs/simulator/wideio_thermal.xml new file mode 100644 index 00000000..fee9e00d --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/wideio_thermal.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/thermalsim/config.json b/DRAMSys/library/resources/configs/thermalsim/config.json deleted file mode 100644 index b88ed84c..00000000 --- a/DRAMSys/library/resources/configs/thermalsim/config.json +++ /dev/null @@ -1,15 +0,0 @@ -{ - "thermalsimconfig": { - "TemperatureScale": "Celsius", - "StaticTemperatureDefaultValue": 89, - "ThermalSimPeriod":100, - "ThermalSimUnit":"us", - "PowerInfoFile": "powerInfo.json", - "IceServerIp": "127.0.0.1", - "IceServerPort": 11880, - "SimPeriodAdjustFactor" : 10, - "NPowStableCyclesToIncreasePeriod": 5, - "GenerateTemperatureMap": true, - "GeneratePowerMap": true - } -} diff --git a/DRAMSys/library/resources/configs/thermalsim/config.xml b/DRAMSys/library/resources/configs/thermalsim/config.xml new file mode 100644 index 00000000..4d32315e --- /dev/null +++ b/DRAMSys/library/resources/configs/thermalsim/config.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/thermalsim/powerInfo.json b/DRAMSys/library/resources/configs/thermalsim/powerInfo.json deleted file mode 100644 index 524f690f..00000000 --- a/DRAMSys/library/resources/configs/thermalsim/powerInfo.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "powerInfo": { - "dram_die_channel0": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel1": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel2": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel3": { - "init_pow": 0, - "threshold": 1.0 - } - } -} diff --git a/DRAMSys/library/resources/configs/thermalsim/powerInfo.xml b/DRAMSys/library/resources/configs/thermalsim/powerInfo.xml new file mode 100644 index 00000000..192cb4ea --- /dev/null +++ b/DRAMSys/library/resources/configs/thermalsim/powerInfo.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/DRAMSys/library/resources/resources.pri b/DRAMSys/library/resources/resources.pri new file mode 100644 index 00000000..ddd5d42b --- /dev/null +++ b/DRAMSys/library/resources/resources.pri @@ -0,0 +1,259 @@ +# Relative paths to "DRAMSys/library" because this file is included in +# "DRAMSys/library/library.pro" + +# Simulation Files +DISTFILES += resources/simulations/ddr3-example.xml +DISTFILES += resources/simulations/ddr3-single-device.xml +DISTFILES += resources/simulations/ddr3-rgr.xml +DISTFILES += resources/simulations/ddr3-rgr00.xml +DISTFILES += resources/simulations/ddr3-rgr01.xml +DISTFILES += resources/simulations/ddr3-rgr02.xml +DISTFILES += resources/simulations/ddr3-rgr03.xml +DISTFILES += resources/simulations/ddr3-rgr04.xml +DISTFILES += resources/simulations/ddr3-rgr05.xml +DISTFILES += resources/simulations/ddr3-rgr06.xml +DISTFILES += resources/simulations/ddr3-rgr07.xml +DISTFILES += resources/simulations/ddr3-rgr08.xml +DISTFILES += resources/simulations/ddr3-rgr09.xml +DISTFILES += resources/simulations/ddr3-rgr10.xml +DISTFILES += resources/simulations/ddr3-rgr11.xml +DISTFILES += resources/simulations/ddr3-rgr12.xml +DISTFILES += resources/simulations/ddr3-rgr13.xml +DISTFILES += resources/simulations/ddr3-rgr14.xml +DISTFILES += resources/simulations/ddr3-rgr15.xml +DISTFILES += resources/simulations/ddr3-rgr16.xml +DISTFILES += resources/simulations/ddr3-rgr17.xml +DISTFILES += resources/simulations/ddr3-rgr18.xml +DISTFILES += resources/simulations/ddr3-rgr19.xml +DISTFILES += resources/simulations/ddr3-rgr20.xml +DISTFILES += resources/simulations/ddr3-rgr21.xml +DISTFILES += resources/simulations/ddr3-rgr22.xml +DISTFILES += resources/simulations/ddr3-rgr23.xml +DISTFILES += resources/simulations/ddr3-rgr24.xml +DISTFILES += resources/simulations/ddr3-rgr25.xml +DISTFILES += resources/simulations/ddr3-rgr26.xml +DISTFILES += resources/simulations/ddr3-rgr27.xml +DISTFILES += resources/simulations/ddr3-rgr28.xml +DISTFILES += resources/simulations/ddr3-rgr29.xml +DISTFILES += resources/simulations/ddr3-rgr30.xml +DISTFILES += resources/simulations/ddr3-rgr31.xml +DISTFILES += resources/simulations/ddr3-rgr32.xml +DISTFILES += resources/simulations/ddr3-rgr33.xml +DISTFILES += resources/simulations/ddr3-rgr34.xml +DISTFILES += resources/simulations/ddr3-rgr35.xml +DISTFILES += resources/simulations/ddr3-rgr36.xml +DISTFILES += resources/simulations/ddr3-rgr37.xml +DISTFILES += resources/simulations/ddr3-rgr38.xml +DISTFILES += resources/simulations/ddr3-rgr39.xml +DISTFILES += resources/simulations/ddr3-rgr40.xml +DISTFILES += resources/simulations/ddr3-rgr41.xml +DISTFILES += resources/simulations/ddr3-rgr42.xml +DISTFILES += resources/simulations/ddr3-rgr43.xml +DISTFILES += resources/simulations/ddr3-rgr44.xml +DISTFILES += resources/simulations/wideio-example.xml +DISTFILES += resources/simulations/wideio-ecc.xml +DISTFILES += resources/simulations/ddr3-ecc.xml +DISTFILES += resources/simulations/sms-example.xml +DISTFILES += resources/simulations/ddr3_postpone_ref_test.xml +DISTFILES += resources/simulations/rgrsim.xml +DISTFILES += resources/simulations/lpddr4-single-device.xml + +# Simulator Files +DISTFILES += resources/configs/simulator/wideio.xml +DISTFILES += resources/configs/simulator/ddr3.xml +DISTFILES += resources/configs/simulator/ddr3-single-device.xml +DISTFILES += resources/configs/simulator/wideio_thermal.xml +DISTFILES += resources/configs/simulator/wideio_ecc.xml +DISTFILES += resources/configs/simulator/ddr3_ecc.xml +DISTFILES += resources/configs/simulator/sms.xml +DISTFILES += resources/configs/simulator/rgrsimcfg.xml +DISTFILES += resources/configs/simulator/lpddr4.xml + +# Scripts +DISTFILES += resources/scripts/address_scrambler.pl +DISTFILES += resources/scripts/createTraceDB.sql +DISTFILES += resources/scripts/stride_detection.pl +DISTFILES += resources/scripts/analyse_trace.pl +DISTFILES += resources/scripts/video_rendering/temperatur.job.pl +DISTFILES += resources/scripts/video_rendering/temperatur.pl +DISTFILES += resources/scripts/video_rendering/Makefile +DISTFILES += resources/scripts/DRAMSylva/collect.sh +DISTFILES += resources/scripts/DRAMSylva/common.in +DISTFILES += resources/scripts/DRAMSylva/DRAMSylva.jobscript +DISTFILES += resources/scripts/DRAMSylva/DRAMSylva.sh +DISTFILES += resources/scripts/DRAMSylva/DRAMSylvaCSVPlot.py +DISTFILES += resources/scripts/DRAMSylva/DRAMSyrup.py +DISTFILES += resources/scripts/DRAMSylva/gem5ilva.jobscript +DISTFILES += resources/scripts/DRAMSylva/gem5ilva.sh +DISTFILES += resources/scripts/DRAMSylva/gem5ilva_fs.jobscript +DISTFILES += resources/scripts/DRAMSylva/gem5ilva_fs.sh +DISTFILES += resources/scripts/DRAMSylva/LICENSE +DISTFILES += resources/scripts/DRAMSylva/README +DISTFILES += resources/scripts/DRAMSylva/configs_json/configs.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc1x.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc1x_gem5.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc2x.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc2x_gem5.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc4x.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc4x_gem5.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x_gem5.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x_gem5_fs.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x_gem5_fs_nodb.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc2x.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc2x_gem5.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc4x.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc4x_gem5.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/ref.json +DISTFILES += resources/scripts/DRAMSylva/configs_json/ref_bw.json +DISTFILES += resources/scripts/trace_gen.py +DISTFILES += resources/scripts/traceGenerationForNNTraining.pl + + +# Trace Files +DISTFILES += resources/traces/chstone-aes_32.stl +DISTFILES += resources/traces/test2.stl +DISTFILES += resources/traces/voco2.stl +DISTFILES += resources/traces/chstone-bf_32.stl +DISTFILES += resources/traces/trace2.stl +DISTFILES += resources/traces/chstone-sha_32.stl +DISTFILES += resources/traces/prettyTest +DISTFILES += resources/traces/test.stl +DISTFILES += resources/traces/mediabench-mpeg2encode_32.stl +DISTFILES += resources/traces/mediabench-unepic_32.stl +DISTFILES += resources/traces/chstone-mips_32.stl +DISTFILES += resources/traces/mediabench-gsmdecode_32.stl +DISTFILES += resources/traces/mediabench-c-ray-1.1_32.stl +DISTFILES += resources/traces/eiersalat.stl +DISTFILES += resources/traces/mediabench-fractal_32.stl +DISTFILES += resources/traces/wideio_multi_channel.stl +DISTFILES += resources/traces/mediabench-g721decode_32.stl +DISTFILES += resources/traces/mediabench-jpegencode_32.stl +DISTFILES += resources/traces/chstone-jpeg_32.stl +DISTFILES += resources/traces/trace.stl +DISTFILES += resources/traces/mediabench-h263decode_32.stl +DISTFILES += resources/traces/mediabench-h263encode_32.stl +DISTFILES += resources/traces/mediabench-mpeg2decode_32.stl +DISTFILES += resources/traces/chstone-gsm_32.stl +DISTFILES += resources/traces/mediabench-epic_32.stl +DISTFILES += resources/traces/empty.stl +DISTFILES += resources/traces/mediabench-adpcmencode_32.stl +DISTFILES += resources/traces/chstone-adpcm_32.stl +DISTFILES += resources/traces/mediabench-jpegdecode_32.stl +DISTFILES += resources/traces/mediabench-g721encode_32.stl +DISTFILES += resources/traces/small.stl +DISTFILES += resources/traces/chstone-motion_32.stl +DISTFILES += resources/traces/mediabench-adpcmdecode_32.stl +DISTFILES += resources/traces/ddr3_example.stl +DISTFILES += resources/traces/ddr3_exampleb.stl +DISTFILES += resources/traces/ddr3_rgr.stl +DISTFILES += resources/traces/ddr3_single_dev_example.stl +DISTFILES += resources/traces/ddr3_SAMSUNG_M471B5674QH0_DIMM_example.stl +DISTFILES += resources/traces/test_ecc.stl +DISTFILES += resources/traces/sms_t1.stl +DISTFILES += resources/traces/sms_t2.stl +DISTFILES += resources/traces/sms_t3.stl +DISTFILES += resources/traces/sms_t4.stl +DISTFILES += resources/traces/ddr3_postpone_ref_test_1.stl +DISTFILES += resources/traces/ddr3_postpone_ref_test_2.stl +DISTFILES += resources/traces/ddr3_postpone_ref_test_3.stl +DISTFILES += resources/traces/ip*.stl +DISTFILES += resources/traces/rgr*.stl +DISTFILES += resources/traces/read_write_switch.stl + +# Memory Controller Configs +DISTFILES += resources/configs/mcconfigs/fifoStrict.xml +DISTFILES += resources/configs/mcconfigs/fifo.xml +DISTFILES += resources/configs/mcconfigs/fr_fcfs.xml +DISTFILES += resources/configs/mcconfigs/par_bs.xml +DISTFILES += resources/configs/mcconfigs/fifo_ecc.xml +DISTFILES += resources/configs/mcconfigs/sms.xml +DISTFILES += resources/configs/mcconfigs/rgrmccfg.xml +DISTFILES += resources/configs/mcconfigs/grp.xml +DISTFILES += resources/configs/mcconfigs/fr_fcfs_rp.xml +DISTFILES += resources/configs/mcconfigs/fr_fcfs_grp.xml + +# Memspecs +DISTFILES += resources/configs/memspecs/memspec.dtd +DISTFILES += resources/configs/memspecs/MatzesWideIO.xml +DISTFILES += resources/configs/memspecs/DDR4.xml +DISTFILES += resources/configs/memspecs/MatzesWideIO-short.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml +DISTFILES += resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-200_128bit.xml +DISTFILES += resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-266_128bit.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.xml +DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.xml +DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.xml +DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.xml +DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.xml +DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.xml +DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.xml +DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.xml +DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.xml +DISTFILES += resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.xml +DISTFILES += resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.xml +DISTFILES += resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.xml +DISTFILES += resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.xml +DISTFILES += resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.xml +DISTFILES += resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.xml +DISTFILES += resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.xml +DISTFILES += resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.xml +DISTFILES += resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml +DISTFILES += resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.xml +DISTFILES += resources/configs/memspecs/orgr_16Gb_ddr4.xml +DISTFILES += resources/configs/memspecs/wideio.xml +DISTFILES += resources/configs/memspecs/wideio_less_refresh.xml +DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.xml +DISTFILES += resources/configs/memspecs/rgrspec.xml +DISTFILES += resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_NDA_NDA_NDA.xml + +# Address Mapping Configs +DISTFILES += resources/configs/amconfigs/am_ddr3.xml +DISTFILES += resources/configs/amconfigs/am_ddr3_x16_brc.xml +DISTFILES += resources/configs/amconfigs/am_ddr3_x16_rbc.xml +DISTFILES += resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml +DISTFILES += resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml +DISTFILES += resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.xml +DISTFILES += resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.xml +DISTFILES += resources/configs/amconfigs/resources/configs/amconfigs/am_ddr4.xml +DISTFILES += resources/configs/amconfigs/am_highHits.xml +DISTFILES += resources/configs/amconfigs/am_highPara.xml +DISTFILES += resources/configs/amconfigs/am_wideio.xml +DISTFILES += resources/configs/amconfigs/am_lowHits.xml +DISTFILES += resources/configs/amconfigs/am_lowPara.xml +DISTFILES += resources/configs/amconfigs/am_wideioFourBanks.xml +DISTFILES += resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml +DISTFILES += resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml +DISTFILES += resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml +DISTFILES += resources/configs/amconfigs/rgram.xml +DISTFILES += resources/configs/amconfigs/am_test_congen_output.json +DISTFILES += resources/configs/amconfigs/am_lpddr4.xml + +# Thermal Simulation configs +DISTFILES += resources/configs/thermalsim/core.flp +DISTFILES += resources/configs/thermalsim/mem.flp +DISTFILES += resources/configs/thermalsim/powerInfo.xml +DISTFILES += resources/configs/thermalsim/stack.stk +DISTFILES += resources/configs/thermalsim/config.xml + +# Add DRAMPower +DISTFILES += src/common/third_party/DRAMPower/* +DISTFILES += src/common/third_party/DRAMPower/src/* + +# Error Simulation data +DISTFILES += resources/error/wideio.csv diff --git a/DRAMSys/library/resources/simulations/ddr3-boot-linux.json b/DRAMSys/library/resources/simulations/ddr3-boot-linux.json deleted file mode 100644 index a6e544a2..00000000 --- a/DRAMSys/library/resources/simulations/ddr3-boot-linux.json +++ /dev/null @@ -1,10 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json", - "mcconfig": "fifoStrict.json", - "memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json", - "simconfig": "ddr3_boot_linux.json", - "simulationid": "ddr3-boot-linux", - "thermalconfig": "config.json" - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/simulations/ddr3-boot-linux.xml b/DRAMSys/library/resources/simulations/ddr3-boot-linux.xml new file mode 100644 index 00000000..4817ba0b --- /dev/null +++ b/DRAMSys/library/resources/simulations/ddr3-boot-linux.xml @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/simulations/ddr3-ecc.json b/DRAMSys/library/resources/simulations/ddr3-ecc.json deleted file mode 100644 index 5847f6ad..00000000 --- a/DRAMSys/library/resources/simulations/ddr3-ecc.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json", - "mcconfig": "fifo.json", - "memspec": "MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json", - "simconfig": "ddr3_ecc.json", - "simulationid": "ddr3-ecc", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 1000, - "name": "test_ecc.stl" - } - ] - } -} diff --git a/DRAMSys/library/resources/simulations/ddr3-ecc.xml b/DRAMSys/library/resources/simulations/ddr3-ecc.xml new file mode 100644 index 00000000..91df0e50 --- /dev/null +++ b/DRAMSys/library/resources/simulations/ddr3-ecc.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + test_ecc.stl + + diff --git a/DRAMSys/library/resources/simulations/ddr3-example.json b/DRAMSys/library/resources/simulations/ddr3-example.json deleted file mode 100644 index 7a5d7c16..00000000 --- a/DRAMSys/library/resources/simulations/ddr3-example.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json", - "mcconfig": "fifoStrict.json", - "memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json", - "simconfig": "ddr3.json", - "simulationid": "ddr3-example", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 800, - "name": "ddr3_example.stl" - } - ] - } -} diff --git a/DRAMSys/library/resources/simulations/ddr3-example.xml b/DRAMSys/library/resources/simulations/ddr3-example.xml new file mode 100644 index 00000000..2c948758 --- /dev/null +++ b/DRAMSys/library/resources/simulations/ddr3-example.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + ddr3_example.stl + + diff --git a/DRAMSys/library/resources/simulations/ddr3-example2.json b/DRAMSys/library/resources/simulations/ddr3-example2.json deleted file mode 100644 index a3886b55..00000000 --- a/DRAMSys/library/resources/simulations/ddr3-example2.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json", - "mcconfig": "fifoStrict.json", - "memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json", - "simconfig": "ddr3.json", - "simulationid": "ddr3-example2", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 300, - "name": "ddr3_example.stl" - }, - { - "clkMhz": 400, - "name": "ddr3_example.stl" - } - ] - } -} diff --git a/DRAMSys/library/resources/simulations/ddr3-example2.xml b/DRAMSys/library/resources/simulations/ddr3-example2.xml new file mode 100644 index 00000000..3bd34757 --- /dev/null +++ b/DRAMSys/library/resources/simulations/ddr3-example2.xml @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + ddr3_example.stl + ddr3_example.stl + + diff --git a/DRAMSys/library/resources/simulations/ddr3-gem5-se.json b/DRAMSys/library/resources/simulations/ddr3-gem5-se.json deleted file mode 100644 index 51b870ad..00000000 --- a/DRAMSys/library/resources/simulations/ddr3-gem5-se.json +++ /dev/null @@ -1,10 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json", - "mcconfig": "fifoStrict.json", - "memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json", - "simconfig": "ddr3_gem5_se.json", - "simulationid": "ddr3-gem5-se", - "thermalconfig": "config.json" - } -} \ No newline at end of file diff --git a/DRAMSys/library/resources/simulations/ddr3-gem5-se.xml b/DRAMSys/library/resources/simulations/ddr3-gem5-se.xml new file mode 100644 index 00000000..480a4131 --- /dev/null +++ b/DRAMSys/library/resources/simulations/ddr3-gem5-se.xml @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/simulations/ddr3-single-device.json b/DRAMSys/library/resources/simulations/ddr3-single-device.json deleted file mode 100644 index 22ba6cf5..00000000 --- a/DRAMSys/library/resources/simulations/ddr3-single-device.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_ddr3_1Gbx8_p1KB_brc.json", - "mcconfig": "fifoStrict.json", - "memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json", - "simconfig": "ddr3-single-device.json", - "simulationid": "ddr3-single-device", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 200, - "name": "ddr3_single_dev_example.stl" - } - ] - } -} diff --git a/DRAMSys/library/resources/simulations/ddr3-single-device.xml b/DRAMSys/library/resources/simulations/ddr3-single-device.xml new file mode 100644 index 00000000..3e827ebc --- /dev/null +++ b/DRAMSys/library/resources/simulations/ddr3-single-device.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + ddr3_single_dev_example.stl + + diff --git a/DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.json b/DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.json deleted file mode 100644 index 64260a2a..00000000 --- a/DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json", - "mcconfig": "fifoStrict.json", - "memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json", - "simconfig": "ddr3.json", - "simulationid": "ddr3_postpone_ref_test", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 1000, - "name": "ddr3_postpone_ref_test_1.stl" - } - ] - } -} diff --git a/DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.xml b/DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.xml new file mode 100644 index 00000000..d8944780 --- /dev/null +++ b/DRAMSys/library/resources/simulations/ddr3_postpone_ref_test.xml @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + + ddr3_postpone_ref_test_1.stl + + diff --git a/DRAMSys/library/resources/simulations/ddr4-example.json b/DRAMSys/library/resources/simulations/ddr4-example.json deleted file mode 100644 index 6b55b665..00000000 --- a/DRAMSys/library/resources/simulations/ddr4-example.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_ddr4_8x4Gbx8_dimm_p1KB_brc.json", - "mcconfig": "fifoStrict.json", - "memspec": "JEDEC_4Gb_DDR4-1866_8bit_A.json", - "simconfig": "ddr4.json", - "simulationid": "ddr4-example", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 200, - "name": "ddr3_example.stl" - } - ] - } -} diff --git a/DRAMSys/library/resources/simulations/ddr4-example.xml b/DRAMSys/library/resources/simulations/ddr4-example.xml new file mode 100644 index 00000000..0d0606db --- /dev/null +++ b/DRAMSys/library/resources/simulations/ddr4-example.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + ddr3_example.stl + + diff --git a/DRAMSys/library/resources/simulations/hbm2-example.json b/DRAMSys/library/resources/simulations/hbm2-example.json deleted file mode 100644 index f81e2f13..00000000 --- a/DRAMSys/library/resources/simulations/hbm2-example.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_hbm2_8Gb_pc_brc.json", - "mcconfig": "fifoStrict.json", - "memspec": "HBM2.json", - "simconfig": "hbm2.json", - "simulationid": "hbm2-example", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 1000, - "name": "ddr3_example.stl" - } - ] - } -} diff --git a/DRAMSys/library/resources/simulations/hbm2-example.xml b/DRAMSys/library/resources/simulations/hbm2-example.xml new file mode 100644 index 00000000..2fac2e74 --- /dev/null +++ b/DRAMSys/library/resources/simulations/hbm2-example.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + ddr3_example.stl + + diff --git a/DRAMSys/library/resources/simulations/lpddr4-example.json b/DRAMSys/library/resources/simulations/lpddr4-example.json deleted file mode 100644 index d9a6726b..00000000 --- a/DRAMSys/library/resources/simulations/lpddr4-example.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_lpddr4_8Gbx16_brc.json", - "mcconfig": "fifoStrict.json", - "memspec": "JEDEC_8Gb_LPDDR4-3200_16bit.json", - "simconfig": "lpddr4.json", - "simulationid": "lpddr4-example", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 200, - "name": "ddr3_example.stl" - } - ] - } -} diff --git a/DRAMSys/library/resources/simulations/lpddr4-example.xml b/DRAMSys/library/resources/simulations/lpddr4-example.xml new file mode 100644 index 00000000..6f227578 --- /dev/null +++ b/DRAMSys/library/resources/simulations/lpddr4-example.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + ddr3_example.stl + + diff --git a/DRAMSys/library/resources/simulations/ranktest.json b/DRAMSys/library/resources/simulations/ranktest.json deleted file mode 100644 index 2c115a4b..00000000 --- a/DRAMSys/library/resources/simulations/ranktest.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_ranktest.json", - "mcconfig": "fifoStrict.json", - "memspec": "memspec_ranktest.json", - "simconfig": "ddr3.json", - "simulationid": "ranktest", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 200, - "name": "ranktest.stl" - } - ] - } -} diff --git a/DRAMSys/library/resources/simulations/ranktest.xml b/DRAMSys/library/resources/simulations/ranktest.xml new file mode 100644 index 00000000..23de6d07 --- /dev/null +++ b/DRAMSys/library/resources/simulations/ranktest.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + ranktest.stl + + diff --git a/DRAMSys/library/resources/simulations/rgrsim-gem5-fs.xml b/DRAMSys/library/resources/simulations/rgrsim-gem5-fs.xml new file mode 100644 index 00000000..a6e1ad3c --- /dev/null +++ b/DRAMSys/library/resources/simulations/rgrsim-gem5-fs.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/simulations/rgrsim-gem5-se.xml b/DRAMSys/library/resources/simulations/rgrsim-gem5-se.xml new file mode 100644 index 00000000..aad4a74a --- /dev/null +++ b/DRAMSys/library/resources/simulations/rgrsim-gem5-se.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/simulations/rgrsim.xml b/DRAMSys/library/resources/simulations/rgrsim.xml new file mode 100644 index 00000000..aa2449ca --- /dev/null +++ b/DRAMSys/library/resources/simulations/rgrsim.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + 1_720x1280_64-Pixelgroesse_imb3_str1_scram_ddr4_8b_same_clock.stl + + diff --git a/DRAMSys/library/resources/simulations/sms-example.xml b/DRAMSys/library/resources/simulations/sms-example.xml new file mode 100644 index 00000000..e5e92a7b --- /dev/null +++ b/DRAMSys/library/resources/simulations/sms-example.xml @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + random.stl + chstone-adpcm_32.stl + stream.stl + + + + diff --git a/DRAMSys/library/resources/simulations/wideio-ecc.xml b/DRAMSys/library/resources/simulations/wideio-ecc.xml new file mode 100644 index 00000000..59670a04 --- /dev/null +++ b/DRAMSys/library/resources/simulations/wideio-ecc.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + test_ecc.stl + + diff --git a/DRAMSys/library/resources/simulations/wideio-example.json b/DRAMSys/library/resources/simulations/wideio-example.json deleted file mode 100644 index 464a2591..00000000 --- a/DRAMSys/library/resources/simulations/wideio-example.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_wideio_4x256Mb_rbc.json", - "mcconfig": "fifoStrict.json", - "memspec": "JEDEC_256Mb_WIDEIO-200_128bit.json", - "simconfig": "wideio.json", - "simulationid": "wideio-example", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 1000, - "name": "chstone-adpcm_32.stl" - } - ] - } -} diff --git a/DRAMSys/library/resources/simulations/wideio-example.xml b/DRAMSys/library/resources/simulations/wideio-example.xml new file mode 100644 index 00000000..3d4f4711 --- /dev/null +++ b/DRAMSys/library/resources/simulations/wideio-example.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + chstone-adpcm_32.stl + + diff --git a/DRAMSys/library/resources/simulations/wideio-thermal.json b/DRAMSys/library/resources/simulations/wideio-thermal.json deleted file mode 100644 index 82c23ff5..00000000 --- a/DRAMSys/library/resources/simulations/wideio-thermal.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_wideio_4x256Mb_rbc.json", - "mcconfig": "fr_fcfs.json", - "memspec": "JEDEC_256Mb_WIDEIO-200_128bit.json", - "simconfig": "wideio_thermal.json", - "simulationid": "wideio-example", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 1000, - "name": "test_error.stl" - } - ] - } -} diff --git a/DRAMSys/library/resources/traces/prettyTest b/DRAMSys/library/resources/traces/prettyTest new file mode 100755 index 00000000..96fed530 --- /dev/null +++ b/DRAMSys/library/resources/traces/prettyTest @@ -0,0 +1,3248 @@ +0: read 0x0 [Channel: 0 Bank: 0 Row:0 Column: 0] +31: read 0x400140 [Channel: 0 Bank: 0 Row:256 Column: 20] +33: read 0x400160 [Channel: 0 Bank: 0 Row:256 Column: 22] +56: read 0x7fff8000 [Channel: 3 Bank: 0 Row:8190 Column: 0] +81: read 0x400180 [Channel: 0 Bank: 0 Row:256 Column: 24] +84: read 0x4001a0 [Channel: 0 Bank: 0 Row:256 Column: 26] +109: read 0x10007180 [Channel: 2 Bank: 6 Row:1 Column: 24] +143: read 0x405740 [Channel: 0 Bank: 2 Row:257 Column: 116] +144: read 0x405bc0 [Channel: 0 Bank: 3 Row:257 Column: 60] +167: read 0x7fff7fe0 [Channel: 3 Bank: 7 Row:8189 Column: 126] +172: read 0x405be0 [Channel: 0 Bank: 3 Row:257 Column: 62] +192: read 0x7fff7fc0 [Channel: 3 Bank: 7 Row:8189 Column: 124] +220: read 0x405c00 [Channel: 0 Bank: 3 Row:257 Column: 64] +250: read 0x409ba0 [Channel: 0 Bank: 3 Row:258 Column: 58] +255: read 0x409bc0 [Channel: 0 Bank: 3 Row:258 Column: 60] +278: read 0x7fff7fa0 [Channel: 3 Bank: 7 Row:8189 Column: 122] +302: read 0x409be0 [Channel: 0 Bank: 3 Row:258 Column: 62] +330: read 0x409c00 [Channel: 0 Bank: 3 Row:258 Column: 64] +364: read 0x40cba0 [Channel: 0 Bank: 1 Row:259 Column: 58] +388: read 0x40cbe0 [Channel: 0 Bank: 1 Row:259 Column: 62] +413: read 0x40cc00 [Channel: 0 Bank: 1 Row:259 Column: 64] +438: read 0x40cc20 [Channel: 0 Bank: 1 Row:259 Column: 66] +440: read 0x40cc40 [Channel: 0 Bank: 1 Row:259 Column: 68] +466: read 0x7fff8120 [Channel: 3 Bank: 0 Row:8190 Column: 18] +491: read 0x40cc60 [Channel: 0 Bank: 1 Row:259 Column: 70] +519: read 0x40cc80 [Channel: 0 Bank: 1 Row:259 Column: 72] +547: read 0x40cca0 [Channel: 0 Bank: 1 Row:259 Column: 74] +575: read 0x40ccc0 [Channel: 0 Bank: 1 Row:259 Column: 76] +605: read 0x40cce0 [Channel: 0 Bank: 1 Row:259 Column: 78] +630: read 0x40cd20 [Channel: 0 Bank: 1 Row:259 Column: 82] +666: read 0x409c20 [Channel: 0 Bank: 3 Row:258 Column: 66] +746: read 0x40cbc0 [Channel: 0 Bank: 1 Row:259 Column: 60] +785: read 0x40cd00 [Channel: 0 Bank: 1 Row:259 Column: 80] +820: read 0x409c40 [Channel: 0 Bank: 3 Row:258 Column: 68] +844: read 0x405c20 [Channel: 0 Bank: 3 Row:257 Column: 66] +848: read 0x405c40 [Channel: 0 Bank: 3 Row:257 Column: 68] +869: read 0x10007060 [Channel: 2 Bank: 6 Row:1 Column: 6] +894: read 0x405760 [Channel: 0 Bank: 2 Row:257 Column: 118] +922: read 0x4001c0 [Channel: 0 Bank: 0 Row:256 Column: 28] +946: read 0x4054c0 [Channel: 0 Bank: 2 Row:257 Column: 76] +974: read 0x4054e0 [Channel: 0 Bank: 2 Row:257 Column: 78] +998: read 0x4056e0 [Channel: 0 Bank: 2 Row:257 Column: 110] +1001: read 0x405700 [Channel: 0 Bank: 2 Row:257 Column: 112] +1026: read 0x10007160 [Channel: 2 Bank: 6 Row:1 Column: 22] +1051: read 0x4055c0 [Channel: 0 Bank: 2 Row:257 Column: 92] +1076: read 0x4055e0 [Channel: 0 Bank: 2 Row:257 Column: 94] +1080: read 0x405600 [Channel: 0 Bank: 2 Row:257 Column: 96] +1104: read 0x10007200 [Channel: 2 Bank: 6 Row:1 Column: 32] +1128: read 0x405640 [Channel: 0 Bank: 2 Row:257 Column: 100] +1153: read 0x405660 [Channel: 0 Bank: 2 Row:257 Column: 102] +1158: read 0x405680 [Channel: 0 Bank: 2 Row:257 Column: 104] +1186: read 0x4056a0 [Channel: 0 Bank: 2 Row:257 Column: 106] +1211: read 0x4059c0 [Channel: 0 Bank: 3 Row:257 Column: 28] +1215: read 0x4059e0 [Channel: 0 Bank: 3 Row:257 Column: 30] +1239: read 0x7fff7f80 [Channel: 3 Bank: 7 Row:8189 Column: 120] +1263: read 0x405a40 [Channel: 0 Bank: 3 Row:257 Column: 36] +1266: read 0x405a60 [Channel: 0 Bank: 3 Row:257 Column: 38] +1291: read 0x10007040 [Channel: 2 Bank: 6 Row:1 Column: 4] +1291: read 0x7fff7f60 [Channel: 3 Bank: 7 Row:8189 Column: 118] +1291: read 0x10006d20 [Channel: 2 Bank: 5 Row:1 Column: 82] +1315: read 0x405ac0 [Channel: 0 Bank: 3 Row:257 Column: 44] +1343: read 0x405ae0 [Channel: 0 Bank: 3 Row:257 Column: 46] +1367: read 0x405b60 [Channel: 0 Bank: 3 Row:257 Column: 54] +1392: read 0x405b80 [Channel: 0 Bank: 3 Row:257 Column: 56] +1427: read 0x405ba0 [Channel: 0 Bank: 3 Row:257 Column: 58] +1455: read 0x405a00 [Channel: 0 Bank: 3 Row:257 Column: 32] +1480: read 0x405a20 [Channel: 0 Bank: 3 Row:257 Column: 34] +1506: read 0x4056c0 [Channel: 0 Bank: 2 Row:257 Column: 108] +1535: read 0x405720 [Channel: 0 Bank: 2 Row:257 Column: 114] +1536: read 0x4052e0 [Channel: 0 Bank: 2 Row:257 Column: 46] +1560: read 0x100071a0 [Channel: 2 Bank: 6 Row:1 Column: 26] +1585: read 0x405300 [Channel: 0 Bank: 2 Row:257 Column: 48] +1589: read 0x405320 [Channel: 0 Bank: 2 Row:257 Column: 50] +1610: read 0x10000000 [Channel: 2 Bank: 0 Row:0 Column: 0] +1620: read 0x405340 [Channel: 0 Bank: 2 Row:257 Column: 52] +1727: read 0x1000dde0 [Channel: 2 Bank: 3 Row:3 Column: 94] +1752: read 0x10000020 [Channel: 2 Bank: 0 Row:0 Column: 2] +1834: read 0x1000de00 [Channel: 2 Bank: 3 Row:3 Column: 96] +1859: read 0x10000040 [Channel: 2 Bank: 0 Row:0 Column: 4] +1941: read 0x1000de20 [Channel: 2 Bank: 3 Row:3 Column: 98] +1966: read 0x10000060 [Channel: 2 Bank: 0 Row:0 Column: 6] +2048: read 0x1000de40 [Channel: 2 Bank: 3 Row:3 Column: 100] +2073: read 0x10000080 [Channel: 2 Bank: 0 Row:0 Column: 8] +2155: read 0x1000de60 [Channel: 2 Bank: 3 Row:3 Column: 102] +2180: read 0x100000a0 [Channel: 2 Bank: 0 Row:0 Column: 10] +2262: read 0x1000de80 [Channel: 2 Bank: 3 Row:3 Column: 104] +2287: read 0x100000c0 [Channel: 2 Bank: 0 Row:0 Column: 12] +2369: read 0x1000dea0 [Channel: 2 Bank: 3 Row:3 Column: 106] +2394: read 0x100000e0 [Channel: 2 Bank: 0 Row:0 Column: 14] +2476: read 0x1000dec0 [Channel: 2 Bank: 3 Row:3 Column: 108] +2501: read 0x10000100 [Channel: 2 Bank: 0 Row:0 Column: 16] +2583: read 0x1000dee0 [Channel: 2 Bank: 3 Row:3 Column: 110] +2608: read 0x10000120 [Channel: 2 Bank: 0 Row:0 Column: 18] +2690: read 0x1000df00 [Channel: 2 Bank: 3 Row:3 Column: 112] +2715: read 0x10000140 [Channel: 2 Bank: 0 Row:0 Column: 20] +2797: read 0x1000df20 [Channel: 2 Bank: 3 Row:3 Column: 114] +2822: read 0x10000160 [Channel: 2 Bank: 0 Row:0 Column: 22] +2904: read 0x1000df40 [Channel: 2 Bank: 3 Row:3 Column: 116] +2929: read 0x10000180 [Channel: 2 Bank: 0 Row:0 Column: 24] +3011: read 0x1000df60 [Channel: 2 Bank: 3 Row:3 Column: 118] +3036: read 0x100001a0 [Channel: 2 Bank: 0 Row:0 Column: 26] +3118: read 0x1000df80 [Channel: 2 Bank: 3 Row:3 Column: 120] +3143: read 0x100001c0 [Channel: 2 Bank: 0 Row:0 Column: 28] +3225: read 0x1000dfa0 [Channel: 2 Bank: 3 Row:3 Column: 122] +3250: read 0x100001e0 [Channel: 2 Bank: 0 Row:0 Column: 30] +3332: read 0x1000dfc0 [Channel: 2 Bank: 3 Row:3 Column: 124] +3357: read 0x10000200 [Channel: 2 Bank: 0 Row:0 Column: 32] +3439: read 0x1000dfe0 [Channel: 2 Bank: 3 Row:3 Column: 126] +3464: read 0x10000220 [Channel: 2 Bank: 0 Row:0 Column: 34] +3546: read 0x1000e000 [Channel: 2 Bank: 4 Row:3 Column: 0] +3571: read 0x10000240 [Channel: 2 Bank: 0 Row:0 Column: 36] +3653: read 0x1000e020 [Channel: 2 Bank: 4 Row:3 Column: 2] +3678: read 0x10000260 [Channel: 2 Bank: 0 Row:0 Column: 38] +3760: read 0x1000e040 [Channel: 2 Bank: 4 Row:3 Column: 4] +3785: read 0x10000280 [Channel: 2 Bank: 0 Row:0 Column: 40] +3867: read 0x1000e060 [Channel: 2 Bank: 4 Row:3 Column: 6] +3892: read 0x100002a0 [Channel: 2 Bank: 0 Row:0 Column: 42] +3974: read 0x1000e080 [Channel: 2 Bank: 4 Row:3 Column: 8] +3999: read 0x100002c0 [Channel: 2 Bank: 0 Row:0 Column: 44] +4081: read 0x1000e0a0 [Channel: 2 Bank: 4 Row:3 Column: 10] +4106: read 0x100002e0 [Channel: 2 Bank: 0 Row:0 Column: 46] +4188: read 0x1000e0c0 [Channel: 2 Bank: 4 Row:3 Column: 12] +4213: read 0x10000300 [Channel: 2 Bank: 0 Row:0 Column: 48] +4295: read 0x1000e0e0 [Channel: 2 Bank: 4 Row:3 Column: 14] +4320: read 0x10000320 [Channel: 2 Bank: 0 Row:0 Column: 50] +4402: read 0x1000e100 [Channel: 2 Bank: 4 Row:3 Column: 16] +4427: read 0x10000340 [Channel: 2 Bank: 0 Row:0 Column: 52] +4509: read 0x1000e120 [Channel: 2 Bank: 4 Row:3 Column: 18] +4534: read 0x10000360 [Channel: 2 Bank: 0 Row:0 Column: 54] +4616: read 0x1000e140 [Channel: 2 Bank: 4 Row:3 Column: 20] +4641: read 0x10000380 [Channel: 2 Bank: 0 Row:0 Column: 56] +4723: read 0x1000e160 [Channel: 2 Bank: 4 Row:3 Column: 22] +4748: read 0x100003a0 [Channel: 2 Bank: 0 Row:0 Column: 58] +4830: read 0x1000e180 [Channel: 2 Bank: 4 Row:3 Column: 24] +4855: read 0x100003c0 [Channel: 2 Bank: 0 Row:0 Column: 60] +4937: read 0x1000e1a0 [Channel: 2 Bank: 4 Row:3 Column: 26] +4962: read 0x100003e0 [Channel: 2 Bank: 0 Row:0 Column: 62] +5044: read 0x1000e1c0 [Channel: 2 Bank: 4 Row:3 Column: 28] +5069: read 0x10000400 [Channel: 2 Bank: 0 Row:0 Column: 64] +5151: read 0x1000e1e0 [Channel: 2 Bank: 4 Row:3 Column: 30] +5176: read 0x10000420 [Channel: 2 Bank: 0 Row:0 Column: 66] +5258: read 0x1000e200 [Channel: 2 Bank: 4 Row:3 Column: 32] +5283: read 0x10000440 [Channel: 2 Bank: 0 Row:0 Column: 68] +5365: read 0x1000e220 [Channel: 2 Bank: 4 Row:3 Column: 34] +5390: read 0x10000460 [Channel: 2 Bank: 0 Row:0 Column: 70] +5472: read 0x1000e240 [Channel: 2 Bank: 4 Row:3 Column: 36] +5497: read 0x10000480 [Channel: 2 Bank: 0 Row:0 Column: 72] +5579: read 0x1000e260 [Channel: 2 Bank: 4 Row:3 Column: 38] +5604: read 0x100004a0 [Channel: 2 Bank: 0 Row:0 Column: 74] +5686: read 0x1000e280 [Channel: 2 Bank: 4 Row:3 Column: 40] +5711: read 0x100004c0 [Channel: 2 Bank: 0 Row:0 Column: 76] +5793: read 0x1000e2a0 [Channel: 2 Bank: 4 Row:3 Column: 42] +5818: read 0x100004e0 [Channel: 2 Bank: 0 Row:0 Column: 78] +5900: read 0x1000e2c0 [Channel: 2 Bank: 4 Row:3 Column: 44] +5925: read 0x10000500 [Channel: 2 Bank: 0 Row:0 Column: 80] +6007: read 0x1000e2e0 [Channel: 2 Bank: 4 Row:3 Column: 46] +6032: read 0x10000520 [Channel: 2 Bank: 0 Row:0 Column: 82] +6114: read 0x1000e300 [Channel: 2 Bank: 4 Row:3 Column: 48] +6139: read 0x10000540 [Channel: 2 Bank: 0 Row:0 Column: 84] +6221: read 0x1000e320 [Channel: 2 Bank: 4 Row:3 Column: 50] +6246: read 0x10000560 [Channel: 2 Bank: 0 Row:0 Column: 86] +6328: read 0x1000e340 [Channel: 2 Bank: 4 Row:3 Column: 52] +6353: read 0x10000580 [Channel: 2 Bank: 0 Row:0 Column: 88] +6435: read 0x1000e360 [Channel: 2 Bank: 4 Row:3 Column: 54] +6460: read 0x100005a0 [Channel: 2 Bank: 0 Row:0 Column: 90] +6542: read 0x1000e380 [Channel: 2 Bank: 4 Row:3 Column: 56] +6567: read 0x100005c0 [Channel: 2 Bank: 0 Row:0 Column: 92] +6649: read 0x1000e3a0 [Channel: 2 Bank: 4 Row:3 Column: 58] +6674: read 0x100005e0 [Channel: 2 Bank: 0 Row:0 Column: 94] +6756: read 0x1000e3c0 [Channel: 2 Bank: 4 Row:3 Column: 60] +6781: read 0x10000600 [Channel: 2 Bank: 0 Row:0 Column: 96] +6863: read 0x1000e3e0 [Channel: 2 Bank: 4 Row:3 Column: 62] +6888: read 0x10000620 [Channel: 2 Bank: 0 Row:0 Column: 98] +6970: read 0x1000e400 [Channel: 2 Bank: 4 Row:3 Column: 64] +6995: read 0x10000640 [Channel: 2 Bank: 0 Row:0 Column: 100] +7077: read 0x1000e420 [Channel: 2 Bank: 4 Row:3 Column: 66] +7102: read 0x10000660 [Channel: 2 Bank: 0 Row:0 Column: 102] +7184: read 0x1000e440 [Channel: 2 Bank: 4 Row:3 Column: 68] +7209: read 0x10000680 [Channel: 2 Bank: 0 Row:0 Column: 104] +7291: read 0x1000e460 [Channel: 2 Bank: 4 Row:3 Column: 70] +7316: read 0x100006a0 [Channel: 2 Bank: 0 Row:0 Column: 106] +7398: read 0x1000e480 [Channel: 2 Bank: 4 Row:3 Column: 72] +7423: read 0x100006c0 [Channel: 2 Bank: 0 Row:0 Column: 108] +7505: read 0x1000e4a0 [Channel: 2 Bank: 4 Row:3 Column: 74] +7530: read 0x100006e0 [Channel: 2 Bank: 0 Row:0 Column: 110] +7612: read 0x1000e4c0 [Channel: 2 Bank: 4 Row:3 Column: 76] +7637: read 0x10000700 [Channel: 2 Bank: 0 Row:0 Column: 112] +7719: read 0x1000e4e0 [Channel: 2 Bank: 4 Row:3 Column: 78] +7744: read 0x10000720 [Channel: 2 Bank: 0 Row:0 Column: 114] +7826: read 0x1000e500 [Channel: 2 Bank: 4 Row:3 Column: 80] +7851: read 0x10000740 [Channel: 2 Bank: 0 Row:0 Column: 116] +7933: read 0x1000e520 [Channel: 2 Bank: 4 Row:3 Column: 82] +7958: read 0x10000760 [Channel: 2 Bank: 0 Row:0 Column: 118] +8040: read 0x1000e540 [Channel: 2 Bank: 4 Row:3 Column: 84] +8065: read 0x10000780 [Channel: 2 Bank: 0 Row:0 Column: 120] +8147: read 0x1000e560 [Channel: 2 Bank: 4 Row:3 Column: 86] +8172: read 0x100007a0 [Channel: 2 Bank: 0 Row:0 Column: 122] +8254: read 0x1000e580 [Channel: 2 Bank: 4 Row:3 Column: 88] +8279: read 0x100007c0 [Channel: 2 Bank: 0 Row:0 Column: 124] +8361: read 0x1000e5a0 [Channel: 2 Bank: 4 Row:3 Column: 90] +8386: read 0x100007e0 [Channel: 2 Bank: 0 Row:0 Column: 126] +8468: read 0x1000e5c0 [Channel: 2 Bank: 4 Row:3 Column: 92] +8493: read 0x10000800 [Channel: 2 Bank: 1 Row:0 Column: 0] +8575: read 0x1000e5e0 [Channel: 2 Bank: 4 Row:3 Column: 94] +8600: read 0x10000820 [Channel: 2 Bank: 1 Row:0 Column: 2] +8682: read 0x1000e600 [Channel: 2 Bank: 4 Row:3 Column: 96] +8707: read 0x10000840 [Channel: 2 Bank: 1 Row:0 Column: 4] +8789: read 0x1000e620 [Channel: 2 Bank: 4 Row:3 Column: 98] +8814: read 0x10000860 [Channel: 2 Bank: 1 Row:0 Column: 6] +8896: read 0x1000e640 [Channel: 2 Bank: 4 Row:3 Column: 100] +8921: read 0x10000880 [Channel: 2 Bank: 1 Row:0 Column: 8] +9003: read 0x1000e660 [Channel: 2 Bank: 4 Row:3 Column: 102] +9028: read 0x100008a0 [Channel: 2 Bank: 1 Row:0 Column: 10] +9110: read 0x1000e680 [Channel: 2 Bank: 4 Row:3 Column: 104] +9135: read 0x100008c0 [Channel: 2 Bank: 1 Row:0 Column: 12] +9217: read 0x1000e6a0 [Channel: 2 Bank: 4 Row:3 Column: 106] +9242: read 0x100008e0 [Channel: 2 Bank: 1 Row:0 Column: 14] +9324: read 0x1000e6c0 [Channel: 2 Bank: 4 Row:3 Column: 108] +9349: read 0x10000900 [Channel: 2 Bank: 1 Row:0 Column: 16] +9431: read 0x1000e6e0 [Channel: 2 Bank: 4 Row:3 Column: 110] +9456: read 0x10000920 [Channel: 2 Bank: 1 Row:0 Column: 18] +9538: read 0x1000e700 [Channel: 2 Bank: 4 Row:3 Column: 112] +9563: read 0x10000940 [Channel: 2 Bank: 1 Row:0 Column: 20] +9645: read 0x1000e720 [Channel: 2 Bank: 4 Row:3 Column: 114] +9670: read 0x10000960 [Channel: 2 Bank: 1 Row:0 Column: 22] +9752: read 0x1000e740 [Channel: 2 Bank: 4 Row:3 Column: 116] +9777: read 0x10000980 [Channel: 2 Bank: 1 Row:0 Column: 24] +9859: read 0x1000e760 [Channel: 2 Bank: 4 Row:3 Column: 118] +9884: read 0x100009a0 [Channel: 2 Bank: 1 Row:0 Column: 26] +9966: read 0x1000e780 [Channel: 2 Bank: 4 Row:3 Column: 120] +9991: read 0x100009c0 [Channel: 2 Bank: 1 Row:0 Column: 28] +10073: read 0x1000e7a0 [Channel: 2 Bank: 4 Row:3 Column: 122] +10098: read 0x100009e0 [Channel: 2 Bank: 1 Row:0 Column: 30] +10180: read 0x1000e7c0 [Channel: 2 Bank: 4 Row:3 Column: 124] +10205: read 0x10000a00 [Channel: 2 Bank: 1 Row:0 Column: 32] +10287: read 0x1000e7e0 [Channel: 2 Bank: 4 Row:3 Column: 126] +10312: read 0x10000a20 [Channel: 2 Bank: 1 Row:0 Column: 34] +10394: read 0x1000e800 [Channel: 2 Bank: 5 Row:3 Column: 0] +10419: read 0x10000a40 [Channel: 2 Bank: 1 Row:0 Column: 36] +10501: read 0x1000e820 [Channel: 2 Bank: 5 Row:3 Column: 2] +10526: read 0x10000a60 [Channel: 2 Bank: 1 Row:0 Column: 38] +10608: read 0x1000e840 [Channel: 2 Bank: 5 Row:3 Column: 4] +10633: read 0x10000a80 [Channel: 2 Bank: 1 Row:0 Column: 40] +10715: read 0x1000e860 [Channel: 2 Bank: 5 Row:3 Column: 6] +10740: read 0x10000aa0 [Channel: 2 Bank: 1 Row:0 Column: 42] +10822: read 0x1000e880 [Channel: 2 Bank: 5 Row:3 Column: 8] +10847: read 0x10000ac0 [Channel: 2 Bank: 1 Row:0 Column: 44] +10929: read 0x1000e8a0 [Channel: 2 Bank: 5 Row:3 Column: 10] +10954: read 0x10000ae0 [Channel: 2 Bank: 1 Row:0 Column: 46] +11036: read 0x1000e8c0 [Channel: 2 Bank: 5 Row:3 Column: 12] +11061: read 0x10000b00 [Channel: 2 Bank: 1 Row:0 Column: 48] +11143: read 0x1000e8e0 [Channel: 2 Bank: 5 Row:3 Column: 14] +11168: read 0x10000b20 [Channel: 2 Bank: 1 Row:0 Column: 50] +11250: read 0x1000e900 [Channel: 2 Bank: 5 Row:3 Column: 16] +11275: read 0x10000b40 [Channel: 2 Bank: 1 Row:0 Column: 52] +11357: read 0x1000e920 [Channel: 2 Bank: 5 Row:3 Column: 18] +11382: read 0x10000b60 [Channel: 2 Bank: 1 Row:0 Column: 54] +11464: read 0x1000e940 [Channel: 2 Bank: 5 Row:3 Column: 20] +11489: read 0x10000b80 [Channel: 2 Bank: 1 Row:0 Column: 56] +11571: read 0x1000e960 [Channel: 2 Bank: 5 Row:3 Column: 22] +11596: read 0x10000ba0 [Channel: 2 Bank: 1 Row:0 Column: 58] +11678: read 0x1000e980 [Channel: 2 Bank: 5 Row:3 Column: 24] +11703: read 0x10000bc0 [Channel: 2 Bank: 1 Row:0 Column: 60] +11785: read 0x1000e9a0 [Channel: 2 Bank: 5 Row:3 Column: 26] +11810: read 0x10000be0 [Channel: 2 Bank: 1 Row:0 Column: 62] +11892: read 0x1000e9c0 [Channel: 2 Bank: 5 Row:3 Column: 28] +11917: read 0x10000c00 [Channel: 2 Bank: 1 Row:0 Column: 64] +11999: read 0x1000e9e0 [Channel: 2 Bank: 5 Row:3 Column: 30] +12024: read 0x10000c20 [Channel: 2 Bank: 1 Row:0 Column: 66] +12106: read 0x1000ea00 [Channel: 2 Bank: 5 Row:3 Column: 32] +12131: read 0x10000c40 [Channel: 2 Bank: 1 Row:0 Column: 68] +12213: read 0x1000ea20 [Channel: 2 Bank: 5 Row:3 Column: 34] +12238: read 0x10000c60 [Channel: 2 Bank: 1 Row:0 Column: 70] +12320: read 0x1000ea40 [Channel: 2 Bank: 5 Row:3 Column: 36] +12345: read 0x10000c80 [Channel: 2 Bank: 1 Row:0 Column: 72] +12427: read 0x1000ea60 [Channel: 2 Bank: 5 Row:3 Column: 38] +12452: read 0x10000ca0 [Channel: 2 Bank: 1 Row:0 Column: 74] +12534: read 0x1000ea80 [Channel: 2 Bank: 5 Row:3 Column: 40] +12559: read 0x10000cc0 [Channel: 2 Bank: 1 Row:0 Column: 76] +12641: read 0x1000eaa0 [Channel: 2 Bank: 5 Row:3 Column: 42] +12666: read 0x10000ce0 [Channel: 2 Bank: 1 Row:0 Column: 78] +12748: read 0x1000eac0 [Channel: 2 Bank: 5 Row:3 Column: 44] +12773: read 0x10000d00 [Channel: 2 Bank: 1 Row:0 Column: 80] +12855: read 0x1000eae0 [Channel: 2 Bank: 5 Row:3 Column: 46] +12880: read 0x10000d20 [Channel: 2 Bank: 1 Row:0 Column: 82] +12962: read 0x1000eb00 [Channel: 2 Bank: 5 Row:3 Column: 48] +12987: read 0x10000d40 [Channel: 2 Bank: 1 Row:0 Column: 84] +13069: read 0x1000eb20 [Channel: 2 Bank: 5 Row:3 Column: 50] +13094: read 0x10000d60 [Channel: 2 Bank: 1 Row:0 Column: 86] +13176: read 0x1000eb40 [Channel: 2 Bank: 5 Row:3 Column: 52] +13201: read 0x10000d80 [Channel: 2 Bank: 1 Row:0 Column: 88] +13283: read 0x1000eb60 [Channel: 2 Bank: 5 Row:3 Column: 54] +13308: read 0x10000da0 [Channel: 2 Bank: 1 Row:0 Column: 90] +13390: read 0x1000eb80 [Channel: 2 Bank: 5 Row:3 Column: 56] +13415: read 0x10000dc0 [Channel: 2 Bank: 1 Row:0 Column: 92] +13497: read 0x1000eba0 [Channel: 2 Bank: 5 Row:3 Column: 58] +13522: read 0x10000de0 [Channel: 2 Bank: 1 Row:0 Column: 94] +13604: read 0x1000ebc0 [Channel: 2 Bank: 5 Row:3 Column: 60] +13629: read 0x10000e00 [Channel: 2 Bank: 1 Row:0 Column: 96] +13711: read 0x1000ebe0 [Channel: 2 Bank: 5 Row:3 Column: 62] +13736: read 0x10000e20 [Channel: 2 Bank: 1 Row:0 Column: 98] +13818: read 0x1000ec00 [Channel: 2 Bank: 5 Row:3 Column: 64] +13843: read 0x10000e40 [Channel: 2 Bank: 1 Row:0 Column: 100] +13925: read 0x1000ec20 [Channel: 2 Bank: 5 Row:3 Column: 66] +13950: read 0x10000e60 [Channel: 2 Bank: 1 Row:0 Column: 102] +14032: read 0x1000ec40 [Channel: 2 Bank: 5 Row:3 Column: 68] +14057: read 0x10000e80 [Channel: 2 Bank: 1 Row:0 Column: 104] +14139: read 0x1000ec60 [Channel: 2 Bank: 5 Row:3 Column: 70] +14164: read 0x10000ea0 [Channel: 2 Bank: 1 Row:0 Column: 106] +14246: read 0x1000ec80 [Channel: 2 Bank: 5 Row:3 Column: 72] +14271: read 0x10000ec0 [Channel: 2 Bank: 1 Row:0 Column: 108] +14353: read 0x1000eca0 [Channel: 2 Bank: 5 Row:3 Column: 74] +14378: read 0x10000ee0 [Channel: 2 Bank: 1 Row:0 Column: 110] +14460: read 0x1000ecc0 [Channel: 2 Bank: 5 Row:3 Column: 76] +14485: read 0x10000f00 [Channel: 2 Bank: 1 Row:0 Column: 112] +14567: read 0x1000ece0 [Channel: 2 Bank: 5 Row:3 Column: 78] +14592: read 0x10000f20 [Channel: 2 Bank: 1 Row:0 Column: 114] +14674: read 0x1000ed00 [Channel: 2 Bank: 5 Row:3 Column: 80] +14699: read 0x10000f40 [Channel: 2 Bank: 1 Row:0 Column: 116] +14781: read 0x1000ed20 [Channel: 2 Bank: 5 Row:3 Column: 82] +14806: read 0x10000f60 [Channel: 2 Bank: 1 Row:0 Column: 118] +14888: read 0x1000ed40 [Channel: 2 Bank: 5 Row:3 Column: 84] +14913: read 0x10000f80 [Channel: 2 Bank: 1 Row:0 Column: 120] +14995: read 0x1000ed60 [Channel: 2 Bank: 5 Row:3 Column: 86] +15020: read 0x10000fa0 [Channel: 2 Bank: 1 Row:0 Column: 122] +15102: read 0x1000ed80 [Channel: 2 Bank: 5 Row:3 Column: 88] +15127: read 0x10000fc0 [Channel: 2 Bank: 1 Row:0 Column: 124] +15209: read 0x1000eda0 [Channel: 2 Bank: 5 Row:3 Column: 90] +15234: read 0x10000fe0 [Channel: 2 Bank: 1 Row:0 Column: 126] +15316: read 0x1000edc0 [Channel: 2 Bank: 5 Row:3 Column: 92] +15347: read 0x10001000 [Channel: 2 Bank: 2 Row:0 Column: 0] +15429: read 0x1000ede0 [Channel: 2 Bank: 5 Row:3 Column: 94] +15454: read 0x10001020 [Channel: 2 Bank: 2 Row:0 Column: 2] +15536: read 0x1000ee00 [Channel: 2 Bank: 5 Row:3 Column: 96] +15561: read 0x10001040 [Channel: 2 Bank: 2 Row:0 Column: 4] +15643: read 0x1000ee20 [Channel: 2 Bank: 5 Row:3 Column: 98] +15668: read 0x10001060 [Channel: 2 Bank: 2 Row:0 Column: 6] +15750: read 0x1000ee40 [Channel: 2 Bank: 5 Row:3 Column: 100] +15775: read 0x10001080 [Channel: 2 Bank: 2 Row:0 Column: 8] +15857: read 0x1000ee60 [Channel: 2 Bank: 5 Row:3 Column: 102] +15882: read 0x100010a0 [Channel: 2 Bank: 2 Row:0 Column: 10] +15964: read 0x1000ee80 [Channel: 2 Bank: 5 Row:3 Column: 104] +15989: read 0x100010c0 [Channel: 2 Bank: 2 Row:0 Column: 12] +16071: read 0x1000eea0 [Channel: 2 Bank: 5 Row:3 Column: 106] +16096: read 0x100010e0 [Channel: 2 Bank: 2 Row:0 Column: 14] +16178: read 0x1000eec0 [Channel: 2 Bank: 5 Row:3 Column: 108] +16203: read 0x10001100 [Channel: 2 Bank: 2 Row:0 Column: 16] +16285: read 0x1000eee0 [Channel: 2 Bank: 5 Row:3 Column: 110] +16310: read 0x10001120 [Channel: 2 Bank: 2 Row:0 Column: 18] +16392: read 0x1000ef00 [Channel: 2 Bank: 5 Row:3 Column: 112] +16417: read 0x10001140 [Channel: 2 Bank: 2 Row:0 Column: 20] +16499: read 0x1000ef20 [Channel: 2 Bank: 5 Row:3 Column: 114] +16524: read 0x10001160 [Channel: 2 Bank: 2 Row:0 Column: 22] +16606: read 0x1000ef40 [Channel: 2 Bank: 5 Row:3 Column: 116] +16631: read 0x10001180 [Channel: 2 Bank: 2 Row:0 Column: 24] +16713: read 0x1000ef60 [Channel: 2 Bank: 5 Row:3 Column: 118] +16738: read 0x100011a0 [Channel: 2 Bank: 2 Row:0 Column: 26] +16820: read 0x1000ef80 [Channel: 2 Bank: 5 Row:3 Column: 120] +16845: read 0x100011c0 [Channel: 2 Bank: 2 Row:0 Column: 28] +16927: read 0x1000efa0 [Channel: 2 Bank: 5 Row:3 Column: 122] +16952: read 0x100011e0 [Channel: 2 Bank: 2 Row:0 Column: 30] +17034: read 0x1000efc0 [Channel: 2 Bank: 5 Row:3 Column: 124] +17059: read 0x10001200 [Channel: 2 Bank: 2 Row:0 Column: 32] +17141: read 0x1000efe0 [Channel: 2 Bank: 5 Row:3 Column: 126] +17166: read 0x10001220 [Channel: 2 Bank: 2 Row:0 Column: 34] +17248: read 0x1000f000 [Channel: 2 Bank: 6 Row:3 Column: 0] +17273: read 0x10001240 [Channel: 2 Bank: 2 Row:0 Column: 36] +17355: read 0x1000f020 [Channel: 2 Bank: 6 Row:3 Column: 2] +17380: read 0x10001260 [Channel: 2 Bank: 2 Row:0 Column: 38] +17462: read 0x1000f040 [Channel: 2 Bank: 6 Row:3 Column: 4] +17487: read 0x10001280 [Channel: 2 Bank: 2 Row:0 Column: 40] +17569: read 0x1000f060 [Channel: 2 Bank: 6 Row:3 Column: 6] +17594: read 0x100012a0 [Channel: 2 Bank: 2 Row:0 Column: 42] +17676: read 0x1000f080 [Channel: 2 Bank: 6 Row:3 Column: 8] +17701: read 0x100012c0 [Channel: 2 Bank: 2 Row:0 Column: 44] +17783: read 0x1000f0a0 [Channel: 2 Bank: 6 Row:3 Column: 10] +17808: read 0x100012e0 [Channel: 2 Bank: 2 Row:0 Column: 46] +17890: read 0x1000f0c0 [Channel: 2 Bank: 6 Row:3 Column: 12] +17915: read 0x10001300 [Channel: 2 Bank: 2 Row:0 Column: 48] +17997: read 0x1000f0e0 [Channel: 2 Bank: 6 Row:3 Column: 14] +18022: read 0x10001320 [Channel: 2 Bank: 2 Row:0 Column: 50] +18104: read 0x1000f100 [Channel: 2 Bank: 6 Row:3 Column: 16] +18129: read 0x10001340 [Channel: 2 Bank: 2 Row:0 Column: 52] +18211: read 0x1000f120 [Channel: 2 Bank: 6 Row:3 Column: 18] +18236: read 0x10001360 [Channel: 2 Bank: 2 Row:0 Column: 54] +18318: read 0x1000f140 [Channel: 2 Bank: 6 Row:3 Column: 20] +18343: read 0x10001380 [Channel: 2 Bank: 2 Row:0 Column: 56] +18425: read 0x1000f160 [Channel: 2 Bank: 6 Row:3 Column: 22] +18450: read 0x100013a0 [Channel: 2 Bank: 2 Row:0 Column: 58] +18532: read 0x1000f180 [Channel: 2 Bank: 6 Row:3 Column: 24] +18557: read 0x100013c0 [Channel: 2 Bank: 2 Row:0 Column: 60] +18639: read 0x1000f1a0 [Channel: 2 Bank: 6 Row:3 Column: 26] +18664: read 0x100013e0 [Channel: 2 Bank: 2 Row:0 Column: 62] +18746: read 0x1000f1c0 [Channel: 2 Bank: 6 Row:3 Column: 28] +18771: read 0x10001400 [Channel: 2 Bank: 2 Row:0 Column: 64] +18853: read 0x1000f1e0 [Channel: 2 Bank: 6 Row:3 Column: 30] +18878: read 0x10001420 [Channel: 2 Bank: 2 Row:0 Column: 66] +18960: read 0x1000f200 [Channel: 2 Bank: 6 Row:3 Column: 32] +18985: read 0x10001440 [Channel: 2 Bank: 2 Row:0 Column: 68] +19050: read 0x1000f220 [Channel: 2 Bank: 6 Row:3 Column: 34] +19080: read 0x401640 [Channel: 0 Bank: 2 Row:256 Column: 100] +19105: read 0x401660 [Channel: 0 Bank: 2 Row:256 Column: 102] +19130: read 0x401680 [Channel: 0 Bank: 2 Row:256 Column: 104] +19155: read 0x4016a0 [Channel: 0 Bank: 2 Row:256 Column: 106] +19183: read 0x4016c0 [Channel: 0 Bank: 2 Row:256 Column: 108] +19183: read 0x10007140 [Channel: 2 Bank: 6 Row:1 Column: 20] +19208: read 0x4016e0 [Channel: 0 Bank: 2 Row:256 Column: 110] +19240: read 0x401700 [Channel: 0 Bank: 2 Row:256 Column: 112] +19268: read 0x401760 [Channel: 0 Bank: 2 Row:256 Column: 118] +19296: read 0x401800 [Channel: 0 Bank: 3 Row:256 Column: 0] +19320: read 0x405940 [Channel: 0 Bank: 3 Row:257 Column: 20] +19345: read 0x405960 [Channel: 0 Bank: 3 Row:257 Column: 22] +19373: read 0x405980 [Channel: 0 Bank: 3 Row:257 Column: 24] +19397: read 0x405f00 [Channel: 0 Bank: 3 Row:257 Column: 112] +19422: read 0x405f20 [Channel: 0 Bank: 3 Row:257 Column: 114] +19425: read 0x405f40 [Channel: 0 Bank: 3 Row:257 Column: 116] +19447: read 0x7fff7f40 [Channel: 3 Bank: 7 Row:8189 Column: 116] +19472: read 0x405f60 [Channel: 0 Bank: 3 Row:257 Column: 118] +19500: read 0x405f80 [Channel: 0 Bank: 3 Row:257 Column: 120] +19503: read 0x405fa0 [Channel: 0 Bank: 3 Row:257 Column: 122] +19528: read 0x10006c80 [Channel: 2 Bank: 5 Row:1 Column: 72] +19556: read 0x405fc0 [Channel: 0 Bank: 3 Row:257 Column: 124] +19583: read 0x405fe0 [Channel: 0 Bank: 3 Row:257 Column: 126] +19584: read 0x10006ca0 [Channel: 2 Bank: 5 Row:1 Column: 74] +19615: read 0x406020 [Channel: 0 Bank: 4 Row:257 Column: 2] +19617: read 0x406040 [Channel: 0 Bank: 4 Row:257 Column: 4] +19643: read 0x10006cc0 [Channel: 2 Bank: 5 Row:1 Column: 76] +19674: read 0x40acc0 [Channel: 0 Bank: 5 Row:258 Column: 76] +19678: read 0x40ace0 [Channel: 0 Bank: 5 Row:258 Column: 78] +19699: read 0x7fff75a0 [Channel: 3 Bank: 6 Row:8189 Column: 90] +19724: read 0x40ad00 [Channel: 0 Bank: 5 Row:258 Column: 80] +19749: read 0x40ad20 [Channel: 0 Bank: 5 Row:258 Column: 82] +19773: read 0x40ad40 [Channel: 0 Bank: 5 Row:258 Column: 84] +19801: read 0x40ad60 [Channel: 0 Bank: 5 Row:258 Column: 86] +19826: read 0x40ada0 [Channel: 0 Bank: 5 Row:258 Column: 90] +19851: read 0x40adc0 [Channel: 0 Bank: 5 Row:258 Column: 92] +19875: read 0x40ade0 [Channel: 0 Bank: 5 Row:258 Column: 94] +19903: read 0x40ae00 [Channel: 0 Bank: 5 Row:258 Column: 96] +19906: read 0x40ae20 [Channel: 0 Bank: 5 Row:258 Column: 98] +19928: read 0x100070a0 [Channel: 2 Bank: 6 Row:1 Column: 10] +19953: read 0x40ae40 [Channel: 0 Bank: 5 Row:258 Column: 100] +19956: read 0x40ae60 [Channel: 0 Bank: 5 Row:258 Column: 102] +19978: read 0x10005b40 [Channel: 2 Bank: 3 Row:1 Column: 52] +20003: read 0x40ae80 [Channel: 0 Bank: 5 Row:258 Column: 104] +20005: read 0x40aea0 [Channel: 0 Bank: 5 Row:258 Column: 106] +20031: read 0x10005b60 [Channel: 2 Bank: 3 Row:1 Column: 54] +20062: read 0x412600 [Channel: 0 Bank: 4 Row:260 Column: 96] +20066: read 0x412620 [Channel: 0 Bank: 4 Row:260 Column: 98] +20090: read 0x7fff7580 [Channel: 3 Bank: 6 Row:8189 Column: 88] +20115: read 0x412640 [Channel: 0 Bank: 4 Row:260 Column: 100] +20143: read 0x412660 [Channel: 0 Bank: 4 Row:260 Column: 102] +20173: read 0x415680 [Channel: 0 Bank: 2 Row:261 Column: 104] +20198: read 0x4156a0 [Channel: 0 Bank: 2 Row:261 Column: 106] +20201: read 0x412680 [Channel: 0 Bank: 4 Row:260 Column: 104] +20223: read 0x7fff7540 [Channel: 3 Bank: 6 Row:8189 Column: 84] +20247: read 0x4126a0 [Channel: 0 Bank: 4 Row:260 Column: 106] +20275: read 0x4126c0 [Channel: 0 Bank: 4 Row:260 Column: 108] +20300: read 0x4156c0 [Channel: 0 Bank: 2 Row:261 Column: 108] +20304: read 0x4156e0 [Channel: 0 Bank: 2 Row:261 Column: 110] +20328: read 0x7fff7520 [Channel: 3 Bank: 6 Row:8189 Column: 82] +20353: read 0x415860 [Channel: 0 Bank: 3 Row:261 Column: 6] +20378: read 0x415880 [Channel: 0 Bank: 3 Row:261 Column: 8] +20403: read 0x415700 [Channel: 0 Bank: 2 Row:261 Column: 112] +20432: read 0x415720 [Channel: 0 Bank: 2 Row:261 Column: 114] +20457: read 0x4126e0 [Channel: 0 Bank: 4 Row:260 Column: 110] +20482: read 0x412700 [Channel: 0 Bank: 4 Row:260 Column: 112] +20485: read 0x412720 [Channel: 0 Bank: 4 Row:260 Column: 114] +20507: read 0x7fff7560 [Channel: 3 Bank: 6 Row:8189 Column: 86] +20535: read 0x40aec0 [Channel: 0 Bank: 5 Row:258 Column: 108] +20560: read 0x40aee0 [Channel: 0 Bank: 5 Row:258 Column: 110] +20584: read 0x40af00 [Channel: 0 Bank: 5 Row:258 Column: 112] +20612: read 0x40af20 [Channel: 0 Bank: 5 Row:258 Column: 114] +20636: read 0x409220 [Channel: 0 Bank: 2 Row:258 Column: 34] +20661: read 0x409240 [Channel: 0 Bank: 2 Row:258 Column: 36] +20691: read 0x409260 [Channel: 0 Bank: 2 Row:258 Column: 38] +20718: read 0x409280 [Channel: 0 Bank: 2 Row:258 Column: 40] +20719: read 0x10007220 [Channel: 2 Bank: 6 Row:1 Column: 34] +20750: read 0x408c80 [Channel: 0 Bank: 1 Row:258 Column: 72] +20752: read 0x408ca0 [Channel: 0 Bank: 1 Row:258 Column: 74] +20780: read 0x10007080 [Channel: 2 Bank: 6 Row:1 Column: 8] +20808: read 0x412280 [Channel: 0 Bank: 4 Row:260 Column: 40] +20842: read 0x414da0 [Channel: 0 Bank: 1 Row:261 Column: 90] +20866: read 0x414dc0 [Channel: 0 Bank: 1 Row:261 Column: 92] +20894: read 0x414de0 [Channel: 0 Bank: 1 Row:261 Column: 94] +20918: read 0x4157e0 [Channel: 0 Bank: 2 Row:261 Column: 126] +20943: read 0x415800 [Channel: 0 Bank: 3 Row:261 Column: 0] +20972: read 0x415820 [Channel: 0 Bank: 3 Row:261 Column: 2] +20997: read 0x414e00 [Channel: 0 Bank: 1 Row:261 Column: 96] +21022: read 0x414e20 [Channel: 0 Bank: 1 Row:261 Column: 98] +21047: read 0x4122a0 [Channel: 0 Bank: 4 Row:260 Column: 42] +21072: read 0x4122c0 [Channel: 0 Bank: 4 Row:260 Column: 44] +21077: read 0x4092a0 [Channel: 0 Bank: 2 Row:258 Column: 42] +21102: read 0x408cc0 [Channel: 0 Bank: 1 Row:258 Column: 76] +21151: read 0x408ce0 [Channel: 0 Bank: 1 Row:258 Column: 78] +21157: read 0x4092c0 [Channel: 0 Bank: 2 Row:258 Column: 44] +21189: read 0x408d00 [Channel: 0 Bank: 1 Row:258 Column: 80] +21214: read 0x408d20 [Channel: 0 Bank: 1 Row:258 Column: 82] +21242: read 0x408d40 [Channel: 0 Bank: 1 Row:258 Column: 84] +21267: read 0x4122e0 [Channel: 0 Bank: 4 Row:260 Column: 46] +21295: read 0x412300 [Channel: 0 Bank: 4 Row:260 Column: 48] +21319: read 0x412340 [Channel: 0 Bank: 4 Row:260 Column: 52] +21344: read 0x412360 [Channel: 0 Bank: 4 Row:260 Column: 54] +21347: read 0x412380 [Channel: 0 Bank: 4 Row:260 Column: 56] +21369: read 0x10010000 [Channel: 2 Bank: 0 Row:4 Column: 0] +21401: read 0x4123a0 [Channel: 0 Bank: 4 Row:260 Column: 58] +21406: read 0x10010020 [Channel: 2 Bank: 0 Row:4 Column: 2] +21411: read 0x10010040 [Channel: 2 Bank: 0 Row:4 Column: 4] +21416: read 0x10010060 [Channel: 2 Bank: 0 Row:4 Column: 6] +21421: read 0x10010080 [Channel: 2 Bank: 0 Row:4 Column: 8] +21426: read 0x100100a0 [Channel: 2 Bank: 0 Row:4 Column: 10] +21431: read 0x100100c0 [Channel: 2 Bank: 0 Row:4 Column: 12] +21436: read 0x100100e0 [Channel: 2 Bank: 0 Row:4 Column: 14] +21441: read 0x10010100 [Channel: 2 Bank: 0 Row:4 Column: 16] +21446: read 0x10010120 [Channel: 2 Bank: 0 Row:4 Column: 18] +21451: read 0x10010140 [Channel: 2 Bank: 0 Row:4 Column: 20] +21456: read 0x10010160 [Channel: 2 Bank: 0 Row:4 Column: 22] +21461: read 0x10010180 [Channel: 2 Bank: 0 Row:4 Column: 24] +21466: read 0x100101a0 [Channel: 2 Bank: 0 Row:4 Column: 26] +21471: read 0x100101c0 [Channel: 2 Bank: 0 Row:4 Column: 28] +21476: read 0x100101e0 [Channel: 2 Bank: 0 Row:4 Column: 30] +21481: read 0x10010200 [Channel: 2 Bank: 0 Row:4 Column: 32] +21486: read 0x10010220 [Channel: 2 Bank: 0 Row:4 Column: 34] +21491: read 0x10010240 [Channel: 2 Bank: 0 Row:4 Column: 36] +21496: read 0x10010260 [Channel: 2 Bank: 0 Row:4 Column: 38] +21501: read 0x10010280 [Channel: 2 Bank: 0 Row:4 Column: 40] +21506: read 0x100102a0 [Channel: 2 Bank: 0 Row:4 Column: 42] +21511: read 0x100102c0 [Channel: 2 Bank: 0 Row:4 Column: 44] +21516: read 0x100102e0 [Channel: 2 Bank: 0 Row:4 Column: 46] +21521: read 0x10010300 [Channel: 2 Bank: 0 Row:4 Column: 48] +21526: read 0x10010320 [Channel: 2 Bank: 0 Row:4 Column: 50] +21531: read 0x10010340 [Channel: 2 Bank: 0 Row:4 Column: 52] +21536: read 0x10010360 [Channel: 2 Bank: 0 Row:4 Column: 54] +21541: read 0x10010380 [Channel: 2 Bank: 0 Row:4 Column: 56] +21546: read 0x100103a0 [Channel: 2 Bank: 0 Row:4 Column: 58] +21551: read 0x100103c0 [Channel: 2 Bank: 0 Row:4 Column: 60] +21556: read 0x100103e0 [Channel: 2 Bank: 0 Row:4 Column: 62] +21561: read 0x10010400 [Channel: 2 Bank: 0 Row:4 Column: 64] +21566: read 0x10010420 [Channel: 2 Bank: 0 Row:4 Column: 66] +21571: read 0x10010440 [Channel: 2 Bank: 0 Row:4 Column: 68] +21576: read 0x10010460 [Channel: 2 Bank: 0 Row:4 Column: 70] +21581: read 0x10010480 [Channel: 2 Bank: 0 Row:4 Column: 72] +21586: read 0x100104a0 [Channel: 2 Bank: 0 Row:4 Column: 74] +21591: read 0x100104c0 [Channel: 2 Bank: 0 Row:4 Column: 76] +21596: read 0x100104e0 [Channel: 2 Bank: 0 Row:4 Column: 78] +21601: read 0x10010500 [Channel: 2 Bank: 0 Row:4 Column: 80] +21606: read 0x10010520 [Channel: 2 Bank: 0 Row:4 Column: 82] +21611: read 0x10010540 [Channel: 2 Bank: 0 Row:4 Column: 84] +21616: read 0x10010560 [Channel: 2 Bank: 0 Row:4 Column: 86] +21621: read 0x10010580 [Channel: 2 Bank: 0 Row:4 Column: 88] +21626: read 0x100105a0 [Channel: 2 Bank: 0 Row:4 Column: 90] +21631: read 0x100105c0 [Channel: 2 Bank: 0 Row:4 Column: 92] +21636: read 0x100105e0 [Channel: 2 Bank: 0 Row:4 Column: 94] +21641: read 0x10010600 [Channel: 2 Bank: 0 Row:4 Column: 96] +21646: read 0x10010620 [Channel: 2 Bank: 0 Row:4 Column: 98] +21651: read 0x10010640 [Channel: 2 Bank: 0 Row:4 Column: 100] +21656: read 0x10010660 [Channel: 2 Bank: 0 Row:4 Column: 102] +21661: read 0x10010680 [Channel: 2 Bank: 0 Row:4 Column: 104] +21666: read 0x100106a0 [Channel: 2 Bank: 0 Row:4 Column: 106] +21671: read 0x100106c0 [Channel: 2 Bank: 0 Row:4 Column: 108] +21676: read 0x100106e0 [Channel: 2 Bank: 0 Row:4 Column: 110] +21681: read 0x10010700 [Channel: 2 Bank: 0 Row:4 Column: 112] +21686: read 0x10010720 [Channel: 2 Bank: 0 Row:4 Column: 114] +21691: read 0x10010740 [Channel: 2 Bank: 0 Row:4 Column: 116] +21696: read 0x10010760 [Channel: 2 Bank: 0 Row:4 Column: 118] +21701: read 0x10010780 [Channel: 2 Bank: 0 Row:4 Column: 120] +21706: read 0x100107a0 [Channel: 2 Bank: 0 Row:4 Column: 122] +21711: read 0x100107c0 [Channel: 2 Bank: 0 Row:4 Column: 124] +21716: read 0x100107e0 [Channel: 2 Bank: 0 Row:4 Column: 126] +21721: read 0x10010800 [Channel: 2 Bank: 1 Row:4 Column: 0] +21726: read 0x10010820 [Channel: 2 Bank: 1 Row:4 Column: 2] +21731: read 0x10010840 [Channel: 2 Bank: 1 Row:4 Column: 4] +21736: read 0x10010860 [Channel: 2 Bank: 1 Row:4 Column: 6] +21741: read 0x10010880 [Channel: 2 Bank: 1 Row:4 Column: 8] +21746: read 0x100108a0 [Channel: 2 Bank: 1 Row:4 Column: 10] +21751: read 0x100108c0 [Channel: 2 Bank: 1 Row:4 Column: 12] +21756: read 0x100108e0 [Channel: 2 Bank: 1 Row:4 Column: 14] +21761: read 0x10010900 [Channel: 2 Bank: 1 Row:4 Column: 16] +21766: read 0x10010920 [Channel: 2 Bank: 1 Row:4 Column: 18] +21771: read 0x10010940 [Channel: 2 Bank: 1 Row:4 Column: 20] +21776: read 0x10010960 [Channel: 2 Bank: 1 Row:4 Column: 22] +21781: read 0x10010980 [Channel: 2 Bank: 1 Row:4 Column: 24] +21786: read 0x100109a0 [Channel: 2 Bank: 1 Row:4 Column: 26] +21791: read 0x100109c0 [Channel: 2 Bank: 1 Row:4 Column: 28] +21796: read 0x100109e0 [Channel: 2 Bank: 1 Row:4 Column: 30] +21801: read 0x10010a00 [Channel: 2 Bank: 1 Row:4 Column: 32] +21806: read 0x10010a20 [Channel: 2 Bank: 1 Row:4 Column: 34] +21811: read 0x10010a40 [Channel: 2 Bank: 1 Row:4 Column: 36] +21816: read 0x10010a60 [Channel: 2 Bank: 1 Row:4 Column: 38] +21821: read 0x10010a80 [Channel: 2 Bank: 1 Row:4 Column: 40] +21826: read 0x10010aa0 [Channel: 2 Bank: 1 Row:4 Column: 42] +21831: read 0x10010ac0 [Channel: 2 Bank: 1 Row:4 Column: 44] +21836: read 0x10010ae0 [Channel: 2 Bank: 1 Row:4 Column: 46] +21841: read 0x10010b00 [Channel: 2 Bank: 1 Row:4 Column: 48] +21846: read 0x10010b20 [Channel: 2 Bank: 1 Row:4 Column: 50] +21851: read 0x10010b40 [Channel: 2 Bank: 1 Row:4 Column: 52] +21856: read 0x10010b60 [Channel: 2 Bank: 1 Row:4 Column: 54] +21861: read 0x10010b80 [Channel: 2 Bank: 1 Row:4 Column: 56] +21866: read 0x10010ba0 [Channel: 2 Bank: 1 Row:4 Column: 58] +21871: read 0x10010bc0 [Channel: 2 Bank: 1 Row:4 Column: 60] +21876: read 0x10010be0 [Channel: 2 Bank: 1 Row:4 Column: 62] +21881: read 0x10010c00 [Channel: 2 Bank: 1 Row:4 Column: 64] +21886: read 0x10010c20 [Channel: 2 Bank: 1 Row:4 Column: 66] +21891: read 0x10010c40 [Channel: 2 Bank: 1 Row:4 Column: 68] +21896: read 0x10010c60 [Channel: 2 Bank: 1 Row:4 Column: 70] +21901: read 0x10010c80 [Channel: 2 Bank: 1 Row:4 Column: 72] +21906: read 0x10010ca0 [Channel: 2 Bank: 1 Row:4 Column: 74] +21911: read 0x10010cc0 [Channel: 2 Bank: 1 Row:4 Column: 76] +21916: read 0x10010ce0 [Channel: 2 Bank: 1 Row:4 Column: 78] +21921: read 0x10010d00 [Channel: 2 Bank: 1 Row:4 Column: 80] +21926: read 0x10010d20 [Channel: 2 Bank: 1 Row:4 Column: 82] +21931: read 0x10010d40 [Channel: 2 Bank: 1 Row:4 Column: 84] +21936: read 0x10010d60 [Channel: 2 Bank: 1 Row:4 Column: 86] +21941: read 0x10010d80 [Channel: 2 Bank: 1 Row:4 Column: 88] +21946: read 0x10010da0 [Channel: 2 Bank: 1 Row:4 Column: 90] +21951: read 0x10010dc0 [Channel: 2 Bank: 1 Row:4 Column: 92] +21956: read 0x10010de0 [Channel: 2 Bank: 1 Row:4 Column: 94] +21961: read 0x10010e00 [Channel: 2 Bank: 1 Row:4 Column: 96] +21966: read 0x10010e20 [Channel: 2 Bank: 1 Row:4 Column: 98] +21971: read 0x10010e40 [Channel: 2 Bank: 1 Row:4 Column: 100] +21976: read 0x10010e60 [Channel: 2 Bank: 1 Row:4 Column: 102] +21981: read 0x10010e80 [Channel: 2 Bank: 1 Row:4 Column: 104] +21986: read 0x10010ea0 [Channel: 2 Bank: 1 Row:4 Column: 106] +21991: read 0x10010ec0 [Channel: 2 Bank: 1 Row:4 Column: 108] +21996: read 0x10010ee0 [Channel: 2 Bank: 1 Row:4 Column: 110] +22001: read 0x10010f00 [Channel: 2 Bank: 1 Row:4 Column: 112] +22006: read 0x10010f20 [Channel: 2 Bank: 1 Row:4 Column: 114] +22011: read 0x10010f40 [Channel: 2 Bank: 1 Row:4 Column: 116] +22016: read 0x10010f60 [Channel: 2 Bank: 1 Row:4 Column: 118] +22021: read 0x10010f80 [Channel: 2 Bank: 1 Row:4 Column: 120] +22026: read 0x10010fa0 [Channel: 2 Bank: 1 Row:4 Column: 122] +22031: read 0x10010fc0 [Channel: 2 Bank: 1 Row:4 Column: 124] +22036: read 0x10010fe0 [Channel: 2 Bank: 1 Row:4 Column: 126] +22041: read 0x10011000 [Channel: 2 Bank: 2 Row:4 Column: 0] +22046: read 0x10011020 [Channel: 2 Bank: 2 Row:4 Column: 2] +22051: read 0x10011040 [Channel: 2 Bank: 2 Row:4 Column: 4] +22056: read 0x10011060 [Channel: 2 Bank: 2 Row:4 Column: 6] +22061: read 0x10011080 [Channel: 2 Bank: 2 Row:4 Column: 8] +22066: read 0x100110a0 [Channel: 2 Bank: 2 Row:4 Column: 10] +22071: read 0x100110c0 [Channel: 2 Bank: 2 Row:4 Column: 12] +22076: read 0x100110e0 [Channel: 2 Bank: 2 Row:4 Column: 14] +22081: read 0x10011100 [Channel: 2 Bank: 2 Row:4 Column: 16] +22086: read 0x10011120 [Channel: 2 Bank: 2 Row:4 Column: 18] +22091: read 0x10011140 [Channel: 2 Bank: 2 Row:4 Column: 20] +22096: read 0x10011160 [Channel: 2 Bank: 2 Row:4 Column: 22] +22101: read 0x10011180 [Channel: 2 Bank: 2 Row:4 Column: 24] +22106: read 0x100111a0 [Channel: 2 Bank: 2 Row:4 Column: 26] +22111: read 0x100111c0 [Channel: 2 Bank: 2 Row:4 Column: 28] +22116: read 0x100111e0 [Channel: 2 Bank: 2 Row:4 Column: 30] +22121: read 0x10011200 [Channel: 2 Bank: 2 Row:4 Column: 32] +22126: read 0x10011220 [Channel: 2 Bank: 2 Row:4 Column: 34] +22131: read 0x10011240 [Channel: 2 Bank: 2 Row:4 Column: 36] +22136: read 0x10011260 [Channel: 2 Bank: 2 Row:4 Column: 38] +22141: read 0x10011280 [Channel: 2 Bank: 2 Row:4 Column: 40] +22146: read 0x100112a0 [Channel: 2 Bank: 2 Row:4 Column: 42] +22151: read 0x100112c0 [Channel: 2 Bank: 2 Row:4 Column: 44] +22156: read 0x100112e0 [Channel: 2 Bank: 2 Row:4 Column: 46] +22161: read 0x10011300 [Channel: 2 Bank: 2 Row:4 Column: 48] +22166: read 0x10011320 [Channel: 2 Bank: 2 Row:4 Column: 50] +22171: read 0x10011340 [Channel: 2 Bank: 2 Row:4 Column: 52] +22176: read 0x10011360 [Channel: 2 Bank: 2 Row:4 Column: 54] +22181: read 0x10011380 [Channel: 2 Bank: 2 Row:4 Column: 56] +22186: read 0x100113a0 [Channel: 2 Bank: 2 Row:4 Column: 58] +22191: read 0x100113c0 [Channel: 2 Bank: 2 Row:4 Column: 60] +22196: read 0x100113e0 [Channel: 2 Bank: 2 Row:4 Column: 62] +22201: read 0x10011400 [Channel: 2 Bank: 2 Row:4 Column: 64] +22206: read 0x10011420 [Channel: 2 Bank: 2 Row:4 Column: 66] +22211: read 0x10011440 [Channel: 2 Bank: 2 Row:4 Column: 68] +22216: read 0x10011460 [Channel: 2 Bank: 2 Row:4 Column: 70] +22221: read 0x10011480 [Channel: 2 Bank: 2 Row:4 Column: 72] +22226: read 0x100114a0 [Channel: 2 Bank: 2 Row:4 Column: 74] +22231: read 0x100114c0 [Channel: 2 Bank: 2 Row:4 Column: 76] +22236: read 0x100114e0 [Channel: 2 Bank: 2 Row:4 Column: 78] +22241: read 0x10011500 [Channel: 2 Bank: 2 Row:4 Column: 80] +22246: read 0x10011520 [Channel: 2 Bank: 2 Row:4 Column: 82] +22251: read 0x10011540 [Channel: 2 Bank: 2 Row:4 Column: 84] +22256: read 0x10011560 [Channel: 2 Bank: 2 Row:4 Column: 86] +22261: read 0x10011580 [Channel: 2 Bank: 2 Row:4 Column: 88] +22266: read 0x100115a0 [Channel: 2 Bank: 2 Row:4 Column: 90] +22271: read 0x100115c0 [Channel: 2 Bank: 2 Row:4 Column: 92] +22276: read 0x100115e0 [Channel: 2 Bank: 2 Row:4 Column: 94] +22281: read 0x10011600 [Channel: 2 Bank: 2 Row:4 Column: 96] +22286: read 0x10011620 [Channel: 2 Bank: 2 Row:4 Column: 98] +22291: read 0x10011640 [Channel: 2 Bank: 2 Row:4 Column: 100] +22296: read 0x10011660 [Channel: 2 Bank: 2 Row:4 Column: 102] +22301: read 0x10011680 [Channel: 2 Bank: 2 Row:4 Column: 104] +22306: read 0x100116a0 [Channel: 2 Bank: 2 Row:4 Column: 106] +22311: read 0x100116c0 [Channel: 2 Bank: 2 Row:4 Column: 108] +22316: read 0x100116e0 [Channel: 2 Bank: 2 Row:4 Column: 110] +22321: read 0x10011700 [Channel: 2 Bank: 2 Row:4 Column: 112] +22326: read 0x10011720 [Channel: 2 Bank: 2 Row:4 Column: 114] +22331: read 0x10011740 [Channel: 2 Bank: 2 Row:4 Column: 116] +22336: read 0x10011760 [Channel: 2 Bank: 2 Row:4 Column: 118] +22341: read 0x10011780 [Channel: 2 Bank: 2 Row:4 Column: 120] +22346: read 0x100117a0 [Channel: 2 Bank: 2 Row:4 Column: 122] +22351: read 0x100117c0 [Channel: 2 Bank: 2 Row:4 Column: 124] +22356: read 0x100117e0 [Channel: 2 Bank: 2 Row:4 Column: 126] +22361: read 0x10011800 [Channel: 2 Bank: 3 Row:4 Column: 0] +22366: read 0x10011820 [Channel: 2 Bank: 3 Row:4 Column: 2] +22371: read 0x10011840 [Channel: 2 Bank: 3 Row:4 Column: 4] +22376: read 0x10011860 [Channel: 2 Bank: 3 Row:4 Column: 6] +22381: read 0x10011880 [Channel: 2 Bank: 3 Row:4 Column: 8] +22386: read 0x100118a0 [Channel: 2 Bank: 3 Row:4 Column: 10] +22391: read 0x100118c0 [Channel: 2 Bank: 3 Row:4 Column: 12] +22396: read 0x100118e0 [Channel: 2 Bank: 3 Row:4 Column: 14] +22401: read 0x10011900 [Channel: 2 Bank: 3 Row:4 Column: 16] +22406: read 0x10011920 [Channel: 2 Bank: 3 Row:4 Column: 18] +22411: read 0x10011940 [Channel: 2 Bank: 3 Row:4 Column: 20] +22416: read 0x10011960 [Channel: 2 Bank: 3 Row:4 Column: 22] +22421: read 0x10011980 [Channel: 2 Bank: 3 Row:4 Column: 24] +22426: read 0x100119a0 [Channel: 2 Bank: 3 Row:4 Column: 26] +22431: read 0x100119c0 [Channel: 2 Bank: 3 Row:4 Column: 28] +22436: read 0x100119e0 [Channel: 2 Bank: 3 Row:4 Column: 30] +22441: read 0x10011a00 [Channel: 2 Bank: 3 Row:4 Column: 32] +22446: read 0x10011a20 [Channel: 2 Bank: 3 Row:4 Column: 34] +22451: read 0x10011a40 [Channel: 2 Bank: 3 Row:4 Column: 36] +22456: read 0x10011a60 [Channel: 2 Bank: 3 Row:4 Column: 38] +22461: read 0x10011a80 [Channel: 2 Bank: 3 Row:4 Column: 40] +22466: read 0x10011aa0 [Channel: 2 Bank: 3 Row:4 Column: 42] +22471: read 0x10011ac0 [Channel: 2 Bank: 3 Row:4 Column: 44] +22476: read 0x10011ae0 [Channel: 2 Bank: 3 Row:4 Column: 46] +22481: read 0x10011b00 [Channel: 2 Bank: 3 Row:4 Column: 48] +22486: read 0x10011b20 [Channel: 2 Bank: 3 Row:4 Column: 50] +22491: read 0x10011b40 [Channel: 2 Bank: 3 Row:4 Column: 52] +22496: read 0x10011b60 [Channel: 2 Bank: 3 Row:4 Column: 54] +22501: read 0x10011b80 [Channel: 2 Bank: 3 Row:4 Column: 56] +22506: read 0x10011ba0 [Channel: 2 Bank: 3 Row:4 Column: 58] +22511: read 0x10011bc0 [Channel: 2 Bank: 3 Row:4 Column: 60] +22516: read 0x10011be0 [Channel: 2 Bank: 3 Row:4 Column: 62] +22521: read 0x10011c00 [Channel: 2 Bank: 3 Row:4 Column: 64] +22526: read 0x10011c20 [Channel: 2 Bank: 3 Row:4 Column: 66] +22531: read 0x10011c40 [Channel: 2 Bank: 3 Row:4 Column: 68] +22536: read 0x10011c60 [Channel: 2 Bank: 3 Row:4 Column: 70] +22541: read 0x10011c80 [Channel: 2 Bank: 3 Row:4 Column: 72] +22546: read 0x10011ca0 [Channel: 2 Bank: 3 Row:4 Column: 74] +22551: read 0x10011cc0 [Channel: 2 Bank: 3 Row:4 Column: 76] +22556: read 0x10011ce0 [Channel: 2 Bank: 3 Row:4 Column: 78] +22561: read 0x10011d00 [Channel: 2 Bank: 3 Row:4 Column: 80] +22566: read 0x10011d20 [Channel: 2 Bank: 3 Row:4 Column: 82] +22571: read 0x10011d40 [Channel: 2 Bank: 3 Row:4 Column: 84] +22576: read 0x10011d60 [Channel: 2 Bank: 3 Row:4 Column: 86] +22581: read 0x10011d80 [Channel: 2 Bank: 3 Row:4 Column: 88] +22586: read 0x10011da0 [Channel: 2 Bank: 3 Row:4 Column: 90] +22591: read 0x10011dc0 [Channel: 2 Bank: 3 Row:4 Column: 92] +22596: read 0x10011de0 [Channel: 2 Bank: 3 Row:4 Column: 94] +22601: read 0x10011e00 [Channel: 2 Bank: 3 Row:4 Column: 96] +22606: read 0x10011e20 [Channel: 2 Bank: 3 Row:4 Column: 98] +22611: read 0x10011e40 [Channel: 2 Bank: 3 Row:4 Column: 100] +22616: read 0x10011e60 [Channel: 2 Bank: 3 Row:4 Column: 102] +22621: read 0x10011e80 [Channel: 2 Bank: 3 Row:4 Column: 104] +22626: read 0x10011ea0 [Channel: 2 Bank: 3 Row:4 Column: 106] +22631: read 0x10011ec0 [Channel: 2 Bank: 3 Row:4 Column: 108] +22636: read 0x10011ee0 [Channel: 2 Bank: 3 Row:4 Column: 110] +22641: read 0x10011f00 [Channel: 2 Bank: 3 Row:4 Column: 112] +22646: read 0x10011f20 [Channel: 2 Bank: 3 Row:4 Column: 114] +22651: read 0x10011f40 [Channel: 2 Bank: 3 Row:4 Column: 116] +22656: read 0x10011f60 [Channel: 2 Bank: 3 Row:4 Column: 118] +22661: read 0x10011f80 [Channel: 2 Bank: 3 Row:4 Column: 120] +22666: read 0x10011fa0 [Channel: 2 Bank: 3 Row:4 Column: 122] +22671: read 0x10011fc0 [Channel: 2 Bank: 3 Row:4 Column: 124] +22676: read 0x10011fe0 [Channel: 2 Bank: 3 Row:4 Column: 126] +22681: read 0x10012000 [Channel: 2 Bank: 4 Row:4 Column: 0] +22686: read 0x10012020 [Channel: 2 Bank: 4 Row:4 Column: 2] +22691: read 0x10012040 [Channel: 2 Bank: 4 Row:4 Column: 4] +22696: read 0x10012060 [Channel: 2 Bank: 4 Row:4 Column: 6] +22701: read 0x10012080 [Channel: 2 Bank: 4 Row:4 Column: 8] +22706: read 0x100120a0 [Channel: 2 Bank: 4 Row:4 Column: 10] +22711: read 0x100120c0 [Channel: 2 Bank: 4 Row:4 Column: 12] +22716: read 0x100120e0 [Channel: 2 Bank: 4 Row:4 Column: 14] +22721: read 0x10012100 [Channel: 2 Bank: 4 Row:4 Column: 16] +22726: read 0x10012120 [Channel: 2 Bank: 4 Row:4 Column: 18] +22731: read 0x10012140 [Channel: 2 Bank: 4 Row:4 Column: 20] +22736: read 0x10012160 [Channel: 2 Bank: 4 Row:4 Column: 22] +22741: read 0x10012180 [Channel: 2 Bank: 4 Row:4 Column: 24] +22746: read 0x100121a0 [Channel: 2 Bank: 4 Row:4 Column: 26] +22751: read 0x100121c0 [Channel: 2 Bank: 4 Row:4 Column: 28] +22756: read 0x100121e0 [Channel: 2 Bank: 4 Row:4 Column: 30] +22761: read 0x10012200 [Channel: 2 Bank: 4 Row:4 Column: 32] +22766: read 0x10012220 [Channel: 2 Bank: 4 Row:4 Column: 34] +22771: read 0x10012240 [Channel: 2 Bank: 4 Row:4 Column: 36] +22776: read 0x10012260 [Channel: 2 Bank: 4 Row:4 Column: 38] +22781: read 0x10012280 [Channel: 2 Bank: 4 Row:4 Column: 40] +22786: read 0x100122a0 [Channel: 2 Bank: 4 Row:4 Column: 42] +22791: read 0x100122c0 [Channel: 2 Bank: 4 Row:4 Column: 44] +22796: read 0x100122e0 [Channel: 2 Bank: 4 Row:4 Column: 46] +22801: read 0x10012300 [Channel: 2 Bank: 4 Row:4 Column: 48] +22806: read 0x10012320 [Channel: 2 Bank: 4 Row:4 Column: 50] +22811: read 0x10012340 [Channel: 2 Bank: 4 Row:4 Column: 52] +22816: read 0x10012360 [Channel: 2 Bank: 4 Row:4 Column: 54] +22821: read 0x10012380 [Channel: 2 Bank: 4 Row:4 Column: 56] +22826: read 0x100123a0 [Channel: 2 Bank: 4 Row:4 Column: 58] +22831: read 0x100123c0 [Channel: 2 Bank: 4 Row:4 Column: 60] +22836: read 0x100123e0 [Channel: 2 Bank: 4 Row:4 Column: 62] +22841: read 0x10012400 [Channel: 2 Bank: 4 Row:4 Column: 64] +22846: read 0x10012420 [Channel: 2 Bank: 4 Row:4 Column: 66] +22851: read 0x10012440 [Channel: 2 Bank: 4 Row:4 Column: 68] +22856: read 0x10012460 [Channel: 2 Bank: 4 Row:4 Column: 70] +22861: read 0x10012480 [Channel: 2 Bank: 4 Row:4 Column: 72] +22866: read 0x100124a0 [Channel: 2 Bank: 4 Row:4 Column: 74] +22871: read 0x100124c0 [Channel: 2 Bank: 4 Row:4 Column: 76] +22876: read 0x100124e0 [Channel: 2 Bank: 4 Row:4 Column: 78] +22881: read 0x10012500 [Channel: 2 Bank: 4 Row:4 Column: 80] +22886: read 0x10012520 [Channel: 2 Bank: 4 Row:4 Column: 82] +22891: read 0x10012540 [Channel: 2 Bank: 4 Row:4 Column: 84] +22896: read 0x10012560 [Channel: 2 Bank: 4 Row:4 Column: 86] +22901: read 0x10012580 [Channel: 2 Bank: 4 Row:4 Column: 88] +22906: read 0x100125a0 [Channel: 2 Bank: 4 Row:4 Column: 90] +22911: read 0x100125c0 [Channel: 2 Bank: 4 Row:4 Column: 92] +22916: read 0x100125e0 [Channel: 2 Bank: 4 Row:4 Column: 94] +22921: read 0x10012600 [Channel: 2 Bank: 4 Row:4 Column: 96] +22926: read 0x10012620 [Channel: 2 Bank: 4 Row:4 Column: 98] +22931: read 0x10012640 [Channel: 2 Bank: 4 Row:4 Column: 100] +22936: read 0x10012660 [Channel: 2 Bank: 4 Row:4 Column: 102] +22941: read 0x10012680 [Channel: 2 Bank: 4 Row:4 Column: 104] +22946: read 0x100126a0 [Channel: 2 Bank: 4 Row:4 Column: 106] +22951: read 0x100126c0 [Channel: 2 Bank: 4 Row:4 Column: 108] +22956: read 0x100126e0 [Channel: 2 Bank: 4 Row:4 Column: 110] +22961: read 0x10012700 [Channel: 2 Bank: 4 Row:4 Column: 112] +22966: read 0x10012720 [Channel: 2 Bank: 4 Row:4 Column: 114] +22971: read 0x10012740 [Channel: 2 Bank: 4 Row:4 Column: 116] +22976: read 0x10012760 [Channel: 2 Bank: 4 Row:4 Column: 118] +22981: read 0x10012780 [Channel: 2 Bank: 4 Row:4 Column: 120] +22986: read 0x100127a0 [Channel: 2 Bank: 4 Row:4 Column: 122] +22991: read 0x100127c0 [Channel: 2 Bank: 4 Row:4 Column: 124] +22996: read 0x100127e0 [Channel: 2 Bank: 4 Row:4 Column: 126] +23001: read 0x10012800 [Channel: 2 Bank: 5 Row:4 Column: 0] +23006: read 0x10012820 [Channel: 2 Bank: 5 Row:4 Column: 2] +23011: read 0x10012840 [Channel: 2 Bank: 5 Row:4 Column: 4] +23016: read 0x10012860 [Channel: 2 Bank: 5 Row:4 Column: 6] +23021: read 0x10012880 [Channel: 2 Bank: 5 Row:4 Column: 8] +23026: read 0x100128a0 [Channel: 2 Bank: 5 Row:4 Column: 10] +23031: read 0x100128c0 [Channel: 2 Bank: 5 Row:4 Column: 12] +23036: read 0x100128e0 [Channel: 2 Bank: 5 Row:4 Column: 14] +23041: read 0x10012900 [Channel: 2 Bank: 5 Row:4 Column: 16] +23046: read 0x10012920 [Channel: 2 Bank: 5 Row:4 Column: 18] +23051: read 0x10012940 [Channel: 2 Bank: 5 Row:4 Column: 20] +23056: read 0x10012960 [Channel: 2 Bank: 5 Row:4 Column: 22] +23061: read 0x10012980 [Channel: 2 Bank: 5 Row:4 Column: 24] +23066: read 0x100129a0 [Channel: 2 Bank: 5 Row:4 Column: 26] +23071: read 0x100129c0 [Channel: 2 Bank: 5 Row:4 Column: 28] +23076: read 0x100129e0 [Channel: 2 Bank: 5 Row:4 Column: 30] +23081: read 0x10012a00 [Channel: 2 Bank: 5 Row:4 Column: 32] +23086: read 0x10012a20 [Channel: 2 Bank: 5 Row:4 Column: 34] +23091: read 0x10012a40 [Channel: 2 Bank: 5 Row:4 Column: 36] +23096: read 0x10012a60 [Channel: 2 Bank: 5 Row:4 Column: 38] +23101: read 0x10012a80 [Channel: 2 Bank: 5 Row:4 Column: 40] +23106: read 0x10012aa0 [Channel: 2 Bank: 5 Row:4 Column: 42] +23111: read 0x10012ac0 [Channel: 2 Bank: 5 Row:4 Column: 44] +23116: read 0x10012ae0 [Channel: 2 Bank: 5 Row:4 Column: 46] +23121: read 0x10012b00 [Channel: 2 Bank: 5 Row:4 Column: 48] +23126: read 0x10012b20 [Channel: 2 Bank: 5 Row:4 Column: 50] +23131: read 0x10012b40 [Channel: 2 Bank: 5 Row:4 Column: 52] +23136: read 0x10012b60 [Channel: 2 Bank: 5 Row:4 Column: 54] +23141: read 0x10012b80 [Channel: 2 Bank: 5 Row:4 Column: 56] +23146: read 0x10012ba0 [Channel: 2 Bank: 5 Row:4 Column: 58] +23151: read 0x10012bc0 [Channel: 2 Bank: 5 Row:4 Column: 60] +23156: read 0x10012be0 [Channel: 2 Bank: 5 Row:4 Column: 62] +23161: read 0x10012c00 [Channel: 2 Bank: 5 Row:4 Column: 64] +23166: read 0x10012c20 [Channel: 2 Bank: 5 Row:4 Column: 66] +23171: read 0x10012c40 [Channel: 2 Bank: 5 Row:4 Column: 68] +23176: read 0x10012c60 [Channel: 2 Bank: 5 Row:4 Column: 70] +23181: read 0x10012c80 [Channel: 2 Bank: 5 Row:4 Column: 72] +23186: read 0x10012ca0 [Channel: 2 Bank: 5 Row:4 Column: 74] +23191: read 0x10012cc0 [Channel: 2 Bank: 5 Row:4 Column: 76] +23196: read 0x10012ce0 [Channel: 2 Bank: 5 Row:4 Column: 78] +23201: read 0x10012d00 [Channel: 2 Bank: 5 Row:4 Column: 80] +23206: read 0x10012d20 [Channel: 2 Bank: 5 Row:4 Column: 82] +23211: read 0x10012d40 [Channel: 2 Bank: 5 Row:4 Column: 84] +23216: read 0x10012d60 [Channel: 2 Bank: 5 Row:4 Column: 86] +23221: read 0x10012d80 [Channel: 2 Bank: 5 Row:4 Column: 88] +23226: read 0x10012da0 [Channel: 2 Bank: 5 Row:4 Column: 90] +23231: read 0x10012dc0 [Channel: 2 Bank: 5 Row:4 Column: 92] +23236: read 0x10012de0 [Channel: 2 Bank: 5 Row:4 Column: 94] +23241: read 0x10012e00 [Channel: 2 Bank: 5 Row:4 Column: 96] +23246: read 0x10012e20 [Channel: 2 Bank: 5 Row:4 Column: 98] +23251: read 0x10012e40 [Channel: 2 Bank: 5 Row:4 Column: 100] +23256: read 0x10012e60 [Channel: 2 Bank: 5 Row:4 Column: 102] +23261: read 0x10012e80 [Channel: 2 Bank: 5 Row:4 Column: 104] +23266: read 0x10012ea0 [Channel: 2 Bank: 5 Row:4 Column: 106] +23271: read 0x10012ec0 [Channel: 2 Bank: 5 Row:4 Column: 108] +23276: read 0x10012ee0 [Channel: 2 Bank: 5 Row:4 Column: 110] +23281: read 0x10012f00 [Channel: 2 Bank: 5 Row:4 Column: 112] +23286: read 0x10012f20 [Channel: 2 Bank: 5 Row:4 Column: 114] +23291: read 0x10012f40 [Channel: 2 Bank: 5 Row:4 Column: 116] +23296: read 0x10012f60 [Channel: 2 Bank: 5 Row:4 Column: 118] +23301: read 0x10012f80 [Channel: 2 Bank: 5 Row:4 Column: 120] +23306: read 0x10012fa0 [Channel: 2 Bank: 5 Row:4 Column: 122] +23311: read 0x10012fc0 [Channel: 2 Bank: 5 Row:4 Column: 124] +23318: read 0x10012fe0 [Channel: 2 Bank: 5 Row:4 Column: 126] +23343: read 0x4123c0 [Channel: 0 Bank: 4 Row:260 Column: 60] +23367: read 0x4123e0 [Channel: 0 Bank: 4 Row:260 Column: 62] +23392: read 0x412400 [Channel: 0 Bank: 4 Row:260 Column: 64] +23417: read 0x412420 [Channel: 0 Bank: 4 Row:260 Column: 66] +23442: read 0x408d60 [Channel: 0 Bank: 1 Row:258 Column: 86] +23467: read 0x408d80 [Channel: 0 Bank: 1 Row:258 Column: 88] +23492: read 0x408da0 [Channel: 0 Bank: 1 Row:258 Column: 90] +23520: read 0x408dc0 [Channel: 0 Bank: 1 Row:258 Column: 92] +23544: read 0x408de0 [Channel: 0 Bank: 1 Row:258 Column: 94] +23580: read 0x408e00 [Channel: 0 Bank: 1 Row:258 Column: 96] +23608: read 0x4092e0 [Channel: 0 Bank: 2 Row:258 Column: 46] +23633: read 0x409300 [Channel: 0 Bank: 2 Row:258 Column: 48] +23660: read 0x409320 [Channel: 0 Bank: 2 Row:258 Column: 50] +23661: read 0x1000f2e0 [Channel: 2 Bank: 6 Row:3 Column: 46] +23708: read 0x409480 [Channel: 0 Bank: 2 Row:258 Column: 72] +23733: read 0x409660 [Channel: 0 Bank: 2 Row:258 Column: 102] +23758: read 0x409680 [Channel: 0 Bank: 2 Row:258 Column: 104] +23786: read 0x4096a0 [Channel: 0 Bank: 2 Row:258 Column: 106] +23811: read 0x4096c0 [Channel: 0 Bank: 2 Row:258 Column: 108] +23839: read 0x4096e0 [Channel: 0 Bank: 2 Row:258 Column: 110] +23864: read 0x409700 [Channel: 0 Bank: 2 Row:258 Column: 112] +23892: read 0x409720 [Channel: 0 Bank: 2 Row:258 Column: 114] +23920: read 0x409800 [Channel: 0 Bank: 3 Row:258 Column: 0] +23945: read 0x408e20 [Channel: 0 Bank: 1 Row:258 Column: 98] +23980: read 0x408e40 [Channel: 0 Bank: 1 Row:258 Column: 100] +24024: read 0x7fff7500 [Channel: 3 Bank: 6 Row:8189 Column: 80] +24031: read 0x409820 [Channel: 0 Bank: 3 Row:258 Column: 2] +24059: read 0x408e60 [Channel: 0 Bank: 1 Row:258 Column: 102] +24083: read 0x408e80 [Channel: 0 Bank: 1 Row:258 Column: 104] +24117: read 0x408ea0 [Channel: 0 Bank: 1 Row:258 Column: 106] +24141: read 0x408ec0 [Channel: 0 Bank: 1 Row:258 Column: 108] +24169: read 0x408ee0 [Channel: 0 Bank: 1 Row:258 Column: 110] +24197: read 0x408f00 [Channel: 0 Bank: 1 Row:258 Column: 112] +24225: read 0x4091a0 [Channel: 0 Bank: 2 Row:258 Column: 26] +24249: read 0x4091c0 [Channel: 0 Bank: 2 Row:258 Column: 28] +24274: read 0x4091e0 [Channel: 0 Bank: 2 Row:258 Column: 30] +24304: read 0x409200 [Channel: 0 Bank: 2 Row:258 Column: 32] +24329: read 0x409840 [Channel: 0 Bank: 3 Row:258 Column: 4] +24354: read 0x409860 [Channel: 0 Bank: 3 Row:258 Column: 6] +24379: read 0x409880 [Channel: 0 Bank: 3 Row:258 Column: 8] +24404: read 0x4098a0 [Channel: 0 Bank: 3 Row:258 Column: 10] +24432: read 0x4098c0 [Channel: 0 Bank: 3 Row:258 Column: 12] +24456: read 0x409b60 [Channel: 0 Bank: 3 Row:258 Column: 54] +24492: read 0x409b80 [Channel: 0 Bank: 3 Row:258 Column: 56] +24517: read 0x4094a0 [Channel: 0 Bank: 2 Row:258 Column: 74] +24542: read 0x4094c0 [Channel: 0 Bank: 2 Row:258 Column: 76] +24567: read 0x4094e0 [Channel: 0 Bank: 2 Row:258 Column: 78] +24592: read 0x409500 [Channel: 0 Bank: 2 Row:258 Column: 80] +24597: read 0x409520 [Channel: 0 Bank: 2 Row:258 Column: 82] +24620: read 0x10013400 [Channel: 2 Bank: 6 Row:4 Column: 64] +24655: read 0x409540 [Channel: 0 Bank: 2 Row:258 Column: 84] +24667: read 0x10013800 [Channel: 2 Bank: 7 Row:4 Column: 0] +24679: read 0x10013c00 [Channel: 2 Bank: 7 Row:4 Column: 64] +24704: read 0x409560 [Channel: 0 Bank: 2 Row:258 Column: 86] +24729: read 0x409580 [Channel: 0 Bank: 2 Row:258 Column: 88] +24754: read 0x4095a0 [Channel: 0 Bank: 2 Row:258 Column: 90] +24779: read 0x4095c0 [Channel: 0 Bank: 2 Row:258 Column: 92] +24804: read 0x4095e0 [Channel: 0 Bank: 2 Row:258 Column: 94] +24829: read 0x409600 [Channel: 0 Bank: 2 Row:258 Column: 96] +24854: read 0x409620 [Channel: 0 Bank: 2 Row:258 Column: 98] +24889: read 0x409640 [Channel: 0 Bank: 2 Row:258 Column: 100] +24913: read 0x40af60 [Channel: 0 Bank: 5 Row:258 Column: 118] +24938: read 0x40af80 [Channel: 0 Bank: 5 Row:258 Column: 120] +24962: read 0x40afa0 [Channel: 0 Bank: 5 Row:258 Column: 122] +24987: read 0x40afc0 [Channel: 0 Bank: 5 Row:258 Column: 124] +25015: read 0x40afe0 [Channel: 0 Bank: 5 Row:258 Column: 126] +25049: read 0x40b000 [Channel: 0 Bank: 6 Row:258 Column: 0] +25074: read 0x40b0e0 [Channel: 0 Bank: 6 Row:258 Column: 14] +25098: read 0x40b100 [Channel: 0 Bank: 6 Row:258 Column: 16] +25123: read 0x40b120 [Channel: 0 Bank: 6 Row:258 Column: 18] +25153: read 0x40b140 [Channel: 0 Bank: 6 Row:258 Column: 20] +25177: read 0x40a0a0 [Channel: 0 Bank: 4 Row:258 Column: 10] +25202: read 0x40a0c0 [Channel: 0 Bank: 4 Row:258 Column: 12] +25227: read 0x40a0e0 [Channel: 0 Bank: 4 Row:258 Column: 14] +25252: read 0x40a100 [Channel: 0 Bank: 4 Row:258 Column: 16] +25280: read 0x40a120 [Channel: 0 Bank: 4 Row:258 Column: 18] +25305: read 0x40a140 [Channel: 0 Bank: 4 Row:258 Column: 20] +25330: read 0x40a160 [Channel: 0 Bank: 4 Row:258 Column: 22] +25355: read 0x40a180 [Channel: 0 Bank: 4 Row:258 Column: 24] +25360: read 0x40a1a0 [Channel: 0 Bank: 4 Row:258 Column: 26] +25384: read 0x40a320 [Channel: 0 Bank: 4 Row:258 Column: 50] +25409: read 0x40a340 [Channel: 0 Bank: 4 Row:258 Column: 52] +25437: read 0x40a360 [Channel: 0 Bank: 4 Row:258 Column: 54] +25465: read 0x40a3e0 [Channel: 0 Bank: 4 Row:258 Column: 62] +25489: read 0x40a420 [Channel: 0 Bank: 4 Row:258 Column: 66] +25517: read 0x40a440 [Channel: 0 Bank: 4 Row:258 Column: 68] +25542: read 0x40a460 [Channel: 0 Bank: 4 Row:258 Column: 70] +25570: read 0x40a480 [Channel: 0 Bank: 4 Row:258 Column: 72] +25595: read 0x40a780 [Channel: 0 Bank: 4 Row:258 Column: 120] +25620: read 0x40a7a0 [Channel: 0 Bank: 4 Row:258 Column: 122] +25645: read 0x40a7c0 [Channel: 0 Bank: 4 Row:258 Column: 124] +25670: read 0x40a7e0 [Channel: 0 Bank: 4 Row:258 Column: 126] +25695: read 0x40a800 [Channel: 0 Bank: 5 Row:258 Column: 0] +25729: read 0x40a820 [Channel: 0 Bank: 5 Row:258 Column: 2] +25754: read 0x40b160 [Channel: 0 Bank: 6 Row:258 Column: 22] +25782: read 0x40b180 [Channel: 0 Bank: 6 Row:258 Column: 24] +25812: read 0x40b1a0 [Channel: 0 Bank: 6 Row:258 Column: 26] +25837: read 0x40b1c0 [Channel: 0 Bank: 6 Row:258 Column: 28] +25866: read 0x40b1e0 [Channel: 0 Bank: 6 Row:258 Column: 30] +25894: read 0x406060 [Channel: 0 Bank: 4 Row:257 Column: 6] +25896: read 0x4060c0 [Channel: 0 Bank: 4 Row:257 Column: 12] +25918: read 0x7fff7ee0 [Channel: 3 Bank: 7 Row:8189 Column: 110] +25946: read 0x4060e0 [Channel: 0 Bank: 4 Row:257 Column: 14] +25971: read 0x40c820 [Channel: 0 Bank: 1 Row:259 Column: 2] +25996: read 0x40c840 [Channel: 0 Bank: 1 Row:259 Column: 4] +26024: read 0x40c860 [Channel: 0 Bank: 1 Row:259 Column: 6] +26051: read 0x40c880 [Channel: 0 Bank: 1 Row:259 Column: 8] +26052: read 0x100070e0 [Channel: 2 Bank: 6 Row:1 Column: 14] +26077: read 0x40ca00 [Channel: 0 Bank: 1 Row:259 Column: 32] +26102: read 0x40ca20 [Channel: 0 Bank: 1 Row:259 Column: 34] +26131: read 0x40ca40 [Channel: 0 Bank: 1 Row:259 Column: 36] +26158: read 0x4083a0 [Channel: 0 Bank: 0 Row:258 Column: 58] +26159: read 0x10005620 [Channel: 2 Bank: 2 Row:1 Column: 98] +26187: read 0x406100 [Channel: 0 Bank: 4 Row:257 Column: 16] +26212: read 0x406240 [Channel: 0 Bank: 4 Row:257 Column: 36] +26285: read 0x406260 [Channel: 0 Bank: 4 Row:257 Column: 38] +26343: read 0x10005640 [Channel: 2 Bank: 2 Row:1 Column: 100] +26368: read 0x406280 [Channel: 0 Bank: 4 Row:257 Column: 40] +26374: read 0x4062a0 [Channel: 0 Bank: 4 Row:257 Column: 42] +26402: read 0x4062c0 [Channel: 0 Bank: 4 Row:257 Column: 44] +26426: read 0x406320 [Channel: 0 Bank: 4 Row:257 Column: 50] +26451: read 0x406340 [Channel: 0 Bank: 4 Row:257 Column: 52] +26476: read 0x406360 [Channel: 0 Bank: 4 Row:257 Column: 54] +26482: read 0x406380 [Channel: 0 Bank: 4 Row:257 Column: 56] +26506: read 0x4063a0 [Channel: 0 Bank: 4 Row:257 Column: 58] +26575: read 0x4063c0 [Channel: 0 Bank: 4 Row:257 Column: 60] +26603: read 0x40b020 [Channel: 0 Bank: 6 Row:258 Column: 2] +26628: read 0x40b040 [Channel: 0 Bank: 6 Row:258 Column: 4] +26658: read 0x40b060 [Channel: 0 Bank: 6 Row:258 Column: 6] +26682: read 0x40b080 [Channel: 0 Bank: 6 Row:258 Column: 8] +26710: read 0x40b0a0 [Channel: 0 Bank: 6 Row:258 Column: 10] +26710: read 0x10013000 [Channel: 2 Bank: 6 Row:4 Column: 0] +26780: read 0x40b0c0 [Channel: 0 Bank: 6 Row:258 Column: 12] +26818: read 0x40a400 [Channel: 0 Bank: 4 Row:258 Column: 64] +26846: read 0x40a4a0 [Channel: 0 Bank: 4 Row:258 Column: 74] +26870: read 0x409d80 [Channel: 0 Bank: 3 Row:258 Column: 88] +26895: read 0x409da0 [Channel: 0 Bank: 3 Row:258 Column: 90] +26920: read 0x409dc0 [Channel: 0 Bank: 3 Row:258 Column: 92] +26925: read 0x409de0 [Channel: 0 Bank: 3 Row:258 Column: 94] +26949: read 0x409e60 [Channel: 0 Bank: 3 Row:258 Column: 102] +26979: read 0x409e80 [Channel: 0 Bank: 3 Row:258 Column: 104] +27007: read 0x409f60 [Channel: 0 Bank: 3 Row:258 Column: 118] +27031: read 0x409f80 [Channel: 0 Bank: 3 Row:258 Column: 120] +27063: read 0x409fa0 [Channel: 0 Bank: 3 Row:258 Column: 122] +27091: read 0x409fc0 [Channel: 0 Bank: 3 Row:258 Column: 124] +27117: read 0x40a080 [Channel: 0 Bank: 4 Row:258 Column: 8] +27145: read 0x40a4c0 [Channel: 0 Bank: 4 Row:258 Column: 76] +27173: read 0x40a4e0 [Channel: 0 Bank: 4 Row:258 Column: 78] +27201: read 0x40a5a0 [Channel: 0 Bank: 4 Row:258 Column: 90] +27226: read 0x40a5c0 [Channel: 0 Bank: 4 Row:258 Column: 92] +27256: read 0x40a5e0 [Channel: 0 Bank: 4 Row:258 Column: 94] +27281: read 0x40c180 [Channel: 0 Bank: 0 Row:259 Column: 24] +27306: read 0x40c1a0 [Channel: 0 Bank: 0 Row:259 Column: 26] +27331: read 0x40c1c0 [Channel: 0 Bank: 0 Row:259 Column: 28] +27359: read 0x40c1e0 [Channel: 0 Bank: 0 Row:259 Column: 30] +27383: read 0x412780 [Channel: 0 Bank: 4 Row:260 Column: 120] +27412: read 0x4127a0 [Channel: 0 Bank: 4 Row:260 Column: 122] +27436: read 0x40c200 [Channel: 0 Bank: 0 Row:259 Column: 32] +27461: read 0x40c220 [Channel: 0 Bank: 0 Row:259 Column: 34] +27486: read 0x40c240 [Channel: 0 Bank: 0 Row:259 Column: 36] +27516: read 0x40c260 [Channel: 0 Bank: 0 Row:259 Column: 38] +27544: read 0x40a600 [Channel: 0 Bank: 4 Row:258 Column: 96] +27568: read 0x40a620 [Channel: 0 Bank: 4 Row:258 Column: 98] +27596: read 0x40a640 [Channel: 0 Bank: 4 Row:258 Column: 100] +27654: read 0x40a660 [Channel: 0 Bank: 4 Row:258 Column: 102] +27682: read 0x4063e0 [Channel: 0 Bank: 4 Row:257 Column: 62] +28083: read 0x406400 [Channel: 0 Bank: 4 Row:257 Column: 64] +28108: read 0x406420 [Channel: 0 Bank: 4 Row:257 Column: 66] +28113: read 0x406440 [Channel: 0 Bank: 4 Row:257 Column: 68] +28137: read 0x4064c0 [Channel: 0 Bank: 4 Row:257 Column: 76] +28162: read 0x4064e0 [Channel: 0 Bank: 4 Row:257 Column: 78] +28187: read 0x406500 [Channel: 0 Bank: 4 Row:257 Column: 80] +28215: read 0x406520 [Channel: 0 Bank: 4 Row:257 Column: 82] +28215: read 0x7fff7f00 [Channel: 3 Bank: 7 Row:8189 Column: 112] +28247: read 0x406600 [Channel: 0 Bank: 4 Row:257 Column: 96] +28272: read 0x406620 [Channel: 0 Bank: 4 Row:257 Column: 98] +28296: read 0x406640 [Channel: 0 Bank: 4 Row:257 Column: 100] +28324: read 0x406660 [Channel: 0 Bank: 4 Row:257 Column: 102] +28348: read 0x4066c0 [Channel: 0 Bank: 4 Row:257 Column: 108] +28351: read 0x4066e0 [Channel: 0 Bank: 4 Row:257 Column: 110] +28373: read 0x100070c0 [Channel: 2 Bank: 6 Row:1 Column: 12] +28377: read 0x406700 [Channel: 0 Bank: 4 Row:257 Column: 112] +28398: read 0x100064c0 [Channel: 2 Bank: 4 Row:1 Column: 76] +28406: read 0x406720 [Channel: 0 Bank: 4 Row:257 Column: 114] +28430: read 0x406760 [Channel: 0 Bank: 4 Row:257 Column: 118] +28458: read 0x406780 [Channel: 0 Bank: 4 Row:257 Column: 120] +28483: read 0x4068c0 [Channel: 0 Bank: 5 Row:257 Column: 12] +28511: read 0x4068e0 [Channel: 0 Bank: 5 Row:257 Column: 14] +28543: read 0x4069a0 [Channel: 0 Bank: 5 Row:257 Column: 26] +28575: read 0x4069c0 [Channel: 0 Bank: 5 Row:257 Column: 28] +28600: read 0x4069e0 [Channel: 0 Bank: 5 Row:257 Column: 30] +28602: read 0x406a00 [Channel: 0 Bank: 5 Row:257 Column: 32] +28625: read 0x10007240 [Channel: 2 Bank: 6 Row:1 Column: 36] +28653: read 0x406a20 [Channel: 0 Bank: 5 Row:257 Column: 34] +28678: read 0x406a40 [Channel: 0 Bank: 5 Row:257 Column: 36] +28706: read 0x406a60 [Channel: 0 Bank: 5 Row:257 Column: 38] +28739: read 0x406a80 [Channel: 0 Bank: 5 Row:257 Column: 40] +28767: read 0x406c60 [Channel: 0 Bank: 5 Row:257 Column: 70] +28795: read 0x406cc0 [Channel: 0 Bank: 5 Row:257 Column: 76] +28823: read 0x406d00 [Channel: 0 Bank: 5 Row:257 Column: 80] +28851: read 0x406d20 [Channel: 0 Bank: 5 Row:257 Column: 82] +28875: read 0x406d60 [Channel: 0 Bank: 5 Row:257 Column: 86] +28900: read 0x406d80 [Channel: 0 Bank: 5 Row:257 Column: 88] +28925: read 0x406da0 [Channel: 0 Bank: 5 Row:257 Column: 90] +28928: read 0x406dc0 [Channel: 0 Bank: 5 Row:257 Column: 92] +28950: read 0x7fff7f20 [Channel: 3 Bank: 7 Row:8189 Column: 114] +28975: read 0x406de0 [Channel: 0 Bank: 5 Row:257 Column: 94] +29000: read 0x406e00 [Channel: 0 Bank: 5 Row:257 Column: 96] +29028: read 0x406e20 [Channel: 0 Bank: 5 Row:257 Column: 98] +29052: read 0x406e40 [Channel: 0 Bank: 5 Row:257 Column: 100] +29077: read 0x406e60 [Channel: 0 Bank: 5 Row:257 Column: 102] +29111: read 0x406e80 [Channel: 0 Bank: 5 Row:257 Column: 104] +29139: read 0x4158a0 [Channel: 0 Bank: 3 Row:261 Column: 10] +29167: read 0x4158c0 [Channel: 0 Bank: 3 Row:261 Column: 12] +29195: read 0x4158e0 [Channel: 0 Bank: 3 Row:261 Column: 14] +29225: read 0x415900 [Channel: 0 Bank: 3 Row:261 Column: 16] +29249: read 0x415940 [Channel: 0 Bank: 3 Row:261 Column: 20] +29274: read 0x415960 [Channel: 0 Bank: 3 Row:261 Column: 22] +29276: read 0x415980 [Channel: 0 Bank: 3 Row:261 Column: 24] +29299: read 0x10006a40 [Channel: 2 Bank: 5 Row:1 Column: 36] +29324: read 0x4159a0 [Channel: 0 Bank: 3 Row:261 Column: 26] +29352: read 0x4159c0 [Channel: 0 Bank: 3 Row:261 Column: 28] +29377: read 0x415c40 [Channel: 0 Bank: 3 Row:261 Column: 68] +29402: read 0x415c60 [Channel: 0 Bank: 3 Row:261 Column: 70] +29427: read 0x415c80 [Channel: 0 Bank: 3 Row:261 Column: 72] +29455: read 0x415ca0 [Channel: 0 Bank: 3 Row:261 Column: 74] +29480: read 0x415ce0 [Channel: 0 Bank: 3 Row:261 Column: 78] +29505: read 0x415d00 [Channel: 0 Bank: 3 Row:261 Column: 80] +29530: read 0x415d20 [Channel: 0 Bank: 3 Row:261 Column: 82] +29560: read 0x415d40 [Channel: 0 Bank: 3 Row:261 Column: 84] +29584: read 0x415d60 [Channel: 0 Bank: 3 Row:261 Column: 86] +29612: read 0x415d80 [Channel: 0 Bank: 3 Row:261 Column: 88] +29642: read 0x416160 [Channel: 0 Bank: 4 Row:261 Column: 22] +29667: read 0x416180 [Channel: 0 Bank: 4 Row:261 Column: 24] +29692: read 0x406ea0 [Channel: 0 Bank: 5 Row:257 Column: 106] +29695: read 0x406ec0 [Channel: 0 Bank: 5 Row:257 Column: 108] +29717: read 0x10006380 [Channel: 2 Bank: 4 Row:1 Column: 56] +29721: read 0x406ee0 [Channel: 0 Bank: 5 Row:257 Column: 110] +29745: read 0x7fff7ec0 [Channel: 3 Bank: 7 Row:8189 Column: 108] +29770: read 0x4161a0 [Channel: 0 Bank: 4 Row:261 Column: 26] +29795: read 0x4161c0 [Channel: 0 Bank: 4 Row:261 Column: 28] +29823: read 0x4161e0 [Channel: 0 Bank: 4 Row:261 Column: 30] +29848: read 0x416240 [Channel: 0 Bank: 4 Row:261 Column: 36] +29852: read 0x416260 [Channel: 0 Bank: 4 Row:261 Column: 38] +29876: read 0x10006b40 [Channel: 2 Bank: 5 Row:1 Column: 52] +29901: read 0x416280 [Channel: 0 Bank: 4 Row:261 Column: 40] +29926: read 0x4162a0 [Channel: 0 Bank: 4 Row:261 Column: 42] +29954: read 0x4162c0 [Channel: 0 Bank: 4 Row:261 Column: 44] +29979: read 0x4162e0 [Channel: 0 Bank: 4 Row:261 Column: 46] +30004: read 0x416300 [Channel: 0 Bank: 4 Row:261 Column: 48] +30029: read 0x416320 [Channel: 0 Bank: 4 Row:261 Column: 50] +30034: read 0x416340 [Channel: 0 Bank: 4 Row:261 Column: 52] +30062: read 0x416360 [Channel: 0 Bank: 4 Row:261 Column: 54] +30086: read 0x416380 [Channel: 0 Bank: 4 Row:261 Column: 56] +30111: read 0x4163a0 [Channel: 0 Bank: 4 Row:261 Column: 58] +30139: read 0x4163c0 [Channel: 0 Bank: 4 Row:261 Column: 60] +30167: read 0x416400 [Channel: 0 Bank: 4 Row:261 Column: 64] +30191: read 0x416b40 [Channel: 0 Bank: 5 Row:261 Column: 52] +30216: read 0x416b60 [Channel: 0 Bank: 5 Row:261 Column: 54] +30397: read 0x406f00 [Channel: 0 Bank: 5 Row:257 Column: 112] +30422: read 0x406f20 [Channel: 0 Bank: 5 Row:257 Column: 114] +30450: read 0x406f40 [Channel: 0 Bank: 5 Row:257 Column: 116] +30475: read 0x406fa0 [Channel: 0 Bank: 5 Row:257 Column: 122] +30480: read 0x406fc0 [Channel: 0 Bank: 5 Row:257 Column: 124] +30504: read 0x406fe0 [Channel: 0 Bank: 5 Row:257 Column: 126] +30538: read 0x407000 [Channel: 0 Bank: 6 Row:257 Column: 0] +30562: read 0x407020 [Channel: 0 Bank: 6 Row:257 Column: 2] +30587: read 0x407040 [Channel: 0 Bank: 6 Row:257 Column: 4] +30615: read 0x407060 [Channel: 0 Bank: 6 Row:257 Column: 6] +30643: read 0x407080 [Channel: 0 Bank: 6 Row:257 Column: 8] +30671: read 0x4070a0 [Channel: 0 Bank: 6 Row:257 Column: 10] +30695: read 0x407140 [Channel: 0 Bank: 6 Row:257 Column: 20] +30723: read 0x407160 [Channel: 0 Bank: 6 Row:257 Column: 22] +30751: read 0x4071e0 [Channel: 0 Bank: 6 Row:257 Column: 30] +30775: read 0x407260 [Channel: 0 Bank: 6 Row:257 Column: 38] +30800: read 0x407280 [Channel: 0 Bank: 6 Row:257 Column: 40] +30805: read 0x4072a0 [Channel: 0 Bank: 6 Row:257 Column: 42] +30829: read 0x407300 [Channel: 0 Bank: 6 Row:257 Column: 48] +30859: read 0x407320 [Channel: 0 Bank: 6 Row:257 Column: 50] +30884: read 0x407480 [Channel: 0 Bank: 6 Row:257 Column: 72] +30909: read 0x4074a0 [Channel: 0 Bank: 6 Row:257 Column: 74] +30915: read 0x4074c0 [Channel: 0 Bank: 6 Row:257 Column: 76] +30939: read 0x407560 [Channel: 0 Bank: 6 Row:257 Column: 86] +30967: read 0x407580 [Channel: 0 Bank: 6 Row:257 Column: 88] +30992: read 0x4075a0 [Channel: 0 Bank: 6 Row:257 Column: 90] +30998: read 0x4075c0 [Channel: 0 Bank: 6 Row:257 Column: 92] +31022: read 0x4075e0 [Channel: 0 Bank: 6 Row:257 Column: 94] +31177: read 0x407600 [Channel: 0 Bank: 6 Row:257 Column: 96] +31205: read 0x407620 [Channel: 0 Bank: 6 Row:257 Column: 98] +31230: read 0x407640 [Channel: 0 Bank: 6 Row:257 Column: 100] +31474: read 0x407660 [Channel: 0 Bank: 6 Row:257 Column: 102] +31498: read 0x40a040 [Channel: 0 Bank: 4 Row:258 Column: 4] +31542: read 0x40a060 [Channel: 0 Bank: 4 Row:258 Column: 6] +31567: read 0x40a500 [Channel: 0 Bank: 4 Row:258 Column: 80] +31684: read 0x40a520 [Channel: 0 Bank: 4 Row:258 Column: 82] +31709: read 0x4083c0 [Channel: 0 Bank: 0 Row:258 Column: 60] +31717: read 0x4083e0 [Channel: 0 Bank: 0 Row:258 Column: 62] +31742: read 0x408420 [Channel: 0 Bank: 0 Row:258 Column: 66] +31767: read 0x408440 [Channel: 0 Bank: 0 Row:258 Column: 68] +31792: read 0x408460 [Channel: 0 Bank: 0 Row:258 Column: 70] +31817: read 0x408480 [Channel: 0 Bank: 0 Row:258 Column: 72] +31842: read 0x4059a0 [Channel: 0 Bank: 3 Row:257 Column: 26] +31867: read 0x401820 [Channel: 0 Bank: 3 Row:256 Column: 2] +31869: read 0x401840 [Channel: 0 Bank: 3 Row:256 Column: 4] +31892: read 0x10006fc0 [Channel: 2 Bank: 5 Row:1 Column: 124] +31896: read 0x401860 [Channel: 0 Bank: 3 Row:256 Column: 6] +31917: read 0x10005280 [Channel: 2 Bank: 2 Row:1 Column: 40] +31942: read 0x401880 [Channel: 0 Bank: 3 Row:256 Column: 8] +31946: read 0x4018a0 [Channel: 0 Bank: 3 Row:256 Column: 10] +31990: read 0x10005960 [Channel: 2 Bank: 3 Row:1 Column: 22] +32015: read 0x401780 [Channel: 0 Bank: 2 Row:256 Column: 120] +32022: read 0x4017a0 [Channel: 0 Bank: 2 Row:256 Column: 122] +32046: read 0x4017c0 [Channel: 0 Bank: 2 Row:256 Column: 124] +35662: read 0x4017e0 [Channel: 0 Bank: 2 Row:256 Column: 126] +35690: read 0x4018e0 [Channel: 0 Bank: 3 Row:256 Column: 14] +35714: read 0x4012e0 [Channel: 0 Bank: 2 Row:256 Column: 46] +35739: read 0x401300 [Channel: 0 Bank: 2 Row:256 Column: 48] +35764: read 0x401320 [Channel: 0 Bank: 2 Row:256 Column: 50] +35789: read 0x401340 [Channel: 0 Bank: 2 Row:256 Column: 52] +35814: read 0x401360 [Channel: 0 Bank: 2 Row:256 Column: 54] +35839: read 0x401380 [Channel: 0 Bank: 2 Row:256 Column: 56] +35925: read 0x4013a0 [Channel: 0 Bank: 2 Row:256 Column: 58] +35950: read 0x7fff7ea0 [Channel: 3 Bank: 7 Row:8189 Column: 106] +36410: read 0x10005580 [Channel: 2 Bank: 2 Row:1 Column: 88] +36448: read 0x10006480 [Channel: 2 Bank: 4 Row:1 Column: 72] +36476: read 0x10005ae0 [Channel: 2 Bank: 3 Row:1 Column: 46] +36501: read 0x406aa0 [Channel: 0 Bank: 5 Row:257 Column: 42] +36507: read 0x406ac0 [Channel: 0 Bank: 5 Row:257 Column: 44] +36531: read 0x406ae0 [Channel: 0 Bank: 5 Row:257 Column: 46] +36556: read 0x406b00 [Channel: 0 Bank: 5 Row:257 Column: 48] +36561: read 0x406b20 [Channel: 0 Bank: 5 Row:257 Column: 50] +36585: read 0x406b40 [Channel: 0 Bank: 5 Row:257 Column: 52] +36610: read 0x406b60 [Channel: 0 Bank: 5 Row:257 Column: 54] +36638: read 0x406b80 [Channel: 0 Bank: 5 Row:257 Column: 56] +36662: read 0x406bc0 [Channel: 0 Bank: 5 Row:257 Column: 60] +36687: read 0x406be0 [Channel: 0 Bank: 5 Row:257 Column: 62] +37719: read 0x406c00 [Channel: 0 Bank: 5 Row:257 Column: 64] +37723: read 0x7fff88e0 [Channel: 3 Bank: 1 Row:8190 Column: 14] +37726: read 0x4013c0 [Channel: 0 Bank: 2 Row:256 Column: 60] +37751: read 0x10006fe0 [Channel: 2 Bank: 5 Row:1 Column: 126] +37779: read 0x4013e0 [Channel: 0 Bank: 2 Row:256 Column: 62] +37804: read 0x401400 [Channel: 0 Bank: 2 Row:256 Column: 64] +37829: read 0x401420 [Channel: 0 Bank: 2 Row:256 Column: 66] +38872: read 0x401440 [Channel: 0 Bank: 2 Row:256 Column: 68] +39882: read 0x401460 [Channel: 0 Bank: 2 Row:256 Column: 70] +39907: read 0x401480 [Channel: 0 Bank: 2 Row:256 Column: 72] +39931: read 0x4014a0 [Channel: 0 Bank: 2 Row:256 Column: 74] +39958: read 0x4014c0 [Channel: 0 Bank: 2 Row:256 Column: 76] +39959: read 0x10007000 [Channel: 2 Bank: 6 Row:1 Column: 0] +39983: read 0x4014e0 [Channel: 0 Bank: 2 Row:256 Column: 78] +40008: read 0x401500 [Channel: 0 Bank: 2 Row:256 Column: 80] +40036: read 0x401520 [Channel: 0 Bank: 2 Row:256 Column: 82] +40060: read 0x401580 [Channel: 0 Bank: 2 Row:256 Column: 88] +40085: read 0x4015a0 [Channel: 0 Bank: 2 Row:256 Column: 90] +40087: read 0x4015c0 [Channel: 0 Bank: 2 Row:256 Column: 92] +40110: read 0x10005340 [Channel: 2 Bank: 2 Row:1 Column: 52] +40135: read 0x4015e0 [Channel: 0 Bank: 2 Row:256 Column: 94] +40138: read 0x401600 [Channel: 0 Bank: 2 Row:256 Column: 96] +40156: read 0x1000d8a0 [Channel: 2 Bank: 3 Row:3 Column: 10] +40161: read 0x1000d8c0 [Channel: 2 Bank: 3 Row:3 Column: 12] +40166: read 0x1000d8e0 [Channel: 2 Bank: 3 Row:3 Column: 14] +40219: read 0x10005360 [Channel: 2 Bank: 2 Row:1 Column: 54] +40224: read 0x1000d900 [Channel: 2 Bank: 3 Row:3 Column: 16] +40234: read 0x1000d920 [Channel: 2 Bank: 3 Row:3 Column: 18] +40297: read 0x10005380 [Channel: 2 Bank: 2 Row:1 Column: 56] +40298: read 0x1000d940 [Channel: 2 Bank: 3 Row:3 Column: 20] +40327: read 0x100053a0 [Channel: 2 Bank: 2 Row:1 Column: 58] +40361: read 0x1000d960 [Channel: 2 Bank: 3 Row:3 Column: 22] +40419: read 0x100053c0 [Channel: 2 Bank: 2 Row:1 Column: 60] +40424: read 0x1000d980 [Channel: 2 Bank: 3 Row:3 Column: 24] +40492: read 0x100053e0 [Channel: 2 Bank: 2 Row:1 Column: 62] +40555: read 0x10005400 [Channel: 2 Bank: 2 Row:1 Column: 64] +40618: read 0x10005420 [Channel: 2 Bank: 2 Row:1 Column: 66] +40661: read 0x10005440 [Channel: 2 Bank: 2 Row:1 Column: 68] +42425: read 0x401620 [Channel: 0 Bank: 2 Row:256 Column: 98] +46267: read 0x100052a0 [Channel: 2 Bank: 2 Row:1 Column: 42] +46282: read 0x1000d9a0 [Channel: 2 Bank: 3 Row:3 Column: 26] +46286: read 0x1000d9c0 [Channel: 2 Bank: 3 Row:3 Column: 28] +46317: read 0x1000d9e0 [Channel: 2 Bank: 3 Row:3 Column: 30] +46322: read 0x1000da00 [Channel: 2 Bank: 3 Row:3 Column: 32] +46372: read 0x1000da20 [Channel: 2 Bank: 3 Row:3 Column: 34] +46377: read 0x1000da40 [Channel: 2 Bank: 3 Row:3 Column: 36] +46451: read 0x1000da60 [Channel: 2 Bank: 3 Row:3 Column: 38] +46600: read 0x1000da80 [Channel: 2 Bank: 3 Row:3 Column: 40] +48330: read 0x7fff8900 [Channel: 3 Bank: 1 Row:8190 Column: 16] +48362: read 0x10005900 [Channel: 2 Bank: 3 Row:1 Column: 16] +48386: read 0x4003c0 [Channel: 0 Bank: 0 Row:256 Column: 60] +48411: read 0x4003e0 [Channel: 0 Bank: 0 Row:256 Column: 62] +48436: read 0x400400 [Channel: 0 Bank: 0 Row:256 Column: 64] +48461: read 0x400420 [Channel: 0 Bank: 0 Row:256 Column: 66] +48486: read 0x400440 [Channel: 0 Bank: 0 Row:256 Column: 68] +48511: read 0x400460 [Channel: 0 Bank: 0 Row:256 Column: 70] +48536: read 0x400480 [Channel: 0 Bank: 0 Row:256 Column: 72] +48561: read 0x4004a0 [Channel: 0 Bank: 0 Row:256 Column: 74] +48586: read 0x4004c0 [Channel: 0 Bank: 0 Row:256 Column: 76] +48589: read 0x4004e0 [Channel: 0 Bank: 0 Row:256 Column: 78] +48611: read 0x100071c0 [Channel: 2 Bank: 6 Row:1 Column: 28] +48636: read 0x400500 [Channel: 0 Bank: 0 Row:256 Column: 80] +48661: read 0x400520 [Channel: 0 Bank: 0 Row:256 Column: 82] +48783: read 0x400540 [Channel: 0 Bank: 0 Row:256 Column: 84] +49632: read 0x10005460 [Channel: 2 Bank: 2 Row:1 Column: 70] +50522: read 0x7fff7e80 [Channel: 3 Bank: 7 Row:8189 Column: 104] +50526: read 0x7fff88c0 [Channel: 3 Bank: 1 Row:8190 Column: 12] +50680: read 0x400560 [Channel: 0 Bank: 0 Row:256 Column: 86] +52178: read 0x10005480 [Channel: 2 Bank: 2 Row:1 Column: 72] +52342: read 0x400580 [Channel: 0 Bank: 0 Row:256 Column: 88] +53966: read 0x100054a0 [Channel: 2 Bank: 2 Row:1 Column: 74] +55754: read 0x4005a0 [Channel: 0 Bank: 0 Row:256 Column: 90] +55883: read 0x4005c0 [Channel: 0 Bank: 0 Row:256 Column: 92] +57379: read 0x100054c0 [Channel: 2 Bank: 2 Row:1 Column: 76] +57407: read 0x4005e0 [Channel: 0 Bank: 0 Row:256 Column: 94] +57435: read 0x400600 [Channel: 0 Bank: 0 Row:256 Column: 96] +57459: read 0x400620 [Channel: 0 Bank: 0 Row:256 Column: 98] +57487: read 0x400640 [Channel: 0 Bank: 0 Row:256 Column: 100] +57515: read 0x400660 [Channel: 0 Bank: 0 Row:256 Column: 102] +57539: read 0x400680 [Channel: 0 Bank: 0 Row:256 Column: 104] +57567: read 0x4006a0 [Channel: 0 Bank: 0 Row:256 Column: 106] +57591: read 0x4006c0 [Channel: 0 Bank: 0 Row:256 Column: 108] +57616: read 0x4006e0 [Channel: 0 Bank: 0 Row:256 Column: 110] +57641: read 0x400700 [Channel: 0 Bank: 0 Row:256 Column: 112] +57666: read 0x400720 [Channel: 0 Bank: 0 Row:256 Column: 114] +57691: read 0x400740 [Channel: 0 Bank: 0 Row:256 Column: 116] +57716: read 0x400760 [Channel: 0 Bank: 0 Row:256 Column: 118] +57741: read 0x400780 [Channel: 0 Bank: 0 Row:256 Column: 120] +57766: read 0x4007a0 [Channel: 0 Bank: 0 Row:256 Column: 122] +57920: read 0x4007c0 [Channel: 0 Bank: 0 Row:256 Column: 124] +59155: read 0x100054e0 [Channel: 2 Bank: 2 Row:1 Column: 78] +59302: read 0x4007e0 [Channel: 0 Bank: 0 Row:256 Column: 126] +60737: read 0x10005500 [Channel: 2 Bank: 2 Row:1 Column: 80] +62347: read 0x400800 [Channel: 0 Bank: 1 Row:256 Column: 0] +62482: read 0x400820 [Channel: 0 Bank: 1 Row:256 Column: 2] +63978: read 0x10005520 [Channel: 2 Bank: 2 Row:1 Column: 82] +64134: read 0x400840 [Channel: 0 Bank: 1 Row:256 Column: 4] +65513: read 0x10005540 [Channel: 2 Bank: 2 Row:1 Column: 84] +65538: read 0x400860 [Channel: 0 Bank: 1 Row:256 Column: 6] +65566: read 0x400880 [Channel: 0 Bank: 1 Row:256 Column: 8] +65590: read 0x4008a0 [Channel: 0 Bank: 1 Row:256 Column: 10] +65617: read 0x4008c0 [Channel: 0 Bank: 1 Row:256 Column: 12] +65618: read 0x100052c0 [Channel: 2 Bank: 2 Row:1 Column: 44] +65642: read 0x4008e0 [Channel: 0 Bank: 1 Row:256 Column: 14] +65670: read 0x400900 [Channel: 0 Bank: 1 Row:256 Column: 16] +65694: read 0x400920 [Channel: 0 Bank: 1 Row:256 Column: 18] +65721: read 0x400940 [Channel: 0 Bank: 1 Row:256 Column: 20] +65722: read 0x100052e0 [Channel: 2 Bank: 2 Row:1 Column: 46] +65746: read 0x400960 [Channel: 0 Bank: 1 Row:256 Column: 22] +65774: read 0x400980 [Channel: 0 Bank: 1 Row:256 Column: 24] +65798: read 0x4009a0 [Channel: 0 Bank: 1 Row:256 Column: 26] +82047: read 0x4009c0 [Channel: 0 Bank: 1 Row:256 Column: 28] +82075: read 0x4009e0 [Channel: 0 Bank: 1 Row:256 Column: 30] +82253: read 0x400a00 [Channel: 0 Bank: 1 Row:256 Column: 32] +82407: read 0x10005560 [Channel: 2 Bank: 2 Row:1 Column: 86] +82432: read 0x4062e0 [Channel: 0 Bank: 4 Row:257 Column: 46] +82460: read 0x406300 [Channel: 0 Bank: 4 Row:257 Column: 48] +82485: read 0x40cd40 [Channel: 0 Bank: 1 Row:259 Column: 84] +82510: read 0x40cd60 [Channel: 0 Bank: 1 Row:259 Column: 86] +82535: read 0x40cd80 [Channel: 0 Bank: 1 Row:259 Column: 88] +82560: read 0x40cda0 [Channel: 0 Bank: 1 Row:259 Column: 90] +82588: read 0x40cdc0 [Channel: 0 Bank: 1 Row:259 Column: 92] +82616: read 0x40cde0 [Channel: 0 Bank: 1 Row:259 Column: 94] +82644: read 0x40ce00 [Channel: 0 Bank: 1 Row:259 Column: 96] +82669: read 0x40ce20 [Channel: 0 Bank: 1 Row:259 Column: 98] +82693: read 0x40ce40 [Channel: 0 Bank: 1 Row:259 Column: 100] +82725: read 0x40ce60 [Channel: 0 Bank: 1 Row:259 Column: 102] +82753: read 0x40ce80 [Channel: 0 Bank: 1 Row:259 Column: 104] +82781: read 0x40cea0 [Channel: 0 Bank: 1 Row:259 Column: 106] +82878: read 0x40cec0 [Channel: 0 Bank: 1 Row:259 Column: 108] +82967: read 0x7fff74c0 [Channel: 3 Bank: 6 Row:8189 Column: 76] +82997: read 0x40cee0 [Channel: 0 Bank: 1 Row:259 Column: 110] +83022: read 0x40cf00 [Channel: 0 Bank: 1 Row:259 Column: 112] +83058: read 0x40cf20 [Channel: 0 Bank: 1 Row:259 Column: 114] +83086: read 0x40cf40 [Channel: 0 Bank: 1 Row:259 Column: 116] +83114: read 0x40cf60 [Channel: 0 Bank: 1 Row:259 Column: 118] +83144: read 0x40d040 [Channel: 0 Bank: 2 Row:259 Column: 4] +83169: read 0x40d060 [Channel: 0 Bank: 2 Row:259 Column: 6] +83194: read 0x40d080 [Channel: 0 Bank: 2 Row:259 Column: 8] +83222: read 0x40d0a0 [Channel: 0 Bank: 2 Row:259 Column: 10] +83247: read 0x412a60 [Channel: 0 Bank: 5 Row:260 Column: 38] +83272: read 0x412a80 [Channel: 0 Bank: 5 Row:260 Column: 40] +83311: read 0x412aa0 [Channel: 0 Bank: 5 Row:260 Column: 42] +83336: read 0x412ac0 [Channel: 0 Bank: 5 Row:260 Column: 44] +83361: read 0x412ae0 [Channel: 0 Bank: 5 Row:260 Column: 46] +83386: read 0x412b00 [Channel: 0 Bank: 5 Row:260 Column: 48] +83411: read 0x412b20 [Channel: 0 Bank: 5 Row:260 Column: 50] +83436: read 0x412b40 [Channel: 0 Bank: 5 Row:260 Column: 52] +83443: read 0x412b60 [Channel: 0 Bank: 5 Row:260 Column: 54] +83467: read 0x412bc0 [Channel: 0 Bank: 5 Row:260 Column: 60] +83503: read 0x412be0 [Channel: 0 Bank: 5 Row:260 Column: 62] +83534: read 0x412b80 [Channel: 0 Bank: 5 Row:260 Column: 56] +83559: read 0x412c20 [Channel: 0 Bank: 5 Row:260 Column: 66] +83565: read 0x412c40 [Channel: 0 Bank: 5 Row:260 Column: 68] +83609: read 0x412c00 [Channel: 0 Bank: 5 Row:260 Column: 64] +83637: read 0x40d0c0 [Channel: 0 Bank: 2 Row:259 Column: 12] +83662: read 0x40d0e0 [Channel: 0 Bank: 2 Row:259 Column: 14] +83670: read 0x40d100 [Channel: 0 Bank: 2 Row:259 Column: 16] +83698: read 0x40cfa0 [Channel: 0 Bank: 1 Row:259 Column: 122] +83755: read 0x40cfc0 [Channel: 0 Bank: 1 Row:259 Column: 124] +83783: read 0x40cfe0 [Channel: 0 Bank: 1 Row:259 Column: 126] +83811: read 0x40d000 [Channel: 0 Bank: 2 Row:259 Column: 0] +83839: read 0x40d020 [Channel: 0 Bank: 2 Row:259 Column: 2] +83867: read 0x40d3a0 [Channel: 0 Bank: 2 Row:259 Column: 58] +83892: read 0x40d3c0 [Channel: 0 Bank: 2 Row:259 Column: 60] +83917: read 0x40d3e0 [Channel: 0 Bank: 2 Row:259 Column: 62] +83979: read 0x40d400 [Channel: 0 Bank: 2 Row:259 Column: 64] +84004: read 0x400a20 [Channel: 0 Bank: 1 Row:256 Column: 34] +84029: read 0x400a40 [Channel: 0 Bank: 1 Row:256 Column: 36] +84059: read 0x400a60 [Channel: 0 Bank: 1 Row:256 Column: 38] +85820: read 0x4018c0 [Channel: 0 Bank: 3 Row:256 Column: 12] +85844: read 0x400ec0 [Channel: 0 Bank: 1 Row:256 Column: 108] +85869: read 0x400ee0 [Channel: 0 Bank: 1 Row:256 Column: 110] +85894: read 0x400f00 [Channel: 0 Bank: 1 Row:256 Column: 112] +85919: read 0x400f20 [Channel: 0 Bank: 1 Row:256 Column: 114] +85944: read 0x400f40 [Channel: 0 Bank: 1 Row:256 Column: 116] +87540: read 0x400f60 [Channel: 0 Bank: 1 Row:256 Column: 118] +87565: read 0x400f80 [Channel: 0 Bank: 1 Row:256 Column: 120] +87592: read 0x400fa0 [Channel: 0 Bank: 1 Row:256 Column: 122] +87593: read 0x10005300 [Channel: 2 Bank: 2 Row:1 Column: 48] +87617: read 0x400fc0 [Channel: 0 Bank: 1 Row:256 Column: 124] +87642: read 0x400fe0 [Channel: 0 Bank: 1 Row:256 Column: 126] +87667: read 0x401000 [Channel: 0 Bank: 2 Row:256 Column: 0] +87778: read 0x401020 [Channel: 0 Bank: 2 Row:256 Column: 2] +88868: read 0x10005600 [Channel: 2 Bank: 2 Row:1 Column: 96] +88893: read 0x401040 [Channel: 0 Bank: 2 Row:256 Column: 4] +88897: read 0x401060 [Channel: 0 Bank: 2 Row:256 Column: 6] +88918: read 0x10005320 [Channel: 2 Bank: 2 Row:1 Column: 50] +88946: read 0x401080 [Channel: 0 Bank: 2 Row:256 Column: 8] +88970: read 0x4010e0 [Channel: 0 Bank: 2 Row:256 Column: 14] +88995: read 0x401100 [Channel: 0 Bank: 2 Row:256 Column: 16] +89020: read 0x401120 [Channel: 0 Bank: 2 Row:256 Column: 18] +89045: read 0x401140 [Channel: 0 Bank: 2 Row:256 Column: 20] +89070: read 0x401160 [Channel: 0 Bank: 2 Row:256 Column: 22] +89095: read 0x401180 [Channel: 0 Bank: 2 Row:256 Column: 24] +89123: read 0x4011a0 [Channel: 0 Bank: 2 Row:256 Column: 26] +89152: read 0x10008de0 [Channel: 2 Bank: 1 Row:2 Column: 94] +89184: read 0x10008e00 [Channel: 2 Bank: 1 Row:2 Column: 96] +89185: read 0x10008e20 [Channel: 2 Bank: 1 Row:2 Column: 98] +90716: read 0x4011c0 [Channel: 0 Bank: 2 Row:256 Column: 28] +90741: read 0x4011e0 [Channel: 0 Bank: 2 Row:256 Column: 30] +90766: read 0x401200 [Channel: 0 Bank: 2 Row:256 Column: 32] +90791: read 0x401220 [Channel: 0 Bank: 2 Row:256 Column: 34] +90816: read 0x401240 [Channel: 0 Bank: 2 Row:256 Column: 36] +90841: read 0x401260 [Channel: 0 Bank: 2 Row:256 Column: 38] +90845: read 0x401280 [Channel: 0 Bank: 2 Row:256 Column: 40] +90866: read 0x1000ce60 [Channel: 2 Bank: 1 Row:3 Column: 102] +90889: read 0x4012a0 [Channel: 0 Bank: 2 Row:256 Column: 42] +90918: read 0x1000ce80 [Channel: 2 Bank: 1 Row:3 Column: 104] +96054: read 0x4012c0 [Channel: 0 Bank: 2 Row:256 Column: 44] +96079: read 0x4010a0 [Channel: 0 Bank: 2 Row:256 Column: 10] +96117: read 0x4010c0 [Channel: 0 Bank: 2 Row:256 Column: 12] +96127: read 0x10008ca0 [Channel: 2 Bank: 1 Row:2 Column: 74] +96159: read 0x10008cc0 [Channel: 2 Bank: 1 Row:2 Column: 76] +97889: read 0x10008ce0 [Channel: 2 Bank: 1 Row:2 Column: 78] +97915: read 0x10008380 [Channel: 2 Bank: 0 Row:2 Column: 56] +97941: read 0x100083a0 [Channel: 2 Bank: 0 Row:2 Column: 58] +97967: read 0x100083c0 [Channel: 2 Bank: 0 Row:2 Column: 60] +97996: read 0x100083e0 [Channel: 2 Bank: 0 Row:2 Column: 62] +98022: read 0x10008400 [Channel: 2 Bank: 0 Row:2 Column: 64] +98048: read 0x10008420 [Channel: 2 Bank: 0 Row:2 Column: 66] +98074: read 0x10008440 [Channel: 2 Bank: 0 Row:2 Column: 68] +98103: read 0x10008460 [Channel: 2 Bank: 0 Row:2 Column: 70] +98129: read 0x10008480 [Channel: 2 Bank: 0 Row:2 Column: 72] +98155: read 0x100084a0 [Channel: 2 Bank: 0 Row:2 Column: 74] +98181: read 0x100084c0 [Channel: 2 Bank: 0 Row:2 Column: 76] +98210: read 0x100084e0 [Channel: 2 Bank: 0 Row:2 Column: 78] +98236: read 0x10008500 [Channel: 2 Bank: 0 Row:2 Column: 80] +98262: read 0x10008520 [Channel: 2 Bank: 0 Row:2 Column: 82] +98288: read 0x10008540 [Channel: 2 Bank: 0 Row:2 Column: 84] +98317: read 0x10008560 [Channel: 2 Bank: 0 Row:2 Column: 86] +98343: read 0x10008580 [Channel: 2 Bank: 0 Row:2 Column: 88] +98369: read 0x100085a0 [Channel: 2 Bank: 0 Row:2 Column: 90] +98395: read 0x100085c0 [Channel: 2 Bank: 0 Row:2 Column: 92] +98424: read 0x100085e0 [Channel: 2 Bank: 0 Row:2 Column: 94] +103179: read 0x10008600 [Channel: 2 Bank: 0 Row:2 Column: 96] +103189: read 0x10008e60 [Channel: 2 Bank: 1 Row:2 Column: 102] +103217: read 0x10008e80 [Channel: 2 Bank: 1 Row:2 Column: 104] +104776: read 0x10008ea0 [Channel: 2 Bank: 1 Row:2 Column: 106] +104789: read 0x1000d260 [Channel: 2 Bank: 2 Row:3 Column: 38] +104814: read 0x1000d280 [Channel: 2 Bank: 2 Row:3 Column: 40] +109927: read 0x1000d2a0 [Channel: 2 Bank: 2 Row:3 Column: 42] +109952: read 0x10008d40 [Channel: 2 Bank: 1 Row:2 Column: 84] +109980: read 0x10008d60 [Channel: 2 Bank: 1 Row:2 Column: 86] +111686: read 0x10008d80 [Channel: 2 Bank: 1 Row:2 Column: 88] +111712: read 0x10008780 [Channel: 2 Bank: 0 Row:2 Column: 120] +111738: read 0x100087a0 [Channel: 2 Bank: 0 Row:2 Column: 122] +111764: read 0x100087c0 [Channel: 2 Bank: 0 Row:2 Column: 124] +111790: read 0x100087e0 [Channel: 2 Bank: 0 Row:2 Column: 126] +111819: read 0x10008800 [Channel: 2 Bank: 1 Row:2 Column: 0] +111845: read 0x10008820 [Channel: 2 Bank: 1 Row:2 Column: 2] +111871: read 0x10008840 [Channel: 2 Bank: 1 Row:2 Column: 4] +111897: read 0x10008860 [Channel: 2 Bank: 1 Row:2 Column: 6] +111926: read 0x10008880 [Channel: 2 Bank: 1 Row:2 Column: 8] +111952: read 0x100088a0 [Channel: 2 Bank: 1 Row:2 Column: 10] +111978: read 0x100088c0 [Channel: 2 Bank: 1 Row:2 Column: 12] +112004: read 0x100088e0 [Channel: 2 Bank: 1 Row:2 Column: 14] +112033: read 0x10008900 [Channel: 2 Bank: 1 Row:2 Column: 16] +112059: read 0x10008920 [Channel: 2 Bank: 1 Row:2 Column: 18] +112085: read 0x10008940 [Channel: 2 Bank: 1 Row:2 Column: 20] +112111: read 0x10008960 [Channel: 2 Bank: 1 Row:2 Column: 22] +112140: read 0x10008980 [Channel: 2 Bank: 1 Row:2 Column: 24] +112166: read 0x100089a0 [Channel: 2 Bank: 1 Row:2 Column: 26] +112192: read 0x100089c0 [Channel: 2 Bank: 1 Row:2 Column: 28] +112218: read 0x100089e0 [Channel: 2 Bank: 1 Row:2 Column: 30] +113998: read 0x10008a00 [Channel: 2 Bank: 1 Row:2 Column: 32] +114023: read 0x400a80 [Channel: 0 Bank: 1 Row:256 Column: 40] +114048: read 0x400aa0 [Channel: 0 Bank: 1 Row:256 Column: 42] +114073: read 0x400ac0 [Channel: 0 Bank: 1 Row:256 Column: 44] +114098: read 0x400ae0 [Channel: 0 Bank: 1 Row:256 Column: 46] +114123: read 0x400b00 [Channel: 0 Bank: 1 Row:256 Column: 48] +114148: read 0x400b20 [Channel: 0 Bank: 1 Row:256 Column: 50] +115535: read 0x400b40 [Channel: 0 Bank: 1 Row:256 Column: 52] +115721: read 0x7fff74e0 [Channel: 3 Bank: 6 Row:8189 Column: 78] +115861: read 0x400b60 [Channel: 0 Bank: 1 Row:256 Column: 54] +117171: read 0x100055a0 [Channel: 2 Bank: 2 Row:1 Column: 90] +117199: read 0x400b80 [Channel: 0 Bank: 1 Row:256 Column: 56] +117223: read 0x400ba0 [Channel: 0 Bank: 1 Row:256 Column: 58] +117248: read 0x400bc0 [Channel: 0 Bank: 1 Row:256 Column: 60] +117273: read 0x400be0 [Channel: 0 Bank: 1 Row:256 Column: 62] +117298: read 0x400c00 [Channel: 0 Bank: 1 Row:256 Column: 64] +117326: read 0x400c20 [Channel: 0 Bank: 1 Row:256 Column: 66] +117351: read 0x400c40 [Channel: 0 Bank: 1 Row:256 Column: 68] +117358: read 0x400c60 [Channel: 0 Bank: 1 Row:256 Column: 70] +117383: read 0x400cc0 [Channel: 0 Bank: 1 Row:256 Column: 76] +117566: read 0x400ce0 [Channel: 0 Bank: 1 Row:256 Column: 78] +119073: read 0x100055c0 [Channel: 2 Bank: 2 Row:1 Column: 92] +119233: read 0x400d00 [Channel: 0 Bank: 1 Row:256 Column: 80] +120475: read 0x100055e0 [Channel: 2 Bank: 2 Row:1 Column: 94] +121808: read 0x400d20 [Channel: 0 Bank: 1 Row:256 Column: 82] +121833: read 0x400d40 [Channel: 0 Bank: 1 Row:256 Column: 84] +121861: read 0x400d60 [Channel: 0 Bank: 1 Row:256 Column: 86] +121885: read 0x400d80 [Channel: 0 Bank: 1 Row:256 Column: 88] +121913: read 0x400da0 [Channel: 0 Bank: 1 Row:256 Column: 90] +121937: read 0x400dc0 [Channel: 0 Bank: 1 Row:256 Column: 92] +121965: read 0x400de0 [Channel: 0 Bank: 1 Row:256 Column: 94] +121989: read 0x400e00 [Channel: 0 Bank: 1 Row:256 Column: 96] +131577: read 0x400e20 [Channel: 0 Bank: 1 Row:256 Column: 98] +131602: read 0x400e40 [Channel: 0 Bank: 1 Row:256 Column: 100] +131627: read 0x400e60 [Channel: 0 Bank: 1 Row:256 Column: 102] +131652: read 0x400e80 [Channel: 0 Bank: 1 Row:256 Column: 104] +131699: read 0x400ea0 [Channel: 0 Bank: 1 Row:256 Column: 106] +131724: read 0x401900 [Channel: 0 Bank: 3 Row:256 Column: 16] +131754: read 0x401920 [Channel: 0 Bank: 3 Row:256 Column: 18] +131782: read 0x405360 [Channel: 0 Bank: 2 Row:257 Column: 54] +131806: read 0x405000 [Channel: 0 Bank: 2 Row:257 Column: 0] +131831: read 0x405020 [Channel: 0 Bank: 2 Row:257 Column: 2] +131856: read 0x405040 [Channel: 0 Bank: 2 Row:257 Column: 4] +131881: read 0x405060 [Channel: 0 Bank: 2 Row:257 Column: 6] +131909: read 0x405080 [Channel: 0 Bank: 2 Row:257 Column: 8] +131934: read 0x4050a0 [Channel: 0 Bank: 2 Row:257 Column: 10] +131959: read 0x4050c0 [Channel: 0 Bank: 2 Row:257 Column: 12] +131961: read 0x4050e0 [Channel: 0 Bank: 2 Row:257 Column: 14] +131984: read 0x100071e0 [Channel: 2 Bank: 6 Row:1 Column: 30] +132009: read 0x405100 [Channel: 0 Bank: 2 Row:257 Column: 16] +132037: read 0x405120 [Channel: 0 Bank: 2 Row:257 Column: 18] +132067: read 0x404500 [Channel: 0 Bank: 0 Row:257 Column: 80] +132092: read 0x404520 [Channel: 0 Bank: 0 Row:257 Column: 82] +132120: read 0x404540 [Channel: 0 Bank: 0 Row:257 Column: 84] +132156: read 0x4045a0 [Channel: 0 Bank: 0 Row:257 Column: 90] +132181: read 0x404560 [Channel: 0 Bank: 0 Row:257 Column: 86] +132185: read 0x404580 [Channel: 0 Bank: 0 Row:257 Column: 88] +132233: read 0x7fff7760 [Channel: 3 Bank: 6 Row:8189 Column: 118] +132283: read 0x7fff7780 [Channel: 3 Bank: 6 Row:8189 Column: 120] +132322: read 0x7fff77a0 [Channel: 3 Bank: 6 Row:8189 Column: 122] +132347: read 0x4045c0 [Channel: 0 Bank: 0 Row:257 Column: 92] +132372: read 0x4045e0 [Channel: 0 Bank: 0 Row:257 Column: 94] +132397: read 0x404600 [Channel: 0 Bank: 0 Row:257 Column: 96] +132401: read 0x404620 [Channel: 0 Bank: 0 Row:257 Column: 98] +132425: read 0x7fff7b80 [Channel: 3 Bank: 7 Row:8189 Column: 56] +132449: read 0x404640 [Channel: 0 Bank: 0 Row:257 Column: 100] +132544: read 0x404660 [Channel: 0 Bank: 0 Row:257 Column: 102] +132564: read 0x7fff7ba0 [Channel: 3 Bank: 7 Row:8189 Column: 58] +132589: read 0x404680 [Channel: 0 Bank: 0 Row:257 Column: 104] +132614: read 0x4046a0 [Channel: 0 Bank: 0 Row:257 Column: 106] +132646: read 0x4046c0 [Channel: 0 Bank: 0 Row:257 Column: 108] +132646: read 0x10008b80 [Channel: 2 Bank: 1 Row:2 Column: 56] +132670: read 0x404740 [Channel: 0 Bank: 0 Row:257 Column: 116] +132695: read 0x404760 [Channel: 0 Bank: 0 Row:257 Column: 118] +132720: read 0x404780 [Channel: 0 Bank: 0 Row:257 Column: 120] +132733: read 0x4047a0 [Channel: 0 Bank: 0 Row:257 Column: 122] +132758: read 0x4046e0 [Channel: 0 Bank: 0 Row:257 Column: 110] +132762: read 0x404700 [Channel: 0 Bank: 0 Row:257 Column: 112] +132783: read 0x10008f00 [Channel: 2 Bank: 1 Row:2 Column: 112] +132786: read 0x404720 [Channel: 0 Bank: 0 Row:257 Column: 114] +132833: read 0x10007660 [Channel: 2 Bank: 6 Row:1 Column: 102] +132864: read 0x10008ba0 [Channel: 2 Bank: 1 Row:2 Column: 58] +132865: read 0x10008f20 [Channel: 2 Bank: 1 Row:2 Column: 114] +132901: read 0x10007680 [Channel: 2 Bank: 6 Row:1 Column: 104] +132921: read 0x10008bc0 [Channel: 2 Bank: 1 Row:2 Column: 60] +132946: read 0x4047c0 [Channel: 0 Bank: 0 Row:257 Column: 124] +132971: read 0x405140 [Channel: 0 Bank: 2 Row:257 Column: 20] +133221: read 0x405160 [Channel: 0 Bank: 2 Row:257 Column: 22] +133231: read 0x10008c20 [Channel: 2 Bank: 1 Row:2 Column: 66] +133233: read 0x10008f80 [Channel: 2 Bank: 1 Row:2 Column: 120] +133255: read 0x100076e0 [Channel: 2 Bank: 6 Row:1 Column: 110] +133256: read 0x10008fa0 [Channel: 2 Bank: 1 Row:2 Column: 122] +133296: read 0x10007700 [Channel: 2 Bank: 6 Row:1 Column: 112] +133353: read 0x10008c40 [Channel: 2 Bank: 1 Row:2 Column: 68] +133360: read 0x10008c60 [Channel: 2 Bank: 1 Row:2 Column: 70] +133385: read 0x405180 [Channel: 0 Bank: 2 Row:257 Column: 24] +133410: read 0x4051a0 [Channel: 0 Bank: 2 Row:257 Column: 26] +133435: read 0x4051c0 [Channel: 0 Bank: 2 Row:257 Column: 28] +133615: read 0x4051e0 [Channel: 0 Bank: 2 Row:257 Column: 30] +133644: read 0x7fff77c0 [Channel: 3 Bank: 6 Row:8189 Column: 124] +133684: read 0x7fff77e0 [Channel: 3 Bank: 6 Row:8189 Column: 126] +133756: read 0x7fff7800 [Channel: 3 Bank: 7 Row:8189 Column: 0] +133774: read 0x7fff7820 [Channel: 3 Bank: 7 Row:8189 Column: 2] +133792: read 0x7fff7840 [Channel: 3 Bank: 7 Row:8189 Column: 4] +133810: read 0x7fff7860 [Channel: 3 Bank: 7 Row:8189 Column: 6] +133828: read 0x7fff7880 [Channel: 3 Bank: 7 Row:8189 Column: 8] +133846: read 0x7fff78a0 [Channel: 3 Bank: 7 Row:8189 Column: 10] +133864: read 0x7fff78c0 [Channel: 3 Bank: 7 Row:8189 Column: 12] +133882: read 0x7fff78e0 [Channel: 3 Bank: 7 Row:8189 Column: 14] +133900: read 0x7fff7900 [Channel: 3 Bank: 7 Row:8189 Column: 16] +133918: read 0x7fff7920 [Channel: 3 Bank: 7 Row:8189 Column: 18] +133936: read 0x7fff7940 [Channel: 3 Bank: 7 Row:8189 Column: 20] +133954: read 0x7fff7960 [Channel: 3 Bank: 7 Row:8189 Column: 22] +133972: read 0x7fff7980 [Channel: 3 Bank: 7 Row:8189 Column: 24] +133990: read 0x7fff79a0 [Channel: 3 Bank: 7 Row:8189 Column: 26] +134008: read 0x7fff79c0 [Channel: 3 Bank: 7 Row:8189 Column: 28] +134042: read 0x7fff79e0 [Channel: 3 Bank: 7 Row:8189 Column: 30] +134164: read 0x7fff7a00 [Channel: 3 Bank: 7 Row:8189 Column: 32] +134208: read 0x7fff7bc0 [Channel: 3 Bank: 7 Row:8189 Column: 60] +134252: read 0x7fff7be0 [Channel: 3 Bank: 7 Row:8189 Column: 62] +134325: read 0x7fff7c00 [Channel: 3 Bank: 7 Row:8189 Column: 64] +134349: read 0x7fff7c20 [Channel: 3 Bank: 7 Row:8189 Column: 66] +134373: read 0x7fff7c40 [Channel: 3 Bank: 7 Row:8189 Column: 68] +134397: read 0x7fff7c60 [Channel: 3 Bank: 7 Row:8189 Column: 70] +134421: read 0x7fff7c80 [Channel: 3 Bank: 7 Row:8189 Column: 72] +134445: read 0x7fff7ca0 [Channel: 3 Bank: 7 Row:8189 Column: 74] +134469: read 0x7fff7cc0 [Channel: 3 Bank: 7 Row:8189 Column: 76] +134493: read 0x7fff7ce0 [Channel: 3 Bank: 7 Row:8189 Column: 78] +134517: read 0x7fff7d00 [Channel: 3 Bank: 7 Row:8189 Column: 80] +134541: read 0x7fff7d20 [Channel: 3 Bank: 7 Row:8189 Column: 82] +134565: read 0x7fff7d40 [Channel: 3 Bank: 7 Row:8189 Column: 84] +134589: read 0x7fff7d60 [Channel: 3 Bank: 7 Row:8189 Column: 86] +134613: read 0x7fff7d80 [Channel: 3 Bank: 7 Row:8189 Column: 88] +134637: read 0x7fff7da0 [Channel: 3 Bank: 7 Row:8189 Column: 90] +134661: read 0x7fff7dc0 [Channel: 3 Bank: 7 Row:8189 Column: 92] +134685: read 0x7fff7de0 [Channel: 3 Bank: 7 Row:8189 Column: 94] +134707: read 0x7fff7e00 [Channel: 3 Bank: 7 Row:8189 Column: 96] +134717: read 0x1000dcc0 [Channel: 2 Bank: 3 Row:3 Column: 76] +134719: read 0x1000d680 [Channel: 2 Bank: 2 Row:3 Column: 104] +134777: read 0x1000dba0 [Channel: 2 Bank: 3 Row:3 Column: 58] +134778: read 0x1000d6a0 [Channel: 2 Bank: 2 Row:3 Column: 106] +134782: read 0x1000dbc0 [Channel: 2 Bank: 3 Row:3 Column: 60] +134858: read 0x1000dce0 [Channel: 2 Bank: 3 Row:3 Column: 78] +134859: read 0x1000d6c0 [Channel: 2 Bank: 2 Row:3 Column: 108] +134863: read 0x1000dbe0 [Channel: 2 Bank: 3 Row:3 Column: 62] +134867: read 0x1000dd00 [Channel: 2 Bank: 3 Row:3 Column: 80] +134892: read 0x405200 [Channel: 0 Bank: 2 Row:257 Column: 32] +136172: read 0x405220 [Channel: 0 Bank: 2 Row:257 Column: 34] +136177: read 0x1000dd40 [Channel: 2 Bank: 3 Row:3 Column: 84] +136179: read 0x1000d700 [Channel: 2 Bank: 2 Row:3 Column: 112] +136197: read 0x1000dc20 [Channel: 2 Bank: 3 Row:3 Column: 66] +136198: read 0x1000d720 [Channel: 2 Bank: 2 Row:3 Column: 114] +136202: read 0x1000dc40 [Channel: 2 Bank: 3 Row:3 Column: 68] +136269: read 0x1000dd60 [Channel: 2 Bank: 3 Row:3 Column: 86] +136270: read 0x1000d740 [Channel: 2 Bank: 2 Row:3 Column: 116] +136274: read 0x1000dc60 [Channel: 2 Bank: 3 Row:3 Column: 70] +136315: read 0x1000dd80 [Channel: 2 Bank: 3 Row:3 Column: 88] +136340: read 0x405240 [Channel: 0 Bank: 2 Row:257 Column: 36] +136365: read 0x405260 [Channel: 0 Bank: 2 Row:257 Column: 38] +136393: read 0x405380 [Channel: 0 Bank: 2 Row:257 Column: 56] +136423: read 0x403240 [Channel: 0 Bank: 6 Row:256 Column: 36] +136448: read 0x403260 [Channel: 0 Bank: 6 Row:256 Column: 38] +136473: read 0x403280 [Channel: 0 Bank: 6 Row:256 Column: 40] +136498: read 0x4032a0 [Channel: 0 Bank: 6 Row:256 Column: 42] +136523: read 0x4032c0 [Channel: 0 Bank: 6 Row:256 Column: 44] +136548: read 0x4032e0 [Channel: 0 Bank: 6 Row:256 Column: 46] +136573: read 0x403300 [Channel: 0 Bank: 6 Row:256 Column: 48] +136582: read 0x403320 [Channel: 0 Bank: 6 Row:256 Column: 50] +136598: read 0x7fff7660 [Channel: 3 Bank: 6 Row:8189 Column: 102] +136623: read 0x403340 [Channel: 0 Bank: 6 Row:256 Column: 52] +136626: read 0x403360 [Channel: 0 Bank: 6 Row:256 Column: 54] +136627: read 0x10009020 [Channel: 2 Bank: 2 Row:2 Column: 2] +136648: read 0x10008dc0 [Channel: 2 Bank: 1 Row:2 Column: 92] +136673: read 0x403380 [Channel: 0 Bank: 6 Row:256 Column: 56] +136678: read 0x4033a0 [Channel: 0 Bank: 6 Row:256 Column: 58] +136702: read 0x403840 [Channel: 0 Bank: 7 Row:256 Column: 4] +136788: read 0x403860 [Channel: 0 Bank: 7 Row:256 Column: 6] +136801: read 0x7fff74a0 [Channel: 3 Bank: 6 Row:8189 Column: 74] +136803: read 0x7fff6b60 [Channel: 3 Bank: 5 Row:8189 Column: 54] +136833: read 0x7fff6b80 [Channel: 3 Bank: 5 Row:8189 Column: 56] +137066: read 0x10005760 [Channel: 2 Bank: 2 Row:1 Column: 118] +137067: read 0x7fff6b20 [Channel: 3 Bank: 5 Row:8189 Column: 50] +137323: read 0x7fff6b40 [Channel: 3 Bank: 5 Row:8189 Column: 52] +137351: read 0x40d180 [Channel: 0 Bank: 2 Row:259 Column: 24] +137379: read 0x40d1a0 [Channel: 0 Bank: 2 Row:259 Column: 26] +137403: read 0x40d1c0 [Channel: 0 Bank: 2 Row:259 Column: 28] +137431: read 0x40d1e0 [Channel: 0 Bank: 2 Row:259 Column: 30] +137455: read 0x40d240 [Channel: 0 Bank: 2 Row:259 Column: 36] +137483: read 0x40d260 [Channel: 0 Bank: 2 Row:259 Column: 38] +137508: read 0x412440 [Channel: 0 Bank: 4 Row:260 Column: 68] +137533: read 0x412460 [Channel: 0 Bank: 4 Row:260 Column: 70] +137558: read 0x412480 [Channel: 0 Bank: 4 Row:260 Column: 72] +137583: read 0x4124a0 [Channel: 0 Bank: 4 Row:260 Column: 74] +137611: read 0x4124c0 [Channel: 0 Bank: 4 Row:260 Column: 76] +137636: read 0x4124e0 [Channel: 0 Bank: 4 Row:260 Column: 78] +137664: read 0x412500 [Channel: 0 Bank: 4 Row:260 Column: 80] +137698: read 0x412520 [Channel: 0 Bank: 4 Row:260 Column: 82] +137723: read 0x414e40 [Channel: 0 Bank: 1 Row:261 Column: 100] +137750: read 0x414e60 [Channel: 0 Bank: 1 Row:261 Column: 102] +137778: read 0x10006a00 [Channel: 2 Bank: 5 Row:1 Column: 32] +137803: read 0x414ec0 [Channel: 0 Bank: 1 Row:261 Column: 108] +137831: read 0x414ee0 [Channel: 0 Bank: 1 Row:261 Column: 110] +137856: read 0x414fe0 [Channel: 0 Bank: 1 Row:261 Column: 126] +137881: read 0x415000 [Channel: 0 Bank: 2 Row:261 Column: 0] +137914: read 0x415020 [Channel: 0 Bank: 2 Row:261 Column: 2] +137938: read 0x412540 [Channel: 0 Bank: 4 Row:260 Column: 84] +137963: read 0x412560 [Channel: 0 Bank: 4 Row:260 Column: 86] +137988: read 0x412580 [Channel: 0 Bank: 4 Row:260 Column: 88] +138013: read 0x4125a0 [Channel: 0 Bank: 4 Row:260 Column: 90] +138038: read 0x4125c0 [Channel: 0 Bank: 4 Row:260 Column: 92] +138063: read 0x4125e0 [Channel: 0 Bank: 4 Row:260 Column: 94] +138091: read 0x40d280 [Channel: 0 Bank: 2 Row:259 Column: 40] +138121: read 0x40d2a0 [Channel: 0 Bank: 2 Row:259 Column: 42] +138501: read 0x40d2e0 [Channel: 0 Bank: 2 Row:259 Column: 46] +139203: read 0x7fff7480 [Channel: 3 Bank: 6 Row:8189 Column: 72] +139375: read 0x7fff6b00 [Channel: 3 Bank: 5 Row:8189 Column: 48] +139400: read 0x403880 [Channel: 0 Bank: 7 Row:256 Column: 8] +139425: read 0x4038a0 [Channel: 0 Bank: 7 Row:256 Column: 10] +139453: read 0x4038c0 [Channel: 0 Bank: 7 Row:256 Column: 12] +139477: read 0x404be0 [Channel: 0 Bank: 1 Row:257 Column: 62] +139502: read 0x404c00 [Channel: 0 Bank: 1 Row:257 Column: 64] +139527: read 0x404c20 [Channel: 0 Bank: 1 Row:257 Column: 66] +139552: read 0x404c40 [Channel: 0 Bank: 1 Row:257 Column: 68] +139577: read 0x404c60 [Channel: 0 Bank: 1 Row:257 Column: 70] +139602: read 0x404c80 [Channel: 0 Bank: 1 Row:257 Column: 72] +139627: read 0x404ca0 [Channel: 0 Bank: 1 Row:257 Column: 74] +139652: read 0x404cc0 [Channel: 0 Bank: 1 Row:257 Column: 76] +139677: read 0x404ce0 [Channel: 0 Bank: 1 Row:257 Column: 78] +139705: read 0x404d00 [Channel: 0 Bank: 1 Row:257 Column: 80] +139730: read 0x4047e0 [Channel: 0 Bank: 0 Row:257 Column: 126] +139755: read 0x404800 [Channel: 0 Bank: 1 Row:257 Column: 0] +139780: read 0x404820 [Channel: 0 Bank: 1 Row:257 Column: 2] +139808: read 0x404840 [Channel: 0 Bank: 1 Row:257 Column: 4] +139833: read 0x404860 [Channel: 0 Bank: 1 Row:257 Column: 6] +139840: read 0x404880 [Channel: 0 Bank: 1 Row:257 Column: 8] +139864: read 0x4048c0 [Channel: 0 Bank: 1 Row:257 Column: 12] +139889: read 0x4048e0 [Channel: 0 Bank: 1 Row:257 Column: 14] +139914: read 0x404900 [Channel: 0 Bank: 1 Row:257 Column: 16] +139918: read 0x404920 [Channel: 0 Bank: 1 Row:257 Column: 18] +139939: read 0x100057e0 [Channel: 2 Bank: 2 Row:1 Column: 126] +139967: read 0x404940 [Channel: 0 Bank: 1 Row:257 Column: 20] +139992: read 0x404960 [Channel: 0 Bank: 1 Row:257 Column: 22] +140017: read 0x404980 [Channel: 0 Bank: 1 Row:257 Column: 24] +140042: read 0x4049a0 [Channel: 0 Bank: 1 Row:257 Column: 26] +140047: read 0x4049c0 [Channel: 0 Bank: 1 Row:257 Column: 28] +140071: read 0x404a20 [Channel: 0 Bank: 1 Row:257 Column: 34] +140096: read 0x404a40 [Channel: 0 Bank: 1 Row:257 Column: 36] +140124: read 0x404a60 [Channel: 0 Bank: 1 Row:257 Column: 38] +140149: read 0x404a80 [Channel: 0 Bank: 1 Row:257 Column: 40] +140201: read 0x404aa0 [Channel: 0 Bank: 1 Row:257 Column: 42] +140240: read 0x100057c0 [Channel: 2 Bank: 2 Row:1 Column: 124] +140265: read 0x404ac0 [Channel: 0 Bank: 1 Row:257 Column: 44] +140290: read 0x404ae0 [Channel: 0 Bank: 1 Row:257 Column: 46] +140315: read 0x404b00 [Channel: 0 Bank: 1 Row:257 Column: 48] +140340: read 0x404b20 [Channel: 0 Bank: 1 Row:257 Column: 50] +140368: read 0x404b40 [Channel: 0 Bank: 1 Row:257 Column: 52] +140392: read 0x404b80 [Channel: 0 Bank: 1 Row:257 Column: 56] +140417: read 0x404ba0 [Channel: 0 Bank: 1 Row:257 Column: 58] +140447: read 0x404bc0 [Channel: 0 Bank: 1 Row:257 Column: 60] +140475: read 0x404d20 [Channel: 0 Bank: 1 Row:257 Column: 82] +140499: read 0x4041e0 [Channel: 0 Bank: 0 Row:257 Column: 30] +140524: read 0x404200 [Channel: 0 Bank: 0 Row:257 Column: 32] +140549: read 0x404220 [Channel: 0 Bank: 0 Row:257 Column: 34] +140577: read 0x404240 [Channel: 0 Bank: 0 Row:257 Column: 36] +140602: read 0x404260 [Channel: 0 Bank: 0 Row:257 Column: 38] +140630: read 0x404280 [Channel: 0 Bank: 0 Row:257 Column: 40] +140654: read 0x404360 [Channel: 0 Bank: 0 Row:257 Column: 54] +140679: read 0x404380 [Channel: 0 Bank: 0 Row:257 Column: 56] +140686: read 0x4043a0 [Channel: 0 Bank: 0 Row:257 Column: 58] +140711: read 0x4043e0 [Channel: 0 Bank: 0 Row:257 Column: 62] +140736: read 0x404400 [Channel: 0 Bank: 0 Row:257 Column: 64] +140764: read 0x404420 [Channel: 0 Bank: 0 Row:257 Column: 66] +140789: read 0x404440 [Channel: 0 Bank: 0 Row:257 Column: 68] +140793: read 0x404460 [Channel: 0 Bank: 0 Row:257 Column: 70] +140814: read 0x10005860 [Channel: 2 Bank: 3 Row:1 Column: 6] +140842: read 0x404480 [Channel: 0 Bank: 0 Row:257 Column: 72] +140866: read 0x4044c0 [Channel: 0 Bank: 0 Row:257 Column: 76] +140892: read 0x4044e0 [Channel: 0 Bank: 0 Row:257 Column: 78] +140917: read 0x404d40 [Channel: 0 Bank: 1 Row:257 Column: 84] +140945: read 0x404d60 [Channel: 0 Bank: 1 Row:257 Column: 86] +140969: read 0x404d80 [Channel: 0 Bank: 1 Row:257 Column: 88] +140994: read 0x404da0 [Channel: 0 Bank: 1 Row:257 Column: 90] +141019: read 0x404dc0 [Channel: 0 Bank: 1 Row:257 Column: 92] +141078: read 0x404de0 [Channel: 0 Bank: 1 Row:257 Column: 94] +141090: read 0x7fff75c0 [Channel: 3 Bank: 6 Row:8189 Column: 92] +141102: read 0x7fff75e0 [Channel: 3 Bank: 6 Row:8189 Column: 94] +141114: read 0x7fff7600 [Channel: 3 Bank: 6 Row:8189 Column: 96] +141126: read 0x7fff7620 [Channel: 3 Bank: 6 Row:8189 Column: 98] +141149: read 0x7fff7640 [Channel: 3 Bank: 6 Row:8189 Column: 100] +141174: read 0x404e00 [Channel: 0 Bank: 1 Row:257 Column: 96] +141199: read 0x404e20 [Channel: 0 Bank: 1 Row:257 Column: 98] +141224: read 0x404e40 [Channel: 0 Bank: 1 Row:257 Column: 100] +141249: read 0x404e60 [Channel: 0 Bank: 1 Row:257 Column: 102] +141274: read 0x404e80 [Channel: 0 Bank: 1 Row:257 Column: 104] +141359: read 0x404ea0 [Channel: 0 Bank: 1 Row:257 Column: 106] +141445: read 0x404a00 [Channel: 0 Bank: 1 Row:257 Column: 32] +141470: read 0x404ec0 [Channel: 0 Bank: 1 Row:257 Column: 108] +141519: read 0x404ee0 [Channel: 0 Bank: 1 Row:257 Column: 110] +141544: read 0x404f00 [Channel: 0 Bank: 1 Row:257 Column: 112] +141569: read 0x404f20 [Channel: 0 Bank: 1 Row:257 Column: 114] +141594: read 0x404f40 [Channel: 0 Bank: 1 Row:257 Column: 116] +141619: read 0x404f60 [Channel: 0 Bank: 1 Row:257 Column: 118] +141622: read 0x404f80 [Channel: 0 Bank: 1 Row:257 Column: 120] +141647: read 0x10005780 [Channel: 2 Bank: 2 Row:1 Column: 120] +141780: read 0x404fa0 [Channel: 0 Bank: 1 Row:257 Column: 122] +142750: read 0x10005840 [Channel: 2 Bank: 3 Row:1 Column: 4] +142810: read 0x4044a0 [Channel: 0 Bank: 0 Row:257 Column: 74] +147718: read 0x4048a0 [Channel: 0 Bank: 1 Row:257 Column: 10] +147743: read 0x404fc0 [Channel: 0 Bank: 1 Row:257 Column: 124] +147775: read 0x404fe0 [Channel: 0 Bank: 1 Row:257 Column: 126] +147800: read 0x4038e0 [Channel: 0 Bank: 7 Row:256 Column: 14] +147825: read 0x403900 [Channel: 0 Bank: 7 Row:256 Column: 16] +147850: read 0x403920 [Channel: 0 Bank: 7 Row:256 Column: 18] +147853: read 0x403940 [Channel: 0 Bank: 7 Row:256 Column: 20] +147875: read 0x7fff7e60 [Channel: 3 Bank: 7 Row:8189 Column: 102] +147902: read 0x403960 [Channel: 0 Bank: 7 Row:256 Column: 22] +147957: read 0x10005660 [Channel: 2 Bank: 2 Row:1 Column: 102] +148012: read 0x10005680 [Channel: 2 Bank: 2 Row:1 Column: 104] +148067: read 0x100056a0 [Channel: 2 Bank: 2 Row:1 Column: 106] +148122: read 0x100056c0 [Channel: 2 Bank: 2 Row:1 Column: 108] +148177: read 0x100056e0 [Channel: 2 Bank: 2 Row:1 Column: 110] +148232: read 0x10005700 [Channel: 2 Bank: 2 Row:1 Column: 112] +148287: read 0x10005720 [Channel: 2 Bank: 2 Row:1 Column: 114] +148322: read 0x10005740 [Channel: 2 Bank: 2 Row:1 Column: 116] +148350: read 0x403980 [Channel: 0 Bank: 7 Row:256 Column: 24] +148375: read 0x4039a0 [Channel: 0 Bank: 7 Row:256 Column: 26] +148663: read 0x4039c0 [Channel: 0 Bank: 7 Row:256 Column: 28] +148691: read 0x4039e0 [Channel: 0 Bank: 7 Row:256 Column: 30] +148716: read 0x401940 [Channel: 0 Bank: 3 Row:256 Column: 20] +148741: read 0x401960 [Channel: 0 Bank: 3 Row:256 Column: 22] +148766: read 0x401980 [Channel: 0 Bank: 3 Row:256 Column: 24] +148791: read 0x4019a0 [Channel: 0 Bank: 3 Row:256 Column: 26] +148816: read 0x4019c0 [Channel: 0 Bank: 3 Row:256 Column: 28] +148841: read 0x4019e0 [Channel: 0 Bank: 3 Row:256 Column: 30] +148866: read 0x401a00 [Channel: 0 Bank: 3 Row:256 Column: 32] +148891: read 0x401a20 [Channel: 0 Bank: 3 Row:256 Column: 34] +148916: read 0x401a40 [Channel: 0 Bank: 3 Row:256 Column: 36] +148941: read 0x401a60 [Channel: 0 Bank: 3 Row:256 Column: 38] +148966: read 0x401a80 [Channel: 0 Bank: 3 Row:256 Column: 40] +148991: read 0x401aa0 [Channel: 0 Bank: 3 Row:256 Column: 42] +149016: read 0x401ac0 [Channel: 0 Bank: 3 Row:256 Column: 44] +149041: read 0x401ae0 [Channel: 0 Bank: 3 Row:256 Column: 46] +149066: read 0x401b00 [Channel: 0 Bank: 3 Row:256 Column: 48] +149091: read 0x401b20 [Channel: 0 Bank: 3 Row:256 Column: 50] +149116: read 0x401b40 [Channel: 0 Bank: 3 Row:256 Column: 52] +149141: read 0x401b60 [Channel: 0 Bank: 3 Row:256 Column: 54] +149166: read 0x401b80 [Channel: 0 Bank: 3 Row:256 Column: 56] +149191: read 0x401ba0 [Channel: 0 Bank: 3 Row:256 Column: 58] +149216: read 0x401bc0 [Channel: 0 Bank: 3 Row:256 Column: 60] +149241: read 0x401be0 [Channel: 0 Bank: 3 Row:256 Column: 62] +149266: read 0x401c00 [Channel: 0 Bank: 3 Row:256 Column: 64] +149291: read 0x401c20 [Channel: 0 Bank: 3 Row:256 Column: 66] +149316: read 0x401c40 [Channel: 0 Bank: 3 Row:256 Column: 68] +149341: read 0x401c60 [Channel: 0 Bank: 3 Row:256 Column: 70] +149366: read 0x401c80 [Channel: 0 Bank: 3 Row:256 Column: 72] +149391: read 0x401ca0 [Channel: 0 Bank: 3 Row:256 Column: 74] +149416: read 0x401cc0 [Channel: 0 Bank: 3 Row:256 Column: 76] +149441: read 0x401ce0 [Channel: 0 Bank: 3 Row:256 Column: 78] +149466: read 0x401d00 [Channel: 0 Bank: 3 Row:256 Column: 80] +149491: read 0x401d20 [Channel: 0 Bank: 3 Row:256 Column: 82] +149516: read 0x401d40 [Channel: 0 Bank: 3 Row:256 Column: 84] +149541: read 0x401d60 [Channel: 0 Bank: 3 Row:256 Column: 86] +149566: read 0x401d80 [Channel: 0 Bank: 3 Row:256 Column: 88] +149591: read 0x401da0 [Channel: 0 Bank: 3 Row:256 Column: 90] +149616: read 0x401dc0 [Channel: 0 Bank: 3 Row:256 Column: 92] +149641: read 0x401de0 [Channel: 0 Bank: 3 Row:256 Column: 94] +149666: read 0x401e00 [Channel: 0 Bank: 3 Row:256 Column: 96] +149691: read 0x401e20 [Channel: 0 Bank: 3 Row:256 Column: 98] +149716: read 0x401e40 [Channel: 0 Bank: 3 Row:256 Column: 100] +149741: read 0x401e60 [Channel: 0 Bank: 3 Row:256 Column: 102] +149766: read 0x401e80 [Channel: 0 Bank: 3 Row:256 Column: 104] +150242: read 0x401ea0 [Channel: 0 Bank: 3 Row:256 Column: 106] +150267: read 0x401ec0 [Channel: 0 Bank: 3 Row:256 Column: 108] +150292: read 0x401ee0 [Channel: 0 Bank: 3 Row:256 Column: 110] +150317: read 0x401f00 [Channel: 0 Bank: 3 Row:256 Column: 112] +150342: read 0x401f20 [Channel: 0 Bank: 3 Row:256 Column: 114] +150367: read 0x401f40 [Channel: 0 Bank: 3 Row:256 Column: 116] +150392: read 0x401f60 [Channel: 0 Bank: 3 Row:256 Column: 118] +150417: read 0x401f80 [Channel: 0 Bank: 3 Row:256 Column: 120] +150442: read 0x401fa0 [Channel: 0 Bank: 3 Row:256 Column: 122] +150467: read 0x401fc0 [Channel: 0 Bank: 3 Row:256 Column: 124] +150492: read 0x401fe0 [Channel: 0 Bank: 3 Row:256 Column: 126] +150523: read 0x402000 [Channel: 0 Bank: 4 Row:256 Column: 0] +150548: read 0x402020 [Channel: 0 Bank: 4 Row:256 Column: 2] +150573: read 0x402040 [Channel: 0 Bank: 4 Row:256 Column: 4] +150598: read 0x402060 [Channel: 0 Bank: 4 Row:256 Column: 6] +150623: read 0x402080 [Channel: 0 Bank: 4 Row:256 Column: 8] +150648: read 0x4020a0 [Channel: 0 Bank: 4 Row:256 Column: 10] +150673: read 0x4020c0 [Channel: 0 Bank: 4 Row:256 Column: 12] +150698: read 0x4020e0 [Channel: 0 Bank: 4 Row:256 Column: 14] +150723: read 0x402100 [Channel: 0 Bank: 4 Row:256 Column: 16] +150748: read 0x402120 [Channel: 0 Bank: 4 Row:256 Column: 18] +150773: read 0x402140 [Channel: 0 Bank: 4 Row:256 Column: 20] +150798: read 0x402160 [Channel: 0 Bank: 4 Row:256 Column: 22] +150823: read 0x402180 [Channel: 0 Bank: 4 Row:256 Column: 24] +150848: read 0x4021a0 [Channel: 0 Bank: 4 Row:256 Column: 26] +150873: read 0x4021c0 [Channel: 0 Bank: 4 Row:256 Column: 28] +150898: read 0x4021e0 [Channel: 0 Bank: 4 Row:256 Column: 30] +150923: read 0x402200 [Channel: 0 Bank: 4 Row:256 Column: 32] +150948: read 0x402220 [Channel: 0 Bank: 4 Row:256 Column: 34] +150973: read 0x402240 [Channel: 0 Bank: 4 Row:256 Column: 36] +150998: read 0x402260 [Channel: 0 Bank: 4 Row:256 Column: 38] +151023: read 0x402280 [Channel: 0 Bank: 4 Row:256 Column: 40] +151048: read 0x4022a0 [Channel: 0 Bank: 4 Row:256 Column: 42] +151073: read 0x4022c0 [Channel: 0 Bank: 4 Row:256 Column: 44] +151098: read 0x4022e0 [Channel: 0 Bank: 4 Row:256 Column: 46] +151123: read 0x402300 [Channel: 0 Bank: 4 Row:256 Column: 48] +151148: read 0x402320 [Channel: 0 Bank: 4 Row:256 Column: 50] +151173: read 0x402340 [Channel: 0 Bank: 4 Row:256 Column: 52] +151642: read 0x402360 [Channel: 0 Bank: 4 Row:256 Column: 54] +151667: read 0x402380 [Channel: 0 Bank: 4 Row:256 Column: 56] +151691: read 0x4023a0 [Channel: 0 Bank: 4 Row:256 Column: 58] +151716: read 0x4023c0 [Channel: 0 Bank: 4 Row:256 Column: 60] +151741: read 0x4023e0 [Channel: 0 Bank: 4 Row:256 Column: 62] +152128: read 0x402400 [Channel: 0 Bank: 4 Row:256 Column: 64] +152153: read 0x402420 [Channel: 0 Bank: 4 Row:256 Column: 66] +152178: read 0x403a00 [Channel: 0 Bank: 7 Row:256 Column: 32] +152203: read 0x403a20 [Channel: 0 Bank: 7 Row:256 Column: 34] +152228: read 0x403a40 [Channel: 0 Bank: 7 Row:256 Column: 36] +152375: read 0x403a60 [Channel: 0 Bank: 7 Row:256 Column: 38] +152403: read 0x403a80 [Channel: 0 Bank: 7 Row:256 Column: 40] +152627: read 0x403aa0 [Channel: 0 Bank: 7 Row:256 Column: 42] +152652: read 0x403ac0 [Channel: 0 Bank: 7 Row:256 Column: 44] +159424: read 0x403ae0 [Channel: 0 Bank: 7 Row:256 Column: 46] +159425: read 0x7fff7a20 [Channel: 3 Bank: 7 Row:8189 Column: 34] +159557: read 0x7fff7a40 [Channel: 3 Bank: 7 Row:8189 Column: 36] +167929: read 0x7fff7a60 [Channel: 3 Bank: 7 Row:8189 Column: 38] +167930: read 0x7fff7a80 [Channel: 3 Bank: 7 Row:8189 Column: 40] +167931: read 0x7fff7aa0 [Channel: 3 Bank: 7 Row:8189 Column: 42] +167932: read 0x7fff7ac0 [Channel: 3 Bank: 7 Row:8189 Column: 44] +167933: read 0x7fff7ae0 [Channel: 3 Bank: 7 Row:8189 Column: 46] +167934: read 0x7fff7b00 [Channel: 3 Bank: 7 Row:8189 Column: 48] +167935: read 0x7fff7b20 [Channel: 3 Bank: 7 Row:8189 Column: 50] +168066: read 0x7fff7b40 [Channel: 3 Bank: 7 Row:8189 Column: 52] +172473: read 0x7fff7b60 [Channel: 3 Bank: 7 Row:8189 Column: 54] +178752: read 0x4049e0 [Channel: 0 Bank: 1 Row:257 Column: 30] +178763: read 0x7fff7680 [Channel: 3 Bank: 6 Row:8189 Column: 104] +178775: read 0x7fff76a0 [Channel: 3 Bank: 6 Row:8189 Column: 106] +178787: read 0x7fff76c0 [Channel: 3 Bank: 6 Row:8189 Column: 108] +178799: read 0x7fff76e0 [Channel: 3 Bank: 6 Row:8189 Column: 110] +178811: read 0x7fff7700 [Channel: 3 Bank: 6 Row:8189 Column: 112] +178823: read 0x7fff7720 [Channel: 3 Bank: 6 Row:8189 Column: 114] +181646: read 0x7fff7740 [Channel: 3 Bank: 6 Row:8189 Column: 116] +181671: read 0x403b00 [Channel: 0 Bank: 7 Row:256 Column: 48] +181696: read 0x403b20 [Channel: 0 Bank: 7 Row:256 Column: 50] +181721: read 0x403b40 [Channel: 0 Bank: 7 Row:256 Column: 52] +181746: read 0x403b60 [Channel: 0 Bank: 7 Row:256 Column: 54] +182009: read 0x403b80 [Channel: 0 Bank: 7 Row:256 Column: 56] +182037: read 0x403ba0 [Channel: 0 Bank: 7 Row:256 Column: 58] +182062: read 0x403bc0 [Channel: 0 Bank: 7 Row:256 Column: 60] +182347: read 0x403be0 [Channel: 0 Bank: 7 Row:256 Column: 62] +183822: read 0x403c00 [Channel: 0 Bank: 7 Row:256 Column: 64] +183847: read 0x403c20 [Channel: 0 Bank: 7 Row:256 Column: 66] +183872: read 0x403c40 [Channel: 0 Bank: 7 Row:256 Column: 68] +183897: read 0x403c60 [Channel: 0 Bank: 7 Row:256 Column: 70] +184044: read 0x403c80 [Channel: 0 Bank: 7 Row:256 Column: 72] +184072: read 0x403ca0 [Channel: 0 Bank: 7 Row:256 Column: 74] +184296: read 0x403cc0 [Channel: 0 Bank: 7 Row:256 Column: 76] +185295: read 0x403ce0 [Channel: 0 Bank: 7 Row:256 Column: 78] +185320: read 0x403d00 [Channel: 0 Bank: 7 Row:256 Column: 80] +185345: read 0x403d20 [Channel: 0 Bank: 7 Row:256 Column: 82] +185370: read 0x403d40 [Channel: 0 Bank: 7 Row:256 Column: 84] +185655: read 0x403d60 [Channel: 0 Bank: 7 Row:256 Column: 86] +185680: read 0x403d80 [Channel: 0 Bank: 7 Row:256 Column: 88] +185705: read 0x403da0 [Channel: 0 Bank: 7 Row:256 Column: 90] +185730: read 0x403dc0 [Channel: 0 Bank: 7 Row:256 Column: 92] +185755: read 0x403de0 [Channel: 0 Bank: 7 Row:256 Column: 94] +186118: read 0x403e00 [Channel: 0 Bank: 7 Row:256 Column: 96] +186119: read 0x7fff7e20 [Channel: 3 Bank: 7 Row:8189 Column: 98] +187438: read 0x7fff7e40 [Channel: 3 Bank: 7 Row:8189 Column: 100] +187466: read 0x403e20 [Channel: 0 Bank: 7 Row:256 Column: 98] +187491: read 0x403e40 [Channel: 0 Bank: 7 Row:256 Column: 100] +187652: read 0x403e60 [Channel: 0 Bank: 7 Row:256 Column: 102] +187677: read 0x403e80 [Channel: 0 Bank: 7 Row:256 Column: 104] +187707: read 0x403ea0 [Channel: 0 Bank: 7 Row:256 Column: 106] +187732: read 0x403ec0 [Channel: 0 Bank: 7 Row:256 Column: 108] +187757: read 0x403ee0 [Channel: 0 Bank: 7 Row:256 Column: 110] +187963: read 0x403f00 [Channel: 0 Bank: 7 Row:256 Column: 112] +187987: read 0x402d40 [Channel: 0 Bank: 5 Row:256 Column: 84] +188012: read 0x402d60 [Channel: 0 Bank: 5 Row:256 Column: 86] +188037: read 0x402d80 [Channel: 0 Bank: 5 Row:256 Column: 88] +188062: read 0x402da0 [Channel: 0 Bank: 5 Row:256 Column: 90] +188087: read 0x402dc0 [Channel: 0 Bank: 5 Row:256 Column: 92] +188112: read 0x402de0 [Channel: 0 Bank: 5 Row:256 Column: 94] +188137: read 0x402e00 [Channel: 0 Bank: 5 Row:256 Column: 96] +188162: read 0x402e20 [Channel: 0 Bank: 5 Row:256 Column: 98] +188187: read 0x402e40 [Channel: 0 Bank: 5 Row:256 Column: 100] +188212: read 0x402e60 [Channel: 0 Bank: 5 Row:256 Column: 102] +188237: read 0x402e80 [Channel: 0 Bank: 5 Row:256 Column: 104] +188262: read 0x402ea0 [Channel: 0 Bank: 5 Row:256 Column: 106] +188287: read 0x402ec0 [Channel: 0 Bank: 5 Row:256 Column: 108] +188315: read 0x402ee0 [Channel: 0 Bank: 5 Row:256 Column: 110] +188339: read 0x402f00 [Channel: 0 Bank: 5 Row:256 Column: 112] +188369: read 0x402f20 [Channel: 0 Bank: 5 Row:256 Column: 114] +188394: read 0x402f40 [Channel: 0 Bank: 5 Row:256 Column: 116] +188418: read 0x402f60 [Channel: 0 Bank: 5 Row:256 Column: 118] +188443: read 0x402f80 [Channel: 0 Bank: 5 Row:256 Column: 120] +188446: read 0x402fa0 [Channel: 0 Bank: 5 Row:256 Column: 122] +188447: read 0x10007780 [Channel: 2 Bank: 6 Row:1 Column: 120] +188448: read 0x10007880 [Channel: 2 Bank: 7 Row:1 Column: 8] +188468: read 0x10007980 [Channel: 2 Bank: 7 Row:1 Column: 24] +188493: read 0x402fc0 [Channel: 0 Bank: 5 Row:256 Column: 124] +188739: read 0x403f20 [Channel: 0 Bank: 7 Row:256 Column: 114] +188740: read 0x100077a0 [Channel: 2 Bank: 6 Row:1 Column: 122] +188741: read 0x100078a0 [Channel: 2 Bank: 7 Row:1 Column: 10] +188971: read 0x100079a0 [Channel: 2 Bank: 7 Row:1 Column: 26] +188972: read 0x100077c0 [Channel: 2 Bank: 6 Row:1 Column: 124] +188973: read 0x100078c0 [Channel: 2 Bank: 7 Row:1 Column: 12] +189203: read 0x100079c0 [Channel: 2 Bank: 7 Row:1 Column: 28] +189204: read 0x100077e0 [Channel: 2 Bank: 6 Row:1 Column: 126] +189205: read 0x100078e0 [Channel: 2 Bank: 7 Row:1 Column: 14] +189435: read 0x100079e0 [Channel: 2 Bank: 7 Row:1 Column: 30] +189436: read 0x10007800 [Channel: 2 Bank: 7 Row:1 Column: 0] +189437: read 0x10007900 [Channel: 2 Bank: 7 Row:1 Column: 16] +189667: read 0x10007a00 [Channel: 2 Bank: 7 Row:1 Column: 32] +189668: read 0x10007820 [Channel: 2 Bank: 7 Row:1 Column: 2] +189669: read 0x10007920 [Channel: 2 Bank: 7 Row:1 Column: 18] +189899: read 0x10007a20 [Channel: 2 Bank: 7 Row:1 Column: 34] +189900: read 0x10007840 [Channel: 2 Bank: 7 Row:1 Column: 4] +189901: read 0x10007940 [Channel: 2 Bank: 7 Row:1 Column: 20] +190131: read 0x10007a40 [Channel: 2 Bank: 7 Row:1 Column: 36] +190132: read 0x10007860 [Channel: 2 Bank: 7 Row:1 Column: 6] +190133: read 0x10007960 [Channel: 2 Bank: 7 Row:1 Column: 22] +190380: read 0x10007a60 [Channel: 2 Bank: 7 Row:1 Column: 38] +190381: read 0x10007a80 [Channel: 2 Bank: 7 Row:1 Column: 40] +190382: read 0x10007b80 [Channel: 2 Bank: 7 Row:1 Column: 56] +190612: read 0x10007c80 [Channel: 2 Bank: 7 Row:1 Column: 72] +190613: read 0x10007aa0 [Channel: 2 Bank: 7 Row:1 Column: 42] +190614: read 0x10007ba0 [Channel: 2 Bank: 7 Row:1 Column: 58] +190844: read 0x10007ca0 [Channel: 2 Bank: 7 Row:1 Column: 74] +190845: read 0x10007ac0 [Channel: 2 Bank: 7 Row:1 Column: 44] +190846: read 0x10007bc0 [Channel: 2 Bank: 7 Row:1 Column: 60] +191076: read 0x10007cc0 [Channel: 2 Bank: 7 Row:1 Column: 76] +191077: read 0x10007ae0 [Channel: 2 Bank: 7 Row:1 Column: 46] +191078: read 0x10007be0 [Channel: 2 Bank: 7 Row:1 Column: 62] +191312: read 0x10007ce0 [Channel: 2 Bank: 7 Row:1 Column: 78] +191313: read 0x10007b00 [Channel: 2 Bank: 7 Row:1 Column: 48] +191314: read 0x10007c00 [Channel: 2 Bank: 7 Row:1 Column: 64] +191544: read 0x10007d00 [Channel: 2 Bank: 7 Row:1 Column: 80] +191545: read 0x10007b20 [Channel: 2 Bank: 7 Row:1 Column: 50] +191546: read 0x10007c20 [Channel: 2 Bank: 7 Row:1 Column: 66] +191776: read 0x10007d20 [Channel: 2 Bank: 7 Row:1 Column: 82] +191777: read 0x10007b40 [Channel: 2 Bank: 7 Row:1 Column: 52] +191778: read 0x10007c40 [Channel: 2 Bank: 7 Row:1 Column: 68] +192008: read 0x10007d40 [Channel: 2 Bank: 7 Row:1 Column: 84] +192009: read 0x10007b60 [Channel: 2 Bank: 7 Row:1 Column: 54] +192010: read 0x10007c60 [Channel: 2 Bank: 7 Row:1 Column: 70] +192254: read 0x10007d60 [Channel: 2 Bank: 7 Row:1 Column: 86] +192255: read 0x10007d80 [Channel: 2 Bank: 7 Row:1 Column: 88] +192256: read 0x10007e80 [Channel: 2 Bank: 7 Row:1 Column: 104] +192486: read 0x10007f80 [Channel: 2 Bank: 7 Row:1 Column: 120] +192487: read 0x10007da0 [Channel: 2 Bank: 7 Row:1 Column: 90] +192488: read 0x10007ea0 [Channel: 2 Bank: 7 Row:1 Column: 106] +192718: read 0x10007fa0 [Channel: 2 Bank: 7 Row:1 Column: 122] +192719: read 0x10007dc0 [Channel: 2 Bank: 7 Row:1 Column: 92] +192720: read 0x10007ec0 [Channel: 2 Bank: 7 Row:1 Column: 108] +192950: read 0x10007fc0 [Channel: 2 Bank: 7 Row:1 Column: 124] +192951: read 0x10007de0 [Channel: 2 Bank: 7 Row:1 Column: 94] +192952: read 0x10007ee0 [Channel: 2 Bank: 7 Row:1 Column: 110] +193182: read 0x10007fe0 [Channel: 2 Bank: 7 Row:1 Column: 126] +193183: read 0x10007e00 [Channel: 2 Bank: 7 Row:1 Column: 96] +193184: read 0x10007f00 [Channel: 2 Bank: 7 Row:1 Column: 112] +193414: read 0x10008000 [Channel: 2 Bank: 0 Row:2 Column: 0] +193415: read 0x10007e20 [Channel: 2 Bank: 7 Row:1 Column: 98] +193416: read 0x10007f20 [Channel: 2 Bank: 7 Row:1 Column: 114] +193646: read 0x10008020 [Channel: 2 Bank: 0 Row:2 Column: 2] +193647: read 0x10007e40 [Channel: 2 Bank: 7 Row:1 Column: 100] +193648: read 0x10007f40 [Channel: 2 Bank: 7 Row:1 Column: 116] +193878: read 0x10008040 [Channel: 2 Bank: 0 Row:2 Column: 4] +193879: read 0x10007e60 [Channel: 2 Bank: 7 Row:1 Column: 102] +193880: read 0x10007f60 [Channel: 2 Bank: 7 Row:1 Column: 118] +194146: read 0x10008060 [Channel: 2 Bank: 0 Row:2 Column: 6] +194147: read 0x10008080 [Channel: 2 Bank: 0 Row:2 Column: 8] +194148: read 0x10008180 [Channel: 2 Bank: 0 Row:2 Column: 24] +194378: read 0x10008280 [Channel: 2 Bank: 0 Row:2 Column: 40] +194379: read 0x100080a0 [Channel: 2 Bank: 0 Row:2 Column: 10] +194380: read 0x100081a0 [Channel: 2 Bank: 0 Row:2 Column: 26] +194610: read 0x100082a0 [Channel: 2 Bank: 0 Row:2 Column: 42] +194611: read 0x100080c0 [Channel: 2 Bank: 0 Row:2 Column: 12] +194612: read 0x100081c0 [Channel: 2 Bank: 0 Row:2 Column: 28] +194842: read 0x100082c0 [Channel: 2 Bank: 0 Row:2 Column: 44] +194843: read 0x100080e0 [Channel: 2 Bank: 0 Row:2 Column: 14] +194844: read 0x100081e0 [Channel: 2 Bank: 0 Row:2 Column: 30] +195074: read 0x100082e0 [Channel: 2 Bank: 0 Row:2 Column: 46] +195075: read 0x10008100 [Channel: 2 Bank: 0 Row:2 Column: 16] +195076: read 0x10008200 [Channel: 2 Bank: 0 Row:2 Column: 32] +195312: read 0x10008300 [Channel: 2 Bank: 0 Row:2 Column: 48] +195313: read 0x10008120 [Channel: 2 Bank: 0 Row:2 Column: 18] +195314: read 0x10008220 [Channel: 2 Bank: 0 Row:2 Column: 34] +195550: read 0x10008320 [Channel: 2 Bank: 0 Row:2 Column: 50] +195551: read 0x10008140 [Channel: 2 Bank: 0 Row:2 Column: 20] +195552: read 0x10008240 [Channel: 2 Bank: 0 Row:2 Column: 36] +195788: read 0x10008340 [Channel: 2 Bank: 0 Row:2 Column: 52] +195789: read 0x10008160 [Channel: 2 Bank: 0 Row:2 Column: 22] +195790: read 0x10008260 [Channel: 2 Bank: 0 Row:2 Column: 38] +196005: read 0x10008360 [Channel: 2 Bank: 0 Row:2 Column: 54] +196030: read 0x403f40 [Channel: 0 Bank: 7 Row:256 Column: 116] +196055: read 0x403f60 [Channel: 0 Bank: 7 Row:256 Column: 118] +196080: read 0x403f80 [Channel: 0 Bank: 7 Row:256 Column: 120] +196105: read 0x403fa0 [Channel: 0 Bank: 7 Row:256 Column: 122] +196133: read 0x403fc0 [Channel: 0 Bank: 7 Row:256 Column: 124] +196157: read 0x402800 [Channel: 0 Bank: 5 Row:256 Column: 0] +196182: read 0x402820 [Channel: 0 Bank: 5 Row:256 Column: 2] +196207: read 0x402840 [Channel: 0 Bank: 5 Row:256 Column: 4] +196232: read 0x402860 [Channel: 0 Bank: 5 Row:256 Column: 6] +196257: read 0x402880 [Channel: 0 Bank: 5 Row:256 Column: 8] +196282: read 0x4028a0 [Channel: 0 Bank: 5 Row:256 Column: 10] +196307: read 0x4028c0 [Channel: 0 Bank: 5 Row:256 Column: 12] +196335: read 0x4028e0 [Channel: 0 Bank: 5 Row:256 Column: 14] +196363: read 0x402900 [Channel: 0 Bank: 5 Row:256 Column: 16] +196391: read 0x402920 [Channel: 0 Bank: 5 Row:256 Column: 18] +196416: read 0x402940 [Channel: 0 Bank: 5 Row:256 Column: 20] +196472: read 0x402960 [Channel: 0 Bank: 5 Row:256 Column: 22] +196508: read 0x402980 [Channel: 0 Bank: 5 Row:256 Column: 24] +196541: read 0x10009080 [Channel: 2 Bank: 2 Row:2 Column: 8] +196574: read 0x100090e0 [Channel: 2 Bank: 2 Row:2 Column: 14] +196580: read 0x10009120 [Channel: 2 Bank: 2 Row:2 Column: 18] +196607: read 0x10009140 [Channel: 2 Bank: 2 Row:2 Column: 20] +196640: read 0x10009180 [Channel: 2 Bank: 2 Row:2 Column: 24] +196673: read 0x100091e0 [Channel: 2 Bank: 2 Row:2 Column: 30] +196706: read 0x10009240 [Channel: 2 Bank: 2 Row:2 Column: 36] +196738: read 0x100092a0 [Channel: 2 Bank: 2 Row:2 Column: 42] +196763: read 0x4029a0 [Channel: 0 Bank: 5 Row:256 Column: 26] +196788: read 0x4029c0 [Channel: 0 Bank: 5 Row:256 Column: 28] +196813: read 0x4029e0 [Channel: 0 Bank: 5 Row:256 Column: 30] +196841: read 0x402a00 [Channel: 0 Bank: 5 Row:256 Column: 32] +196866: read 0x402a20 [Channel: 0 Bank: 5 Row:256 Column: 34] +196891: read 0x402a40 [Channel: 0 Bank: 5 Row:256 Column: 36] +196916: read 0x402a60 [Channel: 0 Bank: 5 Row:256 Column: 38] +196957: read 0x402a80 [Channel: 0 Bank: 5 Row:256 Column: 40] +197002: read 0x402aa0 [Channel: 0 Bank: 5 Row:256 Column: 42] +197082: read 0x402ac0 [Channel: 0 Bank: 5 Row:256 Column: 44] +197133: read 0x100091a0 [Channel: 2 Bank: 2 Row:2 Column: 26] +197219: read 0x10009200 [Channel: 2 Bank: 2 Row:2 Column: 32] +197244: read 0x402ae0 [Channel: 0 Bank: 5 Row:256 Column: 46] +197269: read 0x402b00 [Channel: 0 Bank: 5 Row:256 Column: 48] +197294: read 0x402b20 [Channel: 0 Bank: 5 Row:256 Column: 50] +197319: read 0x402b40 [Channel: 0 Bank: 5 Row:256 Column: 52] +197344: read 0x402b60 [Channel: 0 Bank: 5 Row:256 Column: 54] +197348: read 0x402b80 [Channel: 0 Bank: 5 Row:256 Column: 56] +197369: read 0x10009300 [Channel: 2 Bank: 2 Row:2 Column: 48] +197403: read 0x402ba0 [Channel: 0 Bank: 5 Row:256 Column: 58] +197418: read 0x402bc0 [Channel: 0 Bank: 5 Row:256 Column: 60] +197437: read 0x10009340 [Channel: 2 Bank: 2 Row:2 Column: 52] +197451: read 0x10009360 [Channel: 2 Bank: 2 Row:2 Column: 54] +197484: read 0x100093a0 [Channel: 2 Bank: 2 Row:2 Column: 58] +197517: read 0x10009400 [Channel: 2 Bank: 2 Row:2 Column: 64] +197550: read 0x10009460 [Channel: 2 Bank: 2 Row:2 Column: 70] +197583: read 0x100094c0 [Channel: 2 Bank: 2 Row:2 Column: 76] +197595: read 0x10009500 [Channel: 2 Bank: 2 Row:2 Column: 80] +197616: read 0x10009520 [Channel: 2 Bank: 2 Row:2 Column: 82] +197649: read 0x10009560 [Channel: 2 Bank: 2 Row:2 Column: 86] +197677: read 0x402be0 [Channel: 0 Bank: 5 Row:256 Column: 62] +197705: read 0x402c00 [Channel: 0 Bank: 5 Row:256 Column: 64] +197733: read 0x402c20 [Channel: 0 Bank: 5 Row:256 Column: 66] +197761: read 0x402c40 [Channel: 0 Bank: 5 Row:256 Column: 68] +197786: read 0x402c60 [Channel: 0 Bank: 5 Row:256 Column: 70] +197842: read 0x402c80 [Channel: 0 Bank: 5 Row:256 Column: 72] +197929: read 0x402ca0 [Channel: 0 Bank: 5 Row:256 Column: 74] +198093: read 0x100093c0 [Channel: 2 Bank: 2 Row:2 Column: 60] +198119: read 0x10009580 [Channel: 2 Bank: 2 Row:2 Column: 88] +198144: read 0x402cc0 [Channel: 0 Bank: 5 Row:256 Column: 76] +198172: read 0x402ce0 [Channel: 0 Bank: 5 Row:256 Column: 78] +198200: read 0x402d00 [Channel: 0 Bank: 5 Row:256 Column: 80] +198226: read 0x402d20 [Channel: 0 Bank: 5 Row:256 Column: 82] +198251: read 0x403fe0 [Channel: 0 Bank: 7 Row:256 Column: 126] +198276: read 0x404000 [Channel: 0 Bank: 0 Row:257 Column: 0] +198301: read 0x404020 [Channel: 0 Bank: 0 Row:257 Column: 2] +198329: read 0x404040 [Channel: 0 Bank: 0 Row:257 Column: 4] +198362: read 0x1000a4e0 [Channel: 2 Bank: 4 Row:2 Column: 78] +198395: read 0x1000a540 [Channel: 2 Bank: 4 Row:2 Column: 84] +198428: read 0x1000a5a0 [Channel: 2 Bank: 4 Row:2 Column: 90] +198440: read 0x1000a5e0 [Channel: 2 Bank: 4 Row:2 Column: 94] +198461: read 0x1000a600 [Channel: 2 Bank: 4 Row:2 Column: 96] +198494: read 0x1000a640 [Channel: 2 Bank: 4 Row:2 Column: 100] +198527: read 0x1000a6a0 [Channel: 2 Bank: 4 Row:2 Column: 106] +198560: read 0x1000a700 [Channel: 2 Bank: 4 Row:2 Column: 112] +198743: read 0x1000a760 [Channel: 2 Bank: 4 Row:2 Column: 118] +198882: read 0x1000a660 [Channel: 2 Bank: 4 Row:2 Column: 102] +198888: read 0x1000a7a0 [Channel: 2 Bank: 4 Row:2 Column: 122] +198915: read 0x1000a7c0 [Channel: 2 Bank: 4 Row:2 Column: 124] +198948: read 0x1000a800 [Channel: 2 Bank: 5 Row:2 Column: 0] +198981: read 0x1000a860 [Channel: 2 Bank: 5 Row:2 Column: 6] +199014: read 0x1000a8c0 [Channel: 2 Bank: 5 Row:2 Column: 12] +199047: read 0x1000a920 [Channel: 2 Bank: 5 Row:2 Column: 18] +199080: read 0x1000a980 [Channel: 2 Bank: 5 Row:2 Column: 24] +199098: read 0x1000a9c0 [Channel: 2 Bank: 5 Row:2 Column: 28] +199113: read 0x1000a9e0 [Channel: 2 Bank: 5 Row:2 Column: 30] +199192: read 0x1000aa20 [Channel: 2 Bank: 5 Row:2 Column: 34] +199244: read 0x1000a820 [Channel: 2 Bank: 5 Row:2 Column: 2] +199408: read 0x1000a880 [Channel: 2 Bank: 5 Row:2 Column: 8] +199462: read 0x1000aa40 [Channel: 2 Bank: 5 Row:2 Column: 36] +199495: read 0x1000b9a0 [Channel: 2 Bank: 7 Row:2 Column: 26] +199528: read 0x1000ba00 [Channel: 2 Bank: 7 Row:2 Column: 32] +199561: read 0x1000ba60 [Channel: 2 Bank: 7 Row:2 Column: 38] +199579: read 0x1000baa0 [Channel: 2 Bank: 7 Row:2 Column: 42] +199594: read 0x1000bac0 [Channel: 2 Bank: 7 Row:2 Column: 44] +199627: read 0x1000bb00 [Channel: 2 Bank: 7 Row:2 Column: 48] +199660: read 0x1000bb60 [Channel: 2 Bank: 7 Row:2 Column: 54] +199693: read 0x1000bbc0 [Channel: 2 Bank: 7 Row:2 Column: 60] +199882: read 0x1000bc20 [Channel: 2 Bank: 7 Row:2 Column: 66] +200015: read 0x1000bb20 [Channel: 2 Bank: 7 Row:2 Column: 50] +200027: read 0x1000bc60 [Channel: 2 Bank: 7 Row:2 Column: 70] +200048: read 0x1000bc80 [Channel: 2 Bank: 7 Row:2 Column: 72] +200081: read 0x1000bcc0 [Channel: 2 Bank: 7 Row:2 Column: 76] +200114: read 0x1000bd20 [Channel: 2 Bank: 7 Row:2 Column: 82] +200147: read 0x1000bd80 [Channel: 2 Bank: 7 Row:2 Column: 88] +200180: read 0x1000bde0 [Channel: 2 Bank: 7 Row:2 Column: 94] +200186: read 0x1000be20 [Channel: 2 Bank: 7 Row:2 Column: 98] +200213: read 0x1000be40 [Channel: 2 Bank: 7 Row:2 Column: 100] +200246: read 0x1000be80 [Channel: 2 Bank: 7 Row:2 Column: 104] +200331: read 0x1000bee0 [Channel: 2 Bank: 7 Row:2 Column: 110] +200495: read 0x1000bce0 [Channel: 2 Bank: 7 Row:2 Column: 78] +200547: read 0x1000bea0 [Channel: 2 Bank: 7 Row:2 Column: 106] +200580: read 0x1000bf00 [Channel: 2 Bank: 7 Row:2 Column: 112] +250820: read 0x404060 [Channel: 0 Bank: 0 Row:257 Column: 6] +250871: read 0x10009040 [Channel: 2 Bank: 2 Row:2 Column: 4] +251030: read 0x100090a0 [Channel: 2 Bank: 2 Row:2 Column: 10] +251174: read 0x10009260 [Channel: 2 Bank: 2 Row:2 Column: 38] +251333: read 0x10009100 [Channel: 2 Bank: 2 Row:2 Column: 16] +251478: read 0x100092c0 [Channel: 2 Bank: 2 Row:2 Column: 44] +251785: read 0x10009420 [Channel: 2 Bank: 2 Row:2 Column: 66] +251837: read 0x10009480 [Channel: 2 Bank: 2 Row:2 Column: 72] +251959: read 0x100094e0 [Channel: 2 Bank: 2 Row:2 Column: 78] +252118: read 0x1000a500 [Channel: 2 Bank: 4 Row:2 Column: 80] +252169: read 0x1000a6c0 [Channel: 2 Bank: 4 Row:2 Column: 108] +252262: read 0x1000a720 [Channel: 2 Bank: 4 Row:2 Column: 114] +252313: read 0x1000a560 [Channel: 2 Bank: 4 Row:2 Column: 86] +252472: read 0x1000a5c0 [Channel: 2 Bank: 4 Row:2 Column: 92] +252617: read 0x1000a780 [Channel: 2 Bank: 4 Row:2 Column: 120] +252924: read 0x1000a8e0 [Channel: 2 Bank: 5 Row:2 Column: 14] +253098: read 0x1000a940 [Channel: 2 Bank: 5 Row:2 Column: 20] +253257: read 0x1000b9c0 [Channel: 2 Bank: 7 Row:2 Column: 28] +253401: read 0x1000bb80 [Channel: 2 Bank: 7 Row:2 Column: 56] +253560: read 0x1000ba20 [Channel: 2 Bank: 7 Row:2 Column: 34] +253611: read 0x1000bbe0 [Channel: 2 Bank: 7 Row:2 Column: 62] +253705: read 0x1000bc40 [Channel: 2 Bank: 7 Row:2 Column: 68] +253756: read 0x1000bd40 [Channel: 2 Bank: 7 Row:2 Column: 84] +254063: read 0x1000bda0 [Channel: 2 Bank: 7 Row:2 Column: 90] +303061: read 0x1000be00 [Channel: 2 Bank: 7 Row:2 Column: 96] +303364: read 0x10009160 [Channel: 2 Bank: 2 Row:2 Column: 22] +303415: read 0x100091c0 [Channel: 2 Bank: 2 Row:2 Column: 28] +303509: read 0x10009220 [Channel: 2 Bank: 2 Row:2 Column: 34] +303560: read 0x10009320 [Channel: 2 Bank: 2 Row:2 Column: 50] +303719: read 0x10009380 [Channel: 2 Bank: 2 Row:2 Column: 56] +303865: read 0x10009540 [Channel: 2 Bank: 2 Row:2 Column: 84] +304029: read 0x100093e0 [Channel: 2 Bank: 2 Row:2 Column: 62] +304200: read 0x100095a0 [Channel: 2 Bank: 2 Row:2 Column: 90] +304503: read 0x1000a620 [Channel: 2 Bank: 4 Row:2 Column: 98] +304648: read 0x1000a680 [Channel: 2 Bank: 4 Row:2 Column: 104] +304807: read 0x1000a7e0 [Channel: 2 Bank: 4 Row:2 Column: 126] +304858: read 0x1000a9a0 [Channel: 2 Bank: 5 Row:2 Column: 26] +304952: read 0x1000aa00 [Channel: 2 Bank: 5 Row:2 Column: 32] +305004: read 0x1000a840 [Channel: 2 Bank: 5 Row:2 Column: 4] +305168: read 0x1000a8a0 [Channel: 2 Bank: 5 Row:2 Column: 10] +305288: read 0x1000aa60 [Channel: 2 Bank: 5 Row:2 Column: 38] +305339: read 0x1000ba80 [Channel: 2 Bank: 7 Row:2 Column: 40] +305642: read 0x1000bae0 [Channel: 2 Bank: 7 Row:2 Column: 46] +305787: read 0x1000bb40 [Channel: 2 Bank: 7 Row:2 Column: 52] +305946: read 0x1000bca0 [Channel: 2 Bank: 7 Row:2 Column: 74] +306091: read 0x1000be60 [Channel: 2 Bank: 7 Row:2 Column: 102] +306255: read 0x1000bd00 [Channel: 2 Bank: 7 Row:2 Column: 80] +306307: read 0x1000bec0 [Channel: 2 Bank: 7 Row:2 Column: 108] +354414: read 0x1000bf20 [Channel: 2 Bank: 7 Row:2 Column: 114] +354465: read 0x10009060 [Channel: 2 Bank: 2 Row:2 Column: 6] +354624: read 0x100090c0 [Channel: 2 Bank: 2 Row:2 Column: 12] +354927: read 0x10009280 [Channel: 2 Bank: 2 Row:2 Column: 40] +355072: read 0x100092e0 [Channel: 2 Bank: 2 Row:2 Column: 46] +355379: read 0x10009440 [Channel: 2 Bank: 2 Row:2 Column: 68] +355553: read 0x100094a0 [Channel: 2 Bank: 2 Row:2 Column: 74] +355712: read 0x1000a520 [Channel: 2 Bank: 4 Row:2 Column: 82] +355763: read 0x1000a6e0 [Channel: 2 Bank: 4 Row:2 Column: 110] +355856: read 0x1000a740 [Channel: 2 Bank: 4 Row:2 Column: 116] +356211: read 0x1000a580 [Channel: 2 Bank: 4 Row:2 Column: 88] +356518: read 0x1000a900 [Channel: 2 Bank: 5 Row:2 Column: 16] +356692: read 0x1000a960 [Channel: 2 Bank: 5 Row:2 Column: 22] +356851: read 0x1000b9e0 [Channel: 2 Bank: 7 Row:2 Column: 30] +356995: read 0x1000bba0 [Channel: 2 Bank: 7 Row:2 Column: 58] +357154: read 0x1000ba40 [Channel: 2 Bank: 7 Row:2 Column: 36] +357299: read 0x1000bc00 [Channel: 2 Bank: 7 Row:2 Column: 64] +357350: read 0x1000bd60 [Channel: 2 Bank: 7 Row:2 Column: 86] +402579: read 0x1000bdc0 [Channel: 2 Bank: 7 Row:2 Column: 92] +403718: read 0x100095c0 [Channel: 2 Bank: 2 Row:2 Column: 92] +404857: read 0x1000aa80 [Channel: 2 Bank: 5 Row:2 Column: 40] +495340: read 0x1000bf40 [Channel: 2 Bank: 7 Row:2 Column: 116] +495373: read 0x10009620 [Channel: 2 Bank: 2 Row:2 Column: 98] +495406: read 0x10009680 [Channel: 2 Bank: 2 Row:2 Column: 104] +495412: read 0x100096c0 [Channel: 2 Bank: 2 Row:2 Column: 108] +495439: read 0x100096e0 [Channel: 2 Bank: 2 Row:2 Column: 110] +495472: read 0x10009720 [Channel: 2 Bank: 2 Row:2 Column: 114] +495505: read 0x10009780 [Channel: 2 Bank: 2 Row:2 Column: 120] +495538: read 0x100097e0 [Channel: 2 Bank: 2 Row:2 Column: 126] +495715: read 0x10009840 [Channel: 2 Bank: 3 Row:2 Column: 4] +495766: read 0x10009740 [Channel: 2 Bank: 2 Row:2 Column: 116] +495860: read 0x100097a0 [Channel: 2 Bank: 2 Row:2 Column: 122] +495893: read 0x100098a0 [Channel: 2 Bank: 3 Row:2 Column: 10] +495911: read 0x100098e0 [Channel: 2 Bank: 3 Row:2 Column: 14] +495926: read 0x10009900 [Channel: 2 Bank: 3 Row:2 Column: 16] +495959: read 0x10009940 [Channel: 2 Bank: 3 Row:2 Column: 20] +495992: read 0x100099a0 [Channel: 2 Bank: 3 Row:2 Column: 26] +496025: read 0x10009a00 [Channel: 2 Bank: 3 Row:2 Column: 32] +496058: read 0x10009a60 [Channel: 2 Bank: 3 Row:2 Column: 38] +496070: read 0x10009aa0 [Channel: 2 Bank: 3 Row:2 Column: 42] +496091: read 0x10009ac0 [Channel: 2 Bank: 3 Row:2 Column: 44] +496216: read 0x10009b00 [Channel: 2 Bank: 3 Row:2 Column: 48] +496380: read 0x10009960 [Channel: 2 Bank: 3 Row:2 Column: 22] +496479: read 0x10009b20 [Channel: 2 Bank: 3 Row:2 Column: 50] +496512: read 0x1000aae0 [Channel: 2 Bank: 5 Row:2 Column: 46] +496545: read 0x1000ab40 [Channel: 2 Bank: 5 Row:2 Column: 52] +496557: read 0x1000ab80 [Channel: 2 Bank: 5 Row:2 Column: 56] +496578: read 0x1000aba0 [Channel: 2 Bank: 5 Row:2 Column: 58] +496611: read 0x1000abe0 [Channel: 2 Bank: 5 Row:2 Column: 62] +496644: read 0x1000ac40 [Channel: 2 Bank: 5 Row:2 Column: 68] +496677: read 0x1000aca0 [Channel: 2 Bank: 5 Row:2 Column: 74] +496860: read 0x1000ad00 [Channel: 2 Bank: 5 Row:2 Column: 80] +496999: read 0x1000ac00 [Channel: 2 Bank: 5 Row:2 Column: 64] +497005: read 0x1000ad40 [Channel: 2 Bank: 5 Row:2 Column: 84] +497032: read 0x1000ad60 [Channel: 2 Bank: 5 Row:2 Column: 86] +497065: read 0x1000ada0 [Channel: 2 Bank: 5 Row:2 Column: 90] +497098: read 0x1000ae00 [Channel: 2 Bank: 5 Row:2 Column: 96] +497131: read 0x1000ae60 [Channel: 2 Bank: 5 Row:2 Column: 102] +497164: read 0x1000aec0 [Channel: 2 Bank: 5 Row:2 Column: 108] +497197: read 0x1000af20 [Channel: 2 Bank: 5 Row:2 Column: 114] +497215: read 0x1000af60 [Channel: 2 Bank: 5 Row:2 Column: 118] +497230: read 0x1000af80 [Channel: 2 Bank: 5 Row:2 Column: 120] +497309: read 0x1000afc0 [Channel: 2 Bank: 5 Row:2 Column: 124] +497361: read 0x1000adc0 [Channel: 2 Bank: 5 Row:2 Column: 92] +497525: read 0x1000ae20 [Channel: 2 Bank: 5 Row:2 Column: 98] +497618: read 0x1000afe0 [Channel: 2 Bank: 5 Row:2 Column: 126] +497651: read 0x1000bfa0 [Channel: 2 Bank: 7 Row:2 Column: 122] +497684: read 0x1000c000 [Channel: 2 Bank: 0 Row:3 Column: 0] +497702: read 0x1000c040 [Channel: 2 Bank: 0 Row:3 Column: 4] +497717: read 0x1000c060 [Channel: 2 Bank: 0 Row:3 Column: 6] +497750: read 0x1000c0a0 [Channel: 2 Bank: 0 Row:3 Column: 10] +497783: read 0x1000c100 [Channel: 2 Bank: 0 Row:3 Column: 16] +497816: read 0x1000c160 [Channel: 2 Bank: 0 Row:3 Column: 22] +498005: read 0x1000c1c0 [Channel: 2 Bank: 0 Row:3 Column: 28] +498138: read 0x1000c0c0 [Channel: 2 Bank: 0 Row:3 Column: 12] +498150: read 0x1000c200 [Channel: 2 Bank: 0 Row:3 Column: 32] +498171: read 0x1000c220 [Channel: 2 Bank: 0 Row:3 Column: 34] +498204: read 0x1000c260 [Channel: 2 Bank: 0 Row:3 Column: 38] +498237: read 0x1000c2c0 [Channel: 2 Bank: 0 Row:3 Column: 44] +498270: read 0x1000c320 [Channel: 2 Bank: 0 Row:3 Column: 50] +498303: read 0x1000c380 [Channel: 2 Bank: 0 Row:3 Column: 56] +498309: read 0x1000c3c0 [Channel: 2 Bank: 0 Row:3 Column: 60] +498336: read 0x1000c3e0 [Channel: 2 Bank: 0 Row:3 Column: 62] +498369: read 0x1000c420 [Channel: 2 Bank: 0 Row:3 Column: 66] +498454: read 0x1000c480 [Channel: 2 Bank: 0 Row:3 Column: 72] +498618: read 0x1000c280 [Channel: 2 Bank: 0 Row:3 Column: 40] +498670: read 0x1000c440 [Channel: 2 Bank: 0 Row:3 Column: 68] +518006: read 0x1000c4a0 [Channel: 2 Bank: 0 Row:3 Column: 74] +551769: read 0x4043c0 [Channel: 0 Bank: 0 Row:257 Column: 60] +551820: read 0x100095e0 [Channel: 2 Bank: 2 Row:2 Column: 94] +551979: read 0x10009640 [Channel: 2 Bank: 2 Row:2 Column: 100] +552123: read 0x10009800 [Channel: 2 Bank: 3 Row:2 Column: 0] +552282: read 0x100096a0 [Channel: 2 Bank: 2 Row:2 Column: 106] +552427: read 0x10009860 [Channel: 2 Bank: 3 Row:2 Column: 6] +552734: read 0x100099c0 [Channel: 2 Bank: 3 Row:2 Column: 28] +552786: read 0x10009a20 [Channel: 2 Bank: 3 Row:2 Column: 34] +552908: read 0x10009a80 [Channel: 2 Bank: 3 Row:2 Column: 40] +553067: read 0x1000aaa0 [Channel: 2 Bank: 5 Row:2 Column: 42] +553118: read 0x1000ac60 [Channel: 2 Bank: 5 Row:2 Column: 70] +553211: read 0x1000acc0 [Channel: 2 Bank: 5 Row:2 Column: 76] +553262: read 0x1000ab00 [Channel: 2 Bank: 5 Row:2 Column: 48] +553421: read 0x1000ab60 [Channel: 2 Bank: 5 Row:2 Column: 54] +553566: read 0x1000ad20 [Channel: 2 Bank: 5 Row:2 Column: 82] +553873: read 0x1000ae80 [Channel: 2 Bank: 5 Row:2 Column: 104] +554047: read 0x1000aee0 [Channel: 2 Bank: 5 Row:2 Column: 110] +554206: read 0x1000bf60 [Channel: 2 Bank: 7 Row:2 Column: 118] +554350: read 0x1000c120 [Channel: 2 Bank: 0 Row:3 Column: 18] +554509: read 0x1000bfc0 [Channel: 2 Bank: 7 Row:2 Column: 124] +554560: read 0x1000c180 [Channel: 2 Bank: 0 Row:3 Column: 24] +554654: read 0x1000c1e0 [Channel: 2 Bank: 0 Row:3 Column: 30] +554705: read 0x1000c2e0 [Channel: 2 Bank: 0 Row:3 Column: 46] +555012: read 0x1000c340 [Channel: 2 Bank: 0 Row:3 Column: 52] +608540: read 0x1000c3a0 [Channel: 2 Bank: 0 Row:3 Column: 58] +608843: read 0x10009700 [Channel: 2 Bank: 2 Row:2 Column: 112] +608894: read 0x10009760 [Channel: 2 Bank: 2 Row:2 Column: 118] +608988: read 0x100097c0 [Channel: 2 Bank: 2 Row:2 Column: 124] +609039: read 0x100098c0 [Channel: 2 Bank: 3 Row:2 Column: 12] +609198: read 0x10009920 [Channel: 2 Bank: 3 Row:2 Column: 18] +609344: read 0x10009ae0 [Channel: 2 Bank: 3 Row:2 Column: 46] +609508: read 0x10009980 [Channel: 2 Bank: 3 Row:2 Column: 24] +609679: read 0x10009b40 [Channel: 2 Bank: 3 Row:2 Column: 52] +609982: read 0x1000abc0 [Channel: 2 Bank: 5 Row:2 Column: 60] +610127: read 0x1000ac20 [Channel: 2 Bank: 5 Row:2 Column: 66] +610286: read 0x1000ad80 [Channel: 2 Bank: 5 Row:2 Column: 88] +610337: read 0x1000af40 [Channel: 2 Bank: 5 Row:2 Column: 116] +610431: read 0x1000afa0 [Channel: 2 Bank: 5 Row:2 Column: 122] +610483: read 0x1000ade0 [Channel: 2 Bank: 5 Row:2 Column: 94] +610647: read 0x1000ae40 [Channel: 2 Bank: 5 Row:2 Column: 100] +610767: read 0x1000b000 [Channel: 2 Bank: 6 Row:2 Column: 0] +610818: read 0x1000c020 [Channel: 2 Bank: 0 Row:3 Column: 2] +611121: read 0x1000c080 [Channel: 2 Bank: 0 Row:3 Column: 8] +611266: read 0x1000c0e0 [Channel: 2 Bank: 0 Row:3 Column: 14] +611425: read 0x1000c240 [Channel: 2 Bank: 0 Row:3 Column: 36] +611570: read 0x1000c400 [Channel: 2 Bank: 0 Row:3 Column: 64] +611734: read 0x1000c2a0 [Channel: 2 Bank: 0 Row:3 Column: 42] +611786: read 0x1000c460 [Channel: 2 Bank: 0 Row:3 Column: 70] +664407: read 0x1000c4c0 [Channel: 2 Bank: 0 Row:3 Column: 76] +664458: read 0x10009600 [Channel: 2 Bank: 2 Row:2 Column: 96] +664617: read 0x10009660 [Channel: 2 Bank: 2 Row:2 Column: 102] +664920: read 0x10009820 [Channel: 2 Bank: 3 Row:2 Column: 2] +665065: read 0x10009880 [Channel: 2 Bank: 3 Row:2 Column: 8] +665372: read 0x100099e0 [Channel: 2 Bank: 3 Row:2 Column: 30] +665546: read 0x10009a40 [Channel: 2 Bank: 3 Row:2 Column: 36] +665705: read 0x1000aac0 [Channel: 2 Bank: 5 Row:2 Column: 44] +665756: read 0x1000ac80 [Channel: 2 Bank: 5 Row:2 Column: 72] +665849: read 0x1000ace0 [Channel: 2 Bank: 5 Row:2 Column: 78] +666204: read 0x1000ab20 [Channel: 2 Bank: 5 Row:2 Column: 50] +666511: read 0x1000aea0 [Channel: 2 Bank: 5 Row:2 Column: 106] +666685: read 0x1000af00 [Channel: 2 Bank: 5 Row:2 Column: 112] +666844: read 0x1000bf80 [Channel: 2 Bank: 7 Row:2 Column: 120] +666988: read 0x1000c140 [Channel: 2 Bank: 0 Row:3 Column: 20] +667147: read 0x1000bfe0 [Channel: 2 Bank: 7 Row:2 Column: 126] +667292: read 0x1000c1a0 [Channel: 2 Bank: 0 Row:3 Column: 26] +667343: read 0x1000c300 [Channel: 2 Bank: 0 Row:3 Column: 48] +718869: read 0x1000c360 [Channel: 2 Bank: 0 Row:3 Column: 54] +720008: read 0x10009b60 [Channel: 2 Bank: 3 Row:2 Column: 54] +721147: read 0x1000b020 [Channel: 2 Bank: 6 Row:2 Column: 2] +816285: read 0x1000c4e0 [Channel: 2 Bank: 0 Row:3 Column: 78] +816318: read 0x10009bc0 [Channel: 2 Bank: 3 Row:2 Column: 60] +816351: read 0x10009c20 [Channel: 2 Bank: 3 Row:2 Column: 66] +816357: read 0x10009c60 [Channel: 2 Bank: 3 Row:2 Column: 70] +816384: read 0x10009c80 [Channel: 2 Bank: 3 Row:2 Column: 72] +816417: read 0x10009cc0 [Channel: 2 Bank: 3 Row:2 Column: 76] +816450: read 0x10009d20 [Channel: 2 Bank: 3 Row:2 Column: 82] +816483: read 0x10009d80 [Channel: 2 Bank: 3 Row:2 Column: 88] +816660: read 0x10009de0 [Channel: 2 Bank: 3 Row:2 Column: 94] +816711: read 0x10009ce0 [Channel: 2 Bank: 3 Row:2 Column: 78] +816805: read 0x10009d40 [Channel: 2 Bank: 3 Row:2 Column: 84] +816838: read 0x10009e40 [Channel: 2 Bank: 3 Row:2 Column: 100] +816856: read 0x10009e80 [Channel: 2 Bank: 3 Row:2 Column: 104] +816871: read 0x10009ea0 [Channel: 2 Bank: 3 Row:2 Column: 106] +816904: read 0x10009ee0 [Channel: 2 Bank: 3 Row:2 Column: 110] +816937: read 0x10009f40 [Channel: 2 Bank: 3 Row:2 Column: 116] +816970: read 0x10009fa0 [Channel: 2 Bank: 3 Row:2 Column: 122] +817003: read 0x1000a000 [Channel: 2 Bank: 4 Row:2 Column: 0] +817015: read 0x1000a040 [Channel: 2 Bank: 4 Row:2 Column: 4] +817036: read 0x1000a060 [Channel: 2 Bank: 4 Row:2 Column: 6] +817161: read 0x1000a0a0 [Channel: 2 Bank: 4 Row:2 Column: 10] +817325: read 0x10009f00 [Channel: 2 Bank: 3 Row:2 Column: 112] +817424: read 0x1000a0c0 [Channel: 2 Bank: 4 Row:2 Column: 12] +817457: read 0x1000b080 [Channel: 2 Bank: 6 Row:2 Column: 8] +817490: read 0x1000b0e0 [Channel: 2 Bank: 6 Row:2 Column: 14] +817502: read 0x1000b120 [Channel: 2 Bank: 6 Row:2 Column: 18] +817523: read 0x1000b140 [Channel: 2 Bank: 6 Row:2 Column: 20] +817556: read 0x1000b180 [Channel: 2 Bank: 6 Row:2 Column: 24] +817589: read 0x1000b1e0 [Channel: 2 Bank: 6 Row:2 Column: 30] +817622: read 0x1000b240 [Channel: 2 Bank: 6 Row:2 Column: 36] +817805: read 0x1000b2a0 [Channel: 2 Bank: 6 Row:2 Column: 42] +817944: read 0x1000b1a0 [Channel: 2 Bank: 6 Row:2 Column: 26] +817950: read 0x1000b2e0 [Channel: 2 Bank: 6 Row:2 Column: 46] +817977: read 0x1000b300 [Channel: 2 Bank: 6 Row:2 Column: 48] +818010: read 0x1000b340 [Channel: 2 Bank: 6 Row:2 Column: 52] +818043: read 0x1000b3a0 [Channel: 2 Bank: 6 Row:2 Column: 58] +818076: read 0x1000b400 [Channel: 2 Bank: 6 Row:2 Column: 64] +818109: read 0x1000b460 [Channel: 2 Bank: 6 Row:2 Column: 70] +818142: read 0x1000b4c0 [Channel: 2 Bank: 6 Row:2 Column: 76] +818160: read 0x1000b500 [Channel: 2 Bank: 6 Row:2 Column: 80] +818175: read 0x1000b520 [Channel: 2 Bank: 6 Row:2 Column: 82] +818254: read 0x1000b560 [Channel: 2 Bank: 6 Row:2 Column: 86] +818306: read 0x1000b360 [Channel: 2 Bank: 6 Row:2 Column: 54] +818470: read 0x1000b3c0 [Channel: 2 Bank: 6 Row:2 Column: 60] +818563: read 0x1000b580 [Channel: 2 Bank: 6 Row:2 Column: 88] +818596: read 0x1000c540 [Channel: 2 Bank: 0 Row:3 Column: 84] +818629: read 0x1000c5a0 [Channel: 2 Bank: 0 Row:3 Column: 90] +818647: read 0x1000c5e0 [Channel: 2 Bank: 0 Row:3 Column: 94] +818662: read 0x1000c600 [Channel: 2 Bank: 0 Row:3 Column: 96] +818695: read 0x1000c640 [Channel: 2 Bank: 0 Row:3 Column: 100] +818728: read 0x1000c6a0 [Channel: 2 Bank: 0 Row:3 Column: 106] +818761: read 0x1000c700 [Channel: 2 Bank: 0 Row:3 Column: 112] +818950: read 0x1000c760 [Channel: 2 Bank: 0 Row:3 Column: 118] +819083: read 0x1000c660 [Channel: 2 Bank: 0 Row:3 Column: 102] +819095: read 0x1000c7a0 [Channel: 2 Bank: 0 Row:3 Column: 122] +819116: read 0x1000c7c0 [Channel: 2 Bank: 0 Row:3 Column: 124] +819149: read 0x1000c800 [Channel: 2 Bank: 1 Row:3 Column: 0] +819182: read 0x1000c860 [Channel: 2 Bank: 1 Row:3 Column: 6] +819215: read 0x1000c8c0 [Channel: 2 Bank: 1 Row:3 Column: 12] +819248: read 0x1000c920 [Channel: 2 Bank: 1 Row:3 Column: 18] +819254: read 0x1000c960 [Channel: 2 Bank: 1 Row:3 Column: 22] +819281: read 0x1000c980 [Channel: 2 Bank: 1 Row:3 Column: 24] +819314: read 0x1000c9c0 [Channel: 2 Bank: 1 Row:3 Column: 28] +819399: read 0x1000ca20 [Channel: 2 Bank: 1 Row:3 Column: 34] +819563: read 0x1000c820 [Channel: 2 Bank: 1 Row:3 Column: 2] +819615: read 0x1000c9e0 [Channel: 2 Bank: 1 Row:3 Column: 30] +819835: read 0x1000ca40 [Channel: 2 Bank: 1 Row:3 Column: 36] +871319: read 0x100057a0 [Channel: 2 Bank: 2 Row:1 Column: 122] +871370: read 0x10009b80 [Channel: 2 Bank: 3 Row:2 Column: 56] +871529: read 0x10009be0 [Channel: 2 Bank: 3 Row:2 Column: 62] +871673: read 0x10009da0 [Channel: 2 Bank: 3 Row:2 Column: 90] +871832: read 0x10009c40 [Channel: 2 Bank: 3 Row:2 Column: 68] +871977: read 0x10009e00 [Channel: 2 Bank: 3 Row:2 Column: 96] +872284: read 0x10009f60 [Channel: 2 Bank: 3 Row:2 Column: 118] +872336: read 0x10009fc0 [Channel: 2 Bank: 3 Row:2 Column: 124] +872458: read 0x1000a020 [Channel: 2 Bank: 4 Row:2 Column: 2] +872617: read 0x1000b040 [Channel: 2 Bank: 6 Row:2 Column: 4] +872668: read 0x1000b200 [Channel: 2 Bank: 6 Row:2 Column: 32] +872761: read 0x1000b260 [Channel: 2 Bank: 6 Row:2 Column: 38] +872812: read 0x1000b0a0 [Channel: 2 Bank: 6 Row:2 Column: 10] +872971: read 0x1000b100 [Channel: 2 Bank: 6 Row:2 Column: 16] +873116: read 0x1000b2c0 [Channel: 2 Bank: 6 Row:2 Column: 44] +873423: read 0x1000b420 [Channel: 2 Bank: 6 Row:2 Column: 66] +873597: read 0x1000b480 [Channel: 2 Bank: 6 Row:2 Column: 72] +873756: read 0x1000c500 [Channel: 2 Bank: 0 Row:3 Column: 80] +873900: read 0x1000c6c0 [Channel: 2 Bank: 0 Row:3 Column: 108] +874059: read 0x1000c560 [Channel: 2 Bank: 0 Row:3 Column: 86] +874110: read 0x1000c720 [Channel: 2 Bank: 0 Row:3 Column: 114] +874204: read 0x1000c780 [Channel: 2 Bank: 0 Row:3 Column: 120] +874255: read 0x1000c880 [Channel: 2 Bank: 1 Row:3 Column: 8] +874562: read 0x1000c8e0 [Channel: 2 Bank: 1 Row:3 Column: 14] +927605: read 0x1000c940 [Channel: 2 Bank: 1 Row:3 Column: 20] +927908: read 0x10009ca0 [Channel: 2 Bank: 3 Row:2 Column: 74] +927959: read 0x10009d00 [Channel: 2 Bank: 3 Row:2 Column: 80] +928053: read 0x10009d60 [Channel: 2 Bank: 3 Row:2 Column: 86] +928104: read 0x10009e60 [Channel: 2 Bank: 3 Row:2 Column: 102] +928263: read 0x10009ec0 [Channel: 2 Bank: 3 Row:2 Column: 108] +928409: read 0x1000a080 [Channel: 2 Bank: 4 Row:2 Column: 8] +928573: read 0x10009f20 [Channel: 2 Bank: 3 Row:2 Column: 114] +928744: read 0x1000a0e0 [Channel: 2 Bank: 4 Row:2 Column: 14] +929047: read 0x1000b160 [Channel: 2 Bank: 6 Row:2 Column: 22] +929192: read 0x1000b1c0 [Channel: 2 Bank: 6 Row:2 Column: 28] +929351: read 0x1000b320 [Channel: 2 Bank: 6 Row:2 Column: 50] +929402: read 0x1000b4e0 [Channel: 2 Bank: 6 Row:2 Column: 78] +929496: read 0x1000b540 [Channel: 2 Bank: 6 Row:2 Column: 84] +929548: read 0x1000b380 [Channel: 2 Bank: 6 Row:2 Column: 56] +929712: read 0x1000b3e0 [Channel: 2 Bank: 6 Row:2 Column: 62] +929832: read 0x1000b5a0 [Channel: 2 Bank: 6 Row:2 Column: 90] +929883: read 0x1000c5c0 [Channel: 2 Bank: 0 Row:3 Column: 92] +930186: read 0x1000c620 [Channel: 2 Bank: 0 Row:3 Column: 98] +930331: read 0x1000c680 [Channel: 2 Bank: 0 Row:3 Column: 104] +930490: read 0x1000c7e0 [Channel: 2 Bank: 0 Row:3 Column: 126] +930635: read 0x1000c9a0 [Channel: 2 Bank: 1 Row:3 Column: 26] +930799: read 0x1000c840 [Channel: 2 Bank: 1 Row:3 Column: 4] +930851: read 0x1000ca00 [Channel: 2 Bank: 1 Row:3 Column: 32] +984534: read 0x1000ca60 [Channel: 2 Bank: 1 Row:3 Column: 38] +984585: read 0x10009ba0 [Channel: 2 Bank: 3 Row:2 Column: 58] +984744: read 0x10009c00 [Channel: 2 Bank: 3 Row:2 Column: 64] +985047: read 0x10009dc0 [Channel: 2 Bank: 3 Row:2 Column: 92] +985192: read 0x10009e20 [Channel: 2 Bank: 3 Row:2 Column: 98] +985499: read 0x10009f80 [Channel: 2 Bank: 3 Row:2 Column: 120] +985673: read 0x10009fe0 [Channel: 2 Bank: 3 Row:2 Column: 126] +985832: read 0x1000b060 [Channel: 2 Bank: 6 Row:2 Column: 6] +985883: read 0x1000b220 [Channel: 2 Bank: 6 Row:2 Column: 34] +985976: read 0x1000b280 [Channel: 2 Bank: 6 Row:2 Column: 40] +986331: read 0x1000b0c0 [Channel: 2 Bank: 6 Row:2 Column: 12] +986638: read 0x1000b440 [Channel: 2 Bank: 6 Row:2 Column: 68] +986812: read 0x1000b4a0 [Channel: 2 Bank: 6 Row:2 Column: 74] +986971: read 0x1000c520 [Channel: 2 Bank: 0 Row:3 Column: 82] +987115: read 0x1000c6e0 [Channel: 2 Bank: 0 Row:3 Column: 110] +987274: read 0x1000c580 [Channel: 2 Bank: 0 Row:3 Column: 88] +987419: read 0x1000c740 [Channel: 2 Bank: 0 Row:3 Column: 116] +987470: read 0x1000c8a0 [Channel: 2 Bank: 1 Row:3 Column: 10] +1042117: read 0x1000c900 [Channel: 2 Bank: 1 Row:3 Column: 16] +1043256: read 0x1000a100 [Channel: 2 Bank: 4 Row:2 Column: 16] +1044395: read 0x1000b5c0 [Channel: 2 Bank: 6 Row:2 Column: 92] +1141985: read 0x1000ca80 [Channel: 2 Bank: 1 Row:3 Column: 40] +1142018: read 0x1000a160 [Channel: 2 Bank: 4 Row:2 Column: 22] +1142051: read 0x1000a1c0 [Channel: 2 Bank: 4 Row:2 Column: 28] +1142057: read 0x1000a200 [Channel: 2 Bank: 4 Row:2 Column: 32] +1142084: read 0x1000a220 [Channel: 2 Bank: 4 Row:2 Column: 34] +1142117: read 0x1000a260 [Channel: 2 Bank: 4 Row:2 Column: 38] +1142150: read 0x1000a2c0 [Channel: 2 Bank: 4 Row:2 Column: 44] +1142183: read 0x1000a320 [Channel: 2 Bank: 4 Row:2 Column: 50] +1142360: read 0x1000a380 [Channel: 2 Bank: 4 Row:2 Column: 56] +1142411: read 0x1000a280 [Channel: 2 Bank: 4 Row:2 Column: 40] +1142505: read 0x1000a2e0 [Channel: 2 Bank: 4 Row:2 Column: 46] +1142538: read 0x1000a3e0 [Channel: 2 Bank: 4 Row:2 Column: 62] +1142556: read 0x1000a420 [Channel: 2 Bank: 4 Row:2 Column: 66] +1142571: read 0x1000a440 [Channel: 2 Bank: 4 Row:2 Column: 68] +1142696: read 0x1000a480 [Channel: 2 Bank: 4 Row:2 Column: 72] +1142789: read 0x1000a4a0 [Channel: 2 Bank: 4 Row:2 Column: 74] +1142822: read 0x1000b620 [Channel: 2 Bank: 6 Row:2 Column: 98] +1142855: read 0x1000b680 [Channel: 2 Bank: 6 Row:2 Column: 104] +1142867: read 0x1000b6c0 [Channel: 2 Bank: 6 Row:2 Column: 108] +1142888: read 0x1000b6e0 [Channel: 2 Bank: 6 Row:2 Column: 110] +1142921: read 0x1000b720 [Channel: 2 Bank: 6 Row:2 Column: 114] +1142954: read 0x1000b780 [Channel: 2 Bank: 6 Row:2 Column: 120] +1142987: read 0x1000b7e0 [Channel: 2 Bank: 6 Row:2 Column: 126] +1143170: read 0x1000b840 [Channel: 2 Bank: 7 Row:2 Column: 4] +1143309: read 0x1000b740 [Channel: 2 Bank: 6 Row:2 Column: 116] +1143315: read 0x1000b880 [Channel: 2 Bank: 7 Row:2 Column: 8] +1143342: read 0x1000b8a0 [Channel: 2 Bank: 7 Row:2 Column: 10] +1143375: read 0x1000b8e0 [Channel: 2 Bank: 7 Row:2 Column: 14] +1143454: read 0x1000b940 [Channel: 2 Bank: 7 Row:2 Column: 20] +1143506: read 0x1000b900 [Channel: 2 Bank: 7 Row:2 Column: 16] +1143593: read 0x1000b960 [Channel: 2 Bank: 7 Row:2 Column: 22] +1143626: read 0x1000cae0 [Channel: 2 Bank: 1 Row:3 Column: 46] +1143659: read 0x1000cb40 [Channel: 2 Bank: 1 Row:3 Column: 52] +1143677: read 0x1000cb80 [Channel: 2 Bank: 1 Row:3 Column: 56] +1143692: read 0x1000cba0 [Channel: 2 Bank: 1 Row:3 Column: 58] +1143725: read 0x1000cbe0 [Channel: 2 Bank: 1 Row:3 Column: 62] +1143758: read 0x1000cc40 [Channel: 2 Bank: 1 Row:3 Column: 68] +1143791: read 0x1000cca0 [Channel: 2 Bank: 1 Row:3 Column: 74] +1143980: read 0x1000cd00 [Channel: 2 Bank: 1 Row:3 Column: 80] +1144113: read 0x1000cc00 [Channel: 2 Bank: 1 Row:3 Column: 64] +1144125: read 0x1000cd40 [Channel: 2 Bank: 1 Row:3 Column: 84] +1144146: read 0x1000cd60 [Channel: 2 Bank: 1 Row:3 Column: 86] +1144179: read 0x1000cda0 [Channel: 2 Bank: 1 Row:3 Column: 90] +1144264: read 0x1000ce00 [Channel: 2 Bank: 1 Row:3 Column: 96] +1194011: read 0x1000cdc0 [Channel: 2 Bank: 1 Row:3 Column: 92] +1194062: read 0x1000a120 [Channel: 2 Bank: 4 Row:2 Column: 18] +1194221: read 0x1000a180 [Channel: 2 Bank: 4 Row:2 Column: 24] +1194365: read 0x1000a340 [Channel: 2 Bank: 4 Row:2 Column: 52] +1194524: read 0x1000a1e0 [Channel: 2 Bank: 4 Row:2 Column: 30] +1194815: read 0x1000a3a0 [Channel: 2 Bank: 4 Row:2 Column: 58] +1194974: read 0x1000b5e0 [Channel: 2 Bank: 6 Row:2 Column: 94] +1195025: read 0x1000b7a0 [Channel: 2 Bank: 6 Row:2 Column: 122] +1195118: read 0x1000b800 [Channel: 2 Bank: 7 Row:2 Column: 0] +1195169: read 0x1000b640 [Channel: 2 Bank: 6 Row:2 Column: 100] +1195328: read 0x1000b6a0 [Channel: 2 Bank: 6 Row:2 Column: 106] +1195619: read 0x1000b860 [Channel: 2 Bank: 7 Row:2 Column: 6] +1195778: read 0x1000caa0 [Channel: 2 Bank: 1 Row:3 Column: 42] +1195922: read 0x1000cc60 [Channel: 2 Bank: 1 Row:3 Column: 70] +1196081: read 0x1000cb00 [Channel: 2 Bank: 1 Row:3 Column: 48] +1196132: read 0x1000ccc0 [Channel: 2 Bank: 1 Row:3 Column: 76] +1196226: read 0x1000cd20 [Channel: 2 Bank: 1 Row:3 Column: 82] +1249229: read 0x1000ce20 [Channel: 2 Bank: 1 Row:3 Column: 98] +1249532: read 0x1000a240 [Channel: 2 Bank: 4 Row:2 Column: 36] +1249583: read 0x1000a2a0 [Channel: 2 Bank: 4 Row:2 Column: 42] +1249677: read 0x1000a300 [Channel: 2 Bank: 4 Row:2 Column: 48] +1249728: read 0x1000a400 [Channel: 2 Bank: 4 Row:2 Column: 64] +1249868: read 0x1000a460 [Channel: 2 Bank: 4 Row:2 Column: 70] +1250033: read 0x1000a4c0 [Channel: 2 Bank: 4 Row:2 Column: 76] +1250336: read 0x1000b700 [Channel: 2 Bank: 6 Row:2 Column: 112] +1250481: read 0x1000b760 [Channel: 2 Bank: 6 Row:2 Column: 118] +1250620: read 0x1000b8c0 [Channel: 2 Bank: 7 Row:2 Column: 12] +1250672: read 0x1000b920 [Channel: 2 Bank: 7 Row:2 Column: 18] +1250786: read 0x1000b980 [Channel: 2 Bank: 7 Row:2 Column: 24] +1250837: read 0x1000cb60 [Channel: 2 Bank: 1 Row:3 Column: 54] +1251140: read 0x1000cbc0 [Channel: 2 Bank: 1 Row:3 Column: 60] +1251285: read 0x1000cc20 [Channel: 2 Bank: 1 Row:3 Column: 66] +1251424: read 0x1000cd80 [Channel: 2 Bank: 1 Row:3 Column: 88] +1302772: read 0x1000cde0 [Channel: 2 Bank: 1 Row:3 Column: 94] +1302823: read 0x1000a140 [Channel: 2 Bank: 4 Row:2 Column: 20] +1302982: read 0x1000a1a0 [Channel: 2 Bank: 4 Row:2 Column: 26] +1303285: read 0x1000a360 [Channel: 2 Bank: 4 Row:2 Column: 54] +1303576: read 0x1000a3c0 [Channel: 2 Bank: 4 Row:2 Column: 60] +1303735: read 0x1000b600 [Channel: 2 Bank: 6 Row:2 Column: 96] +1303786: read 0x1000b7c0 [Channel: 2 Bank: 6 Row:2 Column: 124] +1303879: read 0x1000b820 [Channel: 2 Bank: 7 Row:2 Column: 2] +1304380: read 0x1000b660 [Channel: 2 Bank: 6 Row:2 Column: 102] +1304539: read 0x1000cac0 [Channel: 2 Bank: 1 Row:3 Column: 44] +1304683: read 0x1000cc80 [Channel: 2 Bank: 1 Row:3 Column: 72] +1304842: read 0x1000cb20 [Channel: 2 Bank: 1 Row:3 Column: 50] +1304987: read 0x1000cce0 [Channel: 2 Bank: 1 Row:3 Column: 78] +1401669: read 0x1000ce40 [Channel: 2 Bank: 1 Row:3 Column: 100] +1401694: read 0x404080 [Channel: 0 Bank: 0 Row:257 Column: 8] +1401724: read 0x4040a0 [Channel: 0 Bank: 0 Row:257 Column: 10] +1401749: read 0x4053a0 [Channel: 0 Bank: 2 Row:257 Column: 58] +1401774: read 0x4053c0 [Channel: 0 Bank: 2 Row:257 Column: 60] +1401799: read 0x4053e0 [Channel: 0 Bank: 2 Row:257 Column: 62] +1401823: read 0x405400 [Channel: 0 Bank: 2 Row:257 Column: 64] +1401870: read 0x405420 [Channel: 0 Bank: 2 Row:257 Column: 66] +1401970: read 0x10001460 [Channel: 2 Bank: 2 Row:0 Column: 70] +1402070: read 0x10001480 [Channel: 2 Bank: 2 Row:0 Column: 72] +1402170: read 0x100014a0 [Channel: 2 Bank: 2 Row:0 Column: 74] +1402270: read 0x100014c0 [Channel: 2 Bank: 2 Row:0 Column: 76] +1402370: read 0x100014e0 [Channel: 2 Bank: 2 Row:0 Column: 78] +1402470: read 0x10001500 [Channel: 2 Bank: 2 Row:0 Column: 80] +1402570: read 0x10001520 [Channel: 2 Bank: 2 Row:0 Column: 82] +1402670: read 0x10001540 [Channel: 2 Bank: 2 Row:0 Column: 84] +1402770: read 0x10001560 [Channel: 2 Bank: 2 Row:0 Column: 86] +1402870: read 0x10001580 [Channel: 2 Bank: 2 Row:0 Column: 88] +1402970: read 0x100015a0 [Channel: 2 Bank: 2 Row:0 Column: 90] +1403070: read 0x100015c0 [Channel: 2 Bank: 2 Row:0 Column: 92] +1403170: read 0x100015e0 [Channel: 2 Bank: 2 Row:0 Column: 94] +1403270: read 0x10001600 [Channel: 2 Bank: 2 Row:0 Column: 96] +1403370: read 0x10001620 [Channel: 2 Bank: 2 Row:0 Column: 98] +1403470: read 0x10001640 [Channel: 2 Bank: 2 Row:0 Column: 100] +1403570: read 0x10001660 [Channel: 2 Bank: 2 Row:0 Column: 102] +1403670: read 0x10001680 [Channel: 2 Bank: 2 Row:0 Column: 104] +1403770: read 0x100016a0 [Channel: 2 Bank: 2 Row:0 Column: 106] +1403870: read 0x100016c0 [Channel: 2 Bank: 2 Row:0 Column: 108] +1403970: read 0x100016e0 [Channel: 2 Bank: 2 Row:0 Column: 110] +1404070: read 0x10001700 [Channel: 2 Bank: 2 Row:0 Column: 112] +1404170: read 0x10001720 [Channel: 2 Bank: 2 Row:0 Column: 114] +1404270: read 0x10001740 [Channel: 2 Bank: 2 Row:0 Column: 116] +1404370: read 0x10001760 [Channel: 2 Bank: 2 Row:0 Column: 118] +1404470: read 0x10001780 [Channel: 2 Bank: 2 Row:0 Column: 120] +1404570: read 0x100017a0 [Channel: 2 Bank: 2 Row:0 Column: 122] +1404670: read 0x100017c0 [Channel: 2 Bank: 2 Row:0 Column: 124] +1404770: read 0x100017e0 [Channel: 2 Bank: 2 Row:0 Column: 126] +1404870: read 0x10001800 [Channel: 2 Bank: 3 Row:0 Column: 0] +1404970: read 0x10001820 [Channel: 2 Bank: 3 Row:0 Column: 2] +1405070: read 0x10001840 [Channel: 2 Bank: 3 Row:0 Column: 4] +1405170: read 0x10001860 [Channel: 2 Bank: 3 Row:0 Column: 6] +1405270: read 0x10001880 [Channel: 2 Bank: 3 Row:0 Column: 8] +1405370: read 0x100018a0 [Channel: 2 Bank: 3 Row:0 Column: 10] +1405470: read 0x100018c0 [Channel: 2 Bank: 3 Row:0 Column: 12] +1405570: read 0x100018e0 [Channel: 2 Bank: 3 Row:0 Column: 14] +1405670: read 0x10001900 [Channel: 2 Bank: 3 Row:0 Column: 16] +1405770: read 0x10001920 [Channel: 2 Bank: 3 Row:0 Column: 18] +1405870: read 0x10001940 [Channel: 2 Bank: 3 Row:0 Column: 20] +1405970: read 0x10001960 [Channel: 2 Bank: 3 Row:0 Column: 22] +1406070: read 0x10001980 [Channel: 2 Bank: 3 Row:0 Column: 24] +1406170: read 0x100019a0 [Channel: 2 Bank: 3 Row:0 Column: 26] +1406270: read 0x100019c0 [Channel: 2 Bank: 3 Row:0 Column: 28] +1406370: read 0x100019e0 [Channel: 2 Bank: 3 Row:0 Column: 30] +1406470: read 0x10001a00 [Channel: 2 Bank: 3 Row:0 Column: 32] +1406570: read 0x10001a20 [Channel: 2 Bank: 3 Row:0 Column: 34] +1406670: read 0x10001a40 [Channel: 2 Bank: 3 Row:0 Column: 36] +1406770: read 0x10001a60 [Channel: 2 Bank: 3 Row:0 Column: 38] +1406870: read 0x10001a80 [Channel: 2 Bank: 3 Row:0 Column: 40] +1406970: read 0x10001aa0 [Channel: 2 Bank: 3 Row:0 Column: 42] +1407070: read 0x10001ac0 [Channel: 2 Bank: 3 Row:0 Column: 44] +1407170: read 0x10001ae0 [Channel: 2 Bank: 3 Row:0 Column: 46] +1407270: read 0x10001b00 [Channel: 2 Bank: 3 Row:0 Column: 48] +1407370: read 0x10001b20 [Channel: 2 Bank: 3 Row:0 Column: 50] +1407470: read 0x10001b40 [Channel: 2 Bank: 3 Row:0 Column: 52] +1407570: read 0x10001b60 [Channel: 2 Bank: 3 Row:0 Column: 54] +1407670: read 0x10001b80 [Channel: 2 Bank: 3 Row:0 Column: 56] +1407770: read 0x10001ba0 [Channel: 2 Bank: 3 Row:0 Column: 58] +1407870: read 0x10001bc0 [Channel: 2 Bank: 3 Row:0 Column: 60] +1407970: read 0x10001be0 [Channel: 2 Bank: 3 Row:0 Column: 62] +1408070: read 0x10001c00 [Channel: 2 Bank: 3 Row:0 Column: 64] +1408170: read 0x10001c20 [Channel: 2 Bank: 3 Row:0 Column: 66] +1408270: read 0x10001c40 [Channel: 2 Bank: 3 Row:0 Column: 68] +1408370: read 0x10001c60 [Channel: 2 Bank: 3 Row:0 Column: 70] +1408470: read 0x10001c80 [Channel: 2 Bank: 3 Row:0 Column: 72] +1408570: read 0x10001ca0 [Channel: 2 Bank: 3 Row:0 Column: 74] +1408670: read 0x10001cc0 [Channel: 2 Bank: 3 Row:0 Column: 76] +1408770: read 0x10001ce0 [Channel: 2 Bank: 3 Row:0 Column: 78] +1408870: read 0x10001d00 [Channel: 2 Bank: 3 Row:0 Column: 80] +1408970: read 0x10001d20 [Channel: 2 Bank: 3 Row:0 Column: 82] +1409070: read 0x10001d40 [Channel: 2 Bank: 3 Row:0 Column: 84] +1409170: read 0x10001d60 [Channel: 2 Bank: 3 Row:0 Column: 86] +1409270: read 0x10001d80 [Channel: 2 Bank: 3 Row:0 Column: 88] +1409370: read 0x10001da0 [Channel: 2 Bank: 3 Row:0 Column: 90] +1409470: read 0x10001dc0 [Channel: 2 Bank: 3 Row:0 Column: 92] +1409570: read 0x10001de0 [Channel: 2 Bank: 3 Row:0 Column: 94] +1409670: read 0x10001e00 [Channel: 2 Bank: 3 Row:0 Column: 96] +1409770: read 0x10001e20 [Channel: 2 Bank: 3 Row:0 Column: 98] +1409870: read 0x10001e40 [Channel: 2 Bank: 3 Row:0 Column: 100] +1409970: read 0x10001e60 [Channel: 2 Bank: 3 Row:0 Column: 102] +1410070: read 0x10001e80 [Channel: 2 Bank: 3 Row:0 Column: 104] +1410170: read 0x10001ea0 [Channel: 2 Bank: 3 Row:0 Column: 106] +1410270: read 0x10001ec0 [Channel: 2 Bank: 3 Row:0 Column: 108] +1410370: read 0x10001ee0 [Channel: 2 Bank: 3 Row:0 Column: 110] +1410470: read 0x10001f00 [Channel: 2 Bank: 3 Row:0 Column: 112] +1410570: read 0x10001f20 [Channel: 2 Bank: 3 Row:0 Column: 114] +1410670: read 0x10001f40 [Channel: 2 Bank: 3 Row:0 Column: 116] +1410770: read 0x10001f60 [Channel: 2 Bank: 3 Row:0 Column: 118] +1410870: read 0x10001f80 [Channel: 2 Bank: 3 Row:0 Column: 120] +1410970: read 0x10001fa0 [Channel: 2 Bank: 3 Row:0 Column: 122] +1411070: read 0x10001fc0 [Channel: 2 Bank: 3 Row:0 Column: 124] +1411170: read 0x10001fe0 [Channel: 2 Bank: 3 Row:0 Column: 126] +1411276: read 0x10002000 [Channel: 2 Bank: 4 Row:0 Column: 0] +1411376: read 0x10002020 [Channel: 2 Bank: 4 Row:0 Column: 2] +1411476: read 0x10002040 [Channel: 2 Bank: 4 Row:0 Column: 4] +1411576: read 0x10002060 [Channel: 2 Bank: 4 Row:0 Column: 6] +1411676: read 0x10002080 [Channel: 2 Bank: 4 Row:0 Column: 8] +1411776: read 0x100020a0 [Channel: 2 Bank: 4 Row:0 Column: 10] +1411876: read 0x100020c0 [Channel: 2 Bank: 4 Row:0 Column: 12] +1411976: read 0x100020e0 [Channel: 2 Bank: 4 Row:0 Column: 14] +1412076: read 0x10002100 [Channel: 2 Bank: 4 Row:0 Column: 16] +1412176: read 0x10002120 [Channel: 2 Bank: 4 Row:0 Column: 18] +1412276: read 0x10002140 [Channel: 2 Bank: 4 Row:0 Column: 20] +1412376: read 0x10002160 [Channel: 2 Bank: 4 Row:0 Column: 22] +1412476: read 0x10002180 [Channel: 2 Bank: 4 Row:0 Column: 24] +1412576: read 0x100021a0 [Channel: 2 Bank: 4 Row:0 Column: 26] +1412676: read 0x100021c0 [Channel: 2 Bank: 4 Row:0 Column: 28] +1412776: read 0x100021e0 [Channel: 2 Bank: 4 Row:0 Column: 30] +1412876: read 0x10002200 [Channel: 2 Bank: 4 Row:0 Column: 32] +1412976: read 0x10002220 [Channel: 2 Bank: 4 Row:0 Column: 34] +1413076: read 0x10002240 [Channel: 2 Bank: 4 Row:0 Column: 36] +1413176: read 0x10002260 [Channel: 2 Bank: 4 Row:0 Column: 38] +1413276: read 0x10002280 [Channel: 2 Bank: 4 Row:0 Column: 40] +1413376: read 0x100022a0 [Channel: 2 Bank: 4 Row:0 Column: 42] +1413476: read 0x100022c0 [Channel: 2 Bank: 4 Row:0 Column: 44] +1413576: read 0x100022e0 [Channel: 2 Bank: 4 Row:0 Column: 46] +1413676: read 0x10002300 [Channel: 2 Bank: 4 Row:0 Column: 48] +1413776: read 0x10002320 [Channel: 2 Bank: 4 Row:0 Column: 50] +1413876: read 0x10002340 [Channel: 2 Bank: 4 Row:0 Column: 52] +1413976: read 0x10002360 [Channel: 2 Bank: 4 Row:0 Column: 54] +1414076: read 0x10002380 [Channel: 2 Bank: 4 Row:0 Column: 56] +1414176: read 0x100023a0 [Channel: 2 Bank: 4 Row:0 Column: 58] +1414276: read 0x100023c0 [Channel: 2 Bank: 4 Row:0 Column: 60] +1414372: read 0x100023e0 [Channel: 2 Bank: 4 Row:0 Column: 62] +1414468: read 0x10002400 [Channel: 2 Bank: 4 Row:0 Column: 64] +1414568: read 0x10002420 [Channel: 2 Bank: 4 Row:0 Column: 66] +1414668: read 0x10002440 [Channel: 2 Bank: 4 Row:0 Column: 68] +1414768: read 0x10002460 [Channel: 2 Bank: 4 Row:0 Column: 70] +1414868: read 0x10002480 [Channel: 2 Bank: 4 Row:0 Column: 72] +1414968: read 0x100024a0 [Channel: 2 Bank: 4 Row:0 Column: 74] +1415068: read 0x100024c0 [Channel: 2 Bank: 4 Row:0 Column: 76] +1415168: read 0x100024e0 [Channel: 2 Bank: 4 Row:0 Column: 78] +1415268: read 0x10002500 [Channel: 2 Bank: 4 Row:0 Column: 80] +1415368: read 0x10002520 [Channel: 2 Bank: 4 Row:0 Column: 82] +1415468: read 0x10002540 [Channel: 2 Bank: 4 Row:0 Column: 84] +1415568: read 0x10002560 [Channel: 2 Bank: 4 Row:0 Column: 86] +1415664: read 0x10002580 [Channel: 2 Bank: 4 Row:0 Column: 88] +1415764: read 0x100025a0 [Channel: 2 Bank: 4 Row:0 Column: 90] +1415860: read 0x100025c0 [Channel: 2 Bank: 4 Row:0 Column: 92] +1415956: read 0x100025e0 [Channel: 2 Bank: 4 Row:0 Column: 94] +1416056: read 0x10002600 [Channel: 2 Bank: 4 Row:0 Column: 96] +1416152: read 0x10002620 [Channel: 2 Bank: 4 Row:0 Column: 98] +1416252: read 0x10002640 [Channel: 2 Bank: 4 Row:0 Column: 100] +1416348: read 0x10002660 [Channel: 2 Bank: 4 Row:0 Column: 102] +1416444: read 0x10002680 [Channel: 2 Bank: 4 Row:0 Column: 104] +1416544: read 0x100026a0 [Channel: 2 Bank: 4 Row:0 Column: 106] +1416640: read 0x100026c0 [Channel: 2 Bank: 4 Row:0 Column: 108] +1416736: read 0x100026e0 [Channel: 2 Bank: 4 Row:0 Column: 110] +1416832: read 0x10002700 [Channel: 2 Bank: 4 Row:0 Column: 112] +1416928: read 0x10002720 [Channel: 2 Bank: 4 Row:0 Column: 114] +1417024: read 0x10002740 [Channel: 2 Bank: 4 Row:0 Column: 116] +1417120: read 0x10002760 [Channel: 2 Bank: 4 Row:0 Column: 118] +1417216: read 0x10002780 [Channel: 2 Bank: 4 Row:0 Column: 120] +1417312: read 0x100027a0 [Channel: 2 Bank: 4 Row:0 Column: 122] +1417408: read 0x100027c0 [Channel: 2 Bank: 4 Row:0 Column: 124] +1417504: read 0x100027e0 [Channel: 2 Bank: 4 Row:0 Column: 126] +1417600: read 0x10002800 [Channel: 2 Bank: 5 Row:0 Column: 0] +1417696: read 0x10002820 [Channel: 2 Bank: 5 Row:0 Column: 2] +1417792: read 0x10002840 [Channel: 2 Bank: 5 Row:0 Column: 4] +1417888: read 0x10002860 [Channel: 2 Bank: 5 Row:0 Column: 6] +1417984: read 0x10002880 [Channel: 2 Bank: 5 Row:0 Column: 8] +1418080: read 0x100028a0 [Channel: 2 Bank: 5 Row:0 Column: 10] +1418176: read 0x100028c0 [Channel: 2 Bank: 5 Row:0 Column: 12] +1418272: read 0x100028e0 [Channel: 2 Bank: 5 Row:0 Column: 14] +1418349: read 0x10002900 [Channel: 2 Bank: 5 Row:0 Column: 16] +1418374: read 0x405440 [Channel: 0 Bank: 2 Row:257 Column: 68] +1418408: read 0x405460 [Channel: 0 Bank: 2 Row:257 Column: 70] +1418508: read 0x10002920 [Channel: 2 Bank: 5 Row:0 Column: 18] +1418608: read 0x10002940 [Channel: 2 Bank: 5 Row:0 Column: 20] +1418708: read 0x10002960 [Channel: 2 Bank: 5 Row:0 Column: 22] +1418808: read 0x10002980 [Channel: 2 Bank: 5 Row:0 Column: 24] +1418908: read 0x100029a0 [Channel: 2 Bank: 5 Row:0 Column: 26] +1419008: read 0x100029c0 [Channel: 2 Bank: 5 Row:0 Column: 28] +1419108: read 0x100029e0 [Channel: 2 Bank: 5 Row:0 Column: 30] +1419208: read 0x10002a00 [Channel: 2 Bank: 5 Row:0 Column: 32] +1419308: read 0x10002a20 [Channel: 2 Bank: 5 Row:0 Column: 34] +1419408: read 0x10002a40 [Channel: 2 Bank: 5 Row:0 Column: 36] +1419508: read 0x10002a60 [Channel: 2 Bank: 5 Row:0 Column: 38] +1419608: read 0x10002a80 [Channel: 2 Bank: 5 Row:0 Column: 40] +1419708: read 0x10002aa0 [Channel: 2 Bank: 5 Row:0 Column: 42] +1419808: read 0x10002ac0 [Channel: 2 Bank: 5 Row:0 Column: 44] +1419908: read 0x10002ae0 [Channel: 2 Bank: 5 Row:0 Column: 46] +1420008: read 0x10002b00 [Channel: 2 Bank: 5 Row:0 Column: 48] +1420108: read 0x10002b20 [Channel: 2 Bank: 5 Row:0 Column: 50] +1420208: read 0x10002b40 [Channel: 2 Bank: 5 Row:0 Column: 52] +1420308: read 0x10002b60 [Channel: 2 Bank: 5 Row:0 Column: 54] +1420408: read 0x10002b80 [Channel: 2 Bank: 5 Row:0 Column: 56] +1420508: read 0x10002ba0 [Channel: 2 Bank: 5 Row:0 Column: 58] +1420608: read 0x10002bc0 [Channel: 2 Bank: 5 Row:0 Column: 60] +1420708: read 0x10002be0 [Channel: 2 Bank: 5 Row:0 Column: 62] +1420808: read 0x10002c00 [Channel: 2 Bank: 5 Row:0 Column: 64] +1420908: read 0x10002c20 [Channel: 2 Bank: 5 Row:0 Column: 66] +1421008: read 0x10002c40 [Channel: 2 Bank: 5 Row:0 Column: 68] +1421108: read 0x10002c60 [Channel: 2 Bank: 5 Row:0 Column: 70] +1421208: read 0x10002c80 [Channel: 2 Bank: 5 Row:0 Column: 72] +1421308: read 0x10002ca0 [Channel: 2 Bank: 5 Row:0 Column: 74] +1421408: read 0x10002cc0 [Channel: 2 Bank: 5 Row:0 Column: 76] +1421508: read 0x10002ce0 [Channel: 2 Bank: 5 Row:0 Column: 78] +1421608: read 0x10002d00 [Channel: 2 Bank: 5 Row:0 Column: 80] +1421708: read 0x10002d20 [Channel: 2 Bank: 5 Row:0 Column: 82] +1421808: read 0x10002d40 [Channel: 2 Bank: 5 Row:0 Column: 84] +1421908: read 0x10002d60 [Channel: 2 Bank: 5 Row:0 Column: 86] +1422008: read 0x10002d80 [Channel: 2 Bank: 5 Row:0 Column: 88] +1422108: read 0x10002da0 [Channel: 2 Bank: 5 Row:0 Column: 90] +1422208: read 0x10002dc0 [Channel: 2 Bank: 5 Row:0 Column: 92] +1422308: read 0x10002de0 [Channel: 2 Bank: 5 Row:0 Column: 94] +1422408: read 0x10002e00 [Channel: 2 Bank: 5 Row:0 Column: 96] +1422508: read 0x10002e20 [Channel: 2 Bank: 5 Row:0 Column: 98] +1422608: read 0x10002e40 [Channel: 2 Bank: 5 Row:0 Column: 100] +1422708: read 0x10002e60 [Channel: 2 Bank: 5 Row:0 Column: 102] +1422808: read 0x10002e80 [Channel: 2 Bank: 5 Row:0 Column: 104] +1422908: read 0x10002ea0 [Channel: 2 Bank: 5 Row:0 Column: 106] +1423008: read 0x10002ec0 [Channel: 2 Bank: 5 Row:0 Column: 108] +1423108: read 0x10002ee0 [Channel: 2 Bank: 5 Row:0 Column: 110] +1423208: read 0x10002f00 [Channel: 2 Bank: 5 Row:0 Column: 112] +1423308: read 0x10002f20 [Channel: 2 Bank: 5 Row:0 Column: 114] +1423408: read 0x10002f40 [Channel: 2 Bank: 5 Row:0 Column: 116] +1423508: read 0x10002f60 [Channel: 2 Bank: 5 Row:0 Column: 118] +1423608: read 0x10002f80 [Channel: 2 Bank: 5 Row:0 Column: 120] +1423708: read 0x10002fa0 [Channel: 2 Bank: 5 Row:0 Column: 122] +1423808: read 0x10002fc0 [Channel: 2 Bank: 5 Row:0 Column: 124] +1423908: read 0x10002fe0 [Channel: 2 Bank: 5 Row:0 Column: 126] +1424014: read 0x10003000 [Channel: 2 Bank: 6 Row:0 Column: 0] +1424114: read 0x10003020 [Channel: 2 Bank: 6 Row:0 Column: 2] +1424214: read 0x10003040 [Channel: 2 Bank: 6 Row:0 Column: 4] +1424314: read 0x10003060 [Channel: 2 Bank: 6 Row:0 Column: 6] +1424414: read 0x10003080 [Channel: 2 Bank: 6 Row:0 Column: 8] +1424514: read 0x100030a0 [Channel: 2 Bank: 6 Row:0 Column: 10] +1424614: read 0x100030c0 [Channel: 2 Bank: 6 Row:0 Column: 12] +1424714: read 0x100030e0 [Channel: 2 Bank: 6 Row:0 Column: 14] +1424814: read 0x10003100 [Channel: 2 Bank: 6 Row:0 Column: 16] +1424914: read 0x10003120 [Channel: 2 Bank: 6 Row:0 Column: 18] +1425014: read 0x10003140 [Channel: 2 Bank: 6 Row:0 Column: 20] +1425114: read 0x10003160 [Channel: 2 Bank: 6 Row:0 Column: 22] +1425214: read 0x10003180 [Channel: 2 Bank: 6 Row:0 Column: 24] +1425314: read 0x100031a0 [Channel: 2 Bank: 6 Row:0 Column: 26] +1425414: read 0x100031c0 [Channel: 2 Bank: 6 Row:0 Column: 28] +1425514: read 0x100031e0 [Channel: 2 Bank: 6 Row:0 Column: 30] +1425614: read 0x10003200 [Channel: 2 Bank: 6 Row:0 Column: 32] +1425714: read 0x10003220 [Channel: 2 Bank: 6 Row:0 Column: 34] +1425814: read 0x10003240 [Channel: 2 Bank: 6 Row:0 Column: 36] +1425914: read 0x10003260 [Channel: 2 Bank: 6 Row:0 Column: 38] +1426014: read 0x10003280 [Channel: 2 Bank: 6 Row:0 Column: 40] +1426114: read 0x100032a0 [Channel: 2 Bank: 6 Row:0 Column: 42] +1426214: read 0x100032c0 [Channel: 2 Bank: 6 Row:0 Column: 44] +1426314: read 0x100032e0 [Channel: 2 Bank: 6 Row:0 Column: 46] +1426414: read 0x10003300 [Channel: 2 Bank: 6 Row:0 Column: 48] +1426514: read 0x10003320 [Channel: 2 Bank: 6 Row:0 Column: 50] +1426614: read 0x10003340 [Channel: 2 Bank: 6 Row:0 Column: 52] +1426714: read 0x10003360 [Channel: 2 Bank: 6 Row:0 Column: 54] +1426814: read 0x10003380 [Channel: 2 Bank: 6 Row:0 Column: 56] +1426914: read 0x100033a0 [Channel: 2 Bank: 6 Row:0 Column: 58] +1427014: read 0x100033c0 [Channel: 2 Bank: 6 Row:0 Column: 60] +1427114: read 0x100033e0 [Channel: 2 Bank: 6 Row:0 Column: 62] +1427214: read 0x10003400 [Channel: 2 Bank: 6 Row:0 Column: 64] +1427314: read 0x10003420 [Channel: 2 Bank: 6 Row:0 Column: 66] +1427414: read 0x10003440 [Channel: 2 Bank: 6 Row:0 Column: 68] +1427514: read 0x10003460 [Channel: 2 Bank: 6 Row:0 Column: 70] +1427614: read 0x10003480 [Channel: 2 Bank: 6 Row:0 Column: 72] +1427714: read 0x100034a0 [Channel: 2 Bank: 6 Row:0 Column: 74] +1427814: read 0x100034c0 [Channel: 2 Bank: 6 Row:0 Column: 76] +1427914: read 0x100034e0 [Channel: 2 Bank: 6 Row:0 Column: 78] +1428014: read 0x10003500 [Channel: 2 Bank: 6 Row:0 Column: 80] +1428114: read 0x10003520 [Channel: 2 Bank: 6 Row:0 Column: 82] +1428214: read 0x10003540 [Channel: 2 Bank: 6 Row:0 Column: 84] +1428314: read 0x10003560 [Channel: 2 Bank: 6 Row:0 Column: 86] +1428414: read 0x10003580 [Channel: 2 Bank: 6 Row:0 Column: 88] +1428514: read 0x100035a0 [Channel: 2 Bank: 6 Row:0 Column: 90] +1428614: read 0x100035c0 [Channel: 2 Bank: 6 Row:0 Column: 92] +1428714: read 0x100035e0 [Channel: 2 Bank: 6 Row:0 Column: 94] +1428814: read 0x10003600 [Channel: 2 Bank: 6 Row:0 Column: 96] +1428914: read 0x10003620 [Channel: 2 Bank: 6 Row:0 Column: 98] +1429014: read 0x10003640 [Channel: 2 Bank: 6 Row:0 Column: 100] +1429114: read 0x10003660 [Channel: 2 Bank: 6 Row:0 Column: 102] +1429214: read 0x10003680 [Channel: 2 Bank: 6 Row:0 Column: 104] +1429314: read 0x100036a0 [Channel: 2 Bank: 6 Row:0 Column: 106] +1429414: read 0x100036c0 [Channel: 2 Bank: 6 Row:0 Column: 108] +1429514: read 0x100036e0 [Channel: 2 Bank: 6 Row:0 Column: 110] +1429614: read 0x10003700 [Channel: 2 Bank: 6 Row:0 Column: 112] +1429714: read 0x10003720 [Channel: 2 Bank: 6 Row:0 Column: 114] +1429814: read 0x10003740 [Channel: 2 Bank: 6 Row:0 Column: 116] +1429914: read 0x10003760 [Channel: 2 Bank: 6 Row:0 Column: 118] +1430014: read 0x10003780 [Channel: 2 Bank: 6 Row:0 Column: 120] +1430114: read 0x100037a0 [Channel: 2 Bank: 6 Row:0 Column: 122] +1430214: read 0x100037c0 [Channel: 2 Bank: 6 Row:0 Column: 124] +1430314: read 0x100037e0 [Channel: 2 Bank: 6 Row:0 Column: 126] +1430414: read 0x10003800 [Channel: 2 Bank: 7 Row:0 Column: 0] +1430514: read 0x10003820 [Channel: 2 Bank: 7 Row:0 Column: 2] +1430614: read 0x10003840 [Channel: 2 Bank: 7 Row:0 Column: 4] +1430714: read 0x10003860 [Channel: 2 Bank: 7 Row:0 Column: 6] +1430814: read 0x10003880 [Channel: 2 Bank: 7 Row:0 Column: 8] +1430914: read 0x100038a0 [Channel: 2 Bank: 7 Row:0 Column: 10] +1431014: read 0x100038c0 [Channel: 2 Bank: 7 Row:0 Column: 12] +1431114: read 0x100038e0 [Channel: 2 Bank: 7 Row:0 Column: 14] +1431214: read 0x10003900 [Channel: 2 Bank: 7 Row:0 Column: 16] +1431314: read 0x10003920 [Channel: 2 Bank: 7 Row:0 Column: 18] +1431414: read 0x10003940 [Channel: 2 Bank: 7 Row:0 Column: 20] +1431514: read 0x10003960 [Channel: 2 Bank: 7 Row:0 Column: 22] +1431614: read 0x10003980 [Channel: 2 Bank: 7 Row:0 Column: 24] +1431714: read 0x100039a0 [Channel: 2 Bank: 7 Row:0 Column: 26] +1431814: read 0x100039c0 [Channel: 2 Bank: 7 Row:0 Column: 28] +1431914: read 0x100039e0 [Channel: 2 Bank: 7 Row:0 Column: 30] +1432014: read 0x10003a00 [Channel: 2 Bank: 7 Row:0 Column: 32] +1432114: read 0x10003a20 [Channel: 2 Bank: 7 Row:0 Column: 34] +1432214: read 0x10003a40 [Channel: 2 Bank: 7 Row:0 Column: 36] +1432314: read 0x10003a60 [Channel: 2 Bank: 7 Row:0 Column: 38] +1432414: read 0x10003a80 [Channel: 2 Bank: 7 Row:0 Column: 40] +1432514: read 0x10003aa0 [Channel: 2 Bank: 7 Row:0 Column: 42] +1432614: read 0x10003ac0 [Channel: 2 Bank: 7 Row:0 Column: 44] +1432714: read 0x10003ae0 [Channel: 2 Bank: 7 Row:0 Column: 46] +1432814: read 0x10003b00 [Channel: 2 Bank: 7 Row:0 Column: 48] +1432914: read 0x10003b20 [Channel: 2 Bank: 7 Row:0 Column: 50] +1433014: read 0x10003b40 [Channel: 2 Bank: 7 Row:0 Column: 52] +1433114: read 0x10003b60 [Channel: 2 Bank: 7 Row:0 Column: 54] +1433214: read 0x10003b80 [Channel: 2 Bank: 7 Row:0 Column: 56] +1433314: read 0x10003ba0 [Channel: 2 Bank: 7 Row:0 Column: 58] +1433414: read 0x10003bc0 [Channel: 2 Bank: 7 Row:0 Column: 60] +1433514: read 0x10003be0 [Channel: 2 Bank: 7 Row:0 Column: 62] +1433614: read 0x10003c00 [Channel: 2 Bank: 7 Row:0 Column: 64] +1433714: read 0x10003c20 [Channel: 2 Bank: 7 Row:0 Column: 66] +1433814: read 0x10003c40 [Channel: 2 Bank: 7 Row:0 Column: 68] +1433914: read 0x10003c60 [Channel: 2 Bank: 7 Row:0 Column: 70] +1434014: read 0x10003c80 [Channel: 2 Bank: 7 Row:0 Column: 72] +1434114: read 0x10003ca0 [Channel: 2 Bank: 7 Row:0 Column: 74] +1434214: read 0x10003cc0 [Channel: 2 Bank: 7 Row:0 Column: 76] +1434314: read 0x10003ce0 [Channel: 2 Bank: 7 Row:0 Column: 78] +1434414: read 0x10003d00 [Channel: 2 Bank: 7 Row:0 Column: 80] +1434514: read 0x10003d20 [Channel: 2 Bank: 7 Row:0 Column: 82] +1434614: read 0x10003d40 [Channel: 2 Bank: 7 Row:0 Column: 84] +1434714: read 0x10003d60 [Channel: 2 Bank: 7 Row:0 Column: 86] +1434814: read 0x10003d80 [Channel: 2 Bank: 7 Row:0 Column: 88] +1434914: read 0x10003da0 [Channel: 2 Bank: 7 Row:0 Column: 90] +1435023: read 0x10003dc0 [Channel: 2 Bank: 7 Row:0 Column: 92] +1435123: read 0x10003de0 [Channel: 2 Bank: 7 Row:0 Column: 94] +1435223: read 0x10003e00 [Channel: 2 Bank: 7 Row:0 Column: 96] +1435323: read 0x10003e20 [Channel: 2 Bank: 7 Row:0 Column: 98] +1435423: read 0x10003e40 [Channel: 2 Bank: 7 Row:0 Column: 100] +1435523: read 0x10003e60 [Channel: 2 Bank: 7 Row:0 Column: 102] +1435623: read 0x10003e80 [Channel: 2 Bank: 7 Row:0 Column: 104] +1435723: read 0x10003ea0 [Channel: 2 Bank: 7 Row:0 Column: 106] +1435823: read 0x10003ec0 [Channel: 2 Bank: 7 Row:0 Column: 108] +1435923: read 0x10003ee0 [Channel: 2 Bank: 7 Row:0 Column: 110] +1436023: read 0x10003f00 [Channel: 2 Bank: 7 Row:0 Column: 112] +1436123: read 0x10003f20 [Channel: 2 Bank: 7 Row:0 Column: 114] +1436223: read 0x10003f40 [Channel: 2 Bank: 7 Row:0 Column: 116] +1436323: read 0x10003f60 [Channel: 2 Bank: 7 Row:0 Column: 118] +1436423: read 0x10003f80 [Channel: 2 Bank: 7 Row:0 Column: 120] +1436523: read 0x10003fa0 [Channel: 2 Bank: 7 Row:0 Column: 122] +1436623: read 0x10003fc0 [Channel: 2 Bank: 7 Row:0 Column: 124] +1436723: read 0x10003fe0 [Channel: 2 Bank: 7 Row:0 Column: 126] +1436829: read 0x10004000 [Channel: 2 Bank: 0 Row:1 Column: 0] +1436929: read 0x10004020 [Channel: 2 Bank: 0 Row:1 Column: 2] +1437029: read 0x10004040 [Channel: 2 Bank: 0 Row:1 Column: 4] +1437129: read 0x10004060 [Channel: 2 Bank: 0 Row:1 Column: 6] +1437229: read 0x10004080 [Channel: 2 Bank: 0 Row:1 Column: 8] +1437329: read 0x100040a0 [Channel: 2 Bank: 0 Row:1 Column: 10] +1437429: read 0x100040c0 [Channel: 2 Bank: 0 Row:1 Column: 12] +1437529: read 0x100040e0 [Channel: 2 Bank: 0 Row:1 Column: 14] +1437629: read 0x10004100 [Channel: 2 Bank: 0 Row:1 Column: 16] +1437729: read 0x10004120 [Channel: 2 Bank: 0 Row:1 Column: 18] +1437829: read 0x10004140 [Channel: 2 Bank: 0 Row:1 Column: 20] +1437929: read 0x10004160 [Channel: 2 Bank: 0 Row:1 Column: 22] +1438029: read 0x10004180 [Channel: 2 Bank: 0 Row:1 Column: 24] +1438129: read 0x100041a0 [Channel: 2 Bank: 0 Row:1 Column: 26] +1438229: read 0x100041c0 [Channel: 2 Bank: 0 Row:1 Column: 28] +1438329: read 0x100041e0 [Channel: 2 Bank: 0 Row:1 Column: 30] +1438429: read 0x10004200 [Channel: 2 Bank: 0 Row:1 Column: 32] +1438529: read 0x10004220 [Channel: 2 Bank: 0 Row:1 Column: 34] +1438629: read 0x10004240 [Channel: 2 Bank: 0 Row:1 Column: 36] +1438729: read 0x10004260 [Channel: 2 Bank: 0 Row:1 Column: 38] +1438829: read 0x10004280 [Channel: 2 Bank: 0 Row:1 Column: 40] +1438929: read 0x100042a0 [Channel: 2 Bank: 0 Row:1 Column: 42] +1439029: read 0x100042c0 [Channel: 2 Bank: 0 Row:1 Column: 44] +1439129: read 0x100042e0 [Channel: 2 Bank: 0 Row:1 Column: 46] +1439229: read 0x10004300 [Channel: 2 Bank: 0 Row:1 Column: 48] +1439329: read 0x10004320 [Channel: 2 Bank: 0 Row:1 Column: 50] +1439429: read 0x10004340 [Channel: 2 Bank: 0 Row:1 Column: 52] +1439529: read 0x10004360 [Channel: 2 Bank: 0 Row:1 Column: 54] +1439629: read 0x10004380 [Channel: 2 Bank: 0 Row:1 Column: 56] +1439729: read 0x100043a0 [Channel: 2 Bank: 0 Row:1 Column: 58] +1439829: read 0x100043c0 [Channel: 2 Bank: 0 Row:1 Column: 60] +1439929: read 0x100043e0 [Channel: 2 Bank: 0 Row:1 Column: 62] +1440029: read 0x10004400 [Channel: 2 Bank: 0 Row:1 Column: 64] +1440129: read 0x10004420 [Channel: 2 Bank: 0 Row:1 Column: 66] +1440229: read 0x10004440 [Channel: 2 Bank: 0 Row:1 Column: 68] +1440329: read 0x10004460 [Channel: 2 Bank: 0 Row:1 Column: 70] +1440429: read 0x10004480 [Channel: 2 Bank: 0 Row:1 Column: 72] +1440529: read 0x100044a0 [Channel: 2 Bank: 0 Row:1 Column: 74] +1440629: read 0x100044c0 [Channel: 2 Bank: 0 Row:1 Column: 76] +1440729: read 0x100044e0 [Channel: 2 Bank: 0 Row:1 Column: 78] +1440829: read 0x10004500 [Channel: 2 Bank: 0 Row:1 Column: 80] +1440929: read 0x10004520 [Channel: 2 Bank: 0 Row:1 Column: 82] +1441029: read 0x10004540 [Channel: 2 Bank: 0 Row:1 Column: 84] +1441129: read 0x10004560 [Channel: 2 Bank: 0 Row:1 Column: 86] +1441229: read 0x10004580 [Channel: 2 Bank: 0 Row:1 Column: 88] +1441329: read 0x100045a0 [Channel: 2 Bank: 0 Row:1 Column: 90] +1441429: read 0x100045c0 [Channel: 2 Bank: 0 Row:1 Column: 92] +1441529: read 0x100045e0 [Channel: 2 Bank: 0 Row:1 Column: 94] +1441629: read 0x10004600 [Channel: 2 Bank: 0 Row:1 Column: 96] +1441729: read 0x10004620 [Channel: 2 Bank: 0 Row:1 Column: 98] +1441829: read 0x10004640 [Channel: 2 Bank: 0 Row:1 Column: 100] +1441929: read 0x10004660 [Channel: 2 Bank: 0 Row:1 Column: 102] +1442029: read 0x10004680 [Channel: 2 Bank: 0 Row:1 Column: 104] +1442129: read 0x100046a0 [Channel: 2 Bank: 0 Row:1 Column: 106] +1442229: read 0x100046c0 [Channel: 2 Bank: 0 Row:1 Column: 108] +1442329: read 0x100046e0 [Channel: 2 Bank: 0 Row:1 Column: 110] +1442429: read 0x10004700 [Channel: 2 Bank: 0 Row:1 Column: 112] +1442529: read 0x10004720 [Channel: 2 Bank: 0 Row:1 Column: 114] +1442629: read 0x10004740 [Channel: 2 Bank: 0 Row:1 Column: 116] +1442729: read 0x10004760 [Channel: 2 Bank: 0 Row:1 Column: 118] +1442829: read 0x10004780 [Channel: 2 Bank: 0 Row:1 Column: 120] +1442929: read 0x100047a0 [Channel: 2 Bank: 0 Row:1 Column: 122] +1443029: read 0x100047c0 [Channel: 2 Bank: 0 Row:1 Column: 124] +1443129: read 0x100047e0 [Channel: 2 Bank: 0 Row:1 Column: 126] +1443229: read 0x10004800 [Channel: 2 Bank: 1 Row:1 Column: 0] +1443329: read 0x10004820 [Channel: 2 Bank: 1 Row:1 Column: 2] +1443429: read 0x10004840 [Channel: 2 Bank: 1 Row:1 Column: 4] +1443529: read 0x10004860 [Channel: 2 Bank: 1 Row:1 Column: 6] +1443629: read 0x10004880 [Channel: 2 Bank: 1 Row:1 Column: 8] +1443729: read 0x100048a0 [Channel: 2 Bank: 1 Row:1 Column: 10] +1443829: read 0x100048c0 [Channel: 2 Bank: 1 Row:1 Column: 12] +1443929: read 0x100048e0 [Channel: 2 Bank: 1 Row:1 Column: 14] +1444029: read 0x10004900 [Channel: 2 Bank: 1 Row:1 Column: 16] +1444129: read 0x10004920 [Channel: 2 Bank: 1 Row:1 Column: 18] +1444229: read 0x10004940 [Channel: 2 Bank: 1 Row:1 Column: 20] +1444329: read 0x10004960 [Channel: 2 Bank: 1 Row:1 Column: 22] +1444429: read 0x10004980 [Channel: 2 Bank: 1 Row:1 Column: 24] +1444529: read 0x100049a0 [Channel: 2 Bank: 1 Row:1 Column: 26] +1444629: read 0x100049c0 [Channel: 2 Bank: 1 Row:1 Column: 28] +1444729: read 0x100049e0 [Channel: 2 Bank: 1 Row:1 Column: 30] +1444829: read 0x10004a00 [Channel: 2 Bank: 1 Row:1 Column: 32] +1444929: read 0x10004a20 [Channel: 2 Bank: 1 Row:1 Column: 34] +1445029: read 0x10004a40 [Channel: 2 Bank: 1 Row:1 Column: 36] +1445129: read 0x10004a60 [Channel: 2 Bank: 1 Row:1 Column: 38] +1445229: read 0x10004a80 [Channel: 2 Bank: 1 Row:1 Column: 40] +1445329: read 0x10004aa0 [Channel: 2 Bank: 1 Row:1 Column: 42] +1445429: read 0x10004ac0 [Channel: 2 Bank: 1 Row:1 Column: 44] +1445529: read 0x10004ae0 [Channel: 2 Bank: 1 Row:1 Column: 46] +1445629: read 0x10004b00 [Channel: 2 Bank: 1 Row:1 Column: 48] +1445729: read 0x10004b20 [Channel: 2 Bank: 1 Row:1 Column: 50] +1445829: read 0x10004b40 [Channel: 2 Bank: 1 Row:1 Column: 52] +1445929: read 0x10004b60 [Channel: 2 Bank: 1 Row:1 Column: 54] +1446029: read 0x10004b80 [Channel: 2 Bank: 1 Row:1 Column: 56] +1446129: read 0x10004ba0 [Channel: 2 Bank: 1 Row:1 Column: 58] +1446229: read 0x10004bc0 [Channel: 2 Bank: 1 Row:1 Column: 60] +1446329: read 0x10004be0 [Channel: 2 Bank: 1 Row:1 Column: 62] +1446429: read 0x10004c00 [Channel: 2 Bank: 1 Row:1 Column: 64] +1446529: read 0x10004c20 [Channel: 2 Bank: 1 Row:1 Column: 66] +1446629: read 0x10004c40 [Channel: 2 Bank: 1 Row:1 Column: 68] +1446729: read 0x10004c60 [Channel: 2 Bank: 1 Row:1 Column: 70] +1446829: read 0x10004c80 [Channel: 2 Bank: 1 Row:1 Column: 72] +1446929: read 0x10004ca0 [Channel: 2 Bank: 1 Row:1 Column: 74] +1447029: read 0x10004cc0 [Channel: 2 Bank: 1 Row:1 Column: 76] +1447129: read 0x10004ce0 [Channel: 2 Bank: 1 Row:1 Column: 78] +1447229: read 0x10004d00 [Channel: 2 Bank: 1 Row:1 Column: 80] +1447329: read 0x10004d20 [Channel: 2 Bank: 1 Row:1 Column: 82] +1447429: read 0x10004d40 [Channel: 2 Bank: 1 Row:1 Column: 84] +1447529: read 0x10004d60 [Channel: 2 Bank: 1 Row:1 Column: 86] +1447629: read 0x10004d80 [Channel: 2 Bank: 1 Row:1 Column: 88] +1447729: read 0x10004da0 [Channel: 2 Bank: 1 Row:1 Column: 90] +1447829: read 0x10004dc0 [Channel: 2 Bank: 1 Row:1 Column: 92] +1447929: read 0x10004de0 [Channel: 2 Bank: 1 Row:1 Column: 94] +1448029: read 0x10004e00 [Channel: 2 Bank: 1 Row:1 Column: 96] +1448129: read 0x10004e20 [Channel: 2 Bank: 1 Row:1 Column: 98] +1448229: read 0x10004e40 [Channel: 2 Bank: 1 Row:1 Column: 100] +1448329: read 0x10004e60 [Channel: 2 Bank: 1 Row:1 Column: 102] +1448429: read 0x10004e80 [Channel: 2 Bank: 1 Row:1 Column: 104] +1448529: read 0x10004ea0 [Channel: 2 Bank: 1 Row:1 Column: 106] +1448629: read 0x10004ec0 [Channel: 2 Bank: 1 Row:1 Column: 108] +1448729: read 0x10004ee0 [Channel: 2 Bank: 1 Row:1 Column: 110] +1448829: read 0x10004f00 [Channel: 2 Bank: 1 Row:1 Column: 112] +1448929: read 0x10004f20 [Channel: 2 Bank: 1 Row:1 Column: 114] +1449029: read 0x10004f40 [Channel: 2 Bank: 1 Row:1 Column: 116] +1449129: read 0x10004f60 [Channel: 2 Bank: 1 Row:1 Column: 118] +1449229: read 0x10004f80 [Channel: 2 Bank: 1 Row:1 Column: 120] +1449329: read 0x10004fa0 [Channel: 2 Bank: 1 Row:1 Column: 122] +1449429: read 0x10004fc0 [Channel: 2 Bank: 1 Row:1 Column: 124] +1449529: read 0x10004fe0 [Channel: 2 Bank: 1 Row:1 Column: 126] +1449629: read 0x10005000 [Channel: 2 Bank: 2 Row:1 Column: 0] +1449729: read 0x10005020 [Channel: 2 Bank: 2 Row:1 Column: 2] +1449829: read 0x10005040 [Channel: 2 Bank: 2 Row:1 Column: 4] +1449929: read 0x10005060 [Channel: 2 Bank: 2 Row:1 Column: 6] +1450029: read 0x10005080 [Channel: 2 Bank: 2 Row:1 Column: 8] +1450129: read 0x100050a0 [Channel: 2 Bank: 2 Row:1 Column: 10] +1450229: read 0x100050c0 [Channel: 2 Bank: 2 Row:1 Column: 12] +1450329: read 0x100050e0 [Channel: 2 Bank: 2 Row:1 Column: 14] +1450429: read 0x10005100 [Channel: 2 Bank: 2 Row:1 Column: 16] +1450529: read 0x10005120 [Channel: 2 Bank: 2 Row:1 Column: 18] +1450629: read 0x10005140 [Channel: 2 Bank: 2 Row:1 Column: 20] +1450729: read 0x10005160 [Channel: 2 Bank: 2 Row:1 Column: 22] +1450829: read 0x10005180 [Channel: 2 Bank: 2 Row:1 Column: 24] +1450929: read 0x100051a0 [Channel: 2 Bank: 2 Row:1 Column: 26] +1451029: read 0x100051c0 [Channel: 2 Bank: 2 Row:1 Column: 28] +1451129: read 0x100051e0 [Channel: 2 Bank: 2 Row:1 Column: 30] +1451229: read 0x10005200 [Channel: 2 Bank: 2 Row:1 Column: 32] +1451329: read 0x10005220 [Channel: 2 Bank: 2 Row:1 Column: 34] +1451429: read 0x10005240 [Channel: 2 Bank: 2 Row:1 Column: 36] +1451595: read 0x10005260 [Channel: 2 Bank: 2 Row:1 Column: 38] +1451623: read 0x405480 [Channel: 0 Bank: 2 Row:257 Column: 72] +1451666: read 0x4054a0 [Channel: 0 Bank: 2 Row:257 Column: 74] +1452095: read 0x405500 [Channel: 0 Bank: 2 Row:257 Column: 80] +1452847: read 0x406c20 [Channel: 0 Bank: 5 Row:257 Column: 66] +1452875: read 0x405520 [Channel: 0 Bank: 2 Row:257 Column: 82] +1452890: read 0x7fff8960 [Channel: 3 Bank: 1 Row:8190 Column: 22] +1452924: read 0x4001e0 [Channel: 0 Bank: 0 Row:256 Column: 30] +1452949: read 0x405780 [Channel: 0 Bank: 2 Row:257 Column: 120] +1452974: read 0x4057a0 [Channel: 0 Bank: 2 Row:257 Column: 122] +1453002: read 0x4057c0 [Channel: 0 Bank: 2 Row:257 Column: 124] +1453027: read 0x4057e0 [Channel: 0 Bank: 2 Row:257 Column: 126] +1453052: read 0x405800 [Channel: 0 Bank: 3 Row:257 Column: 0] +1453080: read 0x405820 [Channel: 0 Bank: 3 Row:257 Column: 2] +1453112: read 0x405860 [Channel: 0 Bank: 3 Row:257 Column: 6] +1453137: read 0x405540 [Channel: 0 Bank: 2 Row:257 Column: 84] +1453165: read 0x405560 [Channel: 0 Bank: 2 Row:257 Column: 86] +1453190: read 0x4055a0 [Channel: 0 Bank: 2 Row:257 Column: 90] +1453197: read 0x400200 [Channel: 0 Bank: 0 Row:256 Column: 32] +1453225: read 0x405880 [Channel: 0 Bank: 3 Row:257 Column: 8] +1453257: read 0x4058a0 [Channel: 0 Bank: 3 Row:257 Column: 10] +1453281: read 0x405900 [Channel: 0 Bank: 3 Row:257 Column: 16] +1453309: read 0x405920 [Channel: 0 Bank: 3 Row:257 Column: 18] +1453333: read 0x405c80 [Channel: 0 Bank: 3 Row:257 Column: 72] +1453358: read 0x405ca0 [Channel: 0 Bank: 3 Row:257 Column: 74] +1453383: read 0x405cc0 [Channel: 0 Bank: 3 Row:257 Column: 76] +1453408: read 0x405ce0 [Channel: 0 Bank: 3 Row:257 Column: 78] +1453410: read 0x405d00 [Channel: 0 Bank: 3 Row:257 Column: 80] +1453433: read 0x10006c40 [Channel: 2 Bank: 5 Row:1 Column: 68] +1453470: read 0x405d20 [Channel: 0 Bank: 3 Row:257 Column: 82] +1453494: read 0x405d40 [Channel: 0 Bank: 3 Row:257 Column: 84] +1453519: read 0x405d60 [Channel: 0 Bank: 3 Row:257 Column: 86] +1453543: read 0x405d80 [Channel: 0 Bank: 3 Row:257 Column: 88] +1453568: read 0x405da0 [Channel: 0 Bank: 3 Row:257 Column: 90] +1453596: read 0x405dc0 [Channel: 0 Bank: 3 Row:257 Column: 92] +1453620: read 0x405e00 [Channel: 0 Bank: 3 Row:257 Column: 96] +1453650: read 0x405e20 [Channel: 0 Bank: 3 Row:257 Column: 98] +1453674: read 0x405e40 [Channel: 0 Bank: 3 Row:257 Column: 100] +1453677: read 0x405e60 [Channel: 0 Bank: 3 Row:257 Column: 102] +1453705: read 0x10006c60 [Channel: 2 Bank: 5 Row:1 Column: 70] +1453737: read 0x405e80 [Channel: 0 Bank: 3 Row:257 Column: 104] +1453761: read 0x405ea0 [Channel: 0 Bank: 3 Row:257 Column: 106] +1453789: read 0x405ec0 [Channel: 0 Bank: 3 Row:257 Column: 108] +1453813: read 0x40b780 [Channel: 0 Bank: 6 Row:258 Column: 120] +1453838: read 0x40b7a0 [Channel: 0 Bank: 6 Row:258 Column: 122] +1453963: read 0x40b7c0 [Channel: 0 Bank: 6 Row:258 Column: 124] +1453988: read 0x40b7e0 [Channel: 0 Bank: 6 Row:258 Column: 126] +1454039: read 0x405ee0 [Channel: 0 Bank: 3 Row:257 Column: 110] +1454178: read 0x405de0 [Channel: 0 Bank: 3 Row:257 Column: 94] +1454202: read 0x40c0a0 [Channel: 0 Bank: 0 Row:259 Column: 10] +1454227: read 0x40c0c0 [Channel: 0 Bank: 0 Row:259 Column: 12] +1454251: read 0x40c0e0 [Channel: 0 Bank: 0 Row:259 Column: 14] +1454281: read 0x40c100 [Channel: 0 Bank: 0 Row:259 Column: 16] +1454309: read 0x40c120 [Channel: 0 Bank: 0 Row:259 Column: 18] +1454334: read 0x40b800 [Channel: 0 Bank: 7 Row:258 Column: 0] +1454359: read 0x40b820 [Channel: 0 Bank: 7 Row:258 Column: 2] +1454387: read 0x40b840 [Channel: 0 Bank: 7 Row:258 Column: 4] +1454412: read 0x40b860 [Channel: 0 Bank: 7 Row:258 Column: 6] +1454440: read 0x40b880 [Channel: 0 Bank: 7 Row:258 Column: 8] +1454464: read 0x40bd60 [Channel: 0 Bank: 7 Row:258 Column: 86] +1454489: read 0x40bd80 [Channel: 0 Bank: 7 Row:258 Column: 88] +1454514: read 0x40bda0 [Channel: 0 Bank: 7 Row:258 Column: 90] +1454539: read 0x40bdc0 [Channel: 0 Bank: 7 Row:258 Column: 92] +1454564: read 0x40bde0 [Channel: 0 Bank: 7 Row:258 Column: 94] +1454589: read 0x40be00 [Channel: 0 Bank: 7 Row:258 Column: 96] +1454617: read 0x40be20 [Channel: 0 Bank: 7 Row:258 Column: 98] +1454645: read 0x40be40 [Channel: 0 Bank: 7 Row:258 Column: 100] +1454685: read 0x40be60 [Channel: 0 Bank: 7 Row:258 Column: 102] +1454710: read 0x40be80 [Channel: 0 Bank: 7 Row:258 Column: 104] +1454735: read 0x40bea0 [Channel: 0 Bank: 7 Row:258 Column: 106] +1454760: read 0x40bec0 [Channel: 0 Bank: 7 Row:258 Column: 108] +1454785: read 0x40bee0 [Channel: 0 Bank: 7 Row:258 Column: 110] +1454810: read 0x40bf00 [Channel: 0 Bank: 7 Row:258 Column: 112] +1454835: read 0x40bf20 [Channel: 0 Bank: 7 Row:258 Column: 114] +1454860: read 0x40bf40 [Channel: 0 Bank: 7 Row:258 Column: 116] +1454911: read 0x40bf60 [Channel: 0 Bank: 7 Row:258 Column: 118] +1454936: read 0x40b8a0 [Channel: 0 Bank: 7 Row:258 Column: 10] +1454961: read 0x40b8c0 [Channel: 0 Bank: 7 Row:258 Column: 12] +1454986: read 0x40b8e0 [Channel: 0 Bank: 7 Row:258 Column: 14] +1455014: read 0x40b900 [Channel: 0 Bank: 7 Row:258 Column: 16] +1455038: read 0x40b960 [Channel: 0 Bank: 7 Row:258 Column: 22] +1455066: read 0x40b980 [Channel: 0 Bank: 7 Row:258 Column: 24] +1455090: read 0x40b9a0 [Channel: 0 Bank: 7 Row:258 Column: 26] +1455115: read 0x40b9c0 [Channel: 0 Bank: 7 Row:258 Column: 28] +1455140: read 0x40b9e0 [Channel: 0 Bank: 7 Row:258 Column: 30] +1455165: read 0x40ba00 [Channel: 0 Bank: 7 Row:258 Column: 32] +1455173: read 0x40ba20 [Channel: 0 Bank: 7 Row:258 Column: 34] +1455198: read 0x40ba60 [Channel: 0 Bank: 7 Row:258 Column: 38] +1455223: read 0x40ba80 [Channel: 0 Bank: 7 Row:258 Column: 40] +1455248: read 0x40baa0 [Channel: 0 Bank: 7 Row:258 Column: 42] +1455273: read 0x40bac0 [Channel: 0 Bank: 7 Row:258 Column: 44] +1455298: read 0x40bae0 [Channel: 0 Bank: 7 Row:258 Column: 46] +1455323: read 0x40bb00 [Channel: 0 Bank: 7 Row:258 Column: 48] +1455351: read 0x40bb20 [Channel: 0 Bank: 7 Row:258 Column: 50] +1455375: read 0x40bbe0 [Channel: 0 Bank: 7 Row:258 Column: 62] +1455400: read 0x40bc00 [Channel: 0 Bank: 7 Row:258 Column: 64] +1455412: read 0x40bc20 [Channel: 0 Bank: 7 Row:258 Column: 66] +1455436: read 0x40c060 [Channel: 0 Bank: 0 Row:259 Column: 6] +1455462: read 0x40c080 [Channel: 0 Bank: 0 Row:259 Column: 8] +1455508: read 0x40c140 [Channel: 0 Bank: 0 Row:259 Column: 20] +1455532: read 0x40c2e0 [Channel: 0 Bank: 0 Row:259 Column: 46] +1455560: read 0x40c300 [Channel: 0 Bank: 0 Row:259 Column: 48] +1455584: read 0x412800 [Channel: 0 Bank: 5 Row:260 Column: 0] +1455688: read 0x412820 [Channel: 0 Bank: 5 Row:260 Column: 2] +1455752: read 0x10006ce0 [Channel: 2 Bank: 5 Row:1 Column: 78] +1456084: read 0x10006d00 [Channel: 2 Bank: 5 Row:1 Column: 80] +1456112: read 0x4058c0 [Channel: 0 Bank: 3 Row:257 Column: 12] diff --git a/DRAMSys/library/src/common/AddressDecoder.cpp b/DRAMSys/library/src/common/AddressDecoder.cpp index b454cec6..92c6cc4d 100644 --- a/DRAMSys/library/src/common/AddressDecoder.cpp +++ b/DRAMSys/library/src/common/AddressDecoder.cpp @@ -32,7 +32,6 @@ * Authors: * Johannes Feldmann * Lukas Steiner - * Luiza Correa */ #include @@ -42,87 +41,105 @@ #include "utils.h" #include "../configuration/Configuration.h" -using json = nlohmann::json; - -unsigned int AddressDecoder::getUnsignedAttrFromJson(nlohmann::json obj, std::string strName) +tinyxml2::XMLElement *AddressDecoder::getXMLNode(tinyxml2::XMLElement + *pRoot, std::string strName) { - if (!obj[strName].empty()) - { - if (obj[strName].is_number_unsigned()) - { - return obj[strName]; - } - else - { - SC_REPORT_FATAL("AddressDecoder", ("Attribute " + strName + " is not a number.").c_str()); - return (unsigned)(-1); - } - } - else - { - SC_REPORT_FATAL("AddressDecoder", ("Attribute " + strName + " is empty or not found.").c_str()); - return (unsigned)(-1); + tinyxml2::XMLElement *pNode = pRoot->FirstChildElement(strName.c_str()); + if (pNode == nullptr) { + reportFatal("AddressDecorder", + "XML File corrupted. Missing node " + strName + "."); } + return pNode; } -std::vector AddressDecoder::getAttrToVectorFromJson(nlohmann::json obj, std::string strName) +unsigned int AddressDecoder::getUnsignedTextFromXMLNode( + tinyxml2::XMLElement *pRoot) { - std::vector vParameter; - if (!obj[strName].empty()) - { - for (auto it : obj[strName].items()) - { - auto valor = it.value(); - if (valor.is_number_unsigned()) - vParameter.push_back(it.value()); - else - SC_REPORT_FATAL("AddressDecoder", ("Attribute " + strName + " is not a number.").c_str()); - } + std::string str = pRoot->GetText(); + if (str.empty() || std::find_if(str.begin(), str.end(), [](char c) { + return !std::isdigit(c); + }) != str.end()) { + reportFatal("AddressDecoder", + "Node " + std::string(pRoot->Name()) + " is empty or not a number."); + return (unsigned)(-1); } - return vParameter; + return atol(str.c_str()); +} + +unsigned int AddressDecoder::getUnsignedAttrFromXMLNode( + tinyxml2::XMLElement *pRoot, std::string strName) +{ + std::string str = pRoot->Attribute(strName.c_str()); + if (str.empty() || std::find_if(str.begin(), str.end(), [](char c) { + return !std::isdigit(c); + }) != str.end()) { + reportFatal("AddressDecoder", + "Attribute " + strName + " is empty or not a number."); + return (unsigned)(-1); + } + return atol(str.c_str()); } AddressDecoder::AddressDecoder(std::string pathToAddressMapping) { - json addrFile = parseJSON(pathToAddressMapping); - json mapping; - if (addrFile["CONGEN"].empty()) - SC_REPORT_FATAL("AddressDecorder", "Root node name differs from \"CONGEN\". File format not supported."); + tinyxml2::XMLDocument doc; + loadXML(pathToAddressMapping, doc); + tinyxml2::XMLElement *pRoot = doc.RootElement(); + std::string xmlNodeName(pRoot->Name()); + + if (xmlNodeName != "CONGEN") + reportFatal("AddressDecorder", + "Root node name differs from \"CONGEN\". File format not supported."); // Load address mapping - if (!addrFile["CONGEN"]["SOLUTION"].empty()) - { - bool foundID0 = false; - for (auto it : addrFile["CONGEN"]["SOLUTION"].items()) - { - if (getUnsignedAttrFromJson(it.value(), "ID") == 0) - { - foundID0 = true; - mapping = it.value(); - break; - } - } - if (!foundID0) - SC_REPORT_FATAL("AddressDecoder", "No mapping with ID 0 was found."); - } - else - mapping = addrFile["CONGEN"]; + tinyxml2::XMLElement *pNode; - for (auto xorItem : mapping["XOR"].items()) + for (pNode = pRoot->FirstChildElement("SOLUTION"); pNode != nullptr; + pNode = pNode->NextSiblingElement("SOLUTION")) { - auto value = xorItem.value(); - if (!value.empty()) - vXor.push_back(std::pair(getUnsignedAttrFromJson(value, "FIRST"), - getUnsignedAttrFromJson(value, "SECOND"))); + if (getUnsignedAttrFromXMLNode(pNode, "ID") == 0) + break; } - vChannelBits = getAttrToVectorFromJson(mapping,"CHANNEL_BIT"); - vRankBits = getAttrToVectorFromJson(mapping,"RANK_BIT"); - vBankGroupBits = getAttrToVectorFromJson(mapping,"BANKGROUP_BIT"); - vBankBits = getAttrToVectorFromJson(mapping,"BANK_BIT"); - vRowBits = getAttrToVectorFromJson(mapping,"ROW_BIT"); - vColumnBits = getAttrToVectorFromJson(mapping,"COLUMN_BIT"); - vByteBits = getAttrToVectorFromJson(mapping,"BYTE_BIT"); + if (pNode == nullptr) + SC_REPORT_FATAL("AddressDecoder", "No mapping with ID 0 was found."); + + // get XOR connections + // An XOR connection needs two parameters: A first bit and a second bit. + for (tinyxml2::XMLElement *pXor = pNode->FirstChildElement("XOR"); + pXor != nullptr; pXor = pXor->NextSiblingElement("XOR")) + { + vXor.push_back(std::pair(getUnsignedAttrFromXMLNode(pXor, "FIRST"), + getUnsignedAttrFromXMLNode(pXor, "SECOND"))); + } + + for (tinyxml2::XMLElement *pChannel = pNode->FirstChildElement("CHANNEL_BIT"); + pChannel != nullptr; pChannel = pChannel->NextSiblingElement("CHANNEL_BIT")) + vChannelBits.push_back(getUnsignedTextFromXMLNode(pChannel)); + + for (tinyxml2::XMLElement *pRank = pNode->FirstChildElement("RANK_BIT"); + pRank != nullptr; pRank = pRank->NextSiblingElement("RANK_BIT")) + vRankBits.push_back(getUnsignedTextFromXMLNode(pRank)); + + for (tinyxml2::XMLElement *pBankGroup = pNode->FirstChildElement("BANKGROUP_BIT"); + pBankGroup != nullptr; pBankGroup = pBankGroup->NextSiblingElement("BANKGROUP_BIT")) + vBankGroupBits.push_back(getUnsignedTextFromXMLNode(pBankGroup)); + + for (tinyxml2::XMLElement *pBank = pNode->FirstChildElement("BANK_BIT"); + pBank != nullptr; pBank = pBank->NextSiblingElement("BANK_BIT")) + vBankBits.push_back(getUnsignedTextFromXMLNode(pBank)); + + for (tinyxml2::XMLElement *pRow = pNode->FirstChildElement("ROW_BIT"); + pRow != nullptr; pRow = pRow->NextSiblingElement("ROW_BIT")) + vRowBits.push_back(getUnsignedTextFromXMLNode(pRow)); + + for (tinyxml2::XMLElement *pColumn = pNode->FirstChildElement("COLUMN_BIT"); + pColumn != nullptr; pColumn = pColumn->NextSiblingElement("COLUMN_BIT")) + vColumnBits.push_back(getUnsignedTextFromXMLNode(pColumn)); + + for (tinyxml2::XMLElement *pByte = pNode->FirstChildElement("BYTE_BIT"); + pByte != nullptr; pByte = pByte->NextSiblingElement("BYTE_BIT")) + vByteBits.push_back(getUnsignedTextFromXMLNode(pByte)); unsigned channels = pow(2.0, vChannelBits.size()); unsigned ranks = pow(2.0, vRankBits.size()); diff --git a/DRAMSys/library/src/common/AddressDecoder.h b/DRAMSys/library/src/common/AddressDecoder.h index c49c8214..21b2d243 100644 --- a/DRAMSys/library/src/common/AddressDecoder.h +++ b/DRAMSys/library/src/common/AddressDecoder.h @@ -32,7 +32,6 @@ * Authors: * Johannes Feldmann * Lukas Steiner - * Luiza Correa */ #ifndef ADDRESSDECODER_H @@ -44,7 +43,7 @@ #include #include -#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp" +#include "third_party/tinyxml2/tinyxml2.h" struct DecodedAddress { @@ -75,8 +74,11 @@ public: void print(); private: - std::vector getAttrToVectorFromJson(nlohmann::json obj, std::string strName); - unsigned int getUnsignedAttrFromJson(nlohmann::json obj, std::string strName); + tinyxml2::XMLElement *getXMLNode(tinyxml2::XMLElement *pRoot, + std::string strName); + unsigned int getUnsignedTextFromXMLNode(tinyxml2::XMLElement *pRoot); + unsigned int getUnsignedAttrFromXMLNode(tinyxml2::XMLElement *pRoot, + std::string strName); unsigned banksPerGroup; unsigned bankgroupsPerRank; diff --git a/DRAMSys/library/src/common/DebugManager.h b/DRAMSys/library/src/common/DebugManager.h index 20f54c4b..83219115 100644 --- a/DRAMSys/library/src/common/DebugManager.h +++ b/DRAMSys/library/src/common/DebugManager.h @@ -50,19 +50,10 @@ class DebugManager { public: - static DebugManager &getInstance() - { - static DebugManager _instance; - return _instance; - } ~DebugManager(); -private: - DebugManager(); - DebugManager(const DebugManager &); - DebugManager & operator = (const DebugManager &); + DEF_SINGLETON(DebugManager); -public: bool writeToConsole; bool writeToFile; @@ -71,6 +62,9 @@ public: void openDebugFile(std::string filename); private: + DebugManager(); + DebugManager(const DebugManager &) {} + ofstream debugFile; }; #endif diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index ffa604b6..46a8bedb 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -95,8 +95,7 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, if (currentTransactionsInSystem.count(&trans) == 0) introduceTransactionSystem(trans); - //std::string phaseName = phaseNameToString(phase); - std::string phaseName = phase.get_name(); + std::string phaseName = phaseNameToString(phase); std::string phaseBeginPrefix = "BEGIN_"; std::string phaseEndPrefix = "END_"; @@ -233,20 +232,10 @@ void TlmRecorder::openDB(std::string name) } } + void TlmRecorder::createTables(std::string pathToURI) { - std::string initial; - ifstream in(pathToURI.c_str(), ios::in | ios::binary); - - if (!in) - SC_REPORT_FATAL("Error loading file", ("Could not load textfile from " + pathToURI).c_str()); - - in.seekg(0, ios::end); - initial.resize(in.tellg()); - in.seekg(0, ios::beg); - in.read(&initial[0], initial.size()); - in.close(); - + std::string initial = loadTextFileContents(pathToURI); executeSqlCommand(initial); } @@ -363,21 +352,21 @@ void TlmRecorder::insertCommandLengths() { MemSpec *memSpec = Configuration::getInstance().memSpec; - sqlite3_bind_int(insertCommandLengthsStatement, 1, memSpec->getCommandLength(Command::ACT) / memSpec->tCK); - sqlite3_bind_int(insertCommandLengthsStatement, 2, memSpec->getCommandLength(Command::PRE) / memSpec->tCK); - sqlite3_bind_int(insertCommandLengthsStatement, 3, memSpec->getCommandLength(Command::PREA) / memSpec->tCK); - sqlite3_bind_int(insertCommandLengthsStatement, 4, memSpec->getCommandLength(Command::RD) / memSpec->tCK); - sqlite3_bind_int(insertCommandLengthsStatement, 5, memSpec->getCommandLength(Command::RDA) / memSpec->tCK); - sqlite3_bind_int(insertCommandLengthsStatement, 6, memSpec->getCommandLength(Command::WR) / memSpec->tCK); - sqlite3_bind_int(insertCommandLengthsStatement, 7, memSpec->getCommandLength(Command::WRA) / memSpec->tCK); - sqlite3_bind_int(insertCommandLengthsStatement, 8, memSpec->getCommandLength(Command::REFA) / memSpec->tCK); - sqlite3_bind_int(insertCommandLengthsStatement, 9, memSpec->getCommandLength(Command::REFB) / memSpec->tCK); - sqlite3_bind_int(insertCommandLengthsStatement, 10, memSpec->getCommandLength(Command::PDEA) / memSpec->tCK); - sqlite3_bind_int(insertCommandLengthsStatement, 11, memSpec->getCommandLength(Command::PDXA) / memSpec->tCK); - sqlite3_bind_int(insertCommandLengthsStatement, 12, memSpec->getCommandLength(Command::PDEP) / memSpec->tCK); - sqlite3_bind_int(insertCommandLengthsStatement, 13, memSpec->getCommandLength(Command::PDXP) / memSpec->tCK); - sqlite3_bind_int(insertCommandLengthsStatement, 14, memSpec->getCommandLength(Command::SREFEN) / memSpec->tCK); - sqlite3_bind_int(insertCommandLengthsStatement, 15, memSpec->getCommandLength(Command::SREFEX) / memSpec->tCK); + sqlite3_bind_int(insertCommandLengthsStatement, 1, memSpec->commandLengthInCycles[Command::ACT]); + sqlite3_bind_int(insertCommandLengthsStatement, 2, memSpec->commandLengthInCycles[Command::PRE]); + sqlite3_bind_int(insertCommandLengthsStatement, 3, memSpec->commandLengthInCycles[Command::PREA]); + sqlite3_bind_int(insertCommandLengthsStatement, 4, memSpec->commandLengthInCycles[Command::RD]); + sqlite3_bind_int(insertCommandLengthsStatement, 5, memSpec->commandLengthInCycles[Command::RDA]); + sqlite3_bind_int(insertCommandLengthsStatement, 6, memSpec->commandLengthInCycles[Command::WR]); + sqlite3_bind_int(insertCommandLengthsStatement, 7, memSpec->commandLengthInCycles[Command::WRA]); + sqlite3_bind_int(insertCommandLengthsStatement, 8, memSpec->commandLengthInCycles[Command::REFA]); + sqlite3_bind_int(insertCommandLengthsStatement, 9, memSpec->commandLengthInCycles[Command::REFB]); + sqlite3_bind_int(insertCommandLengthsStatement, 10, memSpec->commandLengthInCycles[Command::PDEA]); + sqlite3_bind_int(insertCommandLengthsStatement, 11, memSpec->commandLengthInCycles[Command::PDXA]); + sqlite3_bind_int(insertCommandLengthsStatement, 12, memSpec->commandLengthInCycles[Command::PDEP]); + sqlite3_bind_int(insertCommandLengthsStatement, 13, memSpec->commandLengthInCycles[Command::PDXP]); + sqlite3_bind_int(insertCommandLengthsStatement, 14, memSpec->commandLengthInCycles[Command::SREFEN]); + sqlite3_bind_int(insertCommandLengthsStatement, 15, memSpec->commandLengthInCycles[Command::SREFEX]); executeSqlStatement(insertCommandLengthsStatement); } @@ -439,10 +428,10 @@ void TlmRecorder::insertPhaseInDB(std::string phaseName, const sc_time &begin, void TlmRecorder::executeSqlStatement(sqlite3_stmt *statement) { int errorCode = sqlite3_step(statement); - if (errorCode != SQLITE_DONE) - SC_REPORT_FATAL("Error in TraceRecorder", - (std::string("Could not execute statement. Error code: ") + std::to_string(errorCode)).c_str()); - + if (errorCode != SQLITE_DONE) { + reportFatal("Error in TraceRecorder", + std::string("Could not execute statement. Error code: ") + std::to_string(errorCode)); + } sqlite3_reset(statement); } diff --git a/DRAMSys/library/src/common/third_party/nlohmann b/DRAMSys/library/src/common/third_party/nlohmann deleted file mode 160000 index b7be613b..00000000 --- a/DRAMSys/library/src/common/third_party/nlohmann +++ /dev/null @@ -1 +0,0 @@ -Subproject commit b7be613b6ec6269c829144ff1cc8a633876d3092 diff --git a/DRAMSys/library/src/common/third_party/tinyxml2 b/DRAMSys/library/src/common/third_party/tinyxml2 new file mode 160000 index 00000000..78fca3db --- /dev/null +++ b/DRAMSys/library/src/common/third_party/tinyxml2 @@ -0,0 +1 @@ +Subproject commit 78fca3db835a5e2de1f3e90f5c6362dda750e3ac diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index 65999dc0..2e1795b8 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -33,7 +33,6 @@ * Janik Schlemminger * Robert Gernhardt * Matthias Jung - * Luiza Correa */ #include "utils.h" @@ -43,8 +42,8 @@ #include "dramExtensions.h" #include +using namespace tinyxml2; using namespace tlm; -using json = nlohmann::json; bool TimeInterval::timeIsInInterval(sc_time time) { @@ -57,80 +56,184 @@ bool TimeInterval::intersects(TimeInterval other) || this->timeIsInInterval(other.start); } -sc_time TimeInterval::getLength() +sc_time getDistance(sc_time a, sc_time b) { - if (end > start) - return end - start; + if (a > b) + return a - b; else - return start - end; + return b - a; } -json parseJSON(std::string path) +void reportFatal(std::string sender, std::string message) { - try - { - // parsing input with a syntax error - json j = json::parse(std::ifstream(path)); - return j; + SC_REPORT_FATAL(sender.c_str(), message.c_str()); +} + +std::string phaseNameToString(tlm_phase phase) +{ + std::ostringstream oss; + oss << phase; + std::string str = oss.str(); + return str; +} + +unsigned int queryUIntParameter(XMLElement *node, std::string name) +{ + int result = 0; + XMLElement *element; + for (element = node->FirstChildElement("parameter"); element != NULL; + element = element->NextSiblingElement("parameter")) { + if (element->Attribute("id") == name) { + sc_assert(!strcmp(element->Attribute("type"), "uint")); + XMLError __attribute__((unused)) error = element->QueryIntAttribute("value", + &result); + sc_assert(!error); + return result; + } } - catch (json::parse_error& e) - { - // output exception information - std::cout << "Error while trying to parse file: " << path << '\n' - << "message: " << e.what() << std::endl; + + reportFatal("Query XML", "Parameter '" + name + "' does not exist."); + return 0; +} + +bool parameterExists(tinyxml2::XMLElement *node, std::string name) +{ + XMLElement *element; + for (element = node->FirstChildElement("parameter"); element != NULL; + element = element->NextSiblingElement("parameter")) { + if (element->Attribute("id") == name) { + return true; + } + } + return false; +} + +double queryDoubleParameter(XMLElement *node, std::string name) +{ + double result = 0; + XMLElement *element; + for (element = node->FirstChildElement("parameter"); element != NULL; + element = element->NextSiblingElement("parameter")) { + if (element->Attribute("id") == name) { + sc_assert(!strcmp(element->Attribute("type"), "double")); + XMLError __attribute__((unused)) error = element->QueryDoubleAttribute("value", + &result); + sc_assert(!error); + return result; + } + } + + reportFatal("Query XML", "Parameter '" + name + "' does not exist."); + return 0; +} + +bool queryBoolParameter(XMLElement *node, std::string name) +{ + bool result = false; + XMLElement *element;// = node->FirstChildElement("parameter"); + for (element = node->FirstChildElement("parameter"); element != NULL; + element = element->NextSiblingElement("parameter")) { + if (element->Attribute("id") == name) { + sc_assert(!strcmp(element->Attribute("type"), "bool")); + XMLError __attribute__((unused)) error = element->QueryBoolAttribute("value", + &result); + sc_assert(!error); + return result; + } + } + + reportFatal("Query XML", "Parameter '" + name + "' does not exist."); + return 0; +} + +std::string queryStringParameter(XMLElement *node, std::string name) +{ + XMLElement *element; + for (element = node->FirstChildElement("parameter"); element != NULL; + element = element->NextSiblingElement("parameter")) { + if (element->Attribute("id") == name) { + return element->Attribute("value"); + } + } + + reportFatal("Query XML", "Parameter '" + name + "' does not exist."); + return 0; +} + +std::string errorToString(XMLError error) +{ + switch (error) { + case XML_NO_ERROR: + return "no error"; + case XML_NO_ATTRIBUTE: + return "NO_ATTRIBUTE"; + case XML_WRONG_ATTRIBUTE_TYPE: + return "WRONG_ATTRIBUTE_TYPE"; + case XML_ERROR_FILE_NOT_FOUND: + return "FILE_NOT_FOUND"; + case XML_ERROR_FILE_COULD_NOT_BE_OPENED: + return "FILE_COULD_NOT_BE_OPENED"; + case XML_ERROR_FILE_READ_ERROR: + return "FILE_READ_ERROR"; + case XML_ERROR_ELEMENT_MISMATCH: + return "ERROR_ELEMENT_MISMATCH"; + case XML_ERROR_PARSING_ELEMENT: + return "ERROR_PARSING_ELEMENT"; + case XML_ERROR_PARSING_ATTRIBUTE: + return "ERROR_PARSING_ATTRIBUTE"; + case XML_ERROR_IDENTIFYING_TAG: + return "ERROR_IDENTIFYING_TAG"; + case XML_ERROR_PARSING_TEXT: + return "ERROR_PARSING_TEXT"; + case XML_ERROR_PARSING_CDATA: + return "ERROR_PARSING_CDATA"; + case XML_ERROR_PARSING_COMMENT: + return "ERROR_PARSING_COMMENT"; + case XML_ERROR_PARSING_DECLARATION: + return "ERROR_PARSING_DECLARATION"; + case XML_ERROR_PARSING_UNKNOWN: + return "ERROR_PARSING_UNKNOWN"; + case XML_ERROR_EMPTY_DOCUMENT: + return "ERROR_EMPTY_DOCUMENT"; + case XML_ERROR_MISMATCHED_ELEMENT: + return "ERROR_MISMATCHED_ELEMENT"; + case XML_ERROR_PARSING: + return "ERROR_PARSING"; + case XML_CAN_NOT_CONVERT_TEXT: + return "CAN_NOT_CONVERT_TEXT"; + case XML_NO_TEXT_NODE: + return "NO_TEXT_NODE"; + default: + return ""; } } -bool parseBool(json &obj, std::string name) +void loadXML(std::string uri, XMLDocument &doc) { - if (!obj.empty()) - { - if (obj.is_boolean()) - return obj; - else - throw std::invalid_argument("Expected type for '" + name + "': bool"); + XMLError error = doc.LoadFile(uri.c_str()); + + if (error) { + reportFatal("Configuration", "Error loading xml from: " + uri + " " + + errorToString(error)); } - else - SC_REPORT_FATAL("Query json", ("Parameter '" + name + "' does not exist.").c_str()); } -unsigned int parseUint(json &obj, std::string name) +std::string loadTextFileContents(std::string filename) { - if (!obj.empty()) - { - if (obj.is_number_unsigned()) - return obj; - else - throw std::invalid_argument("Expected type for '" + name + "': unsigned int"); - } - else - SC_REPORT_FATAL("Query json", ("Parameter '" + name + "' does not exist.").c_str()); -} -double parseUdouble(json &obj, std::string name) -{ - if (!obj.empty()) - { - if (obj.is_number() && (obj > 0)) - return obj; - else - throw std::invalid_argument("Expected type for '" + name + "': positive double"); + ifstream in(filename.c_str(), ios::in | ios::binary); + if (in) { + std::string contents; + in.seekg(0, ios::end); + contents.resize(in.tellg()); + in.seekg(0, ios::beg); + in.read(&contents[0], contents.size()); + in.close(); + return (contents); + } else { + reportFatal("Error loading file", "Could not load textfile from " + filename); + return ""; } - else - SC_REPORT_FATAL("Query json", ("Parameter '" + name + "' does not exist.").c_str()); -} - -std::string parseString(json &obj, std::string name) -{ - if (!obj.empty()) - { - if (obj.is_string()) - return obj; - else - throw std::invalid_argument("Expected type for '" + name + "': string"); - } - else - SC_REPORT_FATAL("Query json", ("Parameter '" + name + "' does not exist.").c_str()); } void setUpDummy(tlm_generic_payload &payload, Rank rank, Bank bank) @@ -144,4 +247,23 @@ void setUpDummy(tlm_generic_payload &payload, Rank rank, Bank bank) payload.set_streaming_width(0); payload.set_extension(new DramExtension(Thread(UINT_MAX), rank, BankGroup(0), bank, Row(0), Column(0), 0, 0)); + // payload takes ownership + // TODO: Dummies muessen noch banggruppe und rank sauber bekommen .. noch was ueberlegen!!! +} + +std::string getFileName(std::string uri) +{ + // Remove directory if present. + // Do this before extension removal incase directory has a period character. + const size_t last_slash_idx = uri.find_last_of("\\/"); + if (std::string::npos != last_slash_idx) { + uri.erase(0, last_slash_idx + 1); + } + + // Remove extension if present. + const size_t period_idx = uri.rfind('.'); + if (std::string::npos != period_idx) { + uri.erase(period_idx); + } + return uri; } diff --git a/DRAMSys/library/src/common/utils.h b/DRAMSys/library/src/common/utils.h index 0e52b291..9def2069 100644 --- a/DRAMSys/library/src/common/utils.h +++ b/DRAMSys/library/src/common/utils.h @@ -33,7 +33,6 @@ * Robert Gernhardt * Matthias Jung * Eder F. Zulian - * Luiza Correa */ #ifndef UTILS_H @@ -46,22 +45,52 @@ #include #include #include "dramExtensions.h" -#include -#include -#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp" +#include "third_party/tinyxml2/tinyxml2.h" -class TimeInterval -{ -public: +#define DEF_SINGLETON( NAME ) \ +public: \ + static NAME& getInstance() \ + { \ + static NAME _instance; \ + return _instance; \ + } + +//TODO : move to timing specific header +sc_time getDistance(sc_time a, sc_time b); + +struct TimeInterval { sc_time start, end; TimeInterval() : start(SC_ZERO_TIME), end(SC_ZERO_TIME) {} TimeInterval(sc_time start, sc_time end) : start(start), end(end) {} - sc_time getLength(); + sc_time getLength() + { + return getDistance(start, end); + } bool timeIsInInterval(sc_time time); bool intersects(TimeInterval other); }; +template +inline Val getElementFromMap(const std::map &m, Key key) +{ + if (m.count(key) == 0) { + SC_REPORT_FATAL("Map", "Element not in map"); + } + + return m.at(key); +} + +template +bool isIn(const T &value, const std::vector &collection) +{ + for (T t : collection) { + if (t == value) + return true; + } + return false; +} + constexpr const char headline[] = "==========================================================================="; @@ -102,11 +131,20 @@ static inline void loadbar(unsigned int x, std::cout << "|\r" << std::flush; } -nlohmann::json parseJSON(std::string path); -bool parseBool(nlohmann::json &obj, std::string name); -unsigned int parseUint(nlohmann::json &obj, std::string name); -double parseUdouble(nlohmann::json &obj, std::string name); -std::string parseString(nlohmann::json &obj, std::string name); +//TODO : Move to debug manager +void reportFatal(std::string sender, std::string message); +std::string phaseNameToString(tlm::tlm_phase phase); + + +//TODO : Move to other source specific to xml +std::string getFileName(std::string uri); +bool parameterExists(tinyxml2::XMLElement *node, std::string name); +std::string loadTextFileContents(std::string filename); +void loadXML(std::string uri, tinyxml2::XMLDocument &doc); +unsigned int queryUIntParameter(tinyxml2::XMLElement *node, std::string name); +std::string queryStringParameter(tinyxml2::XMLElement *node, std::string name); +bool queryBoolParameter(tinyxml2::XMLElement *node, std::string name); +double queryDoubleParameter(tinyxml2::XMLElement *node, std::string name); void setUpDummy(tlm::tlm_generic_payload &payload, Rank rank = Rank(0), Bank bank = Bank(0)); diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index 3f8462ba..959b128f 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -34,24 +34,12 @@ * Matthias Jung * Éder F. Zulian * Felipe S. Prado - * Lukas Steiner - * Luiza Correa */ #include #include "Configuration.h" -#include "memspec/MemSpecDDR3.h" -#include "memspec/MemSpecDDR4.h" -#include "memspec/MemSpecWideIO.h" -#include "memspec/MemSpecLPDDR4.h" -#include "memspec/MemSpecWideIO2.h" -#include "memspec/MemSpecHBM2.h" -#include "memspec/MemSpecGDDR5.h" -#include "memspec/MemSpecGDDR5X.h" -#include "memspec/MemSpecGDDR6.h" - -using json = nlohmann::json; +#include "ConfigurationLoader.h" std::string Configuration::memspecUri = ""; std::string Configuration::mcconfigUri = ""; @@ -77,7 +65,7 @@ enum sc_time_unit string2TimeUnit(std::string s) } } -void Configuration::setParameter(std::string name, nlohmann::json value) +void Configuration::setParameter(std::string name, std::string value) { // MCConfig if (name == "PagePolicy") @@ -85,7 +73,7 @@ void Configuration::setParameter(std::string name, nlohmann::json value) else if (name == "Scheduler") scheduler = value; else if (name == "RequestBufferSize") - requestBufferSize = value; + requestBufferSize = std::stoul(value); else if (name == "CmdMux") cmdMux = value; else if (name == "RespQueue") @@ -93,43 +81,43 @@ void Configuration::setParameter(std::string name, nlohmann::json value) else if (name == "RefreshPolicy") refreshPolicy = value; else if (name == "RefreshMode") - refreshMode = value; + refreshMode = std::stoul(value); else if (name == "RefreshMaxPostponed") - refreshMaxPostponed = value; + refreshMaxPostponed = std::stoul(value); else if (name == "RefreshMaxPulledin") - refreshMaxPulledin = value; + refreshMaxPulledin = std::stoul(value); else if (name == "PowerDownPolicy") powerDownPolicy = value; else if (name == "PowerDownTimeout") - powerDownTimeout = value; + powerDownTimeout = std::stoul(value); //SimConfig------------------------------------------------ else if (name == "SimulationName") simulationName = value; else if (name == "DatabaseRecording") - databaseRecording = value; + databaseRecording = std::stoul(value); else if (name == "PowerAnalysis") - powerAnalysis = value; + powerAnalysis = std::stoul(value); else if (name == "EnableWindowing") - enableWindowing = value; + enableWindowing = std::stoul(value); else if (name == "WindowSize") { - windowSize = value; + windowSize = std::stoul(value); if (windowSize == 0) SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + ". This parameter must be at least one.").c_str()); } else if (name == "Debug") - debug = value; + debug = std::stoul(value); else if (name == "NumberOfMemChannels") - numberOfMemChannels = value; + numberOfMemChannels = std::stoul(value); else if (name == "ThermalSimulation") - thermalSimulation = value; + thermalSimulation = std::stoul(value); else if (name == "SimulationProgressBar") - simulationProgressBar = value; + simulationProgressBar = std::stoul(value); else if (name == "NumberOfDevicesOnDIMM") { - numberOfDevicesOnDIMM = value; + numberOfDevicesOnDIMM = std::stoul(value); if (numberOfDevicesOnDIMM == 0) SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + @@ -138,20 +126,20 @@ void Configuration::setParameter(std::string name, nlohmann::json value) else if (name == "AddressOffset") { #ifdef DRAMSYS_GEM5 - addressOffset = value; + addressOffset = std::stoull(value); #else addressOffset = 0; #endif } else if (name == "UseMalloc") - useMalloc = value; + useMalloc = std::stoul(value); else if (name == "CheckTLM2Protocol") - checkTLM2Protocol = value; + checkTLM2Protocol = std::stoul(value); else if (name == "ECCControllerMode") ECCMode = value; // Specification for ErrorChipSeed, ErrorCSVFile path and StoreMode else if (name == "ErrorChipSeed") - errorChipSeed = value; + errorChipSeed = std::stoul(value); else if (name == "ErrorCSVFile") errorCSVFile = value; else if (name == "StoreMode") @@ -162,31 +150,31 @@ void Configuration::setParameter(std::string name, nlohmann::json value) if (value != "Celsius" && value != "Fahrenheit" && value != "Kelvin") SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + ".").c_str()); - temperatureSim.temperatureScale = value; + temperatureSim.TemperatureScale = value; } else if (name == "StaticTemperatureDefaultValue") - temperatureSim.staticTemperatureDefaultValue = value; + temperatureSim.StaticTemperatureDefaultValue = std::stoi(value); else if (name == "ThermalSimPeriod") - temperatureSim.thermalSimPeriod = value; + temperatureSim.ThermalSimPeriod = std::stod(value.c_str()); else if (name == "ThermalSimUnit") - temperatureSim.thermalSimUnit = string2TimeUnit(value); + temperatureSim.ThermalSimUnit = string2TimeUnit(value); else if (name == "PowerInfoFile") { temperatureSim.powerInfoFile = value; temperatureSim.parsePowerInfoFile(); } else if (name == "IceServerIp") - temperatureSim.iceServerIp = value; + temperatureSim.IceServerIp = value; else if (name == "IceServerPort") - temperatureSim.iceServerPort = value; + temperatureSim.IceServerPort = std::stoul(value); else if (name == "SimPeriodAdjustFactor") - temperatureSim.simPeriodAdjustFactor = value; + temperatureSim.SimPeriodAdjustFactor = std::stoi(value.c_str()); else if (name == "NPowStableCyclesToIncreasePeriod") - temperatureSim.nPowStableCyclesToIncreasePeriod = value; + temperatureSim.NPowStableCyclesToIncreasePeriod = std::stoi(value.c_str()); else if (name == "GenerateTemperatureMap") - temperatureSim.generateTemperatureMap = value; + temperatureSim.GenerateTemperatureMap = std::stoul(value); else if (name == "GeneratePowerMap") - temperatureSim.generatePowerMap = value; + temperatureSim.GeneratePowerMap = std::stoul(value); else SC_REPORT_FATAL("Configuration", ("Parameter " + name + " not defined in Configuration").c_str()); @@ -267,55 +255,3 @@ unsigned int Configuration::adjustNumBytesAfterECC(unsigned nBytes) return 0; } } - -void Configuration::loadSimConfig(Configuration &config, std::string simconfigUri) -{ - json doc = parseJSON(simconfigUri); - for (auto& x : doc["simconfig"].items()) - config.setParameter(x.key(), x.value()); -} - -void Configuration::loadTemperatureSimConfig(Configuration &config, std::string thermalsimconfigUri) -{ - json doc = parseJSON(thermalsimconfigUri); - for (auto& x : doc["thermalsimconfig"].items()) - config.setParameter(x.key(), x.value()); -} - -void Configuration::loadMCConfig(Configuration &config, std::string mcconfigUri) -{ - config.mcconfigUri = mcconfigUri; - json doc = parseJSON(mcconfigUri); - for (auto& x : doc["mcconfig"].items()) - config.setParameter(x.key(), x.value()); -} - -void Configuration::loadMemSpec(Configuration &config, std::string memspecUri) -{ - config.memspecUri = memspecUri; - json doc = parseJSON(memspecUri); - json jMemSpec = doc["memspec"]; - - std::string memoryType = jMemSpec["memoryType"]; - - if (memoryType == "DDR3") - memSpec = new MemSpecDDR3(jMemSpec); - else if (memoryType == "DDR4") - memSpec = new MemSpecDDR4(jMemSpec); - else if (memoryType == "LPDDR4") - memSpec = new MemSpecLPDDR4(jMemSpec); - else if (memoryType == "WIDEIO_SDR") - memSpec = new MemSpecWideIO(jMemSpec); - else if (memoryType == "WIDEIO2") - memSpec = new MemSpecWideIO2(jMemSpec); - else if (memoryType == "HBM2") - memSpec = new MemSpecHBM2(jMemSpec); - else if (memoryType == "GDDR5") - memSpec = new MemSpecGDDR5(jMemSpec); - else if (memoryType == "GDDR5X") - memSpec = new MemSpecGDDR5X(jMemSpec); - else if (memoryType == "GDDR6") - memSpec = new MemSpecGDDR6(jMemSpec); - else - SC_REPORT_FATAL("Configuration", "Unsupported DRAM type"); -} diff --git a/DRAMSys/library/src/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h index af0ffff9..69fb9fec 100644 --- a/DRAMSys/library/src/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -34,8 +34,6 @@ * Matthias Jung * Eder F. Zulian * Felipe S. Prado - * Lukas Steiner - * Luiza Correa */ #ifndef CONFIGURATION_H @@ -50,24 +48,16 @@ #include "../error/eccbaseclass.h" -class Configuration -{ -public: - static Configuration &getInstance() - { - static Configuration _instance; - return _instance; - } -private: - Configuration() {} - Configuration(const Configuration &); - Configuration & operator = (const Configuration &); +enum class StorageMode {NoStorage, Store, ErrorModel}; -public: +struct Configuration +{ static std::string memspecUri; static std::string mcconfigUri; std::string pathToResources; + DEF_SINGLETON(Configuration); + // MCConfig: std::string pagePolicy = "Open"; std::string scheduler = "Fifo"; @@ -80,7 +70,6 @@ public: unsigned int refreshMaxPulledin = 0; std::string powerDownPolicy = "NoPowerDown"; unsigned int powerDownTimeout = 3; - // SimConfig std::string simulationName = "default"; bool databaseRecording = false; @@ -99,10 +88,10 @@ public: bool useMalloc = false; unsigned long long int addressOffset = 0; - // MemSpec (from DRAM-Power) + // MemSpec (from DRAM-Power XML) MemSpec *memSpec; - void setParameter(std::string name, nlohmann::json value); + void setParameter(std::string name, std::string value); //Configs for Seed, csv file and StorageMode unsigned int errorChipSeed; @@ -117,11 +106,6 @@ public: unsigned int getBytesPerBurst(); unsigned int adjustNumBytesAfterECC(unsigned bytes); void setPathToResources(std::string path); - - void loadMCConfig(Configuration &config, std::string amconfigUri); - void loadSimConfig(Configuration &config, std::string simconfigUri); - void loadMemSpec(Configuration &config, std::string memspecUri); - void loadTemperatureSimConfig(Configuration &config, std::string simconfigUri); }; #endif // CONFIGURATION_H diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp new file mode 100644 index 00000000..7a8e9579 --- /dev/null +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -0,0 +1,766 @@ +/* + * Copyright (c) 2015, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Janik Schlemminger + * Matthias Jung + * Lukas Steiner + */ + +#include "ConfigurationLoader.h" +#include "memspec/MemSpec.h" +#include "memspec/MemSpecDDR3.h" +#include "memspec/MemSpecDDR4.h" +#include "memspec/MemSpecWideIO.h" +#include "memspec/MemSpecLPDDR4.h" +#include "memspec/MemSpecWideIO2.h" +#include "memspec/MemSpecHBM2.h" +#include "memspec/MemSpecGDDR5.h" +#include "memspec/MemSpecGDDR5X.h" +#include "memspec/MemSpecGDDR6.h" + +using namespace tinyxml2; + +void ConfigurationLoader::loadSimConfig(Configuration &config, + std::string simconfigUri) +{ + tinyxml2::XMLDocument doc; + + loadXML(simconfigUri, doc); + XMLElement *simconfig = doc.FirstChildElement("simconfig"); + loadConfig(config, simconfig); +} + +void ConfigurationLoader::loadSimConfig(Configuration &config, + XMLElement *simconfig) +{ + if (simconfig->Attribute("src")) { + XMLDocument doc; + std::string src(simconfig->Attribute("src")); + loadXML(src, doc); + loadSimConfig(config, doc.FirstChildElement("simconfig")); + } + loadConfig(config, simconfig); +} + +void ConfigurationLoader::loadTemperatureSimConfig(Configuration &config, + std::string thermalsimconfigUri) +{ + loadConfigFromUri(config, thermalsimconfigUri, "thermalsimconfig"); +} + +void ConfigurationLoader::loadTemperatureSimConfig(Configuration &config, + XMLElement *thermalsimconfig) +{ + if (thermalsimconfig->Attribute("src")) { + // Configuration is inside another a file + std::string uri(thermalsimconfig->Attribute("src")); + loadConfigFromUri(config, uri, "thermalsimconfig"); + } else { + loadConfig(config, thermalsimconfig); + } +} + +void ConfigurationLoader::loadConfig(Configuration &config, + XMLElement *configNode) +{ + XMLElement *element; + for (element = configNode->FirstChildElement(); element != NULL; + element = element->NextSiblingElement()) { + config.setParameter(element->Name(), element->Attribute("value")); + + } +} + +void ConfigurationLoader::loadConfigFromUri(Configuration &config, + std::string uri, std::string first_element) +{ + tinyxml2::XMLDocument doc; + loadXML(uri, doc); + XMLElement *e = doc.FirstChildElement(first_element.c_str()); + loadConfig(config, e); +} + +void ConfigurationLoader::loadMCConfig(Configuration &config, + std::string mcconfigUri) +{ + tinyxml2::XMLDocument doc; + config.mcconfigUri = mcconfigUri; + loadXML(mcconfigUri, doc); + XMLElement *mcconfig = doc.FirstChildElement("mcconfig"); + loadConfig(config, mcconfig); +} + +void ConfigurationLoader::loadMCConfig(Configuration &config, + XMLElement *mcconfig) +{ + if (mcconfig->Attribute("src")) + { + XMLDocument doc; + std::string src(mcconfig->Attribute("src")); + config.mcconfigUri = src; + loadXML(src, doc); + loadMCConfig(config, doc.FirstChildElement("mcconfig")); + } + else + loadConfig(config, mcconfig); +} + +void ConfigurationLoader::loadMemSpec(Configuration &config, std::string memspecUri) +{ + tinyxml2::XMLDocument doc; + config.memspecUri = memspecUri; + loadXML(memspecUri, doc); + XMLElement *memspec = doc.FirstChildElement("memspec"); + loadMemSpec(config, memspec); +} + +void ConfigurationLoader::loadMemSpec(Configuration &config, + XMLElement *memspec) +{ + std::string memoryType = queryStringParameter(memspec, "memoryType"); + if (memoryType == "DDR4") + { + Configuration::getInstance().memSpec = new MemSpecDDR4(); + loadCommons(config, memspec); + loadDDR4(config, memspec); + } + else if (memoryType == "DDR3") + { + Configuration::getInstance().memSpec = new MemSpecDDR3(); + loadCommons(config, memspec); + loadDDR3(config, memspec); + } + else if (memoryType == "LPDDR4") + { + Configuration::getInstance().memSpec = new MemSpecLPDDR4(); + loadCommons(config, memspec); + loadLPDDR4(config, memspec); + } + else if (memoryType == "WIDEIO_SDR") + { + Configuration::getInstance().memSpec = new MemSpecWideIO(); + loadCommons(config, memspec); + loadWideIO(config, memspec); + } + else if (memoryType == "WIDEIO2") + { + Configuration::getInstance().memSpec = new MemSpecWideIO2(); + loadCommons(config, memspec); + loadWideIO2(config, memspec); + } + else if (memoryType == "HBM2") + { + Configuration::getInstance().memSpec = new MemSpecHBM2(); + loadCommons(config, memspec); + loadHBM2(config, memspec); + } + else if (memoryType == "GDDR5") + { + Configuration::getInstance().memSpec = new MemSpecGDDR5(); + loadCommons(config, memspec); + loadGDDR5(config, memspec); + } + else if (memoryType == "GDDR5X") + { + Configuration::getInstance().memSpec = new MemSpecGDDR5X(); + loadCommons(config, memspec); + loadGDDR5X(config, memspec); + } + else if (memoryType == "GDDR6") + { + Configuration::getInstance().memSpec = new MemSpecGDDR6(); + loadCommons(config, memspec); + loadGDDR6(config, memspec); + } + else + reportFatal("ConfigurationLoader", "Unsupported DRAM type"); +} + +void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec) +{ + MemSpec *memSpec = config.memSpec; + + memSpec->memoryId = queryStringParameter(xmlSpec, "memoryId"); + memSpec->memoryType = queryStringParameter(xmlSpec, "memoryType"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->burstLength = queryUIntParameter(architecture, "burstLength"); + memSpec->dataRate = queryUIntParameter(architecture, "dataRate"); + memSpec->numberOfRows = queryUIntParameter(architecture, "nbrOfRows"); + memSpec->numberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); + memSpec->bitWidth = queryUIntParameter(architecture, "width"); + + // Clock + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + memSpec->fCKMHz = queryDoubleParameter(timings, "clkMhz"); + memSpec->tCK = sc_time(1.0 / memSpec->fCKMHz, SC_US); + + memSpec->burstDuration = memSpec->tCK * (memSpec->burstLength / memSpec->dataRate); +} + +void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecDDR3 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = 1; + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; + + // MemTimings specific for DDR3 + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); + memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR"); + //memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC"); + memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS"); + memSpec->tCCD = memSpec->tCK * queryUIntParameter(timings, "CCD"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC"); + memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP"); + memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD"); + memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR"); + memSpec->tAL = memSpec->tCK * queryUIntParameter(timings, "AL"); + memSpec->tXPDLL = memSpec->tCK * queryUIntParameter(timings, "XPDLL"); + memSpec->tXSDLL = memSpec->tCK * queryUIntParameter(timings, "XSDLL"); + + // Currents and voltages + XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); + memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->vDD = queryDoubleParameter(powers, "vdd"); + memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); + memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); + memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); + memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); +} + +void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecDDR4 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; + + // MemTimings specific for DDR4 + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); + memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR"); + //memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC"); + memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS"); + memSpec->tCCD_S = memSpec->tCK * queryUIntParameter(timings, "CCD_S"); + memSpec->tCCD_L = memSpec->tCK * queryUIntParameter(timings, "CCD_L"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + unsigned refreshMode = Configuration::getInstance().refreshMode; + if (refreshMode == 1) + { + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC"); + } + else if (refreshMode == 2) + { + memSpec->tREFI = memSpec->tCK * (queryUIntParameter(timings, "REFI") / 2); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC2"); + } + else if (refreshMode == 4) + { + memSpec->tREFI = memSpec->tCK * (queryUIntParameter(timings, "REFI") / 2); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC4"); + } + else + SC_REPORT_FATAL("ConfigurationLoader", "Refresh Mode not supported"); + memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP"); + memSpec->tRRD_S = memSpec->tCK * queryUIntParameter(timings, "RRD_S"); + memSpec->tRRD_L = memSpec->tCK * queryUIntParameter(timings, "RRD_L"); + memSpec->tWTR_S = memSpec->tCK * queryUIntParameter(timings, "WTR_S"); + memSpec->tWTR_L = memSpec->tCK * queryUIntParameter(timings, "WTR_L"); + memSpec->tAL = memSpec->tCK * queryUIntParameter(timings, "AL"); + memSpec->tXPDLL = memSpec->tCK * queryUIntParameter(timings, "XPDLL"); + memSpec->tXSDLL = memSpec->tCK * queryUIntParameter(timings, "XSDLL"); + + // Currents and voltages + XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); + memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->vDD = queryDoubleParameter(powers, "vdd"); + memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); + memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); + memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); + memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); + memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); + memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); + memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); +} + +void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecLPDDR4 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture: + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = 1; + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; + + // MemTimings specific for LPDDR4 + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tREFIpb = memSpec->tCK * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFCab = memSpec->tCK * queryUIntParameter(timings, "RFCAB"); + memSpec->tRFCpb = memSpec->tCK * queryUIntParameter(timings, "RFCPB"); + memSpec->tRPab = memSpec->tCK * queryUIntParameter(timings, "RPAB"); + memSpec->tRPpb = memSpec->tCK * queryUIntParameter(timings, "RPPB"); + memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD"); + memSpec->tCCD = memSpec->tCK * queryUIntParameter(timings, "CCD"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tRPST = memSpec->tCK * queryUIntParameter(timings, "RPST"); + memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tDQSS = memSpec->tCK * queryUIntParameter(timings, "DQSS"); + memSpec->tDQS2DQ = memSpec->tCK * queryUIntParameter(timings, "DQS2DQ"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tWPRE = memSpec->tCK * queryUIntParameter(timings, "WPRE"); + memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tSR = memSpec->tCK * queryUIntParameter(timings, "SR"); + memSpec->tXSR = memSpec->tCK * queryUIntParameter(timings, "XSR"); + memSpec->tESCKE = memSpec->tCK * queryUIntParameter(timings, "ESCKE"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); + memSpec->tCMDCKE = memSpec->tCK * queryUIntParameter(timings, "CMDCKE"); + + // Currents and voltages + // TODO: to be completed +} + +void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecWideIO *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = 1; + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; + + // MemTimings specific for WideIO + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); + memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR"); + memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK"); + memSpec->tAC = memSpec->tCK * queryUIntParameter(timings, "AC"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC"); + memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS"); + memSpec->tCCD_R = memSpec->tCK * queryUIntParameter(timings, "CCD_R"); + memSpec->tCCD_W = memSpec->tCK * queryUIntParameter(timings, "CCD_W"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC"); + memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP"); + memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD"); + memSpec->tTAW = memSpec->tCK * queryUIntParameter(timings, "TAW"); + memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR"); + + // Currents and voltages + XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); + memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->vDD = queryDoubleParameter(powers, "vdd"); + memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); + memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); + memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02"); + memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); + memSpec->iDD2P12 = queryDoubleParameter(powers, "idd2p12"); + memSpec->iDD2N2 = queryDoubleParameter(powers, "idd2n2"); + memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); + memSpec->iDD3P02 = queryDoubleParameter(powers, "idd3p02"); + memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); + memSpec->iDD3P12 = queryDoubleParameter(powers, "idd3p12"); + memSpec->iDD3N2 = queryDoubleParameter(powers, "idd3n2"); + memSpec->iDD4R2 = queryDoubleParameter(powers, "idd4r2"); + memSpec->iDD4W2 = queryDoubleParameter(powers, "idd4w2"); + memSpec->iDD52 = queryDoubleParameter(powers, "idd52"); + memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); + memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); +} + +void ConfigurationLoader::loadWideIO2(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecWideIO2 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = 1; + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; + + // MemTimings specific for WideIO + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK"); + memSpec->tDQSS = memSpec->tCK * queryUIntParameter(timings, "DQSS"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tRCpb = memSpec->tCK * queryUIntParameter(timings, "RCPB"); + memSpec->tRCab = memSpec->tCK * queryUIntParameter(timings, "RCAB"); + memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR"); + memSpec->tXSR = memSpec->tCK * queryUIntParameter(timings, "XSR"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tCCD = memSpec->tCK * queryUIntParameter(timings, "CCD"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD"); + memSpec->tRPpb = memSpec->tCK * queryUIntParameter(timings, "RPPB"); + memSpec->tRPab = memSpec->tCK * queryUIntParameter(timings, "RPAB"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR"); + memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tREFIpb = memSpec->tCK * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFCab = memSpec->tCK * queryUIntParameter(timings, "RFCAB"); + memSpec->tRFCpb = memSpec->tCK * queryUIntParameter(timings, "RFCPB"); + + // Currents and voltages + // TODO: to be completed +} + +void ConfigurationLoader::loadHBM2(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecHBM2 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; + + // MemTimings specific for HBM2 + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK"); +// memSpec->tDQSQ = memSpec->tCK * queryUIntParameter(timings, "DQSQ"); + memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD"); + memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR"); + memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL"); + memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tPL = memSpec->tCK * queryUIntParameter(timings, "PL"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL"); + memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS"); +// memSpec->tCCDR = memSpec->tCK * queryUIntParameter(timings, "CCDR"); + memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL"); + memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS"); + memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); + memSpec->tPD = memSpec->tCKE; + memSpec->tRDPDE = memSpec->tRL + memSpec->tPL + + (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->tCK; + memSpec->tWRPDE = memSpec->tWL + memSpec->tPL + + (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->tCK + memSpec->tWR; + memSpec->tWRAPDE = memSpec->tWL + memSpec->tPL + + (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->tCK + memSpec->tWR; + memSpec->tCKESR = memSpec->tCKE + memSpec->tCK; + memSpec->tRDSRE = memSpec->tRL + memSpec->tPL + + (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->tCK; + memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS"); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC"); + memSpec->tRFCSB = memSpec->tCK * queryUIntParameter(timings, "RFCSB"); + memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tREFISB = memSpec->tCK * queryUIntParameter(timings, "REFISB"); + + // Currents and voltages + // TODO: to be completed +} + +void ConfigurationLoader::loadGDDR5(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecGDDR5 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; + + // MemTimings specific for GDDR5 + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC"); + memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD"); + memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS"); + memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL"); + memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS"); + memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL"); + memSpec->tCL = memSpec->tCK * queryUIntParameter(timings, "CL"); + memSpec->tWCK2CKPIN = memSpec->tCK * queryUIntParameter(timings, "WCK2CKPIN"); + memSpec->tWCK2CK = memSpec->tCK * queryUIntParameter(timings, "WCK2CK"); + memSpec->tWCK2DQO = memSpec->tCK * queryUIntParameter(timings, "WCK2DQO"); + memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tWCK2DQI = memSpec->tCK * queryUIntParameter(timings, "WCK2DQI"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS"); + memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); + memSpec->tPD = memSpec->tCKE; + memSpec->tXPN = memSpec->tCK * queryUIntParameter(timings, "XPN"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tREFIPB = memSpec->tCK * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC"); + memSpec->tRFCPB = memSpec->tCK * queryUIntParameter(timings, "RFCPB"); + memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD"); + memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + memSpec->t32AW = memSpec->tCK * queryUIntParameter(timings, "32AW"); + memSpec->tRDSRE = memSpec->tCL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + + memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + + memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD"); + memSpec->tLK = memSpec->tCK * queryUIntParameter(timings, "LK"); + + // Currents and voltages + // TODO: to be completed +} + +void ConfigurationLoader::loadGDDR5X(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecGDDR5X *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; + + // MemTimings specific for GDDR5X + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC"); + memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD"); + memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS"); + memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL"); + memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS"); + memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tWCK2CKPIN = memSpec->tCK * queryUIntParameter(timings, "WCK2CKPIN"); + memSpec->tWCK2CK = memSpec->tCK * queryUIntParameter(timings, "WCK2CK"); + memSpec->tWCK2DQO = memSpec->tCK * queryUIntParameter(timings, "WCK2DQO"); + memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tWCK2DQI = memSpec->tCK * queryUIntParameter(timings, "WCK2DQI"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS"); + memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); + memSpec->tPD = memSpec->tCKE; + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tREFIPB = memSpec->tCK * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC"); + memSpec->tRFCPB = memSpec->tCK * queryUIntParameter(timings, "RFCPB"); + memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD"); + memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + memSpec->t32AW = memSpec->tCK * queryUIntParameter(timings, "32AW"); + memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + + memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + + memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD"); + memSpec->tLK = memSpec->tCK * queryUIntParameter(timings, "LK"); + + // Currents and voltages + // TODO: to be completed +} + +void ConfigurationLoader::loadGDDR6(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecGDDR6 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; + + // MemTimings specific for GDDR6 + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC"); + memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD"); + memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS"); + memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL"); + memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS"); + memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tWCK2CKPIN = memSpec->tCK * queryUIntParameter(timings, "WCK2CKPIN"); + memSpec->tWCK2CK = memSpec->tCK * queryUIntParameter(timings, "WCK2CK"); + memSpec->tWCK2DQO = memSpec->tCK * queryUIntParameter(timings, "WCK2DQO"); + memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tWCK2DQI = memSpec->tCK * queryUIntParameter(timings, "WCK2DQI"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS"); + memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); + memSpec->tPD = memSpec->tCKE; + memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tREFIPB = memSpec->tCK * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC"); + memSpec->tRFCPB = memSpec->tCK * queryUIntParameter(timings, "RFCPB"); + memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD"); + memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + + memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + + memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD"); + memSpec->tLK = memSpec->tCK * queryUIntParameter(timings, "LK"); + memSpec->tACTPDE = memSpec->tCK * queryUIntParameter(timings, "ACTPDE"); + memSpec->tPREPDE = memSpec->tCK * queryUIntParameter(timings, "PREPDE"); + memSpec->tREFPDE = memSpec->tCK * queryUIntParameter(timings, "REFPDE"); + + // Currents and voltages + // TODO: to be completed +} diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.h b/DRAMSys/library/src/configuration/ConfigurationLoader.h new file mode 100644 index 00000000..b5ea9290 --- /dev/null +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Janik Schlemminger + * Matthias Jung + * Lukas Steiner + */ + +#ifndef CONFIGURATIONLOADER_H +#define CONFIGURATIONLOADER_H + +#include +#include "../common/third_party/tinyxml2/tinyxml2.h" +#include "../common/utils.h" +#include "Configuration.h" + +class ConfigurationLoader +{ +public: + + static void loadMCConfig(Configuration &config, std::string amconfigUri); + static void loadMCConfig(Configuration &config, tinyxml2::XMLElement *mcconfig); + + static void loadSimConfig(Configuration &config, std::string simconfigUri); + static void loadSimConfig(Configuration &config, + tinyxml2::XMLElement *simconfig); + + static void loadMemSpec(Configuration &config, std::string memspecUri); + static void loadMemSpec(Configuration &config, tinyxml2::XMLElement *memspec); + + static void loadTemperatureSimConfig(Configuration &config, + std::string simconfigUri); + static void loadTemperatureSimConfig(Configuration &config, + tinyxml2::XMLElement *simconfig); +private: + ConfigurationLoader() {} + static void loadConfig(Configuration &config, tinyxml2::XMLElement *configNode); + static void loadConfigFromUri(Configuration &config, std::string uri, + std::string first_element); + // Loads common config of DRAMs + static void loadCommons(Configuration &config, tinyxml2::XMLElement *memspec); + // Load specific config + static void loadDDR3(Configuration &config, tinyxml2::XMLElement *memspec); + static void loadDDR4(Configuration &config, tinyxml2::XMLElement *memspec); + static void loadLPDDR4(Configuration &config, tinyxml2::XMLElement *memspec); + static void loadWideIO(Configuration &config, tinyxml2::XMLElement *memspec); + static void loadWideIO2(Configuration &config, tinyxml2::XMLElement *memspec); + static void loadHBM2(Configuration &config, tinyxml2::XMLElement *memspec); + static void loadGDDR5(Configuration &config, tinyxml2::XMLElement *memspec); + static void loadGDDR5X(Configuration &config, tinyxml2::XMLElement *memspec); + static void loadGDDR6(Configuration &config, tinyxml2::XMLElement *memspec); +}; + + +#endif // CONFIGURATIONLOADER_H diff --git a/DRAMSys/library/src/configuration/TemperatureSimConfig.h b/DRAMSys/library/src/configuration/TemperatureSimConfig.h index a0936f53..a0505bbf 100644 --- a/DRAMSys/library/src/configuration/TemperatureSimConfig.h +++ b/DRAMSys/library/src/configuration/TemperatureSimConfig.h @@ -32,7 +32,6 @@ * Authors: * Eder F. Zulian * Matthias Jung - * Luiza Correa */ #ifndef TEMPERATURESIMCONFIG_H @@ -41,13 +40,15 @@ #include #include #include + #include "../common/DebugManager.h" +#include "../common/third_party/tinyxml2/tinyxml2.h" #include "../common/utils.h" struct TemperatureSimConfig { // Temperature Scale - std::string temperatureScale; + std::string TemperatureScale; std::string pathToResources; void setPathToResources(std::string path) @@ -56,17 +57,17 @@ struct TemperatureSimConfig } // Static Temperature Simulation parameters - int staticTemperatureDefaultValue; + int StaticTemperatureDefaultValue; // Thermal Simulation parameters - double thermalSimPeriod; - enum sc_time_unit thermalSimUnit; - std::string iceServerIp; - unsigned int iceServerPort; - unsigned int simPeriodAdjustFactor; - unsigned int nPowStableCyclesToIncreasePeriod; - bool generateTemperatureMap; - bool generatePowerMap; + double ThermalSimPeriod; + enum sc_time_unit ThermalSimUnit; + std::string IceServerIp; + unsigned int IceServerPort; + unsigned int SimPeriodAdjustFactor; + unsigned int NPowStableCyclesToIncreasePeriod; + bool GenerateTemperatureMap; + bool GeneratePowerMap; // Power related information std::string powerInfoFile; @@ -78,49 +79,47 @@ struct TemperatureSimConfig PRINTDEBUGMESSAGE("TemperatureSimConfig", "Power Info File: " + powerInfoFile); powerInfoFile = pathToResources - + "/configs/thermalsim/" - + powerInfoFile; + + "/configs/thermalsim/" + + powerInfoFile; - // Load the JSON file into memory and parse it - nlohmann::json powInfoElem = parseJSON(powerInfoFile); + // Load the XML file into memory and parse it + tinyxml2::XMLDocument xml; + loadXML(powerInfoFile, xml); + tinyxml2::XMLElement *powInfoElem = xml.FirstChildElement("powerInfo"); - if (powInfoElem["powerInfo"].empty()) - { + if (powInfoElem == NULL) { // Invalid file std::string errormsg = "Invalid Power Info File " + powerInfoFile; PRINTDEBUGMESSAGE("TemperatureSimConfig", errormsg); SC_REPORT_FATAL("Temperature Sim Config", errormsg.c_str()); } - else - { - for (auto it : powInfoElem["powerInfo"].items()) - { - // Load initial power values for all devices - auto value= it.value(); - float pow = value["init_pow"]; - powerInitialValues.push_back(pow); - // Load power thresholds for all devices - //Changes in power dissipation that exceed the threshods - //will make the thermal simulation to be executed more often) - float thr = value["threshold"]; - powerThresholds.push_back(thr); - } + for (tinyxml2::XMLElement *e = powInfoElem->FirstChildElement(); e != NULL; + e = e->NextSiblingElement()) { + + // Load initial power values for all devices + std::string init_pow_str = e->Attribute("init_pow"); + float pow = std::stof(init_pow_str); + powerInitialValues.push_back(pow); + + // Load power thresholds for all devices (changes in power dissipation that exceed the threshods will make the thermal simulation to be executed more often) + std::string thr_str = e->Attribute("threshold"); + float thr = std::stof(thr_str); + powerThresholds.push_back(thr); } + showTemperatureSimConfig(); } void showTemperatureSimConfig() { int i __attribute__((unused)) = 0; - for (auto e __attribute__((unused)) : powerInitialValues) - { + for (auto e __attribute__((unused)) : powerInitialValues) { PRINTDEBUGMESSAGE("TemperatureSimConfig", "powerInitialValues[" + std::to_string(i++) + "]: " + std::to_string(e)); } i = 0; - for (auto e __attribute__((unused)) : powerThresholds) - { + for (auto e __attribute__((unused)) : powerThresholds) { PRINTDEBUGMESSAGE("TemperatureSimConfig", "powerThreshold[" + std::to_string(i++) + "]: " + std::to_string(e)); } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 3022440c..b0396643 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -41,27 +41,8 @@ #include "../Configuration.h" using namespace tlm; -using json = nlohmann::json; -MemSpec::MemSpec(json &memspec, unsigned numberOfRanks, unsigned banksPerRank, - unsigned groupsPerRank, unsigned banksPerGroup, - unsigned numberOfBanks, unsigned numberOfBankGroups) - : numberOfRanks(numberOfRanks), - banksPerRank(banksPerRank), - groupsPerRank(groupsPerRank), - banksPerGroup(banksPerGroup), - numberOfBanks(numberOfBanks), - numberOfBankGroups(numberOfBankGroups), - numberOfRows(parseUint(memspec["memarchitecturespec"]["nbrOfRows"],"nbrOfRows")), - numberOfColumns(parseUint(memspec["memarchitecturespec"]["nbrOfColumns"],"nbrOfColumns")), - burstLength(parseUint(memspec["memarchitecturespec"]["burstLength"],"burstLength")), - dataRate(parseUint(memspec["memarchitecturespec"]["dataRate"],"dataRate")), - bitWidth(parseUint(memspec["memarchitecturespec"]["width"],"width")), - fCKMHz(parseUdouble(memspec["memtimingspec"]["clkMhz"], "clkMhz")), - tCK(sc_time(1.0 / fCKMHz, SC_US)), - burstDuration(tCK * (burstLength / dataRate)), - memoryId(parseString(memspec["memoryId"], "memoryId")), - memoryType(parseString(memspec["memoryType"], "memoryType")) +MemSpec::MemSpec() { commandLengthInCycles = std::vector(numberOfCommands(), 1); } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 37185107..ff401235 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -43,30 +43,10 @@ #include "../../common/dramExtensions.h" #include "../../controller/Command.h" #include "../../common/utils.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" -class MemSpec +struct MemSpec { -public: - unsigned numberOfRanks; - unsigned banksPerRank; - unsigned groupsPerRank; - unsigned banksPerGroup; - unsigned numberOfBanks; - unsigned numberOfBankGroups; - unsigned numberOfRows; - unsigned numberOfColumns; - unsigned burstLength; - unsigned dataRate; - unsigned bitWidth; - - // Clock - double fCKMHz; - sc_time tCK; - - std::string memoryId; - std::string memoryType; - + MemSpec(); virtual ~MemSpec() {} virtual sc_time getRefreshIntervalAB() const = 0; @@ -77,14 +57,30 @@ public: sc_time getCommandLength(Command) const; -protected: - MemSpec(nlohmann::json &memspec, unsigned numberOfRanks, unsigned banksPerRank, - unsigned groupsPerRank, unsigned banksPerGroup, - unsigned numberOfBanks, unsigned numberOfBankGroups); + std::string memoryId = "not defined."; + std::string memoryType = "not defined."; + + unsigned int numberOfRanks; + unsigned int numberOfBankGroups; + unsigned int numberOfBanks; + unsigned int numberOfRows; + unsigned int numberOfColumns; + unsigned int burstLength; + unsigned int dataRate; + unsigned int bitWidth; + + unsigned int banksPerRank; + unsigned int banksPerGroup; + unsigned int groupsPerRank; + + // Clock + double fCKMHz; + sc_time tCK; - // Command lengths in cycles on bus, usually one clock cycle - std::vector commandLengthInCycles; sc_time burstDuration; + + // Command lengths on bus, usually one clock cycle + std::vector commandLengthInCycles; }; #endif // MEMSPEC_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 387ec6be..fdf88bd5 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -36,57 +36,6 @@ #include "MemSpecDDR3.h" using namespace tlm; -using json = nlohmann::json; - -MemSpecDDR3::MemSpecDDR3(json &memspec) - : MemSpec(memspec, - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), - 1, - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), - tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), - tPD (tCKE), - tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), - tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), - tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), - tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), - tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")), - tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")), - tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")), - tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")), - tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")), - tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")), - tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")), - tCCD (tCK * parseUint(memspec["memtimingspec"]["CCD"], "CCD")), - tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")), - tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")), - tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")), - tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), - tRRD (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")), - tWTR (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")), - tAL (tCK * parseUint(memspec["memtimingspec"]["AL"], "AL")), - tXPDLL (tCK * parseUint(memspec["memtimingspec"]["XPDLL"], "XPDLL")), - tXSDLL (tCK * parseUint(memspec["memtimingspec"]["XSDLL"], "XSDLL")), - tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")), - tPRPDEN (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")), - tREFPDEN (tCK * parseUint(memspec["memtimingspec"]["REFPDEN"], "REFPDEN")), - tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")), - iDD0 (parseUdouble(memspec["mempowerspec"]["idd0"], "idd0")), - iDD2N (parseUdouble(memspec["mempowerspec"]["idd2n"], "idd2n")), - iDD3N (parseUdouble(memspec["mempowerspec"]["idd3n"], "idd3n")), - iDD4R (parseUdouble(memspec["mempowerspec"]["idd4r"], "idd4r")), - iDD4W (parseUdouble(memspec["mempowerspec"]["idd4w"], "idd4w")), - iDD5 (parseUdouble(memspec["mempowerspec"]["idd5"], "idd5")), - iDD6 (parseUdouble(memspec["mempowerspec"]["idd6"], "idd6")), - vDD (parseUdouble(memspec["mempowerspec"]["vdd"], "vdd")), - iDD2P0 (parseUdouble(memspec["mempowerspec"]["idd2p0"], "idd2p0")), - iDD2P1 (parseUdouble(memspec["mempowerspec"]["idd2p1"], "idd2p1")), - iDD3P0 (parseUdouble(memspec["mempowerspec"]["idd3p0"], "idd3p0")), - iDD3P1 (parseUdouble(memspec["mempowerspec"]["idd3p1"], "idd3p1")) -{} sc_time MemSpecDDR3::getRefreshIntervalAB() const { diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index 1a68abaa..35f861c6 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -37,55 +37,46 @@ #define MEMSPECDDR3_H #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" -class MemSpecDDR3 final : public MemSpec +struct MemSpecDDR3 final : public MemSpec { -public: - MemSpecDDR3(nlohmann::json &memspec); - // Memspec Variables: - const sc_time tCKE; - const sc_time tPD; - const sc_time tCKESR; - const sc_time tRAS; - const sc_time tRC; - const sc_time tRCD; - const sc_time tRL; - const sc_time tRTP; - const sc_time tWL; - const sc_time tWR; - const sc_time tXP; - const sc_time tXS; - const sc_time tREFI; - const sc_time tRFC; - const sc_time tRP; - const sc_time tDQSCK; - const sc_time tCCD; - const sc_time tFAW; - const sc_time tRRD; - const sc_time tWTR; - const sc_time tXPDLL; - const sc_time tXSDLL; - const sc_time tAL; - const sc_time tACTPDEN; - const sc_time tPRPDEN; - const sc_time tREFPDEN; - const sc_time tRTRS; + sc_time tCKE; // min time in pdna or pdnp + sc_time tCKESR; // min time in sref + sc_time tRAS; // active-time (act -> pre same bank) + sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) + sc_time tRCD; // act -> read/write + sc_time tRL; // read latency (read command start to data strobe) + sc_time tRTP; // read to precharge + sc_time tWL; // write latency + sc_time tWR; // write recovery (write to precharge) + sc_time tXP; // min delay to row access command after pdnpx pdnax + sc_time tXS; // min delay to row access command after srefx + sc_time tREFI; + sc_time tRFC; + sc_time tRP; + sc_time tDQSCK; + sc_time tCCD; + sc_time tFAW; + sc_time tRRD; + sc_time tWTR; + sc_time tXPDLL; + sc_time tXSDLL; + sc_time tAL; // Currents and Voltages: - const double iDD0; - const double iDD2N; - const double iDD3N; - const double iDD4R; - const double iDD4W; - const double iDD5; - const double iDD6; - const double vDD; - const double iDD2P0; - const double iDD2P1; - const double iDD3P0; - const double iDD3P1; + double iDD0; + double iDD2N; + double iDD3N; + double iDD4R; + double iDD4W; + double iDD5; + double iDD6; + double vDD; + double iDD2P0; + double iDD2P1; + double iDD3P0; + double iDD3P1; virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalPB() const override; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index 5078ca0e..91d4762c 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -34,76 +34,8 @@ */ #include "MemSpecDDR4.h" -#include "../Configuration.h" using namespace tlm; -using json = nlohmann::json; - -MemSpecDDR4::MemSpecDDR4(json &memspec) - : MemSpec(memspec, - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") - / parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), - tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), - tPD (tCKE), - tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), - tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), - tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), - tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), - tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")), - tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")), - tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")), - tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")), - tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")), - tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")), - tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")), - tCCD_S (tCK * parseUint(memspec["memtimingspec"]["CCD_S"], "CCD_S")), - tCCD_L (tCK * parseUint(memspec["memtimingspec"]["CCD_L"], "CCD_L")), - tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")), - tREFI ((Configuration::getInstance().refreshMode == 1) ? - (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")) : - ((Configuration::getInstance().refreshMode == 2) ? - (tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 2)) : - (tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 4)))), - tRFC ((Configuration::getInstance().refreshMode == 1) ? - (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")) : - ((Configuration::getInstance().refreshMode == 2) ? - (tCK * (parseUint(memspec["memtimingspec"]["RFC2"], "RFC2") / 2)) : - (tCK * (parseUint(memspec["memtimingspec"]["RFC4"], "RFC4") / 4)))), - tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), - tRRD_S (tCK * parseUint(memspec["memtimingspec"]["RRD_S"], "RRD_S")), - tRRD_L (tCK * parseUint(memspec["memtimingspec"]["RRD_L"], "RRD_L")), - tWTR_S (tCK * parseUint(memspec["memtimingspec"]["WTR_S"], "WTR_S")), - tWTR_L (tCK * parseUint(memspec["memtimingspec"]["WTR_L"], "WTR_L")), - tAL (tCK * parseUint(memspec["memtimingspec"]["AL"], "AL")), - tXPDLL (tCK * parseUint(memspec["memtimingspec"]["XPDLL"], "XPDLL")), - tXSDLL (tCK * parseUint(memspec["memtimingspec"]["XSDLL"], "XSDLL")), - tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")), - tPRPDEN (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")), - tREFPDEN (tCK * parseUint(memspec["memtimingspec"]["REFPDEN"], "REFPDEN")), - tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")), - iDD0 (parseUdouble(memspec["mempowerspec"]["idd0"], "idd0")), - iDD2N (parseUdouble(memspec["mempowerspec"]["idd2n"], "idd2n")), - iDD3N (parseUdouble(memspec["mempowerspec"]["idd3n"], "idd3n")), - iDD4R (parseUdouble(memspec["mempowerspec"]["idd4r"], "idd4r")), - iDD4W (parseUdouble(memspec["mempowerspec"]["idd4w"], "idd4w")), - iDD5 (parseUdouble(memspec["mempowerspec"]["idd5"], "idd5")), - iDD6 (parseUdouble(memspec["mempowerspec"]["idd6"], "idd6")), - vDD (parseUdouble(memspec["mempowerspec"]["vdd"], "vdd")), - iDD02 (parseUdouble(memspec["mempowerspec"]["idd02"], "idd02")), - iDD2P0 (parseUdouble(memspec["mempowerspec"]["idd2p0"], "idd2p0")), - iDD2P1 (parseUdouble(memspec["mempowerspec"]["idd2p1"], "idd2p1")), - iDD3P0 (parseUdouble(memspec["mempowerspec"]["idd3p0"], "idd3p0")), - iDD3P1 (parseUdouble(memspec["mempowerspec"]["idd3p1"], "idd3p1")), - iDD62 (parseUdouble(memspec["mempowerspec"]["idd62"], "idd62")), - vDD2 (parseUdouble(memspec["mempowerspec"]["vdd2"], "vdd2")) -{} sc_time MemSpecDDR4::getRefreshIntervalAB() const { diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index 27952d23..b37ff5a6 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -37,61 +37,52 @@ #define MEMSPECDDR4_H #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" -class MemSpecDDR4 final : public MemSpec +struct MemSpecDDR4 final : public MemSpec { -public: - MemSpecDDR4(nlohmann::json &memspec); - // Memspec Variables: - const sc_time tCKE; - const sc_time tPD; - const sc_time tCKESR; - const sc_time tRAS; - const sc_time tRC; - const sc_time tRCD; - const sc_time tRL; - const sc_time tRTP; - const sc_time tWL; - const sc_time tWR; - const sc_time tXP; - const sc_time tXS; - const sc_time tREFI; - const sc_time tRFC; - const sc_time tRP; - const sc_time tDQSCK; - const sc_time tCCD_S; - const sc_time tCCD_L; - const sc_time tFAW; - const sc_time tRRD_S; - const sc_time tRRD_L; - const sc_time tWTR_S; - const sc_time tWTR_L; - const sc_time tAL; - const sc_time tXPDLL; - const sc_time tXSDLL; - const sc_time tACTPDEN; - const sc_time tPRPDEN; - const sc_time tREFPDEN; - const sc_time tRTRS; + sc_time tCKE; // min time in pdna or pdnp + sc_time tCKESR; // min time in sref + sc_time tRAS; // active-time (act -> pre same bank) + sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) + sc_time tRCD; // act -> read/write + sc_time tRL; // read latency (read command start to data strobe) + sc_time tRTP; // read to precharge + sc_time tWL; // write latency + sc_time tWR; // write recovery (write to precharge) + sc_time tXP; // min delay to row access command after pdnpx pdnax + sc_time tXS; // min delay to row access command after srefx + sc_time tREFI; + sc_time tRFC; + sc_time tRP; + sc_time tDQSCK; + sc_time tCCD_S; + sc_time tCCD_L; + sc_time tFAW; + sc_time tRRD_S; + sc_time tRRD_L; + sc_time tWTR_S; + sc_time tWTR_L; + sc_time tAL; + sc_time tXPDLL; + sc_time tXSDLL; // Currents and Voltages: - const double iDD0; - const double iDD2N; - const double iDD3N; - const double iDD4R; - const double iDD4W; - const double iDD5; - const double iDD6; - const double vDD; - const double iDD02; - const double iDD2P0; - const double iDD2P1; - const double iDD3P0; - const double iDD3P1; - const double iDD62; - const double vDD2; + double iDD0; + double iDD2N; + double iDD3N; + double iDD4R; + double iDD4W; + double iDD5; + double iDD6; + double vDD; + double iDD02; + double iDD2P0; + double iDD2P1; + double iDD3P0; + double iDD3P1; + double iDD62; + double vDD2; virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp index 66bd7f7c..6c10ec1a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp @@ -36,54 +36,6 @@ #include "MemSpecGDDR5.h" using namespace tlm; -using json = nlohmann::json; - -MemSpecGDDR5::MemSpecGDDR5(json &memspec) - : MemSpec(memspec, - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") - / parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), - tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), - tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), - tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), - tRCDRD (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")), - tRCDWR (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")), - tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")), - tRRDS (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")), - tRRDL (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")), - tCCDS (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")), - tCCDL (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")), - tCL (tCK * parseUint(memspec["memtimingspec"]["CL"], "CL")), - tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"]["WCK2CKPIN"], "WCK2CKPIN")), - tWCK2CK (tCK * parseUint(memspec["memtimingspec"]["WCK2CK"], "WCK2CK")), - tWCK2DQO (tCK * parseUint(memspec["memtimingspec"]["WCK2DQO"], "WCK2DQO")), - tRTW (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")), - tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")), - tWCK2DQI (tCK * parseUint(memspec["memtimingspec"]["WCK2DQI"], "WCK2DQI")), - tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")), - tWTRS (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")), - tWTRL (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")), - tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), - tPD (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")), - tXPN (tCK * parseUint(memspec["memtimingspec"]["XPN"], "XPN")), - tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")), - tREFIPB (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")), - tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")), - tRFCPB (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")), - tRREFD (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")), - tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")), - tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")), - t32AW (tCK * parseUint(memspec["memtimingspec"]["32AW"], "32AW")), - tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")), - tLK (tCK * parseUint(memspec["memtimingspec"]["LK"], "LK")), - tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")) -{} sc_time MemSpecGDDR5::getRefreshIntervalAB() const { diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h index 761a9201..22fb4e38 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h @@ -37,50 +37,45 @@ #define MEMSPECGDDR5_H #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" -class MemSpecGDDR5 final : public MemSpec +struct MemSpecGDDR5 final : public MemSpec { -public: - MemSpecGDDR5(nlohmann::json &memspec); - // Memspec Variables: - const sc_time tRP; - const sc_time tRAS; - const sc_time tRC; - const sc_time tRCDRD; - const sc_time tRCDWR; - const sc_time tRTP; - const sc_time tRRDS; - const sc_time tRRDL; - const sc_time tCCDS; - const sc_time tCCDL; - const sc_time tCL; - const sc_time tWCK2CKPIN; - const sc_time tWCK2CK; - const sc_time tWCK2DQO; - const sc_time tRTW; - const sc_time tWL; - const sc_time tWCK2DQI; - const sc_time tWR; - const sc_time tWTRS; - const sc_time tWTRL; - const sc_time tCKE; - const sc_time tPD; - const sc_time tXPN; - const sc_time tREFI; - const sc_time tREFIPB; - const sc_time tRFC; - const sc_time tRFCPB; - const sc_time tRREFD; - const sc_time tXS; - const sc_time tFAW; - const sc_time t32AW; -// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; -// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; - const sc_time tPPD; - const sc_time tLK; - const sc_time tRTRS; + sc_time tRP; + sc_time tRAS; + sc_time tRC; + sc_time tRCDRD; + sc_time tRCDWR; + sc_time tRTP; + sc_time tRRDS; + sc_time tRRDL; + sc_time tCCDS; + sc_time tCCDL; + sc_time tCL; + sc_time tWCK2CKPIN; + sc_time tWCK2CK; + sc_time tWCK2DQO; + sc_time tRTW; + sc_time tWL; + sc_time tWCK2DQI; + sc_time tWR; + sc_time tWTRS; + sc_time tWTRL; + sc_time tCKE; + sc_time tPD; // = tCKE; + sc_time tXPN; + sc_time tREFI; + sc_time tREFIPB; + sc_time tRFC; + sc_time tRFCPB; + sc_time tRREFD; + sc_time tXS; + sc_time tFAW; + sc_time t32AW; + sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; + sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; + sc_time tPPD; + sc_time tLK; // Currents and Voltages: // TODO: to be completed diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp index a2897967..779d4107 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp @@ -36,54 +36,6 @@ #include "MemSpecGDDR5X.h" using namespace tlm; -using json = nlohmann::json; - -MemSpecGDDR5X::MemSpecGDDR5X(json &memspec) - : MemSpec(memspec, - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") - / parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), - tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), - tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), - tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), - tRCDRD (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")), - tRCDWR (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")), - tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")), - tRRDS (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")), - tRRDL (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")), - tCCDS (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")), - tCCDL (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")), - tRL (tCK * parseUint(memspec["memtimingspec"]["CL"], "CL")), - tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"]["WCK2CKPIN"], "WCK2CKPIN")), - tWCK2CK (tCK * parseUint(memspec["memtimingspec"]["WCK2CK"], "WCK2CK")), - tWCK2DQO (tCK * parseUint(memspec["memtimingspec"]["WCK2DQO"], "WCK2DQO")), - tRTW (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")), - tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")), - tWCK2DQI (tCK * parseUint(memspec["memtimingspec"]["WCK2DQI"], "WCK2DQI")), - tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")), - tWTRS (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")), - tWTRL (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")), - tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), - tPD (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")), - tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")), - tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")), - tREFIPB (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")), - tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")), - tRFCPB (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")), - tRREFD (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")), - tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")), - tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")), - t32AW (tCK * parseUint(memspec["memtimingspec"]["32AW"], "32AW")), - tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")), - tLK (tCK * parseUint(memspec["memtimingspec"]["LK"], "LK")), - tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")) -{} sc_time MemSpecGDDR5X::getRefreshIntervalAB() const { diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h index f32b4a07..bfa2ece1 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h @@ -37,50 +37,45 @@ #define MEMSPECGDDR5X_H #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" -class MemSpecGDDR5X final : public MemSpec +struct MemSpecGDDR5X final : public MemSpec { -public: - MemSpecGDDR5X(nlohmann::json &memspec); - // Memspec Variables: - const sc_time tRP; - const sc_time tRAS; - const sc_time tRC; - const sc_time tRCDRD; - const sc_time tRCDWR; - const sc_time tRTP; - const sc_time tRRDS; - const sc_time tRRDL; - const sc_time tCCDS; - const sc_time tCCDL; - const sc_time tRL; - const sc_time tWCK2CKPIN; - const sc_time tWCK2CK; - const sc_time tWCK2DQO; - const sc_time tRTW; - const sc_time tWL; - const sc_time tWCK2DQI; - const sc_time tWR; - const sc_time tWTRS; - const sc_time tWTRL; - const sc_time tCKE; - const sc_time tPD; - const sc_time tXP; - const sc_time tREFI; - const sc_time tREFIPB; - const sc_time tRFC; - const sc_time tRFCPB; - const sc_time tRREFD; - const sc_time tXS; - const sc_time tFAW; - const sc_time t32AW; -// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; -// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; - const sc_time tPPD; - const sc_time tLK; - const sc_time tRTRS; + sc_time tRP; + sc_time tRAS; + sc_time tRC; + sc_time tRCDRD; + sc_time tRCDWR; + sc_time tRTP; + sc_time tRRDS; + sc_time tRRDL; + sc_time tCCDS; + sc_time tCCDL; + sc_time tRL; + sc_time tWCK2CKPIN; + sc_time tWCK2CK; + sc_time tWCK2DQO; + sc_time tRTW; + sc_time tWL; + sc_time tWCK2DQI; + sc_time tWR; + sc_time tWTRS; + sc_time tWTRL; + sc_time tCKE; + sc_time tPD; // = tCKE; + sc_time tXP; + sc_time tREFI; + sc_time tREFIPB; + sc_time tRFC; + sc_time tRFCPB; + sc_time tRREFD; + sc_time tXS; + sc_time tFAW; + sc_time t32AW; + sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; + sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; + sc_time tPPD; + sc_time tLK; // Currents and Voltages: // TODO: to be completed diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp index 636a3351..c3365722 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp @@ -36,56 +36,6 @@ #include "MemSpecGDDR6.h" using namespace tlm; -using json = nlohmann::json; - -MemSpecGDDR6::MemSpecGDDR6(json &memspec) - : MemSpec(memspec, - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") - / parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), - tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), - tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), - tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), - tRCDRD (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")), - tRCDWR (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")), - tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")), - tRRDS (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")), - tRRDL (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")), - tCCDS (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")), - tCCDL (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")), - tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")), - tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"]["WCK2CKPIN"], "WCK2CKPIN")), - tWCK2CK (tCK * parseUint(memspec["memtimingspec"]["WCK2CK"], "WCK2CK")), - tWCK2DQO (tCK * parseUint(memspec["memtimingspec"]["WCK2DQO"], "WCK2DQO")), - tRTW (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")), - tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")), - tWCK2DQI (tCK * parseUint(memspec["memtimingspec"]["WCK2DQI"], "WCK2DQI")), - tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")), - tWTRS (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")), - tWTRL (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")), - tPD (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")), - tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), - tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")), - tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")), - tREFIPB (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")), - tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")), - tRFCPB (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")), - tRREFD (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")), - tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")), - tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")), - tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")), - tLK (tCK * parseUint(memspec["memtimingspec"]["LK"], "LK")), - tACTPDE (tCK * parseUint(memspec["memtimingspec"]["ACTPDE"], "ACTPDE")), - tPREPDE (tCK * parseUint(memspec["memtimingspec"]["PREPDE"], "PREPDE")), - tREFPDE (tCK * parseUint(memspec["memtimingspec"]["REFPDE"], "REFPDE")), - tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")) -{} sc_time MemSpecGDDR6::getRefreshIntervalAB() const { diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h index 813381ce..88b0e491 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h @@ -37,52 +37,48 @@ #define MEMSPECGDDR6_H #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" struct MemSpecGDDR6 final : public MemSpec { -public: - MemSpecGDDR6(nlohmann::json &memspec); - // Memspec Variables: - const sc_time tRP; - const sc_time tRAS; - const sc_time tRC; - const sc_time tRCDRD; - const sc_time tRCDWR; - const sc_time tRTP; - const sc_time tRRDS; - const sc_time tRRDL; - const sc_time tCCDS; - const sc_time tCCDL; - const sc_time tRL; - const sc_time tWCK2CKPIN; - const sc_time tWCK2CK; - const sc_time tWCK2DQO; - const sc_time tRTW; - const sc_time tWL; - const sc_time tWCK2DQI; - const sc_time tWR; - const sc_time tWTRS; - const sc_time tWTRL; - const sc_time tPD; - const sc_time tCKESR; - const sc_time tXP; - const sc_time tREFI; - const sc_time tREFIPB; - const sc_time tRFC; - const sc_time tRFCPB; - const sc_time tRREFD; - const sc_time tXS; - const sc_time tFAW; -// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; -// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; - const sc_time tPPD; - const sc_time tLK; - const sc_time tACTPDE; - const sc_time tPREPDE; - const sc_time tREFPDE; - const sc_time tRTRS; + sc_time tRP; + sc_time tRAS; + sc_time tRC; + sc_time tRCDRD; + sc_time tRCDWR; + sc_time tRTP; + sc_time tRRDS; + sc_time tRRDL; + sc_time tCCDS; + sc_time tCCDL; + sc_time tRL; + sc_time tWCK2CKPIN; + sc_time tWCK2CK; + sc_time tWCK2DQO; + sc_time tRTW; + sc_time tWL; + sc_time tWCK2DQI; + sc_time tWR; + sc_time tWTRS; + sc_time tWTRL; + sc_time tCKE; + sc_time tPD; // = tCKE; + sc_time tCKESR; + sc_time tXP; + sc_time tREFI; + sc_time tREFIPB; + sc_time tRFC; + sc_time tRFCPB; + sc_time tRREFD; + sc_time tXS; + sc_time tFAW; + sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; + sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; + sc_time tPPD; + sc_time tLK; + sc_time tACTPDE; + sc_time tPREPDE; + sc_time tREFPDE; // Currents and Voltages: // TODO: to be completed diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index c8afaa93..f7898d5c 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -36,48 +36,8 @@ #include "MemSpecHBM2.h" using namespace tlm; -using json = nlohmann::json; -MemSpecHBM2::MemSpecHBM2(json &memspec) - : MemSpec(memspec, - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") - / parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), - tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), - tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), - tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), - tRCDRD (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")), - tRCDWR (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")), - tRRDL (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")), - tRRDS (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")), - tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")), - tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")), - tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), - tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")), - tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")), - tPL (tCK * parseUint(memspec["memtimingspec"]["PL"], "PL")), - tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")), - tCCDL (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")), - tCCDS (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")), - tWTRL (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")), - tWTRS (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")), - tRTW (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")), - tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")), - tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), - tPD (tCKE), - tCKESR (tCKE + tCK), - tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")), - tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")), - tRFCSB (tCK * parseUint(memspec["memtimingspec"]["RFCSB"], "RFCSB")), - tRREFD (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")), - tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")), - tREFISB (tCK * parseUint(memspec["memtimingspec"]["REFISB"], "REFISB")) +MemSpecHBM2::MemSpecHBM2() { commandLengthInCycles[Command::ACT] = 2; } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h index 33c17397..13217183 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h @@ -37,45 +37,47 @@ #define MEMSPECHBM2_H #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" -class MemSpecHBM2 final : public MemSpec +struct MemSpecHBM2 final : public MemSpec { -public: - MemSpecHBM2(nlohmann::json &memspec); + MemSpecHBM2(); // Memspec Variables: - const sc_time tDQSCK; + sc_time tDQSCK; // sc_time tDQSQ; // TODO: check actual value of this parameter - const sc_time tRC; - const sc_time tRAS; - const sc_time tRCDRD; - const sc_time tRCDWR; - const sc_time tRRDL; - const sc_time tRRDS; - const sc_time tFAW; - const sc_time tRTP; - const sc_time tRP; - const sc_time tRL; - const sc_time tWL; - const sc_time tPL; - const sc_time tWR; - const sc_time tCCDL; - const sc_time tCCDS; + sc_time tRC; + sc_time tRAS; + sc_time tRCDRD; + sc_time tRCDWR; + sc_time tRRDL; + sc_time tRRDS; + sc_time tFAW; + sc_time tRTP; + sc_time tRP; + sc_time tRL; + sc_time tWL; + sc_time tPL; + sc_time tWR; + sc_time tCCDL; + sc_time tCCDS; // sc_time tCCDR; // TODO: consecutive reads to different stack IDs - const sc_time tWTRL; - const sc_time tWTRS; - const sc_time tRTW; - const sc_time tXP; - const sc_time tCKE; - const sc_time tPD; // = tCKE; - const sc_time tCKESR; // = tCKE + tCK; - const sc_time tXS; - const sc_time tRFC; - const sc_time tRFCSB; - const sc_time tRREFD; - const sc_time tREFI; - const sc_time tREFISB; + sc_time tWTRL; + sc_time tWTRS; + sc_time tRTW; + sc_time tXP; + sc_time tCKE; + sc_time tPD; // = tCKE; + sc_time tRDPDE; // = tRL + tPL + (BurstLength / DataRate) * tCK + tCK; + sc_time tWRPDE; // = tWL + tPL + (BurstLength / DataRate) * tCK + tCK + tWR; + sc_time tWRAPDE; // = tWL + tPL + (BurstLength / DataRate) * tCK + tCK + tWR; + sc_time tCKESR; // = tCKE + tCK; + sc_time tRDSRE; // = tRL + tPL + (BurstLength / DataRate) * tCK + tCK; + sc_time tXS; + sc_time tRFC; + sc_time tRFCSB; + sc_time tRREFD; + sc_time tREFI; + sc_time tREFISB; // Currents and Voltages: // TODO: to be completed diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index c16f9b50..b0b6ee34 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -36,48 +36,8 @@ #include "MemSpecLPDDR4.h" using namespace tlm; -using json = nlohmann::json; -MemSpecLPDDR4::MemSpecLPDDR4(json &memspec) - : MemSpec(memspec, - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), - 1, - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), - tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")), - tREFIpb (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")), - tRFCab (tCK * parseUint(memspec["memtimingspec"]["RFCAB"], "RFCAB")), - tRFCpb (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")), - tRPab (tCK * parseUint(memspec["memtimingspec"]["RPAB"], "RPAB")), - tRPpb (tCK * parseUint(memspec["memtimingspec"]["RPPB"], "RPPB")), - tRCab (tCK * parseUint(memspec["memtimingspec"]["RCAB"], "RCAB")), - tRCpb (tCK * parseUint(memspec["memtimingspec"]["RCPB"], "RCPB")), - tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")), - tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), - tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")), - tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")), - tRRD (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")), - tCCD (tCK * parseUint(memspec["memtimingspec"]["CCD"], "CCD")), - tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")), - tRPST (tCK * parseUint(memspec["memtimingspec"]["RPST"], "RPST")), - tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), - tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")), - tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")), - tDQSS (tCK * parseUint(memspec["memtimingspec"]["DQSS"], "DQSS")), - tDQS2DQ (tCK * parseUint(memspec["memtimingspec"]["DQS2DQ"], "DQS2DQ")), - tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")), - tWPRE (tCK * parseUint(memspec["memtimingspec"]["WPRE"], "WPRE")), - tWTR (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")), - tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")), - tSR (tCK * parseUint(memspec["memtimingspec"]["SR"], "SR")), - tXSR (tCK * parseUint(memspec["memtimingspec"]["XSR"], "XSR")), - tESCKE (tCK * parseUint(memspec["memtimingspec"]["ESCKE"], "ESCKE")), - tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), - tCMDCKE (tCK * parseUint(memspec["memtimingspec"]["CMDCKE"], "CMDCKE")), - tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")) +MemSpecLPDDR4::MemSpecLPDDR4() { commandLengthInCycles[Command::ACT] = 4; commandLengthInCycles[Command::PRE] = 2; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index f75f0b2d..5b05150a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -37,45 +37,40 @@ #define MEMSPECLPDDR4_H #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" -class MemSpecLPDDR4 final : public MemSpec +struct MemSpecLPDDR4 final : public MemSpec { -public: - MemSpecLPDDR4(nlohmann::json &memspec); + MemSpecLPDDR4(); // Memspec Variables: - const sc_time tREFI; - const sc_time tREFIpb; - const sc_time tRFCab; - const sc_time tRFCpb; - const sc_time tRAS; - const sc_time tRPab; - const sc_time tRPpb; - const sc_time tRCpb; - const sc_time tRCab; - const sc_time tPPD; - const sc_time tRCD; - const sc_time tFAW; - const sc_time tRRD; - const sc_time tCCD; - const sc_time tRL; - const sc_time tRPST; - const sc_time tDQSCK; - const sc_time tRTP; - const sc_time tWL; - const sc_time tDQSS; - const sc_time tDQS2DQ; - const sc_time tWR; - const sc_time tWPRE; - const sc_time tWTR; - const sc_time tXP; - const sc_time tSR; - const sc_time tXSR; - const sc_time tESCKE; - const sc_time tCKE; - const sc_time tCMDCKE; - const sc_time tRTRS; + sc_time tREFI; + sc_time tREFIpb; + sc_time tRFCab; + sc_time tRFCpb; + sc_time tRPab; + sc_time tRPpb; + sc_time tPPD; + sc_time tRAS; + sc_time tRCD; + sc_time tFAW; + sc_time tRRD; + sc_time tCCD; + sc_time tRL; + sc_time tRPST; + sc_time tDQSCK; + sc_time tRTP; + sc_time tWL; + sc_time tDQSS; + sc_time tDQS2DQ; + sc_time tWR; + sc_time tWPRE; + sc_time tWTR; + sc_time tXP; + sc_time tSR; + sc_time tXSR; + sc_time tESCKE; + sc_time tCKE; + sc_time tCMDCKE; // Currents and Voltages: // TODO: to be completed diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index ecbcb202..314a4df1 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -36,63 +36,6 @@ #include "MemSpecWideIO.h" using namespace tlm; -using json = nlohmann::json; - -MemSpecWideIO::MemSpecWideIO(json &memspec) - : MemSpec(memspec, - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), - 1, - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), - tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), - tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), - tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), - tAC (tCK * parseUint(memspec["memtimingspec"]["AC"], "AC")), - tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), - tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), - tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")), - tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")), - tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")), - tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")), - tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")), - tXSR (tCK * parseUint(memspec["memtimingspec"]["XSR"], "XSR")), - tCCD_R (tCK * parseUint(memspec["memtimingspec"]["CCD_R"], "CCD_R")), - tCCD_W (tCK * parseUint(memspec["memtimingspec"]["CCD_W"], "CCD_W")), - tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")), - tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")), - tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), - tRRD (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")), - tTAW (tCK * parseUint(memspec["memtimingspec"]["TAW"], "TAW")), - tWTR (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")), - tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")), - iDD0 (parseUdouble(memspec["mempowerspec"]["idd0"], "idd0")), - iDD2N (parseUdouble(memspec["mempowerspec"]["idd2n"], "idd2n")), - iDD3N (parseUdouble(memspec["mempowerspec"]["idd3n"], "idd3n")), - iDD4R (parseUdouble(memspec["mempowerspec"]["idd4r"], "idd4r")), - iDD4W (parseUdouble(memspec["mempowerspec"]["idd4w"], "idd4w")), - iDD5 (parseUdouble(memspec["mempowerspec"]["idd5"], "idd5")), - iDD6 (parseUdouble(memspec["mempowerspec"]["idd6"], "idd6")), - vDD (parseUdouble(memspec["mempowerspec"]["vdd"], "vdd")), - iDD02 (parseUdouble(memspec["mempowerspec"]["idd02"], "idd02")), - iDD2P0 (parseUdouble(memspec["mempowerspec"]["idd2p0"], "idd2p0")), - iDD2P02 (parseUdouble(memspec["mempowerspec"]["idd2p02"], "idd2p02")), - iDD2P1 (parseUdouble(memspec["mempowerspec"]["idd2p1"], "idd2p1")), - iDD2P12 (parseUdouble(memspec["mempowerspec"]["idd2p12"], "idd2p12")), - iDD2N2 (parseUdouble(memspec["mempowerspec"]["idd2n2"], "idd2n2")), - iDD3P0 (parseUdouble(memspec["mempowerspec"]["idd3p0"], "idd3p0")), - iDD3P02 (parseUdouble(memspec["mempowerspec"]["idd3p02"], "idd3p02")), - iDD3P1 (parseUdouble(memspec["mempowerspec"]["idd3p1"], "idd3p1")), - iDD3P12 (parseUdouble(memspec["mempowerspec"]["idd3p12"], "idd3p12")), - iDD3N2 (parseUdouble(memspec["mempowerspec"]["idd3n2"], "idd3n2")), - iDD4R2 (parseUdouble(memspec["mempowerspec"]["idd4r2"], "idd4r2")), - iDD4W2 (parseUdouble(memspec["mempowerspec"]["idd4w2"], "idd4w2")), - iDD52 (parseUdouble(memspec["mempowerspec"]["idd52"], "idd52")), - iDD62 (parseUdouble(memspec["mempowerspec"]["idd62"], "idd62")), - vDD2 (parseUdouble(memspec["mempowerspec"]["vdd2"], "vdd2")) -{} sc_time MemSpecWideIO::getRefreshIntervalAB() const { diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index 490804ef..0886ef17 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -37,61 +37,56 @@ #define MEMSPECWIDEIO_H #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" -class MemSpecWideIO final : public MemSpec +struct MemSpecWideIO final : public MemSpec { -public: - MemSpecWideIO(nlohmann::json &memspec); - // Memspec Variables: - const sc_time tCKE; - const sc_time tCKESR; - const sc_time tRAS; - const sc_time tRC; - const sc_time tRCD; - const sc_time tRL; - const sc_time tWL; - const sc_time tWR; - const sc_time tXP; - const sc_time tXSR; - const sc_time tREFI; - const sc_time tRFC; - const sc_time tRP; - const sc_time tDQSCK; - const sc_time tAC; - const sc_time tCCD_R; - const sc_time tCCD_W; - const sc_time tRRD; - const sc_time tTAW; - const sc_time tWTR; - const sc_time tRTRS; + sc_time tCKE; // min time in pdna or pdnp + sc_time tCKESR; // min time in sref + sc_time tRAS; // active-time (act -> pre same bank) + sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) + sc_time tRCD; // act -> read/write + sc_time tRL; // read latency (read command start to data strobe) + sc_time tWL; // write latency + sc_time tWR; // write recovery (write to precharge) + sc_time tXP; // min delay to row access command after pdnpx pdnax + sc_time tXS; // min delay to row access command after srefx + sc_time tREFI; + sc_time tRFC; + sc_time tRP; + sc_time tDQSCK; + sc_time tAC; + sc_time tCCD_R; + sc_time tCCD_W; + sc_time tRRD; + sc_time tTAW; + sc_time tWTR; // Currents and Voltages: - const double iDD0; - const double iDD2N; - const double iDD3N; - const double iDD4R; - const double iDD4W; - const double iDD5; - const double iDD6; - const double vDD; - const double iDD02; - const double iDD2P0; - const double iDD2P02; - const double iDD2P1; - const double iDD2P12; - const double iDD2N2; - const double iDD3P0; - const double iDD3P02; - const double iDD3P1; - const double iDD3P12; - const double iDD3N2; - const double iDD4R2; - const double iDD4W2; - const double iDD52; - const double iDD62; - const double vDD2; + double iDD0; + double iDD2N; + double iDD3N; + double iDD4R; + double iDD4W; + double iDD5; + double iDD6; + double vDD; + double iDD02; + double iDD2P0; + double iDD2P02; + double iDD2P1; + double iDD2P12; + double iDD2N2; + double iDD3P0; + double iDD3P02; + double iDD3P1; + double iDD3P12; + double iDD3N2; + double iDD4R2; + double iDD4W2; + double iDD52; + double iDD62; + double vDD2; virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp index 91e27078..b19e6f96 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -36,45 +36,6 @@ #include "MemSpecWideIO2.h" using namespace tlm; -using json = nlohmann::json; - -MemSpecWideIO2::MemSpecWideIO2(json &memspec) - : MemSpec(memspec, - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), - 1, - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), - tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), - tDQSS (tCK * parseUint(memspec["memtimingspec"]["DQSS"], "DQSS")), - tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), - tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")), - tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")), - tRCpb (tCK * parseUint(memspec["memtimingspec"]["RCPB"], "RCPB")), - tRCab (tCK * parseUint(memspec["memtimingspec"]["RCAB"], "RCAB")), - tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), - tXSR (tCK * parseUint(memspec["memtimingspec"]["XSR"], "XSR")), - tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")), - tCCD (tCK * parseUint(memspec["memtimingspec"]["CCD"], "CCD")), - tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")), - tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")), - tRPpb (tCK * parseUint(memspec["memtimingspec"]["RPPB"], "RPPB")), - tRPab (tCK * parseUint(memspec["memtimingspec"]["RPAB"], "RPAB")), - tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), - tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")), - tWTR (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")), - tRRD (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")), - tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")), - tREFI (tCK * (unsigned)(parseUint(memspec["memtimingspec"]["REFI"], "REFI") - * parseUdouble(memspec["memtimingspec"]["REFM"], "REFM"))), - tREFIpb (tCK * (unsigned)(parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB") - * parseUdouble(memspec["memtimingspec"]["REFM"], "REFM"))), - tRFCab (tCK * parseUint(memspec["memtimingspec"]["RFCAB"], "RFCAB")), - tRFCpb (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")), - tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")) -{} sc_time MemSpecWideIO2::getRefreshIntervalAB() const { diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h index 5e32c644..bd432a8f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h @@ -37,39 +37,34 @@ #define MEMSPECWIDEIO2_H #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" -class MemSpecWideIO2 final : public MemSpec +struct MemSpecWideIO2 final : public MemSpec { -public: - MemSpecWideIO2(nlohmann::json &memspec); - // Memspec Variables: - const sc_time tDQSCK; - const sc_time tDQSS; - const sc_time tCKE; - const sc_time tRL; - const sc_time tWL; - const sc_time tRCpb; - const sc_time tRCab; - const sc_time tCKESR; - const sc_time tXSR; - const sc_time tXP; - const sc_time tCCD; - const sc_time tRTP; - const sc_time tRCD; - const sc_time tRPpb; - const sc_time tRPab; - const sc_time tRAS; - const sc_time tWR; - const sc_time tWTR; - const sc_time tRRD; - const sc_time tFAW; - const sc_time tREFI; - const sc_time tREFIpb; - const sc_time tRFCab; - const sc_time tRFCpb; - const sc_time tRTRS; + sc_time tDQSCK; + sc_time tDQSS; + sc_time tCKE; + sc_time tRL; + sc_time tWL; + sc_time tRCpb; + sc_time tRCab; + sc_time tCKESR; + sc_time tXSR; + sc_time tXP; + sc_time tCCD; + sc_time tRTP; + sc_time tRCD; + sc_time tRPpb; + sc_time tRPab; + sc_time tRAS; + sc_time tWR; + sc_time tWTR; + sc_time tRRD; + sc_time tFAW; + sc_time tREFI; + sc_time tREFIpb; + sc_time tRFCab; + sc_time tRFCpb; // Currents and Voltages: // TODO: to be completed diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index 9b43125c..88e64544 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -43,7 +43,7 @@ using namespace DRAMPower; std::string commandToString(Command command) { - assert(command >= Command::NOP && command <= Command::SREFEX); + assert(command >= 0 && command <= 15); static std::array stringOfCommand = {"NOP", "RD", @@ -71,7 +71,7 @@ unsigned numberOfCommands() tlm_phase commandToPhase(Command command) { - assert(command >= Command::NOP && command <= Command::SREFEX); + assert(command >= 0 && command <= 15); static std::array phaseOfCommand = {UNINITIALIZED_PHASE, BEGIN_RD, @@ -94,7 +94,7 @@ tlm_phase commandToPhase(Command command) Command phaseToCommand(tlm_phase phase) { - assert(phase >= BEGIN_RD && phase <= END_SREF); + assert(phase >= 5 && phase <= 19); static std::array commandOfPhase = {Command::RD, Command::WR, @@ -111,12 +111,12 @@ Command phaseToCommand(tlm_phase phase) Command::PDXP, Command::SREFEN, Command::SREFEX}; - return commandOfPhase[phase - BEGIN_RD]; + return commandOfPhase[phase - 5]; } MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase) { - assert(phase >= BEGIN_RD && phase <= END_SREF); + assert(phase >= 5 && phase <= 19); static std::array phaseOfCommand = {MemCommand::RD, MemCommand::WR, @@ -133,40 +133,40 @@ MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase) MemCommand::PUP_PRE, MemCommand::SREN, MemCommand::SREX}; - return phaseOfCommand[phase - BEGIN_RD]; + return phaseOfCommand[phase - 5]; } bool phaseNeedsEnd(tlm_phase phase) { - return (phase >= BEGIN_RD && phase <= BEGIN_REFA); + return (phase >= 5 && phase <= 13); } tlm_phase getEndPhase(tlm_phase phase) { - assert(phase >= BEGIN_RD && phase <= BEGIN_REFA); + assert(phase >= 5 && phase <= 13); return (phase + 15); } bool isBankCommand(Command command) { - assert(command >= Command::NOP && command <= Command::SREFEX); - return (command <= Command::REFB); + assert(command >= 0 && command <= 15); + return (command <= 7); } bool isRankCommand(Command command) { - assert(command >= Command::NOP && command <= Command::SREFEX); - return (command >= Command::PREA); + assert(command >= 0 && command <= 15); + return (command >= 8); } bool isCasCommand(Command command) { - assert(command >= Command::NOP && command <= Command::SREFEX); - return (command <= Command::WRA); + assert(command >= 0 && command <= 15); + return (command <= 4); } bool isRasCommand(Command command) { - assert(command >= Command::NOP && command <= Command::SREFEX); - return (command >= Command::PRE); + assert(command >= 0 && command <= 15); + return (command >= 5); } diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 6a0a4f0e..e0190723 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -333,23 +333,25 @@ void Controller::controllerMethod() tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { - sc_time notificationDelay = delay + Configuration::getInstance().memSpec->tCK; + sc_time notificationDelay = delay; if (phase == BEGIN_REQ) { + notificationDelay += Configuration::getInstance().memSpec->tCK; payloadToAcquire = &trans; timeToAcquire = sc_time_stamp() + notificationDelay; beginReqEvent.notify(notificationDelay); } else if (phase = END_RESP) { + notificationDelay += Configuration::getInstance().memSpec->tCK; timeToRelease = sc_time_stamp() + notificationDelay; endRespEvent.notify(notificationDelay); } else SC_REPORT_FATAL("Controller", "nb_transport_fw in controller was triggered with unknown phase"); - PRINTDEBUGMESSAGE(name(), "[fw] " + std::string(phase.get_name()) + " notification in " + + PRINTDEBUGMESSAGE(name(), "[fw] " + phaseNameToString(phase) + " notification in " + notificationDelay.to_string()); return TLM_ACCEPTED; @@ -362,9 +364,10 @@ tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &, return TLM_ACCEPTED; } -unsigned int Controller::transport_dbg(tlm_generic_payload &trans) +unsigned int Controller::transport_dbg(tlm_generic_payload &) { - return iSocket->transport_dbg(trans); + SC_REPORT_FATAL("Controller", "Debug Transport not supported"); + return 0; } void Controller::finishBeginReq() diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index e4a36e61..bcfbc836 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -44,11 +44,11 @@ tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans, return Controller::nb_transport_fw(trans, phase, delay); } -tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &, - tlm_phase &, sc_time &) +tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &trans, + tlm_phase &phase, sc_time &delay) { - SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called"); - return TLM_ACCEPTED; + recordPhase(trans, phase, delay); + return Controller::nb_transport_bw(trans, phase, delay); } void ControllerRecordable::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase) @@ -80,7 +80,7 @@ void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase pha unsigned int col __attribute__((unused)) = DramExtension::getExtension(trans).getColumn().ID(); uint64_t id __attribute__((unused)) = DramExtension::getExtension(trans).getPayloadID(); - PRINTDEBUGMESSAGE(name(), "Recording " + std::string(phase.get_name()) + " thread " + + PRINTDEBUGMESSAGE(name(), "Recording " + phaseNameToString(phase) + " thread " + std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string( bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " + std::to_string(col) + " id " + std::to_string(id) + " at " + recTime.to_string()); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 9a9fca19..1daf2dee 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -47,17 +47,7 @@ CheckerDDR3::CheckerDDR3() (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - last4Activates = std::vector>(memSpec->numberOfRanks); - - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; - tRDWR = memSpec->tRL + tBURST + 2 * memSpec->tCK - memSpec->tWL; - tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; - tWRRD = memSpec->tWL + tBURST + memSpec->tWTR; - tWRRD_R = memSpec->tWL + tBURST + memSpec->tRTRS - memSpec->tRL; - tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; - tRDPDEN = memSpec->tRL + tBURST + memSpec->tCK; - tWRPDEN = memSpec->tWL + tBURST + memSpec->tWR; - tWRAPDEN = memSpec->tWL + tBURST + memSpec->tWR + memSpec->tCK; + lastActivates = std::vector>(memSpec->numberOfRanks); } sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const @@ -65,50 +55,86 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); - if (command == Command::RD || command == Command::RDA) + if (command == Command::ACT) { + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD - memSpec->tAL); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + +// lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); + + if (lastActivates[rank.ID()].size() >= 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); + } + else if (command == Command::RD || command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); + + lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + lastCommandStart = lastScheduledByCommand[Command::RDA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; + lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTR); if (command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); } - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD); - - lastCommandStart = lastScheduledByCommand[Command::WR]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD); - lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTR); lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -121,41 +147,26 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr else if (command == Command::WR || command == Command::WRA) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD - memSpec->tAL); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; + lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + memSpec->burstDuration + 2 * memSpec->tCK - memSpec->tWL); - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; + lastCommandStart = lastScheduledByCommand[Command::RDA]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + memSpec->burstDuration + 2 * memSpec->tCK - memSpec->tWL); - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; + lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ? lastScheduledByCommand[Command::WR] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ? lastScheduledByCommand[Command::WRA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); @@ -164,64 +175,19 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSDLL); } - else if (command == Command::ACT) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD); - - lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tAL + memSpec->tRTP + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - - if (last4Activates[rank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); - } else if (command == Command::PRE) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tAL + memSpec->tRTP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -230,24 +196,25 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr else if (command == Command::PREA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tAL + memSpec->tRTP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tAL + memSpec->tRTP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -261,11 +228,12 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tAL + memSpec->tRTP + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -275,43 +243,39 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); } else if (command == Command::PDEA) { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tACTPDEN); - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + 5 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + 5 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPDEN); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + 4 * memSpec->tCK + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPRPDEN); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + 5 * memSpec->tCK + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -321,38 +285,29 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr { lastCommandStart = lastScheduledByCommandAndRank[Command::PDEA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); } else if (command == Command::PDEP) { lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + 5 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + 5 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPRPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPRPDEN); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + 5 * memSpec->tCK + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFPDEN); - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); @@ -361,21 +316,19 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr { lastCommandStart = lastScheduledByCommandAndRank[Command::PDEP][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); } else if (command == Command::SREFEN) { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + std::max(tRDPDEN, memSpec->tAL + memSpec->tRTP + memSpec->tRP)); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + std::max(memSpec->tRL + 5 * memSpec->tCK, memSpec->tAL + memSpec->tRTP + memSpec->tRP)); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + std::max(tWRAPDEN, tWRPRE + memSpec->tRP)); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + std::max(memSpec->tWL + 5 * memSpec->tCK + memSpec->tWR, memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP)); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -404,8 +357,9 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKESR); } else - SC_REPORT_FATAL("CheckerDDR3", "Unknown command!"); + reportFatal("CheckerDDR3", "Unknown command!"); + // Check if command bus is free earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); return earliestTimeToStart; @@ -416,16 +370,15 @@ void CheckerDDR3::insert(Command command, Rank rank, BankGroup, Bank bank) PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); - lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); + lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); - lastCommandOnBus = sc_time_stamp(); if (command == Command::ACT) { - if (last4Activates[rank.ID()].size() == 4) - last4Activates[rank.ID()].pop(); - last4Activates[rank.ID()].push(sc_time_stamp()); + if (lastActivates[rank.ID()].size() == 4) + lastActivates[rank.ID()].pop(); + lastActivates[rank.ID()].push(sc_time_stamp()); } } diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index f1fb5c2a..bf86b726 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -57,17 +57,7 @@ private: sc_time lastCommandOnBus; // Four activate window - std::vector> last4Activates; - - sc_time tBURST; - sc_time tRDWR; - sc_time tRDWR_R; - sc_time tWRRD; - sc_time tWRPRE; - sc_time tWRRD_R; - sc_time tRDPDEN; - sc_time tWRPDEN; - sc_time tWRAPDEN; + std::vector> lastActivates; }; #endif // CHECKERDDR3_H diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index faa5bde8..143d5b90 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -49,18 +49,7 @@ CheckerDDR4::CheckerDDR4() (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - last4Activates = std::vector>(memSpec->numberOfRanks); - - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; - tRDWR = memSpec->tRL + tBURST - memSpec->tWL + 2 * memSpec->tCK; - tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; - tWRRD_S = memSpec->tWL + tBURST + memSpec->tWTR_S; - tWRRD_L = memSpec->tWL + tBURST + memSpec->tWTR_L; - tWRRD_R = memSpec->tWL + tBURST + memSpec->tRTRS - memSpec->tRL; - tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; - tRDPDEN = memSpec->tRL + tBURST + memSpec->tCK; - tWRPDEN = memSpec->tWL + tBURST + memSpec->tWR; - tWRAPDEN = memSpec->tWL + tBURST + memSpec->tCK + memSpec->tWR; + lastActivates = std::vector>(memSpec->numberOfRanks); } sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const @@ -68,131 +57,25 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); - if (command == Command::RD || command == Command::RDA) + if (command == Command::ACT) { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD - memSpec->tAL); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - if (command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP); - } - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_S); - - lastCommandStart = lastScheduledByCommand[Command::WR]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_S); - - lastCommandStart = lastScheduledByCommand[Command::WRA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSDLL); - } - else if (command == Command::WR || command == Command::WRA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD - memSpec->tAL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR); - - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S); - - lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ? lastScheduledByCommand[Command::WR] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S); - - lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ? lastScheduledByCommand[Command::WRA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSDLL); - } - else if (command == Command::ACT) - { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); @@ -205,84 +88,129 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD_S); - lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tAL + memSpec->tRTP + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); + if (lastActivates[rank.ID()].size() >= 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); + } + else if (command == Command::RD || command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - if (last4Activates[rank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + memSpec->burstDuration + memSpec->tWTR_L); + + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); + } + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + memSpec->burstDuration + memSpec->tWTR_S); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + memSpec->burstDuration + memSpec->tWTR_L); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + memSpec->burstDuration + memSpec->tWTR_S); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + + memSpec->burstDuration + 2 * memSpec->tCK - memSpec->tWL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + + memSpec->burstDuration + 2 * memSpec->tCK - memSpec->tWL); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S); } else if (command == Command::PRE) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tAL + memSpec->tRTP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + memSpec->burstDuration + memSpec->tWR); } else if (command == Command::PREA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tAL + memSpec->tRTP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tAL + memSpec->tRTP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + memSpec->burstDuration + memSpec->tWR); } else if (command == Command::REFA) { @@ -292,11 +220,12 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tAL + memSpec->tRTP + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -306,137 +235,14 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - } - else if (command == Command::PDEA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tACTPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPRPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - } - else if (command == Command::PDXA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD); - } - else if (command == Command::PDEP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPRPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPRPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - } - else if (command == Command::PDXP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD); - } - else if (command == Command::SREFEN) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + std::max(tRDPDEN, memSpec->tAL + memSpec->tRTP + memSpec->tRP)); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + std::max(tWRAPDEN, tWRPRE + memSpec->tRP)); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - } - else if (command == Command::SREFEX) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEN][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKESR); } else - SC_REPORT_FATAL("CheckerDDR4", "Unknown command!"); + reportFatal("CheckerDDR4", "Unknown command!"); + // Check if command bus is free earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); return earliestTimeToStart; @@ -455,8 +261,8 @@ void CheckerDDR4::insert(Command command, Rank rank, BankGroup bankgroup, Bank b if (command == Command::ACT) { - if (last4Activates[rank.ID()].size() == 4) - last4Activates[rank.ID()].pop(); - last4Activates[rank.ID()].push(sc_time_stamp()); + if (lastActivates[rank.ID()].size() == 4) + lastActivates[rank.ID()].pop(); + lastActivates[rank.ID()].push(sc_time_stamp()); } } diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.h b/DRAMSys/library/src/controller/checker/CheckerDDR4.h index b8eb4017..3f14d754 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.h @@ -58,20 +58,7 @@ private: sc_time lastCommandOnBus; // Four activate window - std::vector> last4Activates; - - sc_time tBURST; - sc_time tRDWR; - sc_time tRDWR_R; - sc_time tWRRD_S; - sc_time tWRRD_L; - sc_time tWRRD_R; - sc_time tRDAACT; - sc_time tWRPRE; - sc_time tWRAACT; - sc_time tRDPDEN; - sc_time tWRPDEN; - sc_time tWRAPDEN; + std::vector> lastActivates; }; #endif // CHECKERDDR4_H diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp index 962f6795..d8b3c522 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp @@ -51,17 +51,6 @@ CheckerGDDR5::CheckerGDDR5() last4Activates = std::vector>(memSpec->numberOfRanks); last32Activates = std::vector>(memSpec->numberOfRanks); - - bankwiseRefreshCounter = std::vector(memSpec->numberOfRanks); - - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; - tRDSRE = memSpec->tCL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQO + tBURST; - tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQI + tBURST; - tRDWR_R = memSpec->tCL + tBURST + memSpec->tRTRS - memSpec->tWL; - tWRRD_R = memSpec->tWL + tBURST + memSpec->tRTRS - memSpec->tCL; - tWRRD_S = memSpec->tWL + tBURST + memSpec->tWTRS; - tWRRD_L = memSpec->tWL + tBURST + memSpec->tWTRL; - tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; } sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const @@ -69,130 +58,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); - if (command == Command::RD || command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - if (command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP); - } - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_S); - - lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ? lastScheduledByCommand[Command::WR] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_S); - - lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ? lastScheduledByCommand[Command::WRA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXPN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tLK); - } - else if (command == Command::WR || command == Command::WRA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ? lastScheduledByCommand[Command::WR] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ? lastScheduledByCommand[Command::WRA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXPN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tLK); - } - else if (command == Command::ACT) + if (command == Command::ACT) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -212,7 +78,8 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -222,14 +89,6 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXPN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXPN); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); @@ -242,21 +101,94 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - - if (last4Activates[rank.ID()].size() >= 4) + if (last4Activates[rank.ID()].size() == 4) earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); - if (last32Activates[rank.ID()].size() >= 32) + if (last32Activates[rank.ID()].size() == 32) earliestTimeToStart = std::max(earliestTimeToStart, last32Activates[rank.ID()].front() + memSpec->t32AW); } + else if (command == Command::RD || command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); + + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); + } + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + } else if (command == Command::PRE) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -264,21 +196,17 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXPN); } else if (command == Command::PREA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -290,23 +218,17 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXPN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); } else if (command == Command::REFA) { @@ -320,7 +242,8 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -330,21 +253,9 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXPN); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); } else if (command == Command::REFB) { @@ -366,158 +277,36 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXPN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXPN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); +// lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB); lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) { - if (bankwiseRefreshCounter[rank.ID()] == 0) + if (bankwiseRefreshCounter == 0) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); } - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - - if (last4Activates[rank.ID()].size() >= 4) + if (last4Activates[rank.ID()].size() == 4) earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); - if (last32Activates[rank.ID()].size() >= 32) + if (last32Activates[rank.ID()].size() == 32) earliestTimeToStart = std::max(earliestTimeToStart, last32Activates[rank.ID()].front() + memSpec->t32AW); } - else if (command == Command::PDEA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXPN); - } - else if (command == Command::PDXA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD); - } - else if (command == Command::PDEP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXPN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - } - else if (command == Command::PDXP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD); - } - else if (command == Command::SREFEN) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + std::max(memSpec->tRTP + memSpec->tRP, tRDSRE)); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXPN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - } - else if (command == Command::SREFEX) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEN][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - } else - SC_REPORT_FATAL("CheckerGDDR5", "Unknown command!"); - + { + reportFatal("CheckerGDDR5", "Unknown command!"); + } // Check if command bus is free earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); @@ -547,5 +336,5 @@ void CheckerGDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank } if (command == Command::REFB) - bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank; + bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->banksPerRank; } diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h index 45292c23..937fd853 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h @@ -55,23 +55,13 @@ private: std::vector> lastScheduledByCommandAndBankGroup; std::vector> lastScheduledByCommandAndRank; std::vector lastScheduledByCommand; - sc_time lastCommandOnBus; // 4 and 32 activate window std::vector> last4Activates; std::vector> last32Activates; - std::vector bankwiseRefreshCounter; - - sc_time tBURST; - sc_time tRDSRE; - sc_time tWRSRE; - sc_time tRDWR_R; - sc_time tWRRD_S; - sc_time tWRRD_L; - sc_time tWRRD_R; - sc_time tWRPRE; + unsigned bankwiseRefreshCounter = 0; }; #endif // CHECKERGDDR5_H diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp index 5ae1adbb..7c7d51aa 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp @@ -51,17 +51,6 @@ CheckerGDDR5X::CheckerGDDR5X() last4Activates = std::vector>(memSpec->numberOfRanks); last32Activates = std::vector>(memSpec->numberOfRanks); - - bankwiseRefreshCounter = std::vector(memSpec->numberOfRanks); - - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; - tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQO + tBURST; - tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQI + tBURST; - tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; - tWRRD_R = memSpec->tWL + tBURST + memSpec->tRTRS - memSpec->tRL; - tWRRD_S = memSpec->tWL + tBURST + memSpec->tWTRS; - tWRRD_L = memSpec->tWL + tBURST + memSpec->tWTRL; - tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; } sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const @@ -69,130 +58,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); - if (command == Command::RD || command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - if (command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP); - } - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_S); - - lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ? lastScheduledByCommand[Command::WR] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_S); - - lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ? lastScheduledByCommand[Command::WRA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tLK); - } - else if (command == Command::WR || command == Command::WRA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ? lastScheduledByCommand[Command::WR] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ? lastScheduledByCommand[Command::WRA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tLK); - } - else if (command == Command::ACT) + if (command == Command::ACT) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -212,7 +78,8 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -222,14 +89,6 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); @@ -242,21 +101,94 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - - if (last4Activates[rank.ID()].size() >= 4) + if (last4Activates[rank.ID()].size() == 4) earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); - if (last32Activates[rank.ID()].size() >= 32) + if (last32Activates[rank.ID()].size() == 32) earliestTimeToStart = std::max(earliestTimeToStart, last32Activates[rank.ID()].front() + memSpec->t32AW); } + else if (command == Command::RD || command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); + + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); + } + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + } else if (command == Command::PRE) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -264,21 +196,17 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); } else if (command == Command::PREA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -290,23 +218,17 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); } else if (command == Command::REFA) { @@ -320,7 +242,8 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -330,21 +253,9 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); } else if (command == Command::REFB) { @@ -366,158 +277,36 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); +// lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB); lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) { - if (bankwiseRefreshCounter[rank.ID()] == 0) + if (bankwiseRefreshCounter == 0) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); } - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - - if (last4Activates[rank.ID()].size() >= 4) + if (last4Activates[rank.ID()].size() == 4) earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); - if (last32Activates[rank.ID()].size() >= 32) + if (last32Activates[rank.ID()].size() == 32) earliestTimeToStart = std::max(earliestTimeToStart, last32Activates[rank.ID()].front() + memSpec->t32AW); } - else if (command == Command::PDEA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - } - else if (command == Command::PDXA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD); - } - else if (command == Command::PDEP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - } - else if (command == Command::PDXP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD); - } - else if (command == Command::SREFEN) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + std::max(memSpec->tRTP + memSpec->tRP, tRDSRE)); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - } - else if (command == Command::SREFEX) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEN][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - } else - SC_REPORT_FATAL("CheckerGDDR5X", "Unknown command!"); - + { + reportFatal("CheckerGDDR5X", "Unknown command!"); + } // Check if command bus is free earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); @@ -547,5 +336,5 @@ void CheckerGDDR5X::insert(Command command, Rank rank, BankGroup bankgroup, Bank } if (command == Command::REFB) - bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank; + bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->banksPerRank; } diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h index 5b55d281..8f838914 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h @@ -55,23 +55,13 @@ private: std::vector> lastScheduledByCommandAndBankGroup; std::vector> lastScheduledByCommandAndRank; std::vector lastScheduledByCommand; - sc_time lastCommandOnBus; // 4 and 32 activate window std::vector> last4Activates; std::vector> last32Activates; - std::vector bankwiseRefreshCounter; - - sc_time tBURST; - sc_time tRDSRE; - sc_time tWRSRE; - sc_time tRDWR_R; - sc_time tWRRD_S; - sc_time tWRRD_L; - sc_time tWRRD_R; - sc_time tWRPRE; + unsigned bankwiseRefreshCounter = 0; }; #endif // CHECKERGDDR5X_H diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp index 38ef3555..74abbf99 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp @@ -49,18 +49,7 @@ CheckerGDDR6::CheckerGDDR6() (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - last4Activates = std::vector>(memSpec->numberOfRanks); - - bankwiseRefreshCounter = std::vector(memSpec->numberOfRanks); - - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; - tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQO + tBURST; - tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQI + tBURST; - tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; - tWRRD_R = memSpec->tWL + tBURST + memSpec->tRTRS - memSpec->tRL; - tWRRD_S = memSpec->tWL + tBURST + memSpec->tWTRS; - tWRRD_L = memSpec->tWL + tBURST + memSpec->tWTRL; - tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; + lastActivates = std::vector>(memSpec->numberOfRanks); } sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const @@ -68,130 +57,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); - if (command == Command::RD || command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - if (command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP); - } - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_S); - - lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ? lastScheduledByCommand[Command::WR] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_L); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_S); - - lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ? lastScheduledByCommand[Command::WRA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tLK); - } - else if (command == Command::WR || command == Command::WRA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ? lastScheduledByCommand[Command::WR] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ? lastScheduledByCommand[Command::WRA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tLK); - } - else if (command == Command::ACT) + if (command == Command::ACT) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -211,7 +77,8 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -221,14 +88,6 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); @@ -241,18 +100,91 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); + } + else if (command == Command::RD || command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); - if (last4Activates[rank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); + + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); + } + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); } else if (command == Command::PRE) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -260,21 +192,17 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); } else if (command == Command::PREA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -286,23 +214,17 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); } else if (command == Command::REFA) { @@ -316,7 +238,8 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -326,21 +249,9 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); } else if (command == Command::REFB) { @@ -362,183 +273,33 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); +// lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB); lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) { - if (bankwiseRefreshCounter[rank.ID()] == 0) + if (bankwiseRefreshCounter == 0) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); } - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - - if (last4Activates[rank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); - } - else if (command == Command::PDEA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tACTPDE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPREPDE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFPDE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - } - else if (command == Command::PDXA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD); - } - else if (command == Command::PDEP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPREPDE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPREPDE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFPDE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFPDE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - } - else if (command == Command::PDXP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD); - } - else if (command == Command::SREFEN) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDSRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + std::max(memSpec->tRTP + memSpec->tRP, tRDSRE)); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - } - else if (command == Command::SREFEX) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEN][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKESR); + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); } else - SC_REPORT_FATAL("CheckerGDDR6", "Unknown command!"); - + { + reportFatal("CheckerGDDR6", "Unknown command!"); + } // Check if command bus is free earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); @@ -558,11 +319,11 @@ void CheckerGDDR6::insert(Command command, Rank rank, BankGroup bankgroup, Bank if (command == Command::ACT || command == Command::REFB) { - if (last4Activates[rank.ID()].size() == 4) - last4Activates[rank.ID()].pop(); - last4Activates[rank.ID()].push(lastCommandOnBus); + if (lastActivates[rank.ID()].size() == 4) + lastActivates[rank.ID()].pop(); + lastActivates[rank.ID()].push(lastCommandOnBus); } if (command == Command::REFB) - bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank; + bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->banksPerRank; } diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h index 57d80fbb..501c0da6 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h @@ -58,18 +58,9 @@ private: sc_time lastCommandOnBus; // four activate window - std::vector> last4Activates; + std::vector> lastActivates; - std::vector bankwiseRefreshCounter; - - sc_time tBURST; - sc_time tRDSRE; - sc_time tWRSRE; - sc_time tRDWR_R; - sc_time tWRRD_S; - sc_time tWRRD_L; - sc_time tWRRD_R; - sc_time tWRPRE; + unsigned bankwiseRefreshCounter = 0; }; #endif // CHECKERGDDR6_H diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index 17d8a355..e2c92f9e 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -49,17 +49,8 @@ CheckerHBM2::CheckerHBM2() (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - last4Activates = std::vector>(memSpec->numberOfRanks); + lastActivates = std::vector>(memSpec->numberOfRanks); bankwiseRefreshCounter = std::vector(memSpec->numberOfRanks); - - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; - tRDPDE = memSpec->tRL + memSpec->tPL + tBURST + memSpec->tCK; - tRDSRE = tRDPDE; - tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; - tWRPDE = memSpec->tWL + memSpec->tPL + tBURST + memSpec->tCK + memSpec->tWR; - tWRAPDE = memSpec->tWL + memSpec->tPL + tBURST + memSpec->tCK + memSpec->tWR; - tWRRDS = memSpec->tWL + tBURST + memSpec->tWTRS; - tWRRDL = memSpec->tWL + tBURST + memSpec->tWTRL; } sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const @@ -67,94 +58,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); - if (command == Command::RD || command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - if (command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - memSpec->tRTP); - } - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS); - - lastCommandStart = lastScheduledByCommand[Command::PDXA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK); - } - else if (command == Command::WR || command == Command::WRA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommand[Command::PDXA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK); - } - else if (command == Command::ACT) + if (command == Command::ACT) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -170,11 +74,13 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP - memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRTP + memSpec->tRP - memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP - memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP - memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -184,14 +90,6 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->tCK); - lastCommandStart = lastScheduledByCommand[Command::PDXA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP - memSpec->tCK); - - lastCommandStart = lastScheduledByCommand[Command::PDXP]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP - memSpec->tCK); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC - memSpec->tCK); @@ -204,20 +102,98 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD - memSpec->tCK); - lastCommandStart = lastScheduledByCommand[Command::SREFEX]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS - memSpec->tCK); - - if (last4Activates[rank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW - memSpec->tCK); + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, + lastActivates[rank.ID()].front() + memSpec->tFAW - memSpec->tCK); earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); } + else if (command == Command::RD || command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->tCK); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); + + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); + } + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR + memSpec->tCK); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK); + } else if (command == Command::PRE) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -225,19 +201,15 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); - - lastCommandStart = lastScheduledByCommand[Command::PDXA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); } else if (command == Command::PREA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -249,19 +221,13 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); - - lastCommandStart = lastScheduledByCommand[Command::PDXA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); } @@ -277,7 +243,8 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -287,22 +254,10 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommand[Command::PDXP]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB); - - lastCommandStart = lastScheduledByCommand[Command::SREFEX]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); } else if (command == Command::REFB) @@ -325,31 +280,16 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommand[Command::PDXA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommand[Command::PDXP]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB); +// lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB); lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -360,129 +300,15 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); } - lastCommandStart = lastScheduledByCommand[Command::SREFEX]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - - if (last4Activates[rank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::PDEA) - { - lastCommandStart = lastScheduledByCommand[Command::RD]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE); - - lastCommandStart = lastScheduledByCommand[Command::RDA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE); - - lastCommandStart = lastScheduledByCommand[Command::WR]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPDE); - - lastCommandStart = lastScheduledByCommand[Command::WRA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDE); - - lastCommandStart = lastScheduledByCommand[Command::PDXA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::PDXA) - { - lastCommandStart = lastScheduledByCommand[Command::PDEA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::PDEP) - { - lastCommandStart = lastScheduledByCommand[Command::RD]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE); - - lastCommandStart = lastScheduledByCommand[Command::RDA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE); - - lastCommandStart = lastScheduledByCommand[Command::WRA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDE); - - lastCommandStart = lastScheduledByCommand[Command::PDXP]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - - lastCommandStart = lastScheduledByCommand[Command::SREFEX]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::PDXP) - { - lastCommandStart = lastScheduledByCommand[Command::PDEP]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::SREFEN) - { - lastCommandStart = lastScheduledByCommand[Command::ACT]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK); - - lastCommandStart = lastScheduledByCommand[Command::RDA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + std::max(memSpec->tRTP + memSpec->tRP, tRDSRE)); - - lastCommandStart = lastScheduledByCommand[Command::WRA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); - - lastCommandStart = lastScheduledByCommand[Command::PRE]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommand[Command::PREA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommand[Command::PDXP]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommand[Command::REFA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommand[Command::REFB]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB); - - lastCommandStart = lastScheduledByCommand[Command::SREFEX]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::SREFEX) - { - lastCommandStart = lastScheduledByCommand[Command::SREFEN]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKESR); + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); } else - SC_REPORT_FATAL("CheckerHBM2", "Unknown command!"); + { + reportFatal("CheckerHBM2", "Unknown command!"); + } return earliestTimeToStart; } @@ -506,9 +332,9 @@ void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank b if (command == Command::ACT || command == Command::REFB) { - if (last4Activates[rank.ID()].size() == 4) - last4Activates[rank.ID()].pop(); - last4Activates[rank.ID()].push(lastCommandOnRasBus); + if (lastActivates[rank.ID()].size() == 4) + lastActivates[rank.ID()].pop(); + lastActivates[rank.ID()].push(lastCommandOnRasBus); } if (command == Command::REFB) diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.h b/DRAMSys/library/src/controller/checker/CheckerHBM2.h index 51f7c15d..77b27f64 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.h +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.h @@ -55,24 +55,12 @@ private: std::vector> lastScheduledByCommandAndBankGroup; std::vector> lastScheduledByCommandAndRank; std::vector lastScheduledByCommand; - sc_time lastCommandOnRasBus; sc_time lastCommandOnCasBus; // Four activate window - std::vector> last4Activates; + std::vector> lastActivates; std::vector bankwiseRefreshCounter; - - sc_time tBURST; - sc_time tRDPDE; - sc_time tRDSRE; - sc_time tWRPRE; - sc_time tWRPDE; - sc_time tWRAPDE; - sc_time tRTWR; - sc_time tWRRDS; - sc_time tWRRDL; - sc_time tWRRDR; }; #endif // CHECKERHBM2_H diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index 09adc6d1..943298db 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -47,23 +47,7 @@ CheckerLPDDR4::CheckerLPDDR4() (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - last4Activates = std::vector>(memSpec->numberOfRanks); - - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; - tRDWR = memSpec->tRL + memSpec->tDQSCK + tBURST - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST; - tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; - tWRRD = memSpec->tWL + memSpec->tCK + tBURST + memSpec->tWTR; - tWRRD_R = memSpec->tWL + tBURST + memSpec->tRTRS - memSpec->tRL; - tRDPRE = memSpec->tRTP + tBURST - 6 * memSpec->tCK; - tRDAACT = memSpec->tRTP + tBURST - 8 * memSpec->tCK + memSpec->tRPpb; - tWRPRE = memSpec->tWL + tBURST + memSpec->tCK + memSpec->tWR + 2 * memSpec->tCK; - tWRAACT = memSpec->tWL + tBURST + memSpec->tCK + memSpec->tWR + memSpec->tRPpb; - tACTPDEN = 3 * memSpec->tCK + memSpec->tCMDCKE; - tPRPDEN = memSpec->tCK + memSpec->tCMDCKE; - tRDPDEN = 3 * memSpec->tCK + memSpec->tRL + memSpec->tDQSCK + tBURST + memSpec->tRPST; - tWRPDEN = 3 * memSpec->tCK + memSpec->tWL + (std::ceil(memSpec->tDQSS / memSpec->tCK) + std::ceil(memSpec->tDQS2DQ / memSpec->tCK)) * memSpec->tCK + tBURST + memSpec->tWR; - tWRAPDEN = 3 * memSpec->tCK + memSpec->tWL + (std::ceil(memSpec->tDQSS / memSpec->tCK) + std::ceil(memSpec->tDQS2DQ / memSpec->tCK)) * memSpec->tCK + tBURST + memSpec->tWR + 2 * memSpec->tCK; - tREFPDEN = memSpec->tCK + memSpec->tCMDCKE; + lastActivates = std::vector>(memSpec->numberOfRanks); } sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const @@ -71,114 +55,16 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); - if (command == Command::RD || command == Command::RDA) + if (command == Command::ACT) { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - if (command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - tRDPRE); - } - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD); - - lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ? lastScheduledByCommand[Command::WR] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD); - - lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ? lastScheduledByCommand[Command::WRA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - } - else if (command == Command::WR || command == Command::WRA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR); - - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - - lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ? lastScheduledByCommand[Command::WR] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - - lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ? lastScheduledByCommand[Command::WRA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - } - else if (command == Command::ACT) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb); - - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD); - lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDAACT); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAACT); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + + memSpec->tWR + memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -188,13 +74,13 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab - 2 * memSpec->tCK); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD); lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -208,82 +94,119 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD - 2 * memSpec->tCK); - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSR - 2 * memSpec->tCK); + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW - 3 * memSpec->tCK); + } + else if (command == Command::RD || command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - if (last4Activates[rank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW - 3 * memSpec->tCK); + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWTR); + + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); + } + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWTR); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); } else if (command == Command::PRE) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + 2 * memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); } else if (command == Command::PREA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + 2 * memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->tCK); + +// lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); } else if (command == Command::REFA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb + 2 * memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb + 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPRE + memSpec->tRPpb); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRPpb + 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRPpb); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + + memSpec->tWR + 3 * memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -293,27 +216,19 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSR); +// lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); } else if (command == Command::REFB) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb + 2 * memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb + 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -321,174 +236,36 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPRE + memSpec->tRPpb); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRPpb + 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRPpb); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + + memSpec->tWR + 3 * memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb); - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab); +// lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); +// lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSR); - - if (last4Activates[rank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW - memSpec->tCK); - } - else if (command == Command::PDEA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tACTPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tPRPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tREFPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - } - else if (command == Command::PDXA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - } - else if (command == Command::PDEP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tPRPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tPRPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tREFPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tREFPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSR); - } - else if (command == Command::PDXP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - } - else if (command == Command::SREFEN) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb + 2 * memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + std::max(tRDPDEN, tRDPRE + memSpec->tRPpb)); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + std::max(tWRAPDEN, tWRPRE + memSpec->tRPpb)); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSR); - } - else if (command == Command::SREFEX) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEN][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tSR); + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW - memSpec->tCK); } else - SC_REPORT_FATAL("CheckerLPDDR4", "Unknown command!"); - + { + reportFatal("CheckerLPDDR4", "Unknown command!"); + } // Check if command bus is free earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); @@ -503,13 +280,12 @@ void CheckerLPDDR4::insert(Command command, Rank rank, BankGroup, Bank bank) lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); - lastCommandOnBus = sc_time_stamp() + memSpec->getCommandLength(command) - memSpec->tCK; if (command == Command::ACT || command == Command::REFB) { - if (last4Activates[rank.ID()].size() == 4) - last4Activates[rank.ID()].pop(); - last4Activates[rank.ID()].push(lastCommandOnBus); + if (lastActivates[rank.ID()].size() == 4) + lastActivates[rank.ID()].pop(); + lastActivates[rank.ID()].push(lastCommandOnBus); } } diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h index cddab49b..f52c732e 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h @@ -57,25 +57,7 @@ private: sc_time lastCommandOnBus; // Four activate window - std::vector> last4Activates; - - sc_time tBURST; - sc_time tRDWR; - sc_time tRDWR_R; - sc_time tWRRD; - sc_time tWRRD_R; - sc_time tRDPRE; - sc_time tRDAPRE; - sc_time tRDAACT; - sc_time tWRPRE; - sc_time tWRAPRE; - sc_time tWRAACT; - sc_time tACTPDEN; - sc_time tPRPDEN; - sc_time tRDPDEN; - sc_time tWRPDEN; - sc_time tWRAPDEN; - sc_time tREFPDEN; + std::vector> lastActivates; }; #endif // CHECKERLPDDR4_H diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 4b40ecf4..c0236fee 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -47,17 +47,7 @@ CheckerWideIO::CheckerWideIO() (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - last2Activates = std::vector>(memSpec->numberOfRanks); - - tBURST = memSpec->burstLength * memSpec->tCK; - tRDWR = memSpec->tRL + tBURST + memSpec->tCK; - tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL; - tWRPRE = memSpec->tWL + tBURST - memSpec->tCK + memSpec->tWR; - tWRRD = memSpec->tWL + tBURST - memSpec->tCK + memSpec->tWTR; - tWRRD_R = memSpec->tWL + tBURST + memSpec->tRTRS - memSpec->tRL; - tRDPDEN = memSpec->tRL + tBURST; // + memSpec->tCK; ?? - tWRPDEN = memSpec->tWL + tBURST + memSpec->tWR - memSpec->tCK; - tWRAPDEN = memSpec->tWL + tBURST + memSpec->tWR; // + memSpec->tCK; ?? + lastActivates = std::vector>(memSpec->numberOfRanks); } sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const @@ -65,114 +55,16 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); - if (command == Command::RD || command == Command::RDA) + if (command == Command::ACT) { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST); - - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - if (command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - tBURST); - } - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD); - - lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ? lastScheduledByCommand[Command::WR] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD); - - lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ? lastScheduledByCommand[Command::WRA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - } - else if (command == Command::WR || command == Command::WRA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR); - - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST); - - lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ? lastScheduledByCommand[Command::WR] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST); - - lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ? lastScheduledByCommand[Command::WRA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - } - else if (command == Command::ACT) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD); - lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + memSpec->burstDuration - memSpec->tCK + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -182,68 +74,111 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD); + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + if (lastActivates[rank.ID()].size() >= 2) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tTAW); + } + else if (command == Command::RD || command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; + lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration); - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; + lastCommandStart = lastScheduledByCommand[Command::RDA]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSR); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration); - if (last2Activates[rank.ID()].size() >= 2) - earliestTimeToStart = std::max(earliestTimeToStart, last2Activates[rank.ID()].front() + memSpec->tTAW); + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWTR); + + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->tCK + memSpec->tWR); + } + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWTR); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + memSpec->burstDuration + memSpec->tCK); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + memSpec->burstDuration + memSpec->tCK); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration); } else if (command == Command::PRE) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration); lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWR); } else if (command == Command::PREA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration); lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWR); } else if (command == Command::REFA) { @@ -253,11 +188,12 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -270,114 +206,11 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSR); - } - else if (command == Command::PDEA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - } - else if (command == Command::PDXA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - } - else if (command == Command::PDEP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSR); - } - else if (command == Command::PDXP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - } - else if (command == Command::SREFEN) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + std::max(tRDPDEN, tBURST + memSpec->tRP)); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + std::max(tWRAPDEN, tWRPRE + memSpec->tRP)); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSR); - } - else if (command == Command::SREFEX) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEN][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKESR); } else - SC_REPORT_FATAL("CheckerWideIO", "Unknown command!"); - + { + reportFatal("CheckerWideIO", "Unknown command!"); + } // Check if command bus is free earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled + memSpec->tCK); @@ -396,8 +229,8 @@ void CheckerWideIO::insert(Command command, Rank rank, BankGroup, Bank bank) if (command == Command::ACT) { - if (last2Activates[rank.ID()].size() == 2) - last2Activates[rank.ID()].pop(); - last2Activates[rank.ID()].push(sc_time_stamp()); + if (lastActivates[rank.ID()].size() == 2) + lastActivates[rank.ID()].pop(); + lastActivates[rank.ID()].push(sc_time_stamp()); } } diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index 2ad7182d..65a8adee 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -57,17 +57,7 @@ private: sc_time lastScheduled; // Four activate window - std::vector> last2Activates; - - sc_time tBURST; - sc_time tRDWR; - sc_time tRDWR_R; - sc_time tWRPRE; - sc_time tWRRD; - sc_time tWRRD_R; - sc_time tRDPDEN; - sc_time tWRPDEN; - sc_time tWRAPDEN; + std::vector> lastActivates; }; #endif // CHECKERWIDEIO_H diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp index 357f6615..8a2a73fb 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -47,18 +47,7 @@ CheckerWideIO2::CheckerWideIO2() (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - last4Activates = std::vector>(memSpec->numberOfRanks); - - tBURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; - tRDPRE = tBURST + std::max(2 * memSpec->tCK, memSpec->tRTP) - 2 * memSpec->tCK; - tRDPDEN = memSpec->tRL + memSpec->tDQSCK + tBURST + memSpec->tCK; - tRDWR = memSpec->tRL + memSpec->tDQSCK + tBURST + memSpec->tCK - memSpec->tWL; - tRDWR_R = memSpec->tRL + memSpec->tDQSCK + tBURST + memSpec->tRTRS - memSpec->tWL; - tWRPRE = memSpec->tWL + memSpec->tCK + tBURST + memSpec->tWR; - tWRPDEN = memSpec->tWL + memSpec->tCK + tBURST + memSpec->tWR; - tWRAPDEN = memSpec->tWL + memSpec->tCK + tBURST + memSpec->tWR + memSpec->tCK; - tWRRD = memSpec->tWL + memSpec->tCK + tBURST + memSpec->tWTR; - tWRRD_R = memSpec->tWL + memSpec->tCK + tBURST + memSpec->tRTRS - memSpec->tRL; + lastActivates = std::vector>(memSpec->numberOfRanks); } sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const @@ -66,98 +55,7 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); - if (command == Command::RD || command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - if (command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE - tRDPRE); - } - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD); - - lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ? lastScheduledByCommand[Command::WR] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD); - - lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ? lastScheduledByCommand[Command::WRA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - } - else if (command == Command::WR || command == Command::WRA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR); - - lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ? lastScheduledByCommand[Command::RD] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR); - - lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ? lastScheduledByCommand[Command::RDA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_R); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - - lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ? lastScheduledByCommand[Command::WR] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - - lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ? lastScheduledByCommand[Command::WRA] : SC_ZERO_TIME; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - } - else if (command == Command::ACT) + if (command == Command::ACT) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -169,11 +67,13 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPRE + memSpec->tRPpb); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRPpb); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -183,14 +83,6 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); @@ -203,70 +95,108 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD); - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSR); + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); + } + else if (command == Command::RD || command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - if (last4Activates[rank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWTR); + + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); + } + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWTR); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration + memSpec->tCK - memSpec->tWL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration + memSpec->tCK - memSpec->tWL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); } else if (command == Command::PRE) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 2 * memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK); } else if (command == Command::PREA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 2 * memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); } - else if(command == Command::REFA) + else if (command == Command::REFA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -274,11 +204,13 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPRE + memSpec->tRPpb); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRPpb); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -288,23 +220,11 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab); - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSR); } - else if(command == Command::REFB) + else if (command == Command::REFB) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -316,146 +236,29 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPRE + memSpec->tRPpb); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRPpb); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb); - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSR); - - if (last4Activates[rank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); - } - else if (command == Command::PDEA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - } - else if (command == Command::PDXA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - } - else if (command == Command::PDEP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDEN); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSR); - } - else if (command == Command::PDXP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - } - else if (command == Command::SREFEN) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + std::max(tRDPDEN, tRDPRE + memSpec->tRPpb)); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + std::max(tWRAPDEN, tWRPRE + memSpec->tRPpb)); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSR); - } - else if (command == Command::SREFEX) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEN][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKESR); + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); } else - SC_REPORT_FATAL("CheckerWideIO2", "Unknown command!"); - + { + reportFatal("CheckerWideIO2", "Unknown command!"); + } // Check if command bus is free earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); @@ -474,8 +277,8 @@ void CheckerWideIO2::insert(Command command, Rank rank, BankGroup, Bank bank) if (command == Command::ACT || command == Command::REFB) { - if (last4Activates[rank.ID()].size() == 4) - last4Activates[rank.ID()].pop(); - last4Activates[rank.ID()].push(sc_time_stamp()); + if (lastActivates[rank.ID()].size() == 4) + lastActivates[rank.ID()].pop(); + lastActivates[rank.ID()].push(sc_time_stamp()); } } diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h index b6a974cf..7068601a 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h @@ -57,18 +57,7 @@ private: sc_time lastCommandOnBus; // Four activate window - std::vector> last4Activates; - - sc_time tBURST; - sc_time tRDPRE; - sc_time tRDPDEN; - sc_time tRDWR; - sc_time tRDWR_R; - sc_time tWRPRE; - sc_time tWRPDEN; - sc_time tWRAPDEN; - sc_time tWRRD; - sc_time tWRRD_R; + std::vector> lastActivates; }; #endif // CHECKERWIDEIO2_H diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 743ea18d..73810df7 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -37,7 +37,6 @@ #include "Arbiter.h" #include "../common/AddressDecoder.h" -#include "../configuration/Configuration.h" using namespace tlm; @@ -77,7 +76,6 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, if (phase == BEGIN_REQ) { - // TODO: do not adjust address permanently // adjust address offset: payload.set_address(payload.get_address() - Configuration::getInstance().addressOffset); @@ -89,11 +87,11 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, } else if (phase == END_RESP) { - // TODO: why one additional cycle??? notDelay += Configuration::getInstance().memSpec->tCK; + payload.release(); } - PRINTDEBUGMESSAGE(name(), "[fw] " + std::string(phase.get_name()) + " notification in " + + PRINTDEBUGMESSAGE(name(), "[fw] " + phaseNameToString(phase) + " notification in " + notDelay.to_string()); payloadEventQueue.notify(payload, phase, notDelay); return TLM_ACCEPTED; @@ -105,9 +103,10 @@ tlm_sync_enum Arbiter::nb_transport_bw(int channelId, tlm_generic_payload &paylo tlm_phase &phase, sc_time &bwDelay) { // Check channel ID - assert((unsigned int)channelId == DramExtension::getExtension(payload).getChannel().ID()); + if ((unsigned int)channelId != DramExtension::getExtension(payload).getChannel().ID()) + SC_REPORT_FATAL("Arbiter", "Payload extension was corrupted"); - PRINTDEBUGMESSAGE(name(), "[bw] " + std::string(phase.get_name()) + " notification in " + + PRINTDEBUGMESSAGE(name(), "[bw] " + phaseNameToString(phase) + " notification in " + bwDelay.to_string()); payloadEventQueue.notify(payload, phase, bwDelay); return TLM_ACCEPTED; @@ -125,51 +124,39 @@ unsigned int Arbiter::transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans) void Arbiter::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) { - unsigned int threadId = DramExtension::getExtension(payload).getThread().ID(); + unsigned int initiatorSocket = DramExtension::getExtension( + payload).getThread().ID(); unsigned int channelId = DramExtension::getExtension(payload).getChannel().ID(); - // Check the valid range of thread ID and channel Id - // TODO: thread ID not checked + // Check the valid range of initiatorSocket ID and channel Id + // TODO: initiatorSocket ID not checked assert(channelId < Configuration::getInstance().numberOfMemChannels); // Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter) if (phase == BEGIN_REQ) { - if (channelIsFree[channelId]) - { + if (channelIsFree[channelId]) { // This channel was available. Forward the new transaction to the memory controller. channelIsFree[channelId] = false; - tlm_phase tPhase = BEGIN_REQ; - sc_time tDelay = SC_ZERO_TIME; - iSocket[channelId]->nb_transport_fw(payload, tPhase, tDelay); - // TODO: early completion of channel controller!!! - } - else - { + sendToChannel(channelId, payload, phase, SC_ZERO_TIME); + } else { // This channel is busy. Enqueue the new transaction which phase is BEGIN_REQ. pendingRequests[channelId].push(&payload); } } // Phases initiated by the target side from arbiter's point of view (memory side) - else if (phase == END_REQ) - { + else if (phase == END_REQ) { channelIsFree[channelId] = true; // The arbiter receives a transaction which phase is END_REQ from memory controller and forwards it to the requester device. - tlm_phase tPhase = END_REQ; - sc_time tDelay = SC_ZERO_TIME; - tSocket[threadId]->nb_transport_bw(payload, tPhase, tDelay); + sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME); // This channel is now free! Dispatch a new transaction (phase is BEGIN_REQ) from the queue, if any. Send it to the memory controller. - if (!pendingRequests[channelId].empty()) - { - // Send ONE of the enqueued new transactions (phase is BEGIN_REQ) through this channel. - tlm_generic_payload &payloadToSend = *pendingRequests[channelId].front(); + if (!pendingRequests[channelId].empty()) { + tlm_generic_payload *payloadToSend = pendingRequests[channelId].front(); pendingRequests[channelId].pop(); - tlm_phase tPhase = BEGIN_REQ; - sc_time tDelay = SC_ZERO_TIME; - iSocket[channelId]->nb_transport_fw(payloadToSend, tPhase, tDelay); - // TODO: early completion of channel controller + // Send ONE of the enqueued new transactions (phase is BEGIN_REQ) through this channel. + sendToChannel(channelId, *payloadToSend, BEGIN_REQ, SC_ZERO_TIME); // Mark the channel as busy again. channelIsFree[channelId] = false; } @@ -179,48 +166,26 @@ void Arbiter::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) // The arbiter receives a transaction in BEGIN_RESP phase // (that came from the memory side) and forwards it to the requester // device - if (pendingResponses[threadId].empty()) - { - tlm_phase tPhase = BEGIN_RESP; - sc_time tDelay = SC_ZERO_TIME; - tlm_sync_enum returnValue = tSocket[threadId]->nb_transport_bw(payload, tPhase, tDelay); - if (returnValue != TLM_ACCEPTED) - { - tPhase = END_RESP; - payloadEventQueue.notify(payload, tPhase, tDelay); - } + if (receivedResponses[initiatorSocket].empty()) { + sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME); } - // Enqueue the transaction in BEGIN_RESP phase until the initiator - // device acknowledges it (phase changes to END_RESP). - pendingResponses[threadId].push(&payload); + // device acknowledge it (phase changes to END_RESP). + receivedResponses[initiatorSocket].push(&payload); } else if (phase == END_RESP) { // Send the END_RESP message to the memory - { - tlm_phase tPhase = END_RESP; - sc_time tDelay = SC_ZERO_TIME; - iSocket[channelId]->nb_transport_fw(payload, tPhase, tDelay); - } + sendToChannel(channelId, payload, phase, SC_ZERO_TIME); // Drop one element of the queue of BEGIN_RESP from memory to this device - pendingResponses[threadId].pop(); - payload.release(); + receivedResponses[initiatorSocket].pop(); // Check if there are queued transactoins with phase BEGIN_RESP from memory to this device - if (!pendingResponses[threadId].empty()) - { + if (!receivedResponses[initiatorSocket].empty()) { // The queue is not empty. - tlm_generic_payload &payloadToSend = *pendingResponses[threadId].front(); + tlm_generic_payload *payloadToSend = receivedResponses[initiatorSocket].front(); // Send ONE extra BEGIN_RESP to the device - tlm_phase tPhase = BEGIN_RESP; - sc_time tDelay = SC_ZERO_TIME; - tlm_sync_enum returnValue = tSocket[threadId]->nb_transport_bw(payloadToSend, tPhase, tDelay); - if (returnValue != TLM_ACCEPTED) - { - tPhase = END_RESP; - payloadEventQueue.notify(payloadToSend, tPhase, tDelay); - } + sendToInitiator(initiatorSocket, *payloadToSend, BEGIN_RESP, SC_ZERO_TIME); } } else @@ -228,6 +193,22 @@ void Arbiter::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) "Payload event queue in arbiter was triggered with unknown phase"); } +void Arbiter::sendToChannel(unsigned int channelId, tlm_generic_payload &payload, + const tlm_phase &phase, const sc_time &delay) +{ + tlm_phase TPhase = phase; + sc_time TDelay = delay; + iSocket[channelId]->nb_transport_fw(payload, TPhase, TDelay); +} + +void Arbiter::sendToInitiator(unsigned int id, tlm_generic_payload &payload, + const tlm_phase &phase, const sc_time &delay) +{ + tlm_phase TPhase = phase; + sc_time TDelay = delay; + tSocket[id]->nb_transport_bw(payload, TPhase, TDelay); +} + void Arbiter::appendDramExtension(int socketId, tlm_generic_payload &payload) { // Append Generation Extension diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index c8738050..2e0ab39d 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -48,6 +48,7 @@ #include #include "../common/AddressDecoder.h" #include "../common/dramExtensions.h" +#include "../configuration/ConfigurationLoader.h" class Arbiter : public sc_module { @@ -70,7 +71,7 @@ private: std::vector> pendingRequests; // used to account for the response_accept_delay in the initiators (traceplayer, core etc.) // This is a queue of responses comming from the memory side. The phase of these transactions is BEGIN_RESP. - std::map> pendingResponses; + std::map> receivedResponses; // Initiated by initiator side // This function is called when an arbiter's target socket receives a transaction from a device @@ -86,6 +87,12 @@ private: void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase); + void sendToChannel(unsigned int channelId, tlm::tlm_generic_payload &payload, + const tlm::tlm_phase &phase, const sc_time &delay); + + void sendToInitiator(unsigned int id, tlm::tlm_generic_payload &payload, + const tlm::tlm_phase &phase, const sc_time &delay); + void appendDramExtension(int socketId, tlm::tlm_generic_payload &payload); std::vector nextPayloadID; }; diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index fa119ed2..32f77bcd 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -34,7 +34,6 @@ * Matthias Jung * Eder F. Zulian * Felipe S. Prado - * Lukas Steiner */ #include @@ -44,11 +43,15 @@ #include #include "DRAMSys.h" -#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp" +#include "Setup.h" +#include "../common/third_party/tinyxml2/tinyxml2.h" +#include "../common/TlmRecorder.h" #include "../common/DebugManager.h" +#include "../configuration/ConfigurationLoader.h" #include "../common/utils.h" #include "../simulation/TemperatureController.h" #include "../error/ecchamming.h" +#include "dram/DramRecordable.h" #include "dram/DramDDR3.h" #include "dram/DramDDR4.h" #include "dram/DramWideIO.h" @@ -59,12 +62,11 @@ #include "dram/DramGDDR5X.h" #include "dram/DramGDDR6.h" #include "../controller/Controller.h" +#include "../controller/ControllerRecordable.h" DRAMSys::DRAMSys(sc_module_name name, std::string simulationToRun, - std::string pathToResources, - bool initAndBind) - : sc_module(name), tSocket("DRAMSys_tSocket") + std::string pathToResources) : sc_module(name), tSocket("DRAMSys_tSocket") { // Initialize ecc pointer ecc = nullptr; @@ -72,67 +74,71 @@ DRAMSys::DRAMSys(sc_module_name name, logo(); // Read Configuration Setup: - nlohmann::json simulationdoc = parseJSON(simulationToRun); + std::string memspec; + std::string mcconfig; + std::string amconfig; + std::string simconfig; + std::string thermalconfig; - if (simulationdoc["simulation"].empty()) - SC_REPORT_FATAL("SimulationManager", - "Cannot load simulation: simulation node expected"); + Setup setup(simulationToRun, + memspec, + mcconfig, + amconfig, + simconfig, + thermalconfig); Configuration::getInstance().setPathToResources(pathToResources); // Load config and initialize modules - Configuration::getInstance().loadMCConfig(Configuration::getInstance(), - pathToResources - + "configs/mcconfigs/" - + std::string(simulationdoc["simulation"]["mcconfig"])); + ConfigurationLoader::loadMemSpec(Configuration::getInstance(), + pathToResources + + "configs/memspecs/" + + memspec); - Configuration::getInstance().loadMemSpec(Configuration::getInstance(), - pathToResources - + "configs/memspecs/" - + std::string(simulationdoc["simulation"]["memspec"])); + ConfigurationLoader::loadMCConfig(Configuration::getInstance(), + pathToResources + + "configs/mcconfigs/" + + mcconfig); - Configuration::getInstance().loadSimConfig(Configuration::getInstance(), - pathToResources - + "configs/simulator/" - + std::string(simulationdoc["simulation"]["simconfig"])); + ConfigurationLoader::loadSimConfig(Configuration::getInstance(), + pathToResources + + "configs/simulator/" + + simconfig); - Configuration::getInstance().loadTemperatureSimConfig(Configuration::getInstance(), - pathToResources - + "configs/thermalsim/" - + std::string(simulationdoc["simulation"]["thermalconfig"])); + ConfigurationLoader::loadTemperatureSimConfig(Configuration::getInstance(), + pathToResources + + "configs/thermalsim/" + + thermalconfig); // Setup the debug manager: setupDebugManager(Configuration::getInstance().simulationName); - if (initAndBind) - { - // Instantiate all internal DRAMSys modules: - std::string amconfig = simulationdoc["simulation"]["addressmapping"]; - instantiateModules(pathToResources, amconfig); - // Connect all internal DRAMSys modules: - bindSockets(); - report(headline); + // If a simulation file is passed as argument to DRAMSys the simulation ID + // is prepended to the simulation name if found. + std::string simName; + simName = Configuration::getInstance().simulationName; + tinyxml2::XMLDocument simulationdoc; + loadXML(simulationToRun, simulationdoc); + tinyxml2::XMLElement *simulation = + simulationdoc.FirstChildElement("simulation"); + if (simulation != NULL) { + tinyxml2::XMLElement *simid = simulation->FirstChildElement("simulationid"); + if (simid != NULL) { + auto r = simid->Attribute("id"); + if (r != NULL) { + std::string sid; + sid = r; + simName = sid + '_' + Configuration::getInstance().simulationName; + } + } } -} -DRAMSys::~DRAMSys() -{ - if (ecc) - delete ecc; + // Instantiate all internal DRAMSys modules: + instantiateModules(simName, pathToResources, amconfig); + // Connect all internal DRAMSys modules: + bindSockets(); - delete arbiter; - - for (auto dram : drams) - delete dram; - - for (auto controller : controllers) - delete controller; - - for (auto tlmChecker : playersTlmCheckers) - delete tlmChecker; - - for (auto tlmChecker : controllersTlmCheckers) - delete tlmChecker; + report(headline); } void DRAMSys::logo() @@ -163,13 +169,49 @@ void DRAMSys::setupDebugManager(const std::string &traceName __attribute__((unus #endif } -void DRAMSys::instantiateModules(const std::string &pathToResources, +void DRAMSys::setupTlmRecorders(const std::string &traceName, + const std::string &pathToResources) +{ + // Create TLM Recorders, one per channel. + for (size_t i = 0; + i < Configuration::getInstance().numberOfMemChannels; + i++) { + std::string sqlScriptURI = pathToResources + + std::string("scripts/createTraceDB.sql"); + + std::string dbName = traceName + + std::string("_ch") + + std::to_string(i) + + ".tdb"; + + std::string recorderName = "tlmRecorder" + std::to_string(i); + + TlmRecorder *tlmRecorder = + new TlmRecorder(recorderName, sqlScriptURI.c_str(), dbName.c_str()); + tlmRecorder->recordMCconfig(Configuration::getInstance().mcconfigUri); + tlmRecorder->recordMemspec(Configuration::getInstance().memspecUri); + + std::string traceNames = Configuration::getInstance().simulationName; + tlmRecorder->recordTracenames(traceNames); + + tlmRecorders.push_back(tlmRecorder); + } +} + +void DRAMSys::instantiateModules(const std::string &traceName, + const std::string &pathToResources, const std::string &amconfig) { // The first call to getInstance() creates the Temperature Controller. // The same instance will be accessed by all other modules. TemperatureController::getInstance(); + // Create and properly initialize TLM recorders. + // They need to be ready before creating some modules. + bool recordingEnabled = Configuration::getInstance().databaseRecording; + if (recordingEnabled) + setupTlmRecorders(traceName, pathToResources); + // Create new ECC Controller if (Configuration::getInstance().ECCMode == "Hamming") ecc = new ECCHamming("ECCHamming"); @@ -184,43 +226,91 @@ void DRAMSys::instantiateModules(const std::string &pathToResources, // Create arbiter arbiter = new Arbiter("arbiter", pathToResources + "configs/amconfigs/" + amconfig); - // Create controllers and DRAMs + // Create DRAM std::string memoryType = Configuration::getInstance().memSpec->memoryType; for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) { std::string str = "controller" + std::to_string(i); - ControllerIF *controller = new Controller(str.c_str()); + ControllerIF *controller; + if (recordingEnabled) + controller = new ControllerRecordable(str.c_str(), tlmRecorders[i]); + else + controller = new Controller(str.c_str()); controllers.push_back(controller); str = "dram" + std::to_string(i); Dram *dram; if (memoryType == "DDR3") - dram = new DramDDR3(str.c_str()); + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramDDR3(str.c_str()); + } else if (memoryType == "WIDEIO_SDR") - dram = new DramWideIO(str.c_str()); + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramWideIO(str.c_str()); + } else if (memoryType == "DDR4") - dram = new DramDDR4(str.c_str()); + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramDDR4(str.c_str()); + } else if (memoryType == "LPDDR4") - dram = new DramLPDDR4(str.c_str()); + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramLPDDR4(str.c_str()); + } else if (memoryType == "WIDEIO2") - dram = new DramWideIO2(str.c_str()); + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramWideIO2(str.c_str()); + } else if (memoryType == "HBM2") - dram = new DramHBM2(str.c_str()); + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramHBM2(str.c_str()); + } else if (memoryType == "GDDR5") - dram = new DramGDDR5(str.c_str()); + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramGDDR5(str.c_str()); + } else if (memoryType == "GDDR5X") - dram = new DramGDDR5X(str.c_str()); + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramGDDR5X(str.c_str()); + } else if (memoryType == "GDDR6") - dram = new DramGDDR6(str.c_str()); + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramGDDR6(str.c_str()); + } else SC_REPORT_FATAL("DRAMSys", "Unsupported DRAM type"); drams.push_back(dram); - if (Configuration::getInstance().checkTLM2Protocol) - { + if (Configuration::getInstance().checkTLM2Protocol) { str = "TLMCheckerController" + std::to_string(i); tlm_utils::tlm2_base_protocol_checker<> *controllerTlmChecker = new tlm_utils::tlm2_base_protocol_checker<>(str.c_str()); @@ -243,25 +333,53 @@ void DRAMSys::bindSockets() else SC_REPORT_FATAL("DRAMSys", "Unsupported ECC mode"); - if (Configuration::getInstance().checkTLM2Protocol) - { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) - { + if (Configuration::getInstance().checkTLM2Protocol) { + for (size_t i = 0; + i < Configuration::getInstance().numberOfMemChannels; + i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); - controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket); + controllersTlmCheckers[i]->initiator_socket.bind( + controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); } - } - else - { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) - { + } else { + for (size_t i = 0; + i < Configuration::getInstance().numberOfMemChannels; + i++) { arbiter->iSocket.bind(controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); } } } +DRAMSys::~DRAMSys() +{ + if (ecc) + delete ecc; + + delete arbiter; + + for (auto dram : drams) { + delete dram; + } + + for (auto rec : tlmRecorders) { + delete rec; + } + + for (auto tlmChecker : playersTlmCheckers) { + delete tlmChecker; + } + + for (auto tlmChecker : controllersTlmCheckers) { + delete tlmChecker; + } + + for (auto controller : controllers) { + delete controller; + } +} + void DRAMSys::report(std::string message) { PRINTDEBUGMESSAGE(name(), message); diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index 34f47091..841dd22b 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -34,7 +34,6 @@ * Matthias Jung * Eder F. Zulian * Felipe S. Prado - * Lukas Steiner */ #ifndef DRAMSYS_H @@ -45,12 +44,14 @@ #include "dram/Dram.h" #include "Arbiter.h" +#include "TraceGenerator.h" #include "ReorderBuffer.h" #include #include #include "../common/tlm2_base_protocol_checker.h" #include "../error/eccbaseclass.h" #include "../controller/ControllerIF.h" +#include "../common/TlmRecorder.h" class DRAMSys : public sc_module { @@ -60,19 +61,21 @@ public: std::vector*> playersTlmCheckers; + sc_event terminateSimulation; + SC_HAS_PROCESS(DRAMSys); DRAMSys(sc_module_name name, std::string simulationToRun, - std::string pathToResources) - : DRAMSys(name, simulationToRun, pathToResources, true) {} + std::string pathToResources); - virtual ~DRAMSys(); + ~DRAMSys(); -protected: - DRAMSys(sc_module_name name, - std::string simulationToRun, - std::string pathToResources, - bool initAndBind); + void logo(); + +private: + + std::string traceName; + //DramSetup setup; //TLM 2.0 Protocol Checkers std::vector*> @@ -80,28 +83,28 @@ protected: // All transactions pass first through the ECC Controller ECCBaseClass *ecc; + // All transactions pass through the same arbiter + Arbiter *arbiter; + // Each DRAM unit has a controller + std::vector controllers; // TODO: Each DRAM has a reorder buffer (check this!) ReorderBuffer *reorder; - // All transactions pass through the same arbiter - Arbiter *arbiter; - - // Each DRAM unit has a controller - std::vector controllers; - // DRAM units std::vector drams; + // Transaction Recorders (one per channel). + // They generate the output databases. + std::vector tlmRecorders; + void report(std::string message); - -private: - void logo(); - - void instantiateModules(const std::string &pathToResources, + void setupTlmRecorders(const std::string &traceName, + const std::string &pathToResources); + void instantiateModules(const std::string &traceName, + const std::string &pathToResources, const std::string &amconfig); void bindSockets(); - void setupDebugManager(const std::string &traceName); }; diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp deleted file mode 100644 index 60e4dbd9..00000000 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright (c) 2020, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Lukas Steiner - */ - -#include "DRAMSysRecordable.h" -#include "../controller/ControllerRecordable.h" -#include "dram/DramRecordable.h" -#include "dram/DramDDR3.h" -#include "dram/DramDDR4.h" -#include "dram/DramWideIO.h" -#include "dram/DramLPDDR4.h" -#include "dram/DramWideIO2.h" -#include "dram/DramHBM2.h" -#include "dram/DramGDDR5.h" -#include "dram/DramGDDR5X.h" -#include "dram/DramGDDR6.h" -#include "../common/TlmRecorder.h" -#include "../simulation/TemperatureController.h" -#include "../error/ecchamming.h" - -DRAMSysRecordable::DRAMSysRecordable(sc_module_name name, - std::string simulationToRun, - std::string pathToResources) - : DRAMSys(name, simulationToRun, pathToResources, false) -{ - // Read Configuration Setup: - nlohmann::json simulationdoc = parseJSON(simulationToRun); - - // If a simulation file is passed as argument to DRAMSys the simulation ID - // is prepended to the simulation name if found. - std::string traceName; - - if (!simulationdoc["simulation"]["simulationid"].empty()) - { - std::string sid = simulationdoc["simulation"]["simulationid"]; - traceName = sid + '_' + Configuration::getInstance().simulationName; - } - else - traceName = Configuration::getInstance().simulationName; - - std::string amconfig = simulationdoc["simulation"]["addressmapping"]; - instantiateModules(traceName, pathToResources, amconfig); - bindSockets(); - report(headline); -} - -DRAMSysRecordable::~DRAMSysRecordable() -{ - if (Configuration::getInstance().powerAnalysis) - { - for (auto dram : drams) - dram->reportPower(); - } - - for (auto rec : tlmRecorders) - delete rec; -} - -void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName, - const std::string &pathToResources) -{ - // Create TLM Recorders, one per channel. - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) - { - std::string sqlScriptURI = pathToResources - + std::string("scripts/createTraceDB.sql"); - - std::string dbName = traceName + std::string("_ch") + std::to_string(i) + ".tdb"; - - std::string recorderName = "tlmRecorder" + std::to_string(i); - - TlmRecorder *tlmRecorder = - new TlmRecorder(recorderName, sqlScriptURI.c_str(), dbName.c_str()); - tlmRecorder->recordMCconfig(Configuration::getInstance().mcconfigUri); - tlmRecorder->recordMemspec(Configuration::getInstance().memspecUri); - - std::string traceNames = Configuration::getInstance().simulationName; - tlmRecorder->recordTracenames(traceNames); - - tlmRecorders.push_back(tlmRecorder); - } -} - -void DRAMSysRecordable::instantiateModules(const std::string &traceName, - const std::string &pathToResources, - const std::string &amconfig) -{ - // The first call to getInstance() creates the Temperature Controller. - // The same instance will be accessed by all other modules. - TemperatureController::getInstance(); - - // Create and properly initialize TLM recorders. - // They need to be ready before creating some modules. - setupTlmRecorders(traceName, pathToResources); - - // Create new ECC Controller - if (Configuration::getInstance().ECCMode == "Hamming") - ecc = new ECCHamming("ECCHamming"); - else if (Configuration::getInstance().ECCMode == "Disabled") - ecc = nullptr; - else - SC_REPORT_FATAL("DRAMSys", "Unsupported ECC mode"); - - // Save ECC Controller into the configuration struct to adjust it dynamically - Configuration::getInstance().pECC = ecc; - - // Create arbiter - arbiter = new Arbiter("arbiter", pathToResources + "configs/amconfigs/" + amconfig); - - // Create controllers and DRAMs - std::string memoryType = Configuration::getInstance().memSpec->memoryType; - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) - { - std::string str = "controller" + std::to_string(i); - - ControllerIF *controller = new ControllerRecordable(str.c_str(), tlmRecorders[i]); - controllers.push_back(controller); - - str = "dram" + std::to_string(i); - Dram *dram; - - if (memoryType == "DDR3") - dram = new DramRecordable(str.c_str(), tlmRecorders[i]); - else if (memoryType == "WIDEIO_SDR") - dram = new DramRecordable(str.c_str(), tlmRecorders[i]); - else if (memoryType == "DDR4") - dram = new DramRecordable(str.c_str(), tlmRecorders[i]); - else if (memoryType == "LPDDR4") - dram = new DramRecordable(str.c_str(), tlmRecorders[i]); - else if (memoryType == "WIDEIO2") - dram = new DramRecordable(str.c_str(), tlmRecorders[i]); - else if (memoryType == "HBM2") - dram = new DramRecordable(str.c_str(), tlmRecorders[i]); - else if (memoryType == "GDDR5") - dram = new DramRecordable(str.c_str(), tlmRecorders[i]); - else if (memoryType == "GDDR5X") - dram = new DramRecordable(str.c_str(), tlmRecorders[i]); - else if (memoryType == "GDDR6") - dram = new DramRecordable(str.c_str(), tlmRecorders[i]); - else - SC_REPORT_FATAL("DRAMSys", "Unsupported DRAM type"); - - drams.push_back(dram); - - if (Configuration::getInstance().checkTLM2Protocol) - { - str = "TLMCheckerController" + std::to_string(i); - tlm_utils::tlm2_base_protocol_checker<> *controllerTlmChecker = - new tlm_utils::tlm2_base_protocol_checker<>(str.c_str()); - controllersTlmCheckers.push_back(controllerTlmChecker); - } - } -} - -void DRAMSysRecordable::bindSockets() -{ - // If ECC Controller enabled, put it between Trace and arbiter - if (Configuration::getInstance().ECCMode == "Hamming") - { - assert(ecc != nullptr); - tSocket.bind(ecc->t_socket); - ecc->i_socket.bind(arbiter->tSocket); - } - else if (Configuration::getInstance().ECCMode == "Disabled") - tSocket.bind(arbiter->tSocket); - else - SC_REPORT_FATAL("DRAMSys", "Unsupported ECC mode"); - - if (Configuration::getInstance().checkTLM2Protocol) - { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) - { - arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); - controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket); - controllers[i]->iSocket.bind(drams[i]->tSocket); - } - } - else - { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) - { - arbiter->iSocket.bind(controllers[i]->tSocket); - controllers[i]->iSocket.bind(drams[i]->tSocket); - } - } -} diff --git a/DRAMSys/simulator/ExampleInitiator.h b/DRAMSys/library/src/simulation/ExampleInitiator.h similarity index 97% rename from DRAMSys/simulator/ExampleInitiator.h rename to DRAMSys/library/src/simulation/ExampleInitiator.h index b3e3845f..1e0bbcd5 100644 --- a/DRAMSys/simulator/ExampleInitiator.h +++ b/DRAMSys/library/src/simulation/ExampleInitiator.h @@ -5,7 +5,7 @@ #include #include "MemoryManager.h" -#include "common/dramExtensions.h" +#include "../common/dramExtensions.h" #include "TracePlayer.h" struct ExampleInitiator : sc_module @@ -14,11 +14,12 @@ struct ExampleInitiator : sc_module tlm_utils::simple_initiator_socket socket; SC_CTOR(ExampleInitiator) - : socket("socket"), - request_in_progress(0), - m_peq(this, &ExampleInitiator::peq_cb) + : socket("socket") // Construct and name socket + , request_in_progress(0) + , m_peq(this, &ExampleInitiator::peq_cb) { socket.register_nb_transport_bw(this, &ExampleInitiator::nb_transport_bw); + SC_THREAD(thread_process); } diff --git a/DRAMSys/simulator/MemoryManager.cpp b/DRAMSys/library/src/simulation/MemoryManager.cpp similarity index 97% rename from DRAMSys/simulator/MemoryManager.cpp rename to DRAMSys/library/src/simulation/MemoryManager.cpp index 6a73026b..dad4e044 100644 --- a/DRAMSys/simulator/MemoryManager.cpp +++ b/DRAMSys/library/src/simulation/MemoryManager.cpp @@ -35,8 +35,8 @@ */ #include "MemoryManager.h" -#include "common/DebugManager.h" -#include "configuration/Configuration.h" +#include "../common/DebugManager.h" +#include "../configuration/Configuration.h" #include using namespace tlm; diff --git a/DRAMSys/simulator/MemoryManager.h b/DRAMSys/library/src/simulation/MemoryManager.h similarity index 100% rename from DRAMSys/simulator/MemoryManager.h rename to DRAMSys/library/src/simulation/MemoryManager.h diff --git a/DRAMSys/library/src/simulation/ReorderBuffer.h b/DRAMSys/library/src/simulation/ReorderBuffer.h index bb0b925e..d2d84077 100644 --- a/DRAMSys/library/src/simulation/ReorderBuffer.h +++ b/DRAMSys/library/src/simulation/ReorderBuffer.h @@ -39,15 +39,11 @@ #define REORDERBUFFER_H #include -#include #include #include -#include -#include -#include +#include -struct ReorderBuffer : public sc_module -{ +struct ReorderBuffer: public sc_module { public: tlm_utils::simple_initiator_socket iSocket; tlm_utils::simple_target_socket tSocket; diff --git a/DRAMSys/library/src/simulation/Setup.cpp b/DRAMSys/library/src/simulation/Setup.cpp new file mode 100644 index 00000000..b2b8ca79 --- /dev/null +++ b/DRAMSys/library/src/simulation/Setup.cpp @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2017, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Matthias Jung + */ + +#include "Setup.h" + +Setup::Setup(std::string uri, + std::string &memspec, + std::string &mcconfig, + std::string &amconfig, + std::string &simconfig, + std::string &thermalconfig) +{ + // Load Simulation: + tinyxml2::XMLDocument simulationdoc; + loadXML(uri, simulationdoc); + + tinyxml2::XMLElement *simulation = + simulationdoc.FirstChildElement("simulation"); + + std::string xmlNodeName(simulation->Name()); + if ( xmlNodeName != "simulation") + reportFatal("SimulationManager", + "Cannot load simulation: simulation node expected"); + + // Load all sub-configuration XML files: + tinyxml2::XMLElement *s; + + s = simulation->FirstChildElement("memspec"); + memspec = s->Attribute("src"); + + s = simulation->FirstChildElement("mcconfig"); + mcconfig = s->Attribute("src"); + + s = simulation->FirstChildElement("addressmapping"); + amconfig = s->Attribute("src"); + + s = simulation->FirstChildElement("simconfig"); + simconfig = s->Attribute("src"); + + s = simulation->FirstChildElement("thermalconfig"); + thermalconfig = s->Attribute("src"); + +} diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.h b/DRAMSys/library/src/simulation/Setup.h similarity index 64% rename from DRAMSys/library/src/simulation/DRAMSysRecordable.h rename to DRAMSys/library/src/simulation/Setup.h index 318d9307..34d064e1 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.h +++ b/DRAMSys/library/src/simulation/Setup.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, University of Kaiserslautern + * Copyright (c) 2017, University of Kaiserslautern * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,37 +30,29 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: - * Lukas Steiner + * Matthias Jung */ -#ifndef DRAMSYSRECORDABLE_H -#define DRAMSYSRECORDABLE_H +#ifndef SETUP_H +#define SETUP_H -#include "DRAMSys.h" -#include "../common/TlmRecorder.h" +#include +#include -class DRAMSysRecordable : public DRAMSys +#include "../common/utils.h" +#include "TracePlayer.h" +#include "StlPlayer.h" + + +class Setup { public: - DRAMSysRecordable(sc_module_name name, - std::string simulationToRun, - std::string pathToResources); - - virtual ~DRAMSysRecordable(); - -private: - // Transaction Recorders (one per channel). - // They generate the output databases. - std::vector tlmRecorders; - - void setupTlmRecorders(const std::string &traceName, - const std::string &pathToResources); - - void instantiateModules(const std::string &traceName, - const std::string &pathToResources, - const std::string &amconfig); - - void bindSockets(); + Setup(std::string uri, + std::string &memspec, + std::string &mcconfig, + std::string &amconfig, + std::string &simconfig, + std::string &thermalconfig); }; -#endif // DRAMSYSRECORDABLE_H +#endif // SETUP_H diff --git a/DRAMSys/simulator/StlPlayer.h b/DRAMSys/library/src/simulation/StlPlayer.h similarity index 100% rename from DRAMSys/simulator/StlPlayer.h rename to DRAMSys/library/src/simulation/StlPlayer.h diff --git a/DRAMSys/library/src/simulation/TemperatureController.h b/DRAMSys/library/src/simulation/TemperatureController.h index 91e77082..a0ecc5b3 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.h +++ b/DRAMSys/library/src/simulation/TemperatureController.h @@ -59,18 +59,18 @@ public: } SC_CTOR(TemperatureController) { - temperatureScale = Configuration::getInstance().temperatureSim.temperatureScale; + temperatureScale = Configuration::getInstance().temperatureSim.TemperatureScale; dynamicTempSimEnabled = Configuration::getInstance().thermalSimulation; staticTemperature = - Configuration::getInstance().temperatureSim.staticTemperatureDefaultValue; + Configuration::getInstance().temperatureSim.StaticTemperatureDefaultValue; if (dynamicTempSimEnabled == true) { #ifdef THERMALSIM // Connect to the server - std::string ip = Configuration::getInstance().temperatureSim.iceServerIp; - unsigned int port = Configuration::getInstance().temperatureSim.iceServerPort; + std::string ip = Configuration::getInstance().temperatureSim.IceServerIp; + unsigned int port = Configuration::getInstance().temperatureSim.IceServerPort; thermalSimulation = new IceWrapper(ip, port); PRINTDEBUGMESSAGE(name(), "Dynamic temperature simulation. Server @ " + ip + ":" + std::to_string(port)); @@ -87,21 +87,21 @@ public: powerThresholds = Configuration::getInstance().temperatureSim.powerThresholds; decreaseSimPeriod = false; periodAdjustFactor = - Configuration::getInstance().temperatureSim.simPeriodAdjustFactor; + Configuration::getInstance().temperatureSim.SimPeriodAdjustFactor; nPowStableCyclesToIncreasePeriod = - Configuration::getInstance().temperatureSim.nPowStableCyclesToIncreasePeriod; + Configuration::getInstance().temperatureSim.NPowStableCyclesToIncreasePeriod; cyclesSinceLastPeriodAdjust = 0; // Get the target period for the thermal simulation from config. - targetPeriod = Configuration::getInstance().temperatureSim.thermalSimPeriod; + targetPeriod = Configuration::getInstance().temperatureSim.ThermalSimPeriod; period = targetPeriod; - t_unit = Configuration::getInstance().temperatureSim.thermalSimUnit; + t_unit = Configuration::getInstance().temperatureSim.ThermalSimUnit; - genTempMap = Configuration::getInstance().temperatureSim.generateTemperatureMap; + genTempMap = Configuration::getInstance().temperatureSim.GenerateTemperatureMap; temperatureMapFile = "temperature_map"; std::system("rm -f temperature_map*"); - genPowerMap = Configuration::getInstance().temperatureSim.generatePowerMap; + genPowerMap = Configuration::getInstance().temperatureSim.GeneratePowerMap; powerMapFile = "power_map"; std::system("rm -f power_map*"); diff --git a/DRAMSys/simulator/TraceGenerator.h b/DRAMSys/library/src/simulation/TraceGenerator.h similarity index 100% rename from DRAMSys/simulator/TraceGenerator.h rename to DRAMSys/library/src/simulation/TraceGenerator.h diff --git a/DRAMSys/simulator/TracePlayer.cpp b/DRAMSys/library/src/simulation/TracePlayer.cpp similarity index 100% rename from DRAMSys/simulator/TracePlayer.cpp rename to DRAMSys/library/src/simulation/TracePlayer.cpp diff --git a/DRAMSys/simulator/TracePlayer.h b/DRAMSys/library/src/simulation/TracePlayer.h similarity index 97% rename from DRAMSys/simulator/TracePlayer.h rename to DRAMSys/library/src/simulation/TracePlayer.h index 445f8c29..d87e747b 100644 --- a/DRAMSys/simulator/TracePlayer.h +++ b/DRAMSys/library/src/simulation/TracePlayer.h @@ -47,8 +47,8 @@ #include #include #include "MemoryManager.h" -#include "configuration/Configuration.h" -#include "common/DebugManager.h" +#include "../configuration/Configuration.h" +#include "../common/DebugManager.h" #include "TracePlayerListener.h" struct TracePlayer : public sc_module diff --git a/DRAMSys/simulator/TracePlayerListener.h b/DRAMSys/library/src/simulation/TracePlayerListener.h similarity index 100% rename from DRAMSys/simulator/TracePlayerListener.h rename to DRAMSys/library/src/simulation/TracePlayerListener.h diff --git a/DRAMSys/simulator/TraceSetup.cpp b/DRAMSys/library/src/simulation/TraceSetup.cpp similarity index 52% rename from DRAMSys/simulator/TraceSetup.cpp rename to DRAMSys/library/src/simulation/TraceSetup.cpp index a560f0d6..778b25ac 100644 --- a/DRAMSys/simulator/TraceSetup.cpp +++ b/DRAMSys/library/src/simulation/TraceSetup.cpp @@ -31,7 +31,6 @@ * * Authors: * Matthias Jung - * Luiza Correa */ #include "TraceSetup.h" @@ -41,54 +40,64 @@ TraceSetup::TraceSetup(std::string uri, std::vector *devices) { // Load Simulation: - nlohmann::json simulationdoc = parseJSON(uri); + tinyxml2::XMLDocument simulationdoc; + loadXML(uri, simulationdoc); - if (simulationdoc["simulation"].empty()) - SC_REPORT_FATAL("traceSetup", + tinyxml2::XMLElement *simulation = + simulationdoc.FirstChildElement("simulation"); + + std::string xmlNodeName(simulation->Name()); + if ( xmlNodeName != "simulation") + reportFatal("traceSetup", "Cannot load simulation: simulation node expected"); // Load TracePlayers: - for (auto it : simulationdoc["simulation"]["tracesetup"].items()) + tinyxml2::XMLElement *tracesetup = + simulation->FirstChildElement("tracesetup"); + + for (tinyxml2::XMLElement *device = + tracesetup->FirstChildElement("device"); + device != NULL; + device = device->NextSiblingElement("device")) { - auto value = it.value(); - if (!value.empty()) - { - sc_time playerClk; - unsigned int frequencyMHz = value["clkMhz"]; + sc_time playerClk; + unsigned int frequencyMHz = device->IntAttribute("clkMhz"); - if (frequencyMHz == 0) - SC_REPORT_FATAL("traceSetup", "No Frequency Defined"); - else - playerClk = sc_time(1.0 / frequencyMHz, SC_US); + if (frequencyMHz == 0) + reportFatal("traceSetup", "No Frequency Defined"); + else + playerClk = sc_time(1.0 / frequencyMHz, SC_US); - std::string name = value["name"]; + std::string name = device->GetText(); - size_t pos = name.rfind('.'); - if (pos == std::string::npos) - throw std::runtime_error("Name of the trace file does not contain a valid extension."); + size_t pos = name.rfind('.'); + if (pos == std::string::npos) { + throw std::runtime_error("Name of the trace file does not contain a valid extension."); + } - // Get the extension and make it lower case - std::string ext = name.substr(pos + 1); - std::transform(ext.begin(), ext.end(), ext.begin(), ::tolower); + // Get the extension and make it lower case + std::string ext = name.substr(pos + 1); + std::transform(ext.begin(), ext.end(), ext.begin(), ::tolower); - std::string stlFile = pathToResources + std::string("traces/") + name; - std::string moduleName = name; + std::string stlFile = pathToResources + std::string("traces/") + name; + std::string moduleName = name; - // replace all '.' to '_' - std::replace(moduleName.begin(), moduleName.end(), '.', '_'); + // replace all '.' to '_' + std::replace(moduleName.begin(), moduleName.end(), '.', '_'); - TracePlayer *player; - if (ext == "stl") - player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, this); - else if (ext == "rstl") - player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, this); - else - throw std::runtime_error("Unsupported file extension in " + name); + TracePlayer *player; + if (ext == "stl") { + player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, this); + } else if (ext == "rstl") { + player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, this); + } else { + std::string error = "Unsupported file extension in " + name; + throw std::runtime_error(error); + } + devices->push_back(player); - devices->push_back(player); - - if (Configuration::getInstance().simulationProgressBar) - totalTransactions += player->getNumberOfLines(stlFile); + if (Configuration::getInstance().simulationProgressBar) { + totalTransactions += player->getNumberOfLines(stlFile); } } @@ -100,8 +109,9 @@ void TraceSetup::tracePlayerTerminates() { finishedTracePlayers++; - if (finishedTracePlayers == numberOfTracePlayers) + if (finishedTracePlayers == numberOfTracePlayers) { sc_stop(); + } } void TraceSetup::transactionFinished() { @@ -109,6 +119,7 @@ void TraceSetup::transactionFinished() loadbar(totalTransactions - remainingTransactions, totalTransactions); - if (remainingTransactions == 0) + if (remainingTransactions == 0) { std::cout << std::endl; + } } diff --git a/DRAMSys/simulator/TraceSetup.h b/DRAMSys/library/src/simulation/TraceSetup.h similarity index 98% rename from DRAMSys/simulator/TraceSetup.h rename to DRAMSys/library/src/simulation/TraceSetup.h index a8f5fb4a..a65ae1f2 100644 --- a/DRAMSys/simulator/TraceSetup.h +++ b/DRAMSys/library/src/simulation/TraceSetup.h @@ -39,7 +39,7 @@ #include #include -#include "common/utils.h" +#include "../common/utils.h" #include "TracePlayer.h" #include "StlPlayer.h" diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index 16a76f98..feaea294 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -107,22 +107,8 @@ Dram::~Dram() { if (Configuration::getInstance().powerAnalysis) { - reportPower(); - delete DRAMPower; - } - - if (Configuration::getInstance().useMalloc) - free(memory); -} - -void Dram::reportPower() -{ - static bool alreadyCalled = false; - - if (!alreadyCalled) - { - alreadyCalled = true; - DRAMPower->calcEnergy(); + if (!Configuration::getInstance().databaseRecording) + DRAMPower->calcEnergy(); // Print the final total energy and the average power for // the simulation: @@ -138,7 +124,12 @@ void Dram::reportPower() << DRAMPower->getPower().average_power * Configuration::getInstance().numberOfDevicesOnDIMM << std::string(" mW") << std::endl; + + delete DRAMPower; } + + if (Configuration::getInstance().useMalloc) + free(memory); } tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, diff --git a/DRAMSys/library/src/simulation/dram/Dram.h b/DRAMSys/library/src/simulation/dram/Dram.h index 5a068c67..04a286f9 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.h +++ b/DRAMSys/library/src/simulation/dram/Dram.h @@ -73,7 +73,6 @@ protected: public: tlm_utils::simple_target_socket tSocket; - virtual void reportPower(); virtual ~Dram(); }; diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index 67830919..d1a8df14 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -62,12 +62,16 @@ DramRecordable::DramRecordable(sc_module_name name, TlmRecorder *tlmRe } template -void DramRecordable::reportPower() +DramRecordable::~DramRecordable() { - BaseDram::reportPower(); - tlmRecorder->recordPower(sc_time_stamp().to_seconds(), - this->DRAMPower->getPower().window_average_power - * Configuration::getInstance().numberOfDevicesOnDIMM); + if (Configuration::getInstance().powerAnalysis) + { + this->DRAMPower->calcEnergy(); + tlmRecorder->recordPower(sc_time_stamp().to_seconds(), + this->DRAMPower->getPower().window_average_power + * Configuration::getInstance().numberOfDevicesOnDIMM); + } + tlmRecorder->closeConnection(); } template @@ -95,7 +99,7 @@ void DramRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase unsigned int row __attribute__((unused)) = DramExtension::getExtension(trans).getRow().ID(); unsigned int col __attribute__((unused)) = DramExtension::getExtension(trans).getColumn().ID(); - PRINTDEBUGMESSAGE(this->name(), "Recording " + std::string(phase.get_name()) + " thread " + + PRINTDEBUGMESSAGE(this->name(), "Recording " + phaseNameToString(phase) + " thread " + std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string( bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " + std::to_string(col) + " at " + recTime.to_string()); diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.h b/DRAMSys/library/src/simulation/dram/DramRecordable.h index db668652..fe835bf1 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.h +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.h @@ -48,8 +48,7 @@ class DramRecordable final : public BaseDram public: DramRecordable(sc_module_name, TlmRecorder *); SC_HAS_PROCESS(DramRecordable); - - virtual void reportPower(); + ~DramRecordable(); private: virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index 13ebb2ea..f9a25628 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -104,8 +104,8 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) memTimingSpec.WTR_S = memSpec->tWTR / memSpec->tCK; memTimingSpec.XP = memSpec->tXP / memSpec->tCK; memTimingSpec.XPDLL = memSpec->tXP / memSpec->tCK; - memTimingSpec.XS = memSpec->tXSR / memSpec->tCK; - memTimingSpec.XSDLL = memSpec->tXSR / memSpec->tCK; + memTimingSpec.XS = memSpec->tXS / memSpec->tCK; + memTimingSpec.XSDLL = memSpec->tXS / memSpec->tCK; MemPowerSpec memPowerSpec; memPowerSpec.idd0 = memSpec->iDD0; diff --git a/DRAMSys/pct/buildDRAMSys.sh b/DRAMSys/pct/buildDRAMSys.sh new file mode 100755 index 00000000..7b578cc9 --- /dev/null +++ b/DRAMSys/pct/buildDRAMSys.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +JOBS=$(nproc --all) + +rm -rf lib +mkdir lib +cd lib +DRAMSYS_PCT=true qmake ../../simulator/library.pro +DRAMSYS_PCT=true make -j$JOBS diff --git a/DRAMSys/pct/createPlatform.tcl b/DRAMSys/pct/createPlatform.tcl index d6a1c661..d90015b5 100644 --- a/DRAMSys/pct/createPlatform.tcl +++ b/DRAMSys/pct/createPlatform.tcl @@ -47,10 +47,9 @@ ::pct::create_instance Project:DRAMSys /HARDWARE i_DRAMSys DRAMSys {DRAMSys(simulationToRun, pathToResources)} # Add DRAMSys Library // ../[glob -type d ../../build*]/simulator/ -::pct::set_simulation_build_project_setting Debug Libraries "sqlite3 DRAMSysLibrary DRAMPower" -::pct::set_simulation_build_project_setting Debug {Library Search Paths} [concat ../../../build/library/ ../../../build/library/src/common/third_party/DRAMPower] +::pct::set_simulation_build_project_setting Debug Libraries "sqlite3 DRAMSys drampower" +::pct::set_simulation_build_project_setting Debug {Library Search Paths} [concat ../lib/ /usr/lib64/ ../../simulator/src/common/third_party/DRAMPower/src/] ::pct::set_simulation_build_project_setting Debug {Defined Symbols} SC_INCLUDE_DYNAMIC_PROCESSES=1 -::pct::set_simulation_build_project_setting Debug {Compiler Flags} {-std=c++11} # Disable Fast Linking and Caching and Elaboration ::pct::set_simulation_build_project_setting Debug {Cache Objects} false @@ -60,8 +59,8 @@ ::pct::set_simulation_build_project_setting Debug {Make Jobs} 16 # Configure DDR3 Example: -::pct::set_param_value /HARDWARE/i_DRAMSys {Constructor Arguments} pathToResources ../../library/resources/ -::pct::set_param_value /HARDWARE/i_DRAMSys {Constructor Arguments} simulationToRun ../../library/resources/simulations/ddr3-example.xml +::pct::set_param_value /HARDWARE/i_DRAMSys {Constructor Arguments} pathToResources ../../simulator/resources/ +::pct::set_param_value /HARDWARE/i_DRAMSys {Constructor Arguments} simulationToRun ../../simulator/resources/simulations/ddr3-example.xml # Build Rest of the Example system: ::pct::open_library "GFRBM" @@ -72,7 +71,7 @@ ::pct::create_connection C_1 /HARDWARE /HARDWARE/i_ClockGenerator/CLK /HARDWARE/i_GFRBM_TLM2/CLK # Configure GFRBM: -::pct::set_param_value /HARDWARE/i_GFRBM_TLM2 {Scml Properties} InputFile ../../library/resources/traces/pct.stl +::pct::set_param_value /HARDWARE/i_GFRBM_TLM2 {Scml Properties} InputFile ../../simulator/resources/traces/pct.stl ::pct::set_param_value /HARDWARE/i_GFRBM_TLM2 {Template Arguments} NUM_IN_IRQ 0 ::pct::set_param_value /HARDWARE/i_GFRBM_TLM2 {Template Arguments} NUM_OUT_IRQ 0 ::pct::set_param_value /HARDWARE/i_GFRBM_TLM2 {Extra properties} /all_encaps/LogFile foo.log diff --git a/DRAMSys/simulator/CMakeLists.txt b/DRAMSys/simulator/CMakeLists.txt deleted file mode 100644 index 23c68f3a..00000000 --- a/DRAMSys/simulator/CMakeLists.txt +++ /dev/null @@ -1,62 +0,0 @@ -# Copyright (c) 2020, Fraunhofer IESE -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Author: Matthias Jung - -cmake_minimum_required(VERSION 3.10) - -# Project Name -project(DRAMSysSimulator) - -# Configuration: -set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") -set(DCMAKE_SH="CMAKE_SH-NOTFOUND") - -if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/../library/src/simulation/DRAMSysRecordable.cpp) - add_definitions(-DRECORDING) -endif() - -add_executable(DRAMSys - main.cpp - ExampleInitiator.h - MemoryManager.cpp - StlPlayer.h - TraceGenerator.h - TracePlayer.cpp - TracePlayerListener.h - TraceSetup.cpp) - -target_include_directories(DRAMSys - PUBLIC ../library/src/ -) - -target_link_libraries(DRAMSys - PRIVATE DRAMSysLibrary -) diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index 7a99c49e..cf231c5f 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -32,8 +32,6 @@ * Authors: * Robert Gernhardt * Matthias Jung - * Luiza Correa - * Lukas Steiner */ #include @@ -43,15 +41,10 @@ #include #include -#include "simulation/DRAMSys.h" +#include "DRAMSys.h" #include "TraceSetup.h" -#ifdef RECORDING -#include "simulation/DRAMSysRecordable.h" -#include "common/third_party/nlohmann/single_include/nlohmann/json.hpp" - -using json = nlohmann::json; -#endif +std::string resources; std::string pathOfFile(std::string file) { @@ -67,50 +60,39 @@ int sc_main(int argc, char **argv) { sc_set_time_resolution(1, SC_PS); - std::string resources; - std::string simulationJson; - // Run only with default config (ddr3-example.json): + + std::string SimulationXML; + // Run only with default config (ddr-example.xml): if (argc == 1) { // Get path of resources: resources = pathOfFile(argv[0]) - + std::string("/../../DRAMSys/library/resources/"); - simulationJson = resources + "simulations/ddr3-example.json"; + + std::string("/../DRAMSys/library/resources/"); + SimulationXML = resources + "simulations/ddr3-example.xml"; } // Run with specific config but default resource folders: else if (argc == 2) { // Get path of resources: resources = pathOfFile(argv[0]) - + std::string("/../../DRAMSys/library/resources/"); - simulationJson = argv[1]; + + std::string("/../DRAMSys/library/resources/"); + SimulationXML = argv[1]; } // Run with spefific config and specific resource folder: else if (argc == 3) { - simulationJson = argv[1]; + SimulationXML = argv[1]; resources = argv[2]; } std::vector players; // Instantiate DRAMSys: - DRAMSys *dramSys; -#ifdef RECORDING - json simulationdoc = parseJSON(simulationJson); - json simulatordoc = parseJSON(resources + "configs/simulator/" - + std::string(simulationdoc["simulation"]["simconfig"])); - - if (simulatordoc["simconfig"]["DatabaseRecording"]) - dramSys = new DRAMSysRecordable("DRAMSys", simulationJson, resources); - else -#endif - dramSys = new DRAMSys("DRAMSys", simulationJson, resources); + DRAMSys *dramSys = new DRAMSys("DRAMSys", SimulationXML, resources); // Instantiate STL Players: - TraceSetup *ts = new TraceSetup(simulationJson, resources, &players); + TraceSetup *ts = new TraceSetup(SimulationXML, resources, &players); // Bind STL Players with DRAMSys: - for (size_t i = 0; i < players.size(); i++) - { - if (Configuration::getInstance().checkTLM2Protocol) + for (size_t i = 0; i < players.size(); i++) { + if(Configuration::getInstance().checkTLM2Protocol) { std::string str = "TLMCheckerPlayer" + std::to_string(i); tlm_utils::tlm2_base_protocol_checker<> *playerTlmChecker = @@ -129,8 +111,9 @@ int sc_main(int argc, char **argv) auto start = std::chrono::high_resolution_clock::now(); // Kickstart the players: - for (auto &p : players) + for (auto &p : players) { p->nextPayload(); + } // Start SystemC Simulation: sc_set_stop_mode(SC_STOP_FINISH_DELTA); diff --git a/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml b/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml index b2c3af48..39d66692 100644 --- a/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml +++ b/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml @@ -1,34 +1,25 @@ - - - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - - \ No newline at end of file + + + + + + + + + + diff --git a/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml b/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml index 44bf294e..ed869b57 100644 --- a/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml +++ b/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml @@ -1,20 +1,50 @@ - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml b/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml index 7240485d..20db08cd 100644 --- a/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml +++ b/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml @@ -1,20 +1,50 @@ - - - + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/tests/DDR3/scripts/createTraceDB.sql b/DRAMSys/tests/DDR3/scripts/createTraceDB.sql index 7a127fac..1ba6c3aa 100644 --- a/DRAMSys/tests/DDR3/scripts/createTraceDB.sql +++ b/DRAMSys/tests/DDR3/scripts/createTraceDB.sql @@ -1,6 +1,5 @@ DROP TABLE IF EXISTS Phases; DROP TABLE IF EXISTS GeneralInfo; -DROP TABLE IF EXISTS CommandLengths; DROP TABLE IF EXISTS Comments; DROP TABLE IF EXISTS ranges; DROP TABLE IF EXISTS Transactions; @@ -18,7 +17,6 @@ CREATE TABLE Phases( CREATE TABLE GeneralInfo( NumberOfTransactions INTEGER, TraceEnd INTEGER, - NumberOfRanks INTEGER, NumberOfBanks INTEGER, clk INTEGER, UnitOfTime TEXT, @@ -31,24 +29,6 @@ CREATE TABLE GeneralInfo( ControllerThread INTEGER ); -CREATE TABLE CommandLengths( - ACT INTEGER, - PRE INTEGER, - PREA INTEGER, - RD INTEGER, - RDA INTEGER, - WR INTEGER, - WRA INTEGER, - REFA INTEGER, - REFB INTEGER, - PDEA INTEGER, - PDXA INTEGER, - PDEP INTEGER, - PDXP INTEGER, - SREFEN INTEGER, - SREFEX INTEGER -); - CREATE TABLE Power( time DOUBLE, AveragePower DOUBLE @@ -78,9 +58,8 @@ CREATE TABLE Transactions( Burstlength INTEGER, TThread INTEGER, TChannel INTEGER, - TRank INTEGER, - TBankgroup INTEGER, TBank INTEGER, + TBankgroup INTEGER, TRow INTEGER, TColumn INTEGER, DataStrobeBegin INTEGER, diff --git a/DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql b/DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql index 7a127fac..1ba6c3aa 100644 --- a/DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql +++ b/DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql @@ -1,6 +1,5 @@ DROP TABLE IF EXISTS Phases; DROP TABLE IF EXISTS GeneralInfo; -DROP TABLE IF EXISTS CommandLengths; DROP TABLE IF EXISTS Comments; DROP TABLE IF EXISTS ranges; DROP TABLE IF EXISTS Transactions; @@ -18,7 +17,6 @@ CREATE TABLE Phases( CREATE TABLE GeneralInfo( NumberOfTransactions INTEGER, TraceEnd INTEGER, - NumberOfRanks INTEGER, NumberOfBanks INTEGER, clk INTEGER, UnitOfTime TEXT, @@ -31,24 +29,6 @@ CREATE TABLE GeneralInfo( ControllerThread INTEGER ); -CREATE TABLE CommandLengths( - ACT INTEGER, - PRE INTEGER, - PREA INTEGER, - RD INTEGER, - RDA INTEGER, - WR INTEGER, - WRA INTEGER, - REFA INTEGER, - REFB INTEGER, - PDEA INTEGER, - PDXA INTEGER, - PDEP INTEGER, - PDXP INTEGER, - SREFEN INTEGER, - SREFEX INTEGER -); - CREATE TABLE Power( time DOUBLE, AveragePower DOUBLE @@ -78,9 +58,8 @@ CREATE TABLE Transactions( Burstlength INTEGER, TThread INTEGER, TChannel INTEGER, - TRank INTEGER, - TBankgroup INTEGER, TBank INTEGER, + TBankgroup INTEGER, TRow INTEGER, TColumn INTEGER, DataStrobeBegin INTEGER, diff --git a/DRAMSys/traceAnalyzer/CMakeLists.txt b/DRAMSys/traceAnalyzer/CMakeLists.txt index 00a70740..3db02a3b 100644 --- a/DRAMSys/traceAnalyzer/CMakeLists.txt +++ b/DRAMSys/traceAnalyzer/CMakeLists.txt @@ -30,20 +30,25 @@ # # Author: Matthias Jung -cmake_minimum_required(VERSION 3.12) +cmake_minimum_required(VERSION 3.10) # Project Name: project(TraceAnalyzer) -# Add Python3 Dependency: -find_package(Python3 COMPONENTS Development) +# Add Python Dependency: +find_library(PYTHON3_LIBRARY NAMES Python3) + +# Add sqlite3 Dependency: +find_package(PythonLibs REQUIRED) # Add QWT Dependency: -find_library(QWT_LIBRARY NAMES "qwt-qt5" "qwt" PATHS "$ENV{QWT_HOME}/lib") -find_path(QWT_INCLUDE_DIRS NAMES "qwt_plot.h" PATHS +find_library(QWT_LIBRARY NAMES "qwt-qt5" "qwt") +find_path (QWT_INCLUDE_DIRS NAMES "qwt_plot.h" PATHS "/usr/include/qwt-qt5" "/usr/include/qwt" - "$ENV{QWT_HOME}/include" + "C:\\Qwt\\" + "C:\\Qwt-6.1.4\\" + "C:\\Users\\jung\\Zeugs\\qwt\\qwt-614-install\\include" ) # Add QT Library: @@ -54,9 +59,21 @@ set(CMAKE_AUTORCC ON) set(CMAKE_INCLUDE_CURRENT_DIR ON) # Configure: -set(CMAKE_CXX_STANDARD 11) +set (CMAKE_CXX_STANDARD 11) set(DCMAKE_SH="CMAKE_SH-NOTFOUND") +include_directories( + ${QWT_INCLUDE_DIRS} + ${PYTHON_INCLUDE_DIRS} + ./ + businessObjects/ + businessObjects/phases/ + data/ + presentation/ + presentation/util/ +) + + add_executable(TraceAnalyzer main.cpp businessObjects/transaction.cpp @@ -69,7 +86,7 @@ add_executable(TraceAnalyzer gototimedialog.cpp presentation/traceplot.cpp tracefiletab.cpp - presentation/tracescroller.cpp + presentation/pornotracescroller.cpp traceanalyzer.cpp presentation/transactiontreewidget.cpp presentation/commenttreewidget.cpp @@ -87,7 +104,6 @@ add_executable(TraceAnalyzer businessObjects/tracetestresults.cpp presentation/tracemetrictreewidget.cpp businessObjects/phases/phase.cpp - selectmetrics.ui preferences.ui evaluationtool.ui @@ -95,24 +111,11 @@ add_executable(TraceAnalyzer tracefiletab.ui queryeditor.ui traceanalyzer.ui - - scripts/memUtil.py - scripts/metrics.py - scripts/tests.py - scripts/plots.py - scripts/sonification.pl - scripts/dataExtractForNN.pl -) - -target_include_directories(TraceAnalyzer - PRIVATE ${QWT_INCLUDE_DIRS} - PRIVATE ${Python3_INCLUDE_DIRS} ) # Build: target_link_libraries(TraceAnalyzer - PRIVATE ${Python3_LIBRARIES} - PRIVATE ${QWT_LIBRARY} - PRIVATE Qt5::Widgets - PRIVATE Qt5::Sql + ${PYTHON_LIBRARIES} + ${QWT_LIBRARY} ) +qt5_use_modules(TraceAnalyzer Widgets Sql) diff --git a/DRAMSys/traceAnalyzer/mainwindow.cpp b/DRAMSys/traceAnalyzer/mainwindow.cpp index 0e911285..9bdc2565 100644 --- a/DRAMSys/traceAnalyzer/mainwindow.cpp +++ b/DRAMSys/traceAnalyzer/mainwindow.cpp @@ -52,7 +52,7 @@ MainWindow::MainWindow(QWidget *parent) : db = new TraceDB("tpr.tdb", true); traceNavigator = new TraceNavigator(db->getGeneralInfo(), this); ui->tracePlot->init(traceNavigator, db); - ui->traceScroller->init(traceNavigator, db, ui->tracePlot); + ui->pornoTraceScroller->init(traceNavigator, db, ui->tracePlot); phases = db->getPhasesInTimespan( traceNavigator->GeneralTraceInfo().TraceSpan()); transactions = db->getTransactionsInTimespan( diff --git a/DRAMSys/traceAnalyzer/presentation/tracescroller.cpp b/DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp similarity index 91% rename from DRAMSys/traceAnalyzer/presentation/tracescroller.cpp rename to DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp index 64506edf..8b66efd2 100644 --- a/DRAMSys/traceAnalyzer/presentation/tracescroller.cpp +++ b/DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp @@ -38,11 +38,11 @@ #include #include #include -#include "tracescroller.h" +#include "pornotracescroller.h" #include "traceplotitem.h" #include "util/engineeringScaleDraw.h" -TraceScroller::TraceScroller(QWidget *parent): +PornoTraceScroller::PornoTraceScroller(QWidget *parent): QwtPlot(parent), isInitialized(false), drawingProperties(false, false, ColorGrouping::PhaseType) { @@ -53,7 +53,7 @@ TraceScroller::TraceScroller(QWidget *parent): canvasClip->attach(this); } -void TraceScroller::init(TraceNavigator *navigator, TracePlot *tracePlot) +void PornoTraceScroller::init(TraceNavigator *navigator, TracePlot *tracePlot) { Q_ASSERT(isInitialized == false); isInitialized = true; @@ -76,7 +76,7 @@ void TraceScroller::init(TraceNavigator *navigator, TracePlot *tracePlot) } -void TraceScroller::setUpTracePlotItem() +void PornoTraceScroller::setUpTracePlotItem() { TracePlotItem *tracePlotItem = new TracePlotItem(transactions, *navigator, drawingProperties); @@ -84,7 +84,7 @@ void TraceScroller::setUpTracePlotItem() tracePlotItem->attach(this); } -void TraceScroller::setUpDrawingProperties() +void PornoTraceScroller::setUpDrawingProperties() { drawingProperties.numberOfRanks = navigator->GeneralTraceInfo().numberOfRanks; drawingProperties.numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; @@ -96,14 +96,14 @@ void TraceScroller::setUpDrawingProperties() } -void TraceScroller::setUpAxis() +void PornoTraceScroller::setUpAxis() { setAxisScale(yLeft, -1, navigator->GeneralTraceInfo().numberOfBanks + 2, 1.0); axisScaleDraw(yLeft)->enableComponent(QwtAbstractScaleDraw::Labels, false ); axisScaleDraw(yLeft)->enableComponent(QwtAbstractScaleDraw::Ticks, false ); } -void TraceScroller::connectNavigatorQ_SIGNALS() +void PornoTraceScroller::connectNavigatorQ_SIGNALS() { QObject::connect(navigator, SIGNAL(currentTraceTimeChanged()), this, SLOT(currentTraceTimeChanged())); @@ -113,15 +113,15 @@ void TraceScroller::connectNavigatorQ_SIGNALS() SLOT(selectedTransactionsChanged())); } -Timespan TraceScroller::GetCurrentTimespan() +Timespan PornoTraceScroller::GetCurrentTimespan() { traceTime deltaOnTracePlot = navigator->GeneralTraceInfo().span.End() - tracePlot->ZoomLevel(); - traceTime deltaOnTraceScroller = navigator->GeneralTraceInfo().span.End() - + traceTime deltaOnPornoTraceScroller = navigator->GeneralTraceInfo().span.End() - zoomLevel; traceTime newBegin = static_cast - (tracePlot->GetCurrentTimespan().Begin() * (1.0 * deltaOnTraceScroller) / + (tracePlot->GetCurrentTimespan().Begin() * (1.0 * deltaOnPornoTraceScroller) / deltaOnTracePlot); Timespan span(newBegin, newBegin + zoomLevel); @@ -133,7 +133,7 @@ Timespan TraceScroller::GetCurrentTimespan() } -void TraceScroller::getAndDrawComments() +void PornoTraceScroller::getAndDrawComments() { for (const auto &pair : navigator->getComments()) { const Comment &comment = pair.second; @@ -151,18 +151,18 @@ void TraceScroller::getAndDrawComments() * */ -void TraceScroller::selectedTransactionsChanged() +void PornoTraceScroller::selectedTransactionsChanged() { replot(); } -void TraceScroller::colorGroupingChanged(ColorGrouping colorGrouping) +void PornoTraceScroller::colorGroupingChanged(ColorGrouping colorGrouping) { drawingProperties.colorGrouping = colorGrouping; replot(); } -void TraceScroller::currentTraceTimeChanged() +void PornoTraceScroller::currentTraceTimeChanged() { Timespan spanOnTracePlot = tracePlot->GetCurrentTimespan(); canvasClip->setInterval(spanOnTracePlot.Begin(), spanOnTracePlot.End()); @@ -172,21 +172,21 @@ void TraceScroller::currentTraceTimeChanged() replot(); } -void TraceScroller::commentsChanged() +void PornoTraceScroller::commentsChanged() { detachItems(QwtPlotItem::Rtti_PlotMarker); getAndDrawComments(); replot(); } -void TraceScroller::tracePlotZoomChanged() +void PornoTraceScroller::tracePlotZoomChanged() { zoomLevel = tracePlot->ZoomLevel() * tracePlotEnlargementFactor; if (zoomLevel > navigator->GeneralTraceInfo().span.timeCovered()) zoomLevel = navigator->GeneralTraceInfo().span.timeCovered(); } -bool TraceScroller::eventFilter( QObject *object, QEvent *event ) +bool PornoTraceScroller::eventFilter( QObject *object, QEvent *event ) { if (object == canvas()) { static bool clipDragged = false; diff --git a/DRAMSys/traceAnalyzer/presentation/tracescroller.h b/DRAMSys/traceAnalyzer/presentation/pornotracescroller.h similarity index 93% rename from DRAMSys/traceAnalyzer/presentation/tracescroller.h rename to DRAMSys/traceAnalyzer/presentation/pornotracescroller.h index b9166f2e..98f5a97b 100644 --- a/DRAMSys/traceAnalyzer/presentation/tracescroller.h +++ b/DRAMSys/traceAnalyzer/presentation/pornotracescroller.h @@ -35,8 +35,8 @@ * Matthias Jung */ -#ifndef TRACESCROLLER_H -#define TRACESCROLLER_H +#ifndef PORNOTRACESCROLLER_H +#define PORNOTRACESCROLLER_H #include #include @@ -45,7 +45,7 @@ #include "traceplot.h" -class TraceScroller : public QwtPlot +class PornoTraceScroller : public QwtPlot { Q_OBJECT private: @@ -67,7 +67,7 @@ private: TraceDrawingProperties drawingProperties; public: - TraceScroller(QWidget *parent = NULL); + PornoTraceScroller(QWidget *parent = NULL); void init(TraceNavigator *navigator, TracePlot *tracePlot); Timespan GetCurrentTimespan(); @@ -80,4 +80,4 @@ public Q_SLOTS: }; -#endif // TraceScroller_H +#endif // PORNOTRACESCROLLER_H diff --git a/DRAMSys/traceAnalyzer/scripts/memUtil.py b/DRAMSys/traceAnalyzer/scripts/memUtil.py index b7136faa..7ca5f07f 100755 --- a/DRAMSys/traceAnalyzer/scripts/memUtil.py +++ b/DRAMSys/traceAnalyzer/scripts/memUtil.py @@ -1,4 +1,5 @@ -import json +import xml.etree.ElementTree as ET + class MCConfig(object): """ Memory Controller Configuration Class @@ -8,7 +9,7 @@ class MCConfig(object): uses the proper format when searching for elements. """ def getValue(self, id): - return self.jsonMCConfig['mcconfig'][id] + return self.xmlMCConfig.findall(id)[0].attrib['value'] def getIntValue(self, id): return int(self.getValue(id)) @@ -17,7 +18,7 @@ class MCConfig(object): cursor = dbconnection.cursor() cursor.execute("SELECT MCconfig FROM GeneralInfo") result = cursor.fetchone() - self.jsonMCConfig = json.load(open(result[0])) + self.xmlMCConfig = ET.parse(result[0]) class MemSpec(object): @@ -28,18 +29,18 @@ class MemSpec(object): proper format when searching for elements. """ def getValue(self, id): - val = self.jsonMemSpec['memspec'][id] + match = ".//parameter[@id='{0}']".format(id) + val = self.xmlMemSpec.findall(match)[0].attrib['value'] return val - def getIntValue(self, group, id): - val = self.jsonMemSpec['memspec'][group][id] - return int(val) + def getIntValue(self, id): + return int(self.getValue(id)) def __init__(self, dbconnection): cursor = dbconnection.cursor() cursor.execute("SELECT Memspec FROM GeneralInfo") result = cursor.fetchone() - self.jsonMemSpec = json.load(open(result[0])) + self.xmlMemSpec = ET.parse(result[0]) def getClock(dbconnection): @@ -71,8 +72,8 @@ def maximum_data_rate(connection): else: if (memoryType.find("WIDEIO") != -1): width = memspec.getValue("width") - clk = memspec.getIntValue("memtimingspec", "clkMhz") - rate = memspec.getIntValue("memarchitecturespec", "dataRate") + clk = memspec.getValue("clkMhz") + rate = memspec.getValue("dataRate") maxDataRate = float(clk)*float(width)*float(rate) return maxDataRate diff --git a/DRAMSys/traceAnalyzer/scripts/metrics.py b/DRAMSys/traceAnalyzer/scripts/metrics.py index cc4e8e5e..d3fc044d 100644 --- a/DRAMSys/traceAnalyzer/scripts/metrics.py +++ b/DRAMSys/traceAnalyzer/scripts/metrics.py @@ -462,9 +462,7 @@ def time_in_SREFB_percent(connection): @metric def time_in_power_down_states_in_ns(connection): mcconfig = MCConfig(connection) - #bankwiseLogic = mcconfig.getValue("BankwiseLogic") - bankwiseLogic = "0" - + bankwiseLogic = mcconfig.getValue("BankwiseLogic") if bankwiseLogic == "0": totalTimeInPDNA = time_in_PDNA_in_ns(connection) totalTimeInPDNP = time_in_PDNP_in_ns(connection) @@ -482,9 +480,7 @@ def time_in_power_down_states_in_ns(connection): @metric def time_in_power_down_states_percent(connection): mcconfig = MCConfig(connection) - #bankwiseLogic = mcconfig.getValue("BankwiseLogic") - bankwiseLogic = "0" - + bankwiseLogic = mcconfig.getValue("BankwiseLogic") if bankwiseLogic == "0": totalTimeAllBanks = trace_length_in_ns(connection) else: @@ -542,8 +538,7 @@ def getMetrics(pathToTrace): connection = sqlite3.connect(pathToTrace) mcconfig = MCConfig(connection) - #bankwiseLogic = mcconfig.getValue("BankwiseLogic") - bankwiseLogic = "0" + bankwiseLogic = mcconfig.getValue("BankwiseLogic") if bankwiseLogic == "0": pdnMetrics = [time_in_PDNA_in_ns, time_in_PDNA_percent, time_in_PDNP_in_ns, time_in_PDNP_percent, time_in_SREF_in_ns, time_in_SREF_percent] @@ -577,8 +572,7 @@ def calculateMetrics(pathToTrace, selectedMetrics=[]): connection = sqlite3.connect(pathToTrace) mcconfig = MCConfig(connection) - #bankwiseLogic = mcconfig.getValue("BankwiseLogic") - bankwiseLogic = "0" + bankwiseLogic = mcconfig.getValue("BankwiseLogic") if bankwiseLogic == "0": pdnMetrics = [time_in_PDNA_in_ns, time_in_PDNA_percent, diff --git a/DRAMSys/traceAnalyzer/scripts/scripts.pri b/DRAMSys/traceAnalyzer/scripts/scripts.pri new file mode 100644 index 00000000..7415e798 --- /dev/null +++ b/DRAMSys/traceAnalyzer/scripts/scripts.pri @@ -0,0 +1,10 @@ +# Relative paths to "DRAMSys/traceAnalyzer" because this file is included in +# "DRAMSys/traceAnalyzer/traceAnalyzer.pro" + +DISTFILES += scripts/memUtil.py +DISTFILES += scripts/metrics.py +DISTFILES += scripts/tests.py +DISTFILES += scripts/plots.py +DISTFILES += scripts/sonification.pl +DISTFILES += scripts/dataExtractForNN.pl + diff --git a/DRAMSys/traceAnalyzer/scripts/tests.py b/DRAMSys/traceAnalyzer/scripts/tests.py index c23be21f..dd5c022f 100755 --- a/DRAMSys/traceAnalyzer/scripts/tests.py +++ b/DRAMSys/traceAnalyzer/scripts/tests.py @@ -2,7 +2,7 @@ import sys import traceback import sqlite3 import os -import json +import xml.etree.ElementTree as ET from memUtil import * @@ -52,102 +52,102 @@ class DramConfig(object): self.clk = clkWithUnit[0] self.unitOfTime = clkWithUnit[1].lower() - self.bankwiseLogic = 0 - self.refMode = 0 + self.bankwiseLogic = mcconfig.getValue("BankwiseLogic") + self.refMode = mcconfig.getValue("ControllerCoreRefMode") self.scheduler = mcconfig.getValue("Scheduler") - self.numberOfBanks = memspec.getIntValue("memarchitecturespec","nbrOfBanks") - self.burstLength = memspec.getIntValue("memarchitecturespec","burstLength") + self.numberOfBanks = memspec.getIntValue("nbrOfBanks") + self.burstLength = memspec.getIntValue("burstLength") self.memoryType = memspec.getValue("memoryType") - self.dataRate = memspec.getIntValue("memarchitecturespec","dataRate") + self.dataRate = memspec.getIntValue("dataRate") if (self.memoryType == "WIDEIO_SDR"): self.nActivateWindow = 2 - self.tRP = self.clk * memspec.getIntValue("memtimingspec","RP") - self.tRAS = self.clk * memspec.getIntValue("memtimingspec","RAS") - self.tRC = self.clk * memspec.getIntValue("memtimingspec","RC") - self.tRRD_S = self.clk * memspec.getIntValue("memtimingspec","RRD") + self.tRP = self.clk * memspec.getIntValue("RP") + self.tRAS = self.clk * memspec.getIntValue("RAS") + self.tRC = self.clk * memspec.getIntValue("RC") + self.tRRD_S = self.clk * memspec.getIntValue("RRD") self.tRRD_L = self.tRRD_S - self.tCCD_S = self.clk * memspec.getIntValue("memtimingspec","CCD") + self.tCCD_S = self.clk * memspec.getIntValue("CCD") self.tCCD_L = self.tCCD_S - self.tRCD = self.clk * memspec.getIntValue("memtimingspec","RCD") - self.tNAW = self.clk * memspec.getIntValue("memtimingspec","TAW") - self.tRL = self.clk * memspec.getIntValue("memtimingspec","RL") - self.tWL = self.clk * memspec.getIntValue("memtimingspec","WL") - self.tWR = self.clk * memspec.getIntValue("memtimingspec","WR") - self.tWTR_S = self.clk * memspec.getIntValue("memtimingspec","WTR") + self.tRCD = self.clk * memspec.getIntValue("RCD") + self.tNAW = self.clk * memspec.getIntValue("TAW") + self.tRL = self.clk * memspec.getIntValue("RL") + self.tWL = self.clk * memspec.getIntValue("WL") + self.tWR = self.clk * memspec.getIntValue("WR") + self.tWTR_S = self.clk * memspec.getIntValue("WTR") self.tWTR_L = self.tWTR_S - self.tRTP = self.clk * memspec.getIntValue("memtimingspec","RTP") - self.tCKESR = self.clk * memspec.getIntValue("memtimingspec","CKESR") - self.tCKE = self.clk * memspec.getIntValue("memtimingspec","CKE") - self.tXP = self.clk * memspec.getIntValue("memtimingspec","XP") + self.tRTP = self.clk * memspec.getIntValue("RTP") + self.tCKESR = self.clk * memspec.getIntValue("CKESR") + self.tCKE = self.clk * memspec.getIntValue("CKE") + self.tXP = self.clk * memspec.getIntValue("XP") self.tXPDLL = self.tXP - self.tXS = self.clk * memspec.getIntValue("memtimingspec","XS") + self.tXS = self.clk * memspec.getIntValue("XS") self.tXSDLL = self.tXS - self.tAL = self.clk * memspec.getIntValue("memtimingspec","AL") - self.tRFC = self.clk * memspec.getIntValue("memtimingspec","RFC") - self.tREFI = self.clk * memspec.getIntValue("memtimingspec","REFI") + self.tAL = self.clk * memspec.getIntValue("AL") + self.tRFC = self.clk * memspec.getIntValue("RFC") + self.tREFI = self.clk * memspec.getIntValue("REFI") elif (self. memoryType == "DDR4"): self.nActivateWindow = 4 - self.tRP = self.clk * memspec.getIntValue("memtimingspec","RP") - self.tRAS = self.clk * memspec.getIntValue("memtimingspec","RAS") - self.tRC = self.clk * memspec.getIntValue("memtimingspec","RC") - self.tRTP = self.clk * memspec.getIntValue("memtimingspec","RTP") - self.tRRD_S = self.clk * memspec.getIntValue("memtimingspec","RRD_S") - self.tRRD_L = self.clk * memspec.getIntValue("memtimingspec","RRD_L") - self.tCCD_S = self.clk * memspec.getIntValue("memtimingspec","CCD_S") - self.tCCD_L = self.clk * memspec.getIntValue("memtimingspec","CCD_L") - self.tRCD = self.clk * memspec.getIntValue("memtimingspec","RCD") - self.tNAW = self.clk * memspec.getIntValue("memtimingspec","FAW") - self.tRL = self.clk * memspec.getIntValue("memtimingspec","RL") - self.tWL = self.clk * memspec.getIntValue("memtimingspec","WL") - self.tWR = self.clk * memspec.getIntValue("memtimingspec","WR") - self.tWTR_S = self.clk * memspec.getIntValue("memtimingspec","WTR_S") - self.tWTR_L = self.clk * memspec.getIntValue("memtimingspec","WTR_L") - self.tCKESR = self.clk * memspec.getIntValue("memtimingspec","CKESR") - self.tCKE = self.clk * memspec.getIntValue("memtimingspec","CKE") - self.tXP = self.clk * memspec.getIntValue("memtimingspec","XP") - self.tXPDLL = self.clk * memspec.getIntValue("memtimingspec","XPDLL") - self.tXS = self.clk * memspec.getIntValue("memtimingspec","XS") - self.tXSDLL = self.clk * memspec.getIntValue("memtimingspec","XSDLL") - self.tAL = self.clk * memspec.getIntValue("memtimingspec","AL") + self.tRP = self.clk * memspec.getIntValue("RP") + self.tRAS = self.clk * memspec.getIntValue("RAS") + self.tRC = self.clk * memspec.getIntValue("RC") + self.tRTP = self.clk * memspec.getIntValue("RTP") + self.tRRD_S = self.clk * memspec.getIntValue("RRD_S") + self.tRRD_L = self.clk * memspec.getIntValue("RRD_L") + self.tCCD_S = self.clk * memspec.getIntValue("CCD_S") + self.tCCD_L = self.clk * memspec.getIntValue("CCD_L") + self.tRCD = self.clk * memspec.getIntValue("RCD") + self.tNAW = self.clk * memspec.getIntValue("FAW") + self.tRL = self.clk * memspec.getIntValue("RL") + self.tWL = self.clk * memspec.getIntValue("WL") + self.tWR = self.clk * memspec.getIntValue("WR") + self.tWTR_S = self.clk * memspec.getIntValue("WTR_S") + self.tWTR_L = self.clk * memspec.getIntValue("WTR_L") + self.tCKESR = self.clk * memspec.getIntValue("CKESR") + self.tCKE = self.clk * memspec.getIntValue("CKE") + self.tXP = self.clk * memspec.getIntValue("XP") + self.tXPDLL = self.clk * memspec.getIntValue("XPDLL") + self.tXS = self.clk * memspec.getIntValue("XS") + self.tXSDLL = self.clk * memspec.getIntValue("XSDLL") + self.tAL = self.clk * memspec.getIntValue("AL") if (self.refMode == "4"): - self.tRFC = self.clk * memspec.getIntValue("memtimingspec","RFC4") - self.tREFI = self.clk * (memspec.getIntValue("memtimingspec","REFI") / 4) + self.tRFC = self.clk * memspec.getIntValue("RFC4") + self.tREFI = self.clk * (memspec.getIntValue("REFI") / 4) elif (self.refMode == "2"): - self.tRFC = self.clk * memspec.getIntValue("memtimingspec","RFC2") - self.tREFI = self.clk * (memspec.getIntValue("memtimingspec","REFI") / 2) + self.tRFC = self.clk * memspec.getIntValue("RFC2") + self.tREFI = self.clk * (memspec.getIntValue("REFI") / 2) else: - self.tRFC = self.clk * memspec.getIntValue("memtimingspec","RFC") - self.tREFI = self.clk * memspec.getIntValue("memtimingspec","REFI") + self.tRFC = self.clk * memspec.getIntValue("RFC") + self.tREFI = self.clk * memspec.getIntValue("REFI") elif (self. memoryType == "DDR3"): self.nActivateWindow = 4 - self.tRP = self.clk * memspec.getIntValue("memtimingspec","RP") - self.tRAS = self.clk * memspec.getIntValue("memtimingspec","RAS") - self.tRC = self.clk * memspec.getIntValue("memtimingspec","RC") - self.tRTP = self.clk * memspec.getIntValue("memtimingspec","RTP") - self.tRRD_S = self.clk * memspec.getIntValue("memtimingspec","RRD") - self.tRRD_L = self.clk * memspec.getIntValue("memtimingspec","RRD") - self.tCCD_S = self.clk * memspec.getIntValue("memtimingspec","CCD") - self.tCCD_L = self.clk * memspec.getIntValue("memtimingspec","CCD") - self.tRCD = self.clk * memspec.getIntValue("memtimingspec","RCD") - self.tNAW = self.clk * memspec.getIntValue("memtimingspec","FAW") - self.tRL = self.clk * memspec.getIntValue("memtimingspec","RL") - self.tWL = self.clk * memspec.getIntValue("memtimingspec","WL") - self.tWR = self.clk * memspec.getIntValue("memtimingspec","WR") - self.tWTR_S = self.clk * memspec.getIntValue("memtimingspec","WTR") - self.tWTR_L = self.clk * memspec.getIntValue("memtimingspec","WTR") - self.tCKESR = self.clk * memspec.getIntValue("memtimingspec","CKESR") - self.tCKE = self.clk * memspec.getIntValue("memtimingspec","CKE") - self.tXP = self.clk * memspec.getIntValue("memtimingspec","XP") - self.tXPDLL = self.clk * memspec.getIntValue("memtimingspec","XPDLL") - self.tXS = self.clk * memspec.getIntValue("memtimingspec","XS") - self.tXSDLL = self.clk * memspec.getIntValue("memtimingspec","XSDLL") - self.tAL = self.clk * memspec.getIntValue("memtimingspec","AL") - self.tRFC = self.clk * memspec.getIntValue("memtimingspec","RFC") - self.tREFI = self.clk * memspec.getIntValue("memtimingspec","REFI") + self.tRP = self.clk * memspec.getIntValue("RP") + self.tRAS = self.clk * memspec.getIntValue("RAS") + self.tRC = self.clk * memspec.getIntValue("RC") + self.tRTP = self.clk * memspec.getIntValue("RTP") + self.tRRD_S = self.clk * memspec.getIntValue("RRD") + self.tRRD_L = self.clk * memspec.getIntValue("RRD") + self.tCCD_S = self.clk * memspec.getIntValue("CCD") + self.tCCD_L = self.clk * memspec.getIntValue("CCD") + self.tRCD = self.clk * memspec.getIntValue("RCD") + self.tNAW = self.clk * memspec.getIntValue("FAW") + self.tRL = self.clk * memspec.getIntValue("RL") + self.tWL = self.clk * memspec.getIntValue("WL") + self.tWR = self.clk * memspec.getIntValue("WR") + self.tWTR_S = self.clk * memspec.getIntValue("WTR") + self.tWTR_L = self.clk * memspec.getIntValue("WTR") + self.tCKESR = self.clk * memspec.getIntValue("CKESR") + self.tCKE = self.clk * memspec.getIntValue("CKE") + self.tXP = self.clk * memspec.getIntValue("XP") + self.tXPDLL = self.clk * memspec.getIntValue("XPDLL") + self.tXS = self.clk * memspec.getIntValue("XS") + self.tXSDLL = self.clk * memspec.getIntValue("XSDLL") + self.tAL = self.clk * memspec.getIntValue("AL") + self.tRFC = self.clk * memspec.getIntValue("RFC") + self.tREFI = self.clk * memspec.getIntValue("REFI") else: raise Exception("MemoryType not supported yet. Insert a coin into the coin machine and try again") diff --git a/DRAMSys/traceAnalyzer/tracefiletab.cpp b/DRAMSys/traceAnalyzer/tracefiletab.cpp index a0d638f5..bf0ff6ef 100644 --- a/DRAMSys/traceAnalyzer/tracefiletab.cpp +++ b/DRAMSys/traceAnalyzer/tracefiletab.cpp @@ -75,9 +75,9 @@ void TraceFileTab::initNavigatorAndItsDependentWidgets(QString path) ui->traceplot->init(navigator); - ui->traceScroller->init(navigator, ui->traceplot); + ui->pornoTraceScroller->init(navigator, ui->traceplot); connect(this, SIGNAL(colorGroupingChanged(ColorGrouping)), - ui->traceScroller, SLOT(colorGroupingChanged(ColorGrouping))); + ui->pornoTraceScroller, SLOT(colorGroupingChanged(ColorGrouping))); ui->selectedTransactionTree->init(navigator); //ui->debugMessages->init(navigator,ui->traceplot); diff --git a/DRAMSys/traceAnalyzer/tracefiletab.h b/DRAMSys/traceAnalyzer/tracefiletab.h index 5629a6c5..3bef247c 100644 --- a/DRAMSys/traceAnalyzer/tracefiletab.h +++ b/DRAMSys/traceAnalyzer/tracefiletab.h @@ -43,7 +43,7 @@ #include #include "presentation/tracenavigator.h" #include "presentation/traceplot.h" -#include "presentation/tracescroller.h" +#include "presentation/pornotracescroller.h" namespace Ui { class TraceFileTab; diff --git a/DRAMSys/traceAnalyzer/tracefiletab.ui b/DRAMSys/traceAnalyzer/tracefiletab.ui index d6951f1b..e3d18d6f 100644 --- a/DRAMSys/traceAnalyzer/tracefiletab.ui +++ b/DRAMSys/traceAnalyzer/tracefiletab.ui @@ -38,7 +38,7 @@ - + 4 @@ -162,9 +162,9 @@
presentation/traceplot.h
- TraceScroller + PornoTraceScroller QListView -
presentation/tracescroller.h
+
presentation/pornotracescroller.h
 CommentTreeWidget diff --git a/DRAMSys/unitTests/googleTest.pri b/DRAMSys/unitTests/googleTest.pri new file mode 100644 index 00000000..122881e3 --- /dev/null +++ b/DRAMSys/unitTests/googleTest.pri @@ -0,0 +1,23 @@ +GOOGLETEST_DIR = googletest + +!isEmpty(GOOGLETEST_DIR): { + GTEST_SRCDIR = $$GOOGLETEST_DIR/googletest + GMOCK_SRCDIR = $$GOOGLETEST_DIR/googlemock +} + +requires(exists($$GTEST_SRCDIR):exists($$GMOCK_SRCDIR)) + +!exists($$GOOGLETEST_DIR):message("No googletest src dir found - set GOOGLETEST_DIR to enable.") + +DEFINES += \ + GTEST_LANG_CXX11 + +INCLUDEPATH *= \ + $$GTEST_SRCDIR \ + $$GTEST_SRCDIR/include \ + $$GMOCK_SRCDIR \ + $$GMOCK_SRCDIR/include + +SOURCES += \ + $$GTEST_SRCDIR/src/gtest-all.cc \ + $$GMOCK_SRCDIR/src/gmock-all.cc diff --git a/DRAMSys/unitTests/unitTests.pro b/DRAMSys/unitTests/unitTests.pro new file mode 100644 index 00000000..a39ed9a7 --- /dev/null +++ b/DRAMSys/unitTests/unitTests.pro @@ -0,0 +1,81 @@ +TARGET = unitTestsDRAMSys + +TEMPLATE = app +CONFIG += console +CONFIG -= app_bundle +CONFIG -= qt + +systemc_home = $$(SYSTEMC_HOME) +isEmpty(systemc_home) { + systemc_home = /opt/systemc +} +message(SystemC home is $${systemc_home}) + +systemc_target_arch = $$(SYSTEMC_TARGET_ARCH) +isEmpty(systemc_target_arch) { + systemc_target_arch = linux64 +} + +message(SystemC target architecture is $${systemc_target_arch}) + +dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK) +isEmpty(dramsys_disable_coverage_check) { + coverage_check = true + message(Coverage check ENABLED) +} else { + coverage_check = false + message(Coverage check DISABLED) +} + +unix:!macx { + message(Building on a GNU/Linux) + QMAKE_RPATHDIR += $${systemc_home}/lib-$${systemc_target_arch} + message(Linker options QMAKE_RPATHDIR is $${QMAKE_RPATHDIR}) +} + +DEFINES += TIXML_USE_STL +DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES + +unix:!macx { + QMAKE_CXXFLAGS += -std=c++11 -O0 -g + $$eval(coverage_check) { + QMAKE_CXXFLAGS += -fprofile-arcs -ftest-coverage -fPIC -O0 + QMAKE_LFLAGS += -lgcov --coverage + } +} + +macx: { + CONFIG += c++11 + QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ -O0 -g + $$eval(coverage_check) { + QMAKE_CXXFLAGS += --coverage + QMAKE_LFLAGS += --coverage + } +} + +QMAKE_CXXFLAGS += -pthread + +INCLUDEPATH += ../library/src/simulation/ +INCLUDEPATH += $${systemc_home}/include + +LIBS += -L$${systemc_home}/lib-$${systemc_target_arch} -lsystemc -lpthread + +SOURCEHOME = ../library/src/ + +SOURCES += \ + main.cpp \ + CommandMuxTests.cpp \ + $${SOURCEHOME}/controller/CommandMux.cpp \ + $${SOURCEHOME}/controller/Command.cpp + + + +HEADERS += \ + Testfile.h \ + $${SOURCEHOME}/controller/CommandMux.h \ + $${SOURCEHOME}/controller/Command.h + +DISTFILES += ../DRAMSys.astylerc + +include(googleTest.pri) +DISTFILES += googleTest.pri diff --git a/README.md b/README.md index 44bad0a1..bc1c6595 100644 --- a/README.md +++ b/README.md @@ -121,20 +121,20 @@ $ ./DRAMSys To run DRAMSys with a specific config: ```bash -$ ./DRAMSys ../../DRAMSys/library/resources/simulations/ddr3-example.json +$ ./DRAMSys ../../DRAMSys/library/resources/simulations/ddr3-example.xml ``` To run DRAMSys with a specific config and a resource folder somewhere else to the standard: ```bash -$ ./DRAMSys ../../DRAMSys/tests/example_ddr3/simulations/ddr3-example.json ../../DRAMSys/tests/example_ddr3/ +$ ./DRAMSys ../../DRAMSys/tests/example_ddr3/simulations/ddr3-example.xml ../../DRAMSys/tests/example_ddr3/ ``` -From the build directory use the commands below to execute the Trace Analyzer. +From the build directory use the commands below to execute the traceAnalyzer. ```bash $ cd traceAnalyzer $ export QT_QPA_PLATFORMTHEME=qgnomeplatform -$ ./TraceAnalyzer +$ ./traceAnalyzer ``` ### Building on MacOS (Formerly OSX) @@ -175,54 +175,50 @@ section. ### DRAMSys Configuration -The **DRAMSys** executable supports one argument which is a JSON file that -contains certain arguments and the path of other configuration files for the -desired simulation. If no argument is passed through the command line a default -configuration file will be loaded. +The **DRAMSys** executable supports one argument which is a XML file that +contains configurable aspects of the desired simulation. If no argument is +passed through the command line a default configuration file will be loaded. -The JSON code below shows a typic configuration: +The XML code below shows a typic configuration: -```json -{ - "simulation": { - "simulationid": "ddr3-example", - "simconfig": "ddr3.json", - "thermalconfig": "config.json", - "memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json", - "addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json", - "mcconfig":"fifoStrict.json", - "tracesetup": [{ - "clkMhz": 300, - "name": "ddr3_example.stl"}, - { - "clkMhz": 400, - "name": "ddr3_example.stl"} - ] - } -} -``` -Fields Description - "simulationid": Simulation file identifier - "simconfig": Configuration file for the DRAMSys Simulator - "thermalconfig": Temperature Simulator Configuration File - "memspec": Memory Device Specification File - "addressmapping": Addressmapping Configuration of the Memory Controller File. - "mcconfig": Memory Controller Configuration File. - "tracesetup": The trace setup is only used in standalone mode. +```xml + + + + + + + + + + + + + + + + + ddr3_example.stl + ddr3_SAMSUNG_M471B5674QH0_DIMM_example.stl + + +``` +Some configuration fields reference other XML files which contain more specialized chunks of the configuration like memory specification, address -mapping and memory configurations +mapping and memory configurations. -The JSON configuration files are parsed by the program and the configuration +The XML configuration files are parsed by the program and the configuration details extracted are assigned to the correspondent attributes of the internal configuration structure. +The **device** configuration consists of two parameters - clkMhz +(operation frequency for this device) - and a **trace file**. #### Trace files @@ -283,108 +279,98 @@ Below, the sub-configurations are listed and explained. - **Simulator Configuration** - The content of [ddr3.json](DRAMSys/library/resources/configs/simulator/ddr3.json) is presented below as an example. + The content of + [ddr3.xml](DRAMSys/library/resources/configs/simulator/ddr3.xml) is + presented below as an example. -```json -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, - "PowerAnalysis": false, - "SimulationName": "ddr3", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} -``` + ```xml + + + + + + + + + + + + + + + ``` - *SimulationName* (boolean) - - Give the name of the simulation for distingushing from other simulations. - *Debug* (boolean) - - true: enables debug output on console - - false: disables debug output + - "1": enables debug output on console + - "0": disables debug output - *DatabaseRecording* (boolean) - - true: enables trace file recording for the trace analyser tool - - false: disables trace file recording + - "1": enables trace file recording for the trace analyser tool + - "0": disables trace file recording - *PowerAnalysis* (boolean) - - true: enables live power analysis with the DRAMPower tool - - false: disables power analysis + - "1": enables live power analysis with the DRAMPower tool + - "0": disables power analysis - *EnableWindowing* (boolean) - - true: enables temporal windowing - - false: disables temporal windowing + - "1": enables temporal windowing + - "0": disables temporal windowing - *WindowSize* (unisgned int) - - Size of the window in clock cycles used to evaluate average bandwidth and average power consumption - *NumberOfMemChannels* (unsigned int) - - Number of memory channels - *ControllerCoreRefDisable* (boolean) - - true: disables refreshes - - false: normal operation (refreshes enabled) + - "1": disables refreshes + - "0": normal operation (refreshes enabled) - *ControllerCoreRGR* (boolean) - - true: enable row granular refresh - - false: normal operation + - "1": enable row granular refresh + - "0": normal operation - *ThermalSimulation* (boolean) - - true: enables thermal simulation - - false: static temperature during simulation + - "1": enables thermal simulation + - "0": static temperature during simulation - *SimulationProgressBar* (boolean) - - true: enables the simulation progress bar - - false: disables the simulation progress bar + - "1": enables the simulation progress bar + - "0": disables the simulation progress bar - *NumberOfDevicesOnDIMM* (unsigned int) - - Number of devices on dual inline memory module - *CheckTLM2Protocol* (boolean) - - true: enables the TLM-2.0 Protocol Checking - - false: disables the TLM-2.0 Protocol Checking + - "1": enables the TLM-2.0 Protocol Checking + - "0": disables the TLM-2.0 Protocol Checking - *ECCControllerMode* (string) - "Disabled": No ECC Controller is used - "Hamming": Enables an ECC Controller with classic SECDED implementation using Hamming Code - *UseMalloc* (boolean) - - false: model storage using mmap() (DEFAULT) - - true: allocate memory for modeling storage using malloc() + - "0": model storage using mmap() (DEFAULT) + - "1": allocate memory for modeling storage using malloc() - **Temperature Simulator Configuration** - The content of [config.json](DRAMSys/library/resources/configs/thermalsim/config.json) is presented below as an example. + The content of + [config.xml](DRAMSys/library/resources/configs/thermalsim/config.xml) is + presented below as an example. + + ```xml + + + + + + + + + + + + + + ``` -```json -{ - "thermalsimconfig": { - "TemperatureScale": "Celsius", - "StaticTemperatureDefaultValue": 89, - "ThermalSimPeriod":100, - "ThermalSimUnit":"us", - "PowerInfoFile": "powerInfo.json", - "IceServerIp": "127.0.0.1", - "IceServerPort": 11880, - "SimPeriodAdjustFactor" : 10, - "NPowStableCyclesToIncreasePeriod": 5, - "GenerateTemperatureMap": true, - "GeneratePowerMap": true - } -} -``` - *TemperatureScale* (string) - "Celsius" - "Fahrenheit" - "Kelvin" - *StaticTemperatureDefaultValue* (int) - - Temperature value for simulations with static temperature - *ThermalSimPeriod* (double) - - Period of the thermal simulation - *ThermalSimUnit* (string) - "s": seconds @@ -394,89 +380,147 @@ Below, the sub-configurations are listed and explained. - "ps": picoseconds - "fs": femtoseconds - *PowerInfoFile* (string) - - File containing power related information: devices identifiers, initial power values and power thresholds. - *IceServerIp* (string) - - 3D-Ice server IP address - *IceServerPort* (unsigned int) - - 3D-Ice server port - *SimPeriodAdjustFactor* (unsigned int) - - When substantial changes in power occur (i.e., changes that exceed the thresholds), then the simulation period will be divided by this number causing the thermal simulation to be executed more often. - *NPowStableCyclesToIncreasePeriod* (unsigned int) - - Wait this number of thermal simulation cycles with power stability (i.e., changes that do not exceed the thresholds) to start increasing the simulation period back to its configured value. - *GenerateTemperatureMap* (boolean) - - true: generate temperature map files during thermal simulation - - false: do not generate temperature map files during thermal simulation + - "1": generate temperature map files during thermal simulation + - "0": do not generate temperature map files during thermal simulation - *GeneratePowerMap* (boolean) - - true: generate power map files during thermal simulation - - false: do not generate power map files during thermal simulation + - "1": generate power map files during thermal simulation + - "0": do not generate power map files during thermal simulation - **Memory Specification** A file with memory specifications. This information comes from datasheets and measurements, and usually does not change. - The fields inside "mempowerspec" can be written directly as a **double** type. "memoryId" and "memoryType" are **string**. The others are **unsigned int** as it can be checked in the files at . - - - **Address Mapping** - Currently the CONGEN format is supported. It provides bit-wise granularity. It also provides the possibility of XOR address bits in order to map page misses to different banks and reduce latencies. - There is an optional field called **SOLUTION**. If added it will look for the solution with the field "ID" equals to 0. - Example with "SOLUTION" field at: - Example without "SOLUTION" field at: + There are currently two different file formats to describe the address mapping. This software automatically chooses the correct interpreter using the name of the xml root node as selection criterion. +- **Standard XML file format** + + XML files describe the address mapping to be used in the simulation. + + Example for 1GB x64 DIMM with: 8 x 1 Gbit x8 Devices (Micron MT41J128M8) with Page Size: 1KB + + [am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml](DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml) + + ```xml + + + + + + + + + + ``` + + Some more examples with graphical representation follow: + + [am_wideio.xml](DRAMSys/library/resources/configs/amconfigs/am_wideio.xml) + + ```xml + + + + + + + + + + ``` + + ![Address Mapping Sample 1](DRAMSys/docs/images/am_wideio_rbc.png) + + ```xml + + + + + + + + + + ``` + + ![Address Mapping Sample 2](DRAMSys/docs/images/am_wideio_brc.png) - **ConGen XML file format** This file format is generated by ConGen. The format delivers more information than needed for an address mapping. - Optional data (unused): - + Unused data: - "NAME": Name of the trace file which was used by ConGen -- "COSTS": Number of row misses which this configuration produces while playing the trace. - - - "CONFIG": Gives you information about the ConGen configuration - + - "COSTS": Number of row misses which this configuration produces while playing the trace. + Used data: - - - "SOLUTION": (OBS.:Different solutions should be added as json objects inside the "SOLUTION" array) - - "ID": Unique identifier for this solution. It is used to specify a certain solution. + - "CONFIG": Gives you information about the ConGen configuration + - "SOLUTION": + - Attribute "ID": Unique identifier for this solution. It is used to specify a certain solution. - "XOR": Defines an xor connection of a bank and row bit - - "BYTE_BIT": Address bits that are connected to the byte bits in ascending order - - "COLUMN_BIT": Address bits that are connected to the column bits in ascending order - - "ROW_BIT": Address bits that are connected to the row bits in ascending order - - "BANK_BIT": Address bits that are connected to the bank bits in ascending order - - "BANKGROUP_BIT": Address bits that are connected to the bankgroup bits in ascending order - - "RANK_BIT": Address bits that are connected to the rank bits in ascending order - - "CHANNEL_BIT": Address bits that are connected to the channel bits in ascending order - -```json -{ - "CONGEN": { - "SOLUTION": [ - { - "ID": 0, - "XOR": [ - { - "FIRST": 13, - "SECOND": 16 - } - ], - "BYTE_BIT": [0,1,2], - "COLUMN_BIT": [3,4,5,6,7,8,9,10,11,12], - "BANK_BIT": [13,14,15], - "ROW_BIT": [16,17,18,19,20,21,22,23,24,25,26,27,28,29] - } - ] - } -} + - "BANK_BIT": Number of an address bit which is connected to a bank bit + - "ROW_BIT": Number of an address bit which is connected to a row bit +```xml + + test + 84 + + 3 + 14 + 10 + 3 + 3 + + + + 28 + 27 + 29 + 16 + 11 + 14 + 15 + 25 + 26 + 22 + 24 + 23 + 21 + 20 + 19 + 18 + 17 + + ``` @@ -484,30 +528,65 @@ Below, the sub-configurations are listed and explained. An example follows. -```json -{ - "mcconfig": { - "PagePolicy": "Open", - "Scheduler": "Fifo", - "RequestBufferSize": 8, - "CmdMux": "Oldest", - "RespQueue": "Fifo", - "RefreshPolicy": "Rankwise", - "RefreshMode": 1, - "RefreshMaxPostponed": 8, - "RefreshMaxPulledin": 8, - "PowerDownPolicy": "NoPowerDown", - "PowerDownTimeout": 100 - } -} -``` + ```xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ``` - *BankwiseLogic* (boolean) - - true: perform bankwise-refresh [3] and bankwise-powerdown [4] - - false: do not perform bankwise operations + - "1": perform bankwise-refresh [3] and bankwise-powerdown [4] + - "0": do not perform bankwise operations - *OpenPagePolicy* (boolean) - - true: use open page precharge policy - - false: do not use open page precharge policy + - "1": use open page precharge policy + - "0": do not use open page precharge policy - *MaxNrOfTransactions* (unsigned int) - Maximum number of transactions. - *Scheduler* (string) @@ -526,11 +605,11 @@ Below, the sub-configurations are listed and explained. - "TimeoutPDN": precharge idle - "TimeoutSREF": self refresh - *ReadWriteGrouping* (boolean) - - true: enable read writing grouping - - false: disable read writing grouping + - "1": enable read writing grouping + - "0": disable read writing grouping - *ReorderBuffer* (boolean) - - true: use reordering buffer - - false: do not use reordering buffer + - "1": use reordering buffer + - "0": do not use reordering buffer - *ErrorChipSeed* (unsigned int) - Seed to initialize the random error generator. - *ErrorCSVFile* (string) @@ -540,82 +619,82 @@ Below, the sub-configurations are listed and explained. - "Store": store data without error model - "ErrorModel": store data with error model [6] - *ControllerCoreRefDisable* (boolean) - - true: disables refreshes - - false: normal operation (refreshes enabled) + - "1": disables refreshes + - "0": normal operation (refreshes enabled) - ControllerCoreRefMode (unsigned int) - Refresh mode. 1: 1X, 2: 2X, 4: 4X. Refresh period is tREFI, tREFI/2, tREFI/4, respectively. Number of rows per refresh is affected. Maximum values for pull-in and postpone are affected. There are different values of tRFC for each mode that come from memory specifications. - *ControllerCoreRefForceMaxPostponeBurst* (boolean) - - true: always postpone, resulting in a ControllerCoreRefMaxPostponed burst - - false: normal operation + - "1": always postpone, resulting in a ControllerCoreRefMaxPostponed burst + - "0": normal operation - *ControllerCoreRefEnablePostpone* (boolean) - - true: enables the postpone refresh feature - - false: normal operation + - "1": enables the postpone refresh feature + - "0": normal operation - *ControllerCoreRefEnablePullIn* (boolean) - - true: enables the pull-in refresh feature - - false: normal operation + - "1": enables the pull-in refresh feature + - "0": normal operation - *ControllerCoreRefMaxPostponed* (unsigned int) - Max AR commands to be postponed. Refresh mode affects this config. - *ControllerCoreRefMaxPulledIn* (unsigned int) - Max AR commands to be pulled-in. Refresh mode affects this config. - *ControllerCoreRGR* (boolean) - - true: enables row granular refresh feature (RGR) - - false: normal operation + - "1": enables row granular refresh feature (RGR) + - "0": normal operation - *ControllerCoreRefNumARCmdsIntREFI* (unsigned int) - Number of AR commands to to be issued in a refresh period tREFI in 1X mode - *ControllerCoreRGRRowInc* (unsigned int) - Row increment for each AR command (selective refresh) - *ControllerCoreRGRB0* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB1* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB2* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB3* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB4* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB5* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB6* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB7* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB8* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB9* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB10* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB11* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB12* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB13* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB14* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRB15* (boolean) - - true: RGR this bank - - false: skip this bank + - "1": RGR this bank + - "0": skip this bank - *ControllerCoreRGRtRASBInClkCycles* (unsigned int) - Timing can be changed to explore optimum row granular refresh (ORGR) - *ControllerCoreRGRtRRDB_LInClkCycles* (unsigned int) @@ -712,7 +791,7 @@ $ cd DRAMSys/library/resources A description of the content each directory follows. - **resources** - - **configs**: JSON files that specify details of the simulation. + - **configs**: XML files that specify details of the simulation. - amconfigs: address mapping configs. - mcconfigs: memory controller configs. - memspecs: memory specification files (technology dependent). @@ -788,9 +867,9 @@ There is a list of main configuration files on the top of the script: ```bash sim_files=" -ddr3-example.json -ddr3-single-device.json -wideio-example.json +ddr3-example.xml +ddr3-single-device.xml +wideio-example.xml " ``` @@ -992,11 +1071,11 @@ running before starting. For more information about 3D-ICE visit the [official w #### Installing the lastest 3D-ICE version -[Download](https://www.epfl.ch/labs/esl/open-source-software-projects/3d-ice/3d-ice-download/) the lastest version. Make sure you got version 2.2.6 or greater: +[Download](http://esl.epfl.ch/3d-ice/download.html) the lastest version. Make sure you got version 2.2.6 or greater: ```bash -$ wget https://www.epfl.ch/labs/esl/wp-content/uploads/2018/12/3d-ice-latest.zip -$ unzip 3d-ice-latest.zip +$ wget http://esl.epfl.ch/files/content/sites/esl/files/3dice/releases/3d-ice-latest.zip +$ tar -xvzf 3d-ice-latest.zip ``` Install [SuperLU](http://crd-legacy.lbl.gov/~xiaoye/SuperLU/superlu_5.2.1.tar.gz) dependencies: @@ -1126,6 +1205,53 @@ simulation server. #### Usage Example with Thermal Simulation +The DRAMSys' main configuration file is presented below. + +```xml + + + + + + + + + + + + + + + test_error.stl + + +``` + +Enable the error model in fr_fcfs.xml. + +```xml + + + + + + + + + + + + + + +``` + Generate the input trace file for DRAMSys. ```bash @@ -1256,7 +1382,7 @@ in a conf directory of this building directory. Then the simulation can be started with: ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml config.ini 1 ``` Let the simulation run for some seconds and then stop it with **CTRL-C**. @@ -1270,7 +1396,7 @@ All essential files for some functional examples are provided. Execute a hello world application: ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/configs/hello.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/configs/hello.ini 1 ``` A **Hello world!** message should be printed to the standard output. @@ -1278,11 +1404,11 @@ A **Hello world!** message should be printed to the standard output. Execute applications: ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/Oscar/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/Oscar/config.ini 1 ``` ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/Bubblesort/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/Bubblesort/config.ini 1 ``` Wait some minutes for the application to finish. @@ -1336,7 +1462,7 @@ library, benchmarks, disk image, etc.) can be obtained with [gem5.TnT]. Start a simulation. Example: ```bash -dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json ../../DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/config.ini 1 +dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.xml ../../DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/config.ini 1 ``` Optionally, open another terminal or tab and connect to gem5. @@ -1458,7 +1584,7 @@ executable=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes Start a simulation. Example: ```bash -dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-se.json ../../DRAMSys/gem5/gem5_se/parsec-arm/config.ini 1 +dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-se.xml ../../DRAMSys/gem5/gem5_se/parsec-arm/config.ini 1 ``` ### Boot Linux with gem5 and DRAMSys @@ -1481,35 +1607,42 @@ The config.ini should be copied again to the DRAMSys_gem5 build folder. The simconfig should be changed in order to support storage and address offsets: -``` json -{ - "simconfig": { - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, - "PowerAnalysis": false, - "SimulationName": "ddr3", - "SimulationProgressBar": true, - "ThermalSimulation": false, - "WindowSize": 1000, +``` xml + + + + + + + + + + + + + + + + - "StoreMode": "Store", - "AddressOffset": 2147483648, - "UseMalloc": true - } -} + + + + + ``` Then start DRAMSys_gem5 with the following command: ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml config.ini 1 ``` For further sophisticated address mappings or scenarios checkout the file DRAMSys/gem5/main.cpp @@ -1527,7 +1660,7 @@ tar -xaf DRAMSys/gem5/boot_linux/linux-aarch32-ael.img.tar.gz -C DRAMSys/gem5/bo Execute the example: ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-boot-linux.json ../../DRAMSys/gem5/configs/boot_linux.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-boot-linux.xml ../../DRAMSys/gem5/configs/boot_linux.ini 1 ``` Open a new terminal and connect to gem5: @@ -1550,7 +1683,7 @@ python files are stored [here](DRAMSys/gem5/examples). This is an example for running an elastic trace: ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/singleElasticTraceReplay.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/singleElasticTraceReplay.ini 1 ``` An overview of the architcture being simulated is presented below: @@ -1562,13 +1695,13 @@ Note that the address offset is usually zero for elastic traces. Another example with L2 cache: ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini 1 ``` If two elastic traces should be used run the simulation with the following example: ``` -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/dualElasticTraceReplay.ini 2 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/dualElasticTraceReplay.ini 2 ``` An overview of the architcture being simulated is presented below: @@ -1783,7 +1916,7 @@ After building, go the the folder where *DRAMSys_gem5* is located. Test with a hello world application for X86. ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/hello-x86/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/hello-x86/config.ini 1 ``` A **Hello world!** message should be printed to the standard output. @@ -1798,98 +1931,98 @@ Examples: **Basicmath** ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/large/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/large/config.ini 1 ``` **Bitcount** ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/large/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/large/config.ini 1 ``` **Qsort** ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/large/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/large/config.ini 1 ``` **Susan** ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/corners/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/corners/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/corners/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/corners/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/edges/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/edges/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/edges/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/edges/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/smoothing/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/smoothing/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/smoothing/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/smoothing/config.ini 1 ``` **Network Applications** **Dijkstra** ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/large/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/large/config.ini 1 ``` **Patricia** ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/large/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/large/config.ini 1 ``` **Security Applications** **Blowfish Encode** ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/large/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/large/config.ini 1 ``` **Blowfish Decode** ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/large/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/large/config.ini 1 ``` **SHA** ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/large/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/large/config.ini 1 ``` **Telecom Applications** **CRC32** ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/large/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/large/config.ini 1 ``` **FFT** ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/large/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/large/config.ini 1 ``` **FFT-INV** ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/large/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/large/config.ini 1 ``` **GSM Encode** ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/large/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/large/config.ini 1 ``` **GSM Decode** ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/large/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/large/config.ini 1 ``` Check the folder [DRAMSys/gem5/gem5_se/MiBench](DRAMSys/gem5/gem5_se/MiBench) for all applications and configuration files. @@ -1908,7 +2041,7 @@ library, benchmarks, disk image, etc.) can be obtained with [gem5.TnT]. Start a simulation. Example: ```bash -dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json ../../DRAMSys/gem5/gem5_fs/arm64/config.ini 1 +dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.xml ../../DRAMSys/gem5/gem5_fs/arm64/config.ini 1 ``` Optionally, open another terminal or tab and connect to gem5.