From 14b93bd145d5ffce16038ad68783f860fd4812a4 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 9 Jun 2020 16:06:27 +0200 Subject: [PATCH 01/53] Adapt PCT project to new recording structure. --- DRAMSys/library/src/common/TlmRecorder.cpp | 3 +-- DRAMSys/library/src/common/utils.cpp | 7 +++++++ DRAMSys/library/src/common/utils.h | 2 ++ DRAMSys/library/src/controller/Controller.cpp | 2 +- .../src/controller/ControllerRecordable.cpp | 2 +- DRAMSys/library/src/simulation/Arbiter.cpp | 4 ++-- DRAMSys/library/src/simulation/DRAMSys.cpp | 6 ++++++ DRAMSys/library/src/simulation/DRAMSys.h | 3 +-- .../src/simulation/dram/DramRecordable.cpp | 2 +- DRAMSys/pct/createPlatform.tcl | 5 +++-- DRAMSys/pct/dummy.h | 17 +++++++++++++---- 11 files changed, 38 insertions(+), 15 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index ffa604b6..a15789f2 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -95,8 +95,7 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, if (currentTransactionsInSystem.count(&trans) == 0) introduceTransactionSystem(trans); - //std::string phaseName = phaseNameToString(phase); - std::string phaseName = phase.get_name(); + std::string phaseName = getPhaseName(phase); std::string phaseBeginPrefix = "BEGIN_"; std::string phaseEndPrefix = "END_"; diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index 65999dc0..6918ab16 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -65,6 +65,13 @@ sc_time TimeInterval::getLength() return start - end; } +std::string getPhaseName(tlm_phase phase) +{ + std::ostringstream oss; + oss << phase; + return oss.str(); +} + json parseJSON(std::string path) { try diff --git a/DRAMSys/library/src/common/utils.h b/DRAMSys/library/src/common/utils.h index 0e52b291..47318b60 100644 --- a/DRAMSys/library/src/common/utils.h +++ b/DRAMSys/library/src/common/utils.h @@ -102,6 +102,8 @@ static inline void loadbar(unsigned int x, std::cout << "|\r" << std::flush; } +std::string getPhaseName(tlm::tlm_phase phase); + nlohmann::json parseJSON(std::string path); bool parseBool(nlohmann::json &obj, std::string name); unsigned int parseUint(nlohmann::json &obj, std::string name); diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 6a0a4f0e..137aa3db 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -349,7 +349,7 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, else SC_REPORT_FATAL("Controller", "nb_transport_fw in controller was triggered with unknown phase"); - PRINTDEBUGMESSAGE(name(), "[fw] " + std::string(phase.get_name()) + " notification in " + + PRINTDEBUGMESSAGE(name(), "[fw] " + getPhaseName(phase) + " notification in " + notificationDelay.to_string()); return TLM_ACCEPTED; diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index e4a36e61..5c155e34 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -80,7 +80,7 @@ void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase pha unsigned int col __attribute__((unused)) = DramExtension::getExtension(trans).getColumn().ID(); uint64_t id __attribute__((unused)) = DramExtension::getExtension(trans).getPayloadID(); - PRINTDEBUGMESSAGE(name(), "Recording " + std::string(phase.get_name()) + " thread " + + PRINTDEBUGMESSAGE(name(), "Recording " + getPhaseName(phase) + " thread " + std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string( bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " + std::to_string(col) + " id " + std::to_string(id) + " at " + recTime.to_string()); diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 743ea18d..098c6013 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -93,7 +93,7 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, notDelay += Configuration::getInstance().memSpec->tCK; } - PRINTDEBUGMESSAGE(name(), "[fw] " + std::string(phase.get_name()) + " notification in " + + PRINTDEBUGMESSAGE(name(), "[fw] " + getPhaseName(phase) + " notification in " + notDelay.to_string()); payloadEventQueue.notify(payload, phase, notDelay); return TLM_ACCEPTED; @@ -107,7 +107,7 @@ tlm_sync_enum Arbiter::nb_transport_bw(int channelId, tlm_generic_payload &paylo // Check channel ID assert((unsigned int)channelId == DramExtension::getExtension(payload).getChannel().ID()); - PRINTDEBUGMESSAGE(name(), "[bw] " + std::string(phase.get_name()) + " notification in " + + PRINTDEBUGMESSAGE(name(), "[bw] " + getPhaseName(phase) + " notification in " + bwDelay.to_string()); payloadEventQueue.notify(payload, phase, bwDelay); return TLM_ACCEPTED; diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index fa119ed2..b210438d 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -60,6 +60,12 @@ #include "dram/DramGDDR6.h" #include "../controller/Controller.h" +DRAMSys::DRAMSys(sc_module_name name, + std::string simulationToRun, + std::string pathToResources) + : DRAMSys(name, simulationToRun, pathToResources, true) +{} + DRAMSys::DRAMSys(sc_module_name name, std::string simulationToRun, std::string pathToResources, diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index 34f47091..4738a4fb 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -63,8 +63,7 @@ public: SC_HAS_PROCESS(DRAMSys); DRAMSys(sc_module_name name, std::string simulationToRun, - std::string pathToResources) - : DRAMSys(name, simulationToRun, pathToResources, true) {} + std::string pathToResources); virtual ~DRAMSys(); diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index 67830919..c2319ddb 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -95,7 +95,7 @@ void DramRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase unsigned int row __attribute__((unused)) = DramExtension::getExtension(trans).getRow().ID(); unsigned int col __attribute__((unused)) = DramExtension::getExtension(trans).getColumn().ID(); - PRINTDEBUGMESSAGE(this->name(), "Recording " + std::string(phase.get_name()) + " thread " + + PRINTDEBUGMESSAGE(this->name(), "Recording " + getPhaseName(phase) + " thread " + std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string( bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " + std::to_string(col) + " at " + recTime.to_string()); diff --git a/DRAMSys/pct/createPlatform.tcl b/DRAMSys/pct/createPlatform.tcl index d6a1c661..fd567c82 100644 --- a/DRAMSys/pct/createPlatform.tcl +++ b/DRAMSys/pct/createPlatform.tcl @@ -44,7 +44,8 @@ ::pct::set_dynamic_port_arrays_flag true ::pct::set_import_scml_properties_flag true ::pct::load_all_modules "--set-category" "dummy.h" -::pct::create_instance Project:DRAMSys /HARDWARE i_DRAMSys DRAMSys {DRAMSys(simulationToRun, pathToResources)} +#::pct::create_instance Project:DRAMSys /HARDWARE i_DRAMSys DRAMSys {DRAMSys(simulationToRun, pathToResources)} +::pct::create_instance Project:DRAMSysRecordable /HARDWARE i_DRAMSys DRAMSysRecordable {DRAMSysRecordable(simulationToRun, pathToResources)} # Add DRAMSys Library // ../[glob -type d ../../build*]/simulator/ ::pct::set_simulation_build_project_setting Debug Libraries "sqlite3 DRAMSysLibrary DRAMPower" @@ -61,7 +62,7 @@ # Configure DDR3 Example: ::pct::set_param_value /HARDWARE/i_DRAMSys {Constructor Arguments} pathToResources ../../library/resources/ -::pct::set_param_value /HARDWARE/i_DRAMSys {Constructor Arguments} simulationToRun ../../library/resources/simulations/ddr3-example.xml +::pct::set_param_value /HARDWARE/i_DRAMSys {Constructor Arguments} simulationToRun ../../library/resources/simulations/ddr3-example.json # Build Rest of the Example system: ::pct::open_library "GFRBM" diff --git a/DRAMSys/pct/dummy.h b/DRAMSys/pct/dummy.h index cd199d30..d4ad3fbc 100644 --- a/DRAMSys/pct/dummy.h +++ b/DRAMSys/pct/dummy.h @@ -31,10 +31,11 @@ * * Authors: * Matthias Jung + * Lukas Steiner */ -#ifndef DRAMSYS_H_ -#define DRAMSYS_H_ +#ifndef DUMMY_H +#define DUMMY_H #include #include @@ -48,7 +49,7 @@ * real module... */ -class DRAMSys: public sc_module +class DRAMSys : public sc_module { public: tlm_utils::multi_passthrough_target_socket tSocket; @@ -61,5 +62,13 @@ public: string pathToResources); }; -#endif /* SIMULATIONMANAGER_H_ */ +class DRAMSysRecordable : public DRAMSys +{ +public: + DRAMSysRecordable(sc_module_name name, + std::string simulationToRun, + std::string pathToResources); +}; + +#endif // DUMMY_H From 3f8f12358bb7415fa2813b7b995ad855f7b79483 Mon Sep 17 00:00:00 2001 From: scorrea Date: Wed, 10 Jun 2020 12:32:20 +0200 Subject: [PATCH 02/53] new test files --- .../configs/amconfigs/am_hbm2_8Gb_pc_brc.json | 46 +++++++++ .../HBM2/configs/mcconfigs/fifoStrict.json | 11 +++ DRAMSys/tests/HBM2/configs/memspecs/HBM2.json | 46 +++++++++ .../tests/HBM2/configs/simulator/hbm2.json | 21 +++++ .../tests/HBM2/configs/thermalsim/config.json | 15 +++ .../tests/HBM2/configs/thermalsim/core.flp | 45 +++++++++ DRAMSys/tests/HBM2/configs/thermalsim/mem.flp | 16 ++++ .../HBM2/configs/thermalsim/powerInfo.json | 20 ++++ .../tests/HBM2/configs/thermalsim/stack.stk | 49 ++++++++++ DRAMSys/tests/HBM2/scripts/createTraceDB.sql | 94 +++++++++++++++++++ .../tests/HBM2/simulations/hbm2-example.json | 20 ++++ ..._ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json | 51 ++++++++++ .../configs/mcconfigs/fr_fcfs_grp.json | 12 +++ .../MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 55 +++++++++++ .../configs/simulator/ddr3.json | 21 +++++ .../configs/thermalsim/config.json | 15 +++ .../configs/thermalsim/core.flp | 45 +++++++++ .../ddr3_multirank/configs/thermalsim/mem.flp | 16 ++++ .../configs/thermalsim/powerInfo.json | 20 ++++ .../configs/thermalsim/stack.stk | 49 ++++++++++ .../ddr3_multirank/scripts/createTraceDB.sql | 94 +++++++++++++++++++ .../simulations/ddr3-example.json | 16 ++++ .../am_ddr4_8x4Gbx8_dimm_p1KB_brc.json | 46 +++++++++ .../configs/mcconfigs/fr_fcfs.json | 12 +++ .../memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json | 66 +++++++++++++ .../configs/simulator/ddr4.json | 21 +++++ .../configs/thermalsim/config.json | 15 +++ .../configs/thermalsim/core.flp | 45 +++++++++ .../configs/thermalsim/mem.flp | 16 ++++ .../configs/thermalsim/powerInfo.json | 20 ++++ .../configs/thermalsim/stack.stk | 49 ++++++++++ .../ddr4_bankgroups/scripts/createTraceDB.sql | 94 +++++++++++++++++++ .../simulations/ddr4-example.json | 16 ++++ .../amconfigs/am_lpddr4_8Gbx16_brc.json | 42 +++++++++ .../tests/lpddr4/configs/mcconfigs/fifo.json | 11 +++ .../memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json | 46 +++++++++ .../lpddr4/configs/simulator/lpddr4.json | 21 +++++ .../lpddr4/configs/thermalsim/config.json | 15 +++ .../tests/lpddr4/configs/thermalsim/core.flp | 45 +++++++++ .../tests/lpddr4/configs/thermalsim/mem.flp | 16 ++++ .../lpddr4/configs/thermalsim/powerInfo.json | 20 ++++ .../tests/lpddr4/configs/thermalsim/stack.stk | 49 ++++++++++ .../tests/lpddr4/scripts/createTraceDB.sql | 94 +++++++++++++++++++ .../lpddr4/simulations/lpddr4-example.json | 16 ++++ 44 files changed, 1552 insertions(+) create mode 100644 DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json create mode 100644 DRAMSys/tests/HBM2/configs/mcconfigs/fifoStrict.json create mode 100644 DRAMSys/tests/HBM2/configs/memspecs/HBM2.json create mode 100644 DRAMSys/tests/HBM2/configs/simulator/hbm2.json create mode 100644 DRAMSys/tests/HBM2/configs/thermalsim/config.json create mode 100755 DRAMSys/tests/HBM2/configs/thermalsim/core.flp create mode 100755 DRAMSys/tests/HBM2/configs/thermalsim/mem.flp create mode 100644 DRAMSys/tests/HBM2/configs/thermalsim/powerInfo.json create mode 100755 DRAMSys/tests/HBM2/configs/thermalsim/stack.stk create mode 100644 DRAMSys/tests/HBM2/scripts/createTraceDB.sql create mode 100644 DRAMSys/tests/HBM2/simulations/hbm2-example.json create mode 100644 DRAMSys/tests/ddr3_multirank/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json create mode 100644 DRAMSys/tests/ddr3_multirank/configs/mcconfigs/fr_fcfs_grp.json create mode 100644 DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json create mode 100644 DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json create mode 100644 DRAMSys/tests/ddr3_multirank/configs/thermalsim/config.json create mode 100755 DRAMSys/tests/ddr3_multirank/configs/thermalsim/core.flp create mode 100755 DRAMSys/tests/ddr3_multirank/configs/thermalsim/mem.flp create mode 100644 DRAMSys/tests/ddr3_multirank/configs/thermalsim/powerInfo.json create mode 100755 DRAMSys/tests/ddr3_multirank/configs/thermalsim/stack.stk create mode 100644 DRAMSys/tests/ddr3_multirank/scripts/createTraceDB.sql create mode 100644 DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json create mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json create mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/mcconfigs/fr_fcfs.json create mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json create mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json create mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json create mode 100755 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp create mode 100755 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp create mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json create mode 100755 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk create mode 100644 DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql create mode 100644 DRAMSys/tests/ddr4_bankgroups/simulations/ddr4-example.json create mode 100644 DRAMSys/tests/lpddr4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json create mode 100644 DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json create mode 100644 DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json create mode 100644 DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json create mode 100644 DRAMSys/tests/lpddr4/configs/thermalsim/config.json create mode 100755 DRAMSys/tests/lpddr4/configs/thermalsim/core.flp create mode 100755 DRAMSys/tests/lpddr4/configs/thermalsim/mem.flp create mode 100644 DRAMSys/tests/lpddr4/configs/thermalsim/powerInfo.json create mode 100755 DRAMSys/tests/lpddr4/configs/thermalsim/stack.stk create mode 100644 DRAMSys/tests/lpddr4/scripts/createTraceDB.sql create mode 100644 DRAMSys/tests/lpddr4/simulations/lpddr4-example.json diff --git a/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json b/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json new file mode 100644 index 00000000..354217a5 --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json @@ -0,0 +1,46 @@ +{ + "CONGEN": { + "RANK_BIT":[ + 29 + ], + "BANKGROUP_BIT":[ + 27, + 28 + ], + "BANK_BIT": [ + 25, + 26 + ], + "BYTE_BIT": [ + 0, + 1, + 2 + ], + "COLUMN_BIT": [ + 3, + 4, + 5, + 6, + 7, + 8, + 9 + ], + "ROW_BIT": [ + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24 + ] + } +} diff --git a/DRAMSys/tests/HBM2/configs/mcconfigs/fifoStrict.json b/DRAMSys/tests/HBM2/configs/mcconfigs/fifoStrict.json new file mode 100644 index 00000000..3546377c --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/mcconfigs/fifoStrict.json @@ -0,0 +1,11 @@ +{"mcconfig": {"PagePolicy": "Closed", +"Scheduler": "Fifo", +"RequestBufferSize": 8, +"CmdMux": "Strict", +"RespQueue": "Fifo", +"RefreshPolicy": "Rankwise", +"RefreshMode": 1, +"RefreshMaxPostponed": 0, +"RefreshMaxPulledin": 0, +"PowerDownPolicy": "NoPowerDown", +"PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json new file mode 100644 index 00000000..efa8ee9e --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json @@ -0,0 +1,46 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 4, + "dataRate": 2, + "nbrOfBankGroups": 4, + "nbrOfBanks": 16, + "nbrOfColumns": 128, + "nbrOfRanks": 2, + "nbrOfRows": 32768, + "width": 64 + }, + "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", + "memoryType": "HBM2", + "memtimingspec": { + "CCDL": 3, + "CCDS": 2, + "CKE": 8, + "DQSCK": 1, + "FAW": 16, + "PL": 0, + "RAS": 28, + "RC": 42, + "RCDRD": 12, + "RCDWR": 6, + "REFI": 3900, + "REFISB": 244, + "RFC": 220, + "RFCSB": 96, + "RL": 17, + "RP": 14, + "RRDL": 6, + "RRDS": 4, + "RREFD": 8, + "RTP": 5, + "RTW": 18, + "WL": 7, + "WR": 14, + "WTRL": 9, + "WTRS": 4, + "XP": 8, + "XS": 216, + "clkMhz": 1000 + } + } +} \ No newline at end of file diff --git a/DRAMSys/tests/HBM2/configs/simulator/hbm2.json b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json new file mode 100644 index 00000000..9589611f --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json @@ -0,0 +1,21 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1, + "PowerAnalysis": false, + "SimulationName": "hbm2", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} \ No newline at end of file diff --git a/DRAMSys/tests/HBM2/configs/thermalsim/config.json b/DRAMSys/tests/HBM2/configs/thermalsim/config.json new file mode 100644 index 00000000..b88ed84c --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/thermalsim/config.json @@ -0,0 +1,15 @@ +{ + "thermalsimconfig": { + "TemperatureScale": "Celsius", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, + "ThermalSimUnit":"us", + "PowerInfoFile": "powerInfo.json", + "IceServerIp": "127.0.0.1", + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true + } +} diff --git a/DRAMSys/tests/HBM2/configs/thermalsim/core.flp b/DRAMSys/tests/HBM2/configs/thermalsim/core.flp new file mode 100755 index 00000000..e85e6801 --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/thermalsim/core.flp @@ -0,0 +1,45 @@ +CPUs : + + position 0, 0 ; + dimension 2750, 4300 ; + +GPU : + + position 3350, 0 ; + dimension 2750, 4000 ; + +BASEBAND1 : + + position 4250, 4000 ; + dimension 1850, 3300 ; + +BASEBAND2 : + + position 3350, 7300 ; + dimension 2750, 3300 ; + +LLCACHE : + + position 0, 4300 ; + dimension 1900, 3000 ; + +DRAMCTRL1 : + + position 1900, 4300 ; + dimension 850, 3000 ; + +DRAMCTRL2 : + + position 3350, 4000 ; + dimension 900, 3300 ; + +TSVS : + + position 2750, 2300 ; + dimension 600, 6000 ; + +ACELLERATORS : + + position 0, 7300 ; + dimension 2750, 3300 ; + diff --git a/DRAMSys/tests/HBM2/configs/thermalsim/mem.flp b/DRAMSys/tests/HBM2/configs/thermalsim/mem.flp new file mode 100755 index 00000000..29d02254 --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/thermalsim/mem.flp @@ -0,0 +1,16 @@ +channel0 : + position 150, 100 ; + dimension 2600, 5200 ; + +channel1 : + position 3350, 100 ; + dimension 2600, 5200 ; + +channel2 : + position 150, 5300 ; + dimension 2600, 5200 ; + +channel3 : + position 3350, 5300 ; + dimension 2600, 5200 ; + diff --git a/DRAMSys/tests/HBM2/configs/thermalsim/powerInfo.json b/DRAMSys/tests/HBM2/configs/thermalsim/powerInfo.json new file mode 100644 index 00000000..524f690f --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/thermalsim/powerInfo.json @@ -0,0 +1,20 @@ +{ + "powerInfo": { + "dram_die_channel0": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel1": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel2": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel3": { + "init_pow": 0, + "threshold": 1.0 + } + } +} diff --git a/DRAMSys/tests/HBM2/configs/thermalsim/stack.stk b/DRAMSys/tests/HBM2/configs/thermalsim/stack.stk new file mode 100755 index 00000000..ec74f020 --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/thermalsim/stack.stk @@ -0,0 +1,49 @@ +material SILICON : + thermal conductivity 1.30e-4 ; + volumetric heat capacity 1.628e-12 ; + +material BEOL : + thermal conductivity 2.25e-6 ; + volumetric heat capacity 2.175e-12 ; + +material COPPER : + thermal conductivity 4.01e-04 ; + volumetric heat capacity 3.37e-12 ; + +top heat sink : + //sink height 1e03, area 100e06, material COPPER ; + //spreader height 0.5e03, area 70e06, material SILICON ; + heat transfer coefficient 1.3e-09 ; + temperature 318.15 ; +dimensions : + chip length 6100, width 10600 ; + cell length 100, width 100 ; + + +layer PCB : + height 10 ; + material BEOL ; + +die DRAM : + layer 58.5 SILICON ; + source 2 SILICON ; + layer 1.5 BEOL ; + layer 58.5 SILICON ; + + +stack: + die DRAM_DIE DRAM floorplan "./mem.flp" ; + layer CONN_TO_PCB PCB ; + +solver: + transient step 0.01, slot 0.05 ; + initial temperature 300.0 ; + +output: + Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); + Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); + Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); + Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); + Tmap (DRAM_DIE, "output1.txt", slot) ; + Pmap (DRAM_DIE, "output2.txt", slot) ; + diff --git a/DRAMSys/tests/HBM2/scripts/createTraceDB.sql b/DRAMSys/tests/HBM2/scripts/createTraceDB.sql new file mode 100644 index 00000000..7a127fac --- /dev/null +++ b/DRAMSys/tests/HBM2/scripts/createTraceDB.sql @@ -0,0 +1,94 @@ +DROP TABLE IF EXISTS Phases; +DROP TABLE IF EXISTS GeneralInfo; +DROP TABLE IF EXISTS CommandLengths; +DROP TABLE IF EXISTS Comments; +DROP TABLE IF EXISTS ranges; +DROP TABLE IF EXISTS Transactions; +DROP TABLE IF EXISTS DebugMessages; +DROP TABLE IF EXISTS Power; + +CREATE TABLE Phases( + ID INTEGER PRIMARY KEY, + PhaseName TEXT, + PhaseBegin INTEGER, + PhaseEnd INTEGER, + Transact INTEGER +); + +CREATE TABLE GeneralInfo( + NumberOfTransactions INTEGER, + TraceEnd INTEGER, + NumberOfRanks INTEGER, + NumberOfBanks INTEGER, + clk INTEGER, + UnitOfTime TEXT, + MCconfig TEXT, + Memspec TEXT, + Traces TEXT, + WindowSize INTEGER, + FlexibleRefresh INTEGER, + MaxRefBurst INTEGER, + ControllerThread INTEGER +); + +CREATE TABLE CommandLengths( + ACT INTEGER, + PRE INTEGER, + PREA INTEGER, + RD INTEGER, + RDA INTEGER, + WR INTEGER, + WRA INTEGER, + REFA INTEGER, + REFB INTEGER, + PDEA INTEGER, + PDXA INTEGER, + PDEP INTEGER, + PDXP INTEGER, + SREFEN INTEGER, + SREFEX INTEGER +); + +CREATE TABLE Power( + time DOUBLE, + AveragePower DOUBLE +); + + +CREATE TABLE Comments( + Time INTEGER, + Text TEXT +); + +CREATE TABLE DebugMessages( + Time INTEGER, + Message TEXT +); + +-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) +CREATE VIRTUAL TABLE ranges USING rtree( + id, + begin, end +); + +CREATE TABLE Transactions( + ID INTEGER, + Range INTEGER, + Address INTEGER, + Burstlength INTEGER, + TThread INTEGER, + TChannel INTEGER, + TRank INTEGER, + TBankgroup INTEGER, + TBank INTEGER, + TRow INTEGER, + TColumn INTEGER, + DataStrobeBegin INTEGER, + DataStrobeEnd INTEGER, + TimeOfGeneration INTEGER, + Command TEXT + ); + +CREATE INDEX ranges_index ON Transactions(Range); +CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); +CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/HBM2/simulations/hbm2-example.json b/DRAMSys/tests/HBM2/simulations/hbm2-example.json new file mode 100644 index 00000000..6fd5f064 --- /dev/null +++ b/DRAMSys/tests/HBM2/simulations/hbm2-example.json @@ -0,0 +1,20 @@ +{ + "simulation": { + "addressmapping": "am_hbm2_8Gb_pc_brc.json", + "mcconfig": "fifoStrict.json", + "memspec": "HBM2.json", + "simconfig": "hbm2.json", + "simulationid": "hbm2-example", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 1000, + "name": "trace1_test4.stl" + }, + { + "clkMhz": 1000, + "name": "trace2_test4.stl" + } + ] + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json b/DRAMSys/tests/ddr3_multirank/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json new file mode 100644 index 00000000..c82926c9 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json @@ -0,0 +1,51 @@ +{ + "CONGEN": { + "XOR":[ + { + "FIRST":13, + "SECOND":16 + } + ], + "BANK_BIT": [ + 13, + 14, + 15 + ], + "BYTE_BIT": [ + 0, + 1, + 2 + ], + "COLUMN_BIT": [ + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12 + ], + "ROW_BIT": [ + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29 + ], + "RANK_BIT": [ + 30 + ] + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/mcconfigs/fr_fcfs_grp.json b/DRAMSys/tests/ddr3_multirank/configs/mcconfigs/fr_fcfs_grp.json new file mode 100644 index 00000000..4ac02e30 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/mcconfigs/fr_fcfs_grp.json @@ -0,0 +1,12 @@ +{"mcconfig": + {"PagePolicy": "Open", + "Scheduler": "FrFcfsGrp", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "Rankwise", + "RefreshMode": 1, + "RefreshMaxPostponed": 0, + "RefreshMaxPulledin": 0, + "PowerDownPolicy": "Staggered", + "PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json new file mode 100644 index 00000000..13d9fef5 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -0,0 +1,55 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 8, + "dataRate": 2, + "nbrOfBanks": 8, + "nbrOfColumns": 1024, + "nbrOfRanks": 2, + "nbrOfRows": 16384, + "width": 8 + }, + "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", + "memoryType": "DDR3", + "mempowerspec": { + "idd0": 720.0, + "idd2n": 400.0, + "idd2p0": 80.0, + "idd2p1": 200.0, + "idd3n": 440.0, + "idd3p0": 240.0, + "idd3p1": 240.0, + "idd4r": 1200.0, + "idd4w": 1200.0, + "idd5": 1760.0, + "idd6": 48.0, + "vdd": 1.5 + }, + "memtimingspec": { + "AL": 0, + "CCD": 4, + "CKE": 3, + "CKESR": 4, + "CL": 7, + "DQSCK": 0, + "FAW": 20, + "RAS": 20, + "RC": 27, + "RCD": 7, + "REFI": 4160, + "RFC": 59, + "RL": 7, + "RP": 7, + "RRD": 4, + "RTP": 4, + "WL": 6, + "WR": 8, + "WTR": 4, + "XP": 4, + "XPDLL": 13, + "XS": 64, + "XSDLL": 512, + "clkMhz": 533 + } + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json new file mode 100644 index 00000000..4e9faadc --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json @@ -0,0 +1,21 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1, + "PowerAnalysis": false, + "SimulationName": "ddr3", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/config.json b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/config.json new file mode 100644 index 00000000..b88ed84c --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/config.json @@ -0,0 +1,15 @@ +{ + "thermalsimconfig": { + "TemperatureScale": "Celsius", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, + "ThermalSimUnit":"us", + "PowerInfoFile": "powerInfo.json", + "IceServerIp": "127.0.0.1", + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/core.flp b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/core.flp new file mode 100755 index 00000000..e85e6801 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/core.flp @@ -0,0 +1,45 @@ +CPUs : + + position 0, 0 ; + dimension 2750, 4300 ; + +GPU : + + position 3350, 0 ; + dimension 2750, 4000 ; + +BASEBAND1 : + + position 4250, 4000 ; + dimension 1850, 3300 ; + +BASEBAND2 : + + position 3350, 7300 ; + dimension 2750, 3300 ; + +LLCACHE : + + position 0, 4300 ; + dimension 1900, 3000 ; + +DRAMCTRL1 : + + position 1900, 4300 ; + dimension 850, 3000 ; + +DRAMCTRL2 : + + position 3350, 4000 ; + dimension 900, 3300 ; + +TSVS : + + position 2750, 2300 ; + dimension 600, 6000 ; + +ACELLERATORS : + + position 0, 7300 ; + dimension 2750, 3300 ; + diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/mem.flp b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/mem.flp new file mode 100755 index 00000000..29d02254 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/mem.flp @@ -0,0 +1,16 @@ +channel0 : + position 150, 100 ; + dimension 2600, 5200 ; + +channel1 : + position 3350, 100 ; + dimension 2600, 5200 ; + +channel2 : + position 150, 5300 ; + dimension 2600, 5200 ; + +channel3 : + position 3350, 5300 ; + dimension 2600, 5200 ; + diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/powerInfo.json b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/powerInfo.json new file mode 100644 index 00000000..524f690f --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/powerInfo.json @@ -0,0 +1,20 @@ +{ + "powerInfo": { + "dram_die_channel0": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel1": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel2": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel3": { + "init_pow": 0, + "threshold": 1.0 + } + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/stack.stk b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/stack.stk new file mode 100755 index 00000000..ec74f020 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/stack.stk @@ -0,0 +1,49 @@ +material SILICON : + thermal conductivity 1.30e-4 ; + volumetric heat capacity 1.628e-12 ; + +material BEOL : + thermal conductivity 2.25e-6 ; + volumetric heat capacity 2.175e-12 ; + +material COPPER : + thermal conductivity 4.01e-04 ; + volumetric heat capacity 3.37e-12 ; + +top heat sink : + //sink height 1e03, area 100e06, material COPPER ; + //spreader height 0.5e03, area 70e06, material SILICON ; + heat transfer coefficient 1.3e-09 ; + temperature 318.15 ; +dimensions : + chip length 6100, width 10600 ; + cell length 100, width 100 ; + + +layer PCB : + height 10 ; + material BEOL ; + +die DRAM : + layer 58.5 SILICON ; + source 2 SILICON ; + layer 1.5 BEOL ; + layer 58.5 SILICON ; + + +stack: + die DRAM_DIE DRAM floorplan "./mem.flp" ; + layer CONN_TO_PCB PCB ; + +solver: + transient step 0.01, slot 0.05 ; + initial temperature 300.0 ; + +output: + Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); + Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); + Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); + Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); + Tmap (DRAM_DIE, "output1.txt", slot) ; + Pmap (DRAM_DIE, "output2.txt", slot) ; + diff --git a/DRAMSys/tests/ddr3_multirank/scripts/createTraceDB.sql b/DRAMSys/tests/ddr3_multirank/scripts/createTraceDB.sql new file mode 100644 index 00000000..7a127fac --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/scripts/createTraceDB.sql @@ -0,0 +1,94 @@ +DROP TABLE IF EXISTS Phases; +DROP TABLE IF EXISTS GeneralInfo; +DROP TABLE IF EXISTS CommandLengths; +DROP TABLE IF EXISTS Comments; +DROP TABLE IF EXISTS ranges; +DROP TABLE IF EXISTS Transactions; +DROP TABLE IF EXISTS DebugMessages; +DROP TABLE IF EXISTS Power; + +CREATE TABLE Phases( + ID INTEGER PRIMARY KEY, + PhaseName TEXT, + PhaseBegin INTEGER, + PhaseEnd INTEGER, + Transact INTEGER +); + +CREATE TABLE GeneralInfo( + NumberOfTransactions INTEGER, + TraceEnd INTEGER, + NumberOfRanks INTEGER, + NumberOfBanks INTEGER, + clk INTEGER, + UnitOfTime TEXT, + MCconfig TEXT, + Memspec TEXT, + Traces TEXT, + WindowSize INTEGER, + FlexibleRefresh INTEGER, + MaxRefBurst INTEGER, + ControllerThread INTEGER +); + +CREATE TABLE CommandLengths( + ACT INTEGER, + PRE INTEGER, + PREA INTEGER, + RD INTEGER, + RDA INTEGER, + WR INTEGER, + WRA INTEGER, + REFA INTEGER, + REFB INTEGER, + PDEA INTEGER, + PDXA INTEGER, + PDEP INTEGER, + PDXP INTEGER, + SREFEN INTEGER, + SREFEX INTEGER +); + +CREATE TABLE Power( + time DOUBLE, + AveragePower DOUBLE +); + + +CREATE TABLE Comments( + Time INTEGER, + Text TEXT +); + +CREATE TABLE DebugMessages( + Time INTEGER, + Message TEXT +); + +-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) +CREATE VIRTUAL TABLE ranges USING rtree( + id, + begin, end +); + +CREATE TABLE Transactions( + ID INTEGER, + Range INTEGER, + Address INTEGER, + Burstlength INTEGER, + TThread INTEGER, + TChannel INTEGER, + TRank INTEGER, + TBankgroup INTEGER, + TBank INTEGER, + TRow INTEGER, + TColumn INTEGER, + DataStrobeBegin INTEGER, + DataStrobeEnd INTEGER, + TimeOfGeneration INTEGER, + Command TEXT + ); + +CREATE INDEX ranges_index ON Transactions(Range); +CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); +CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json b/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json new file mode 100644 index 00000000..e3d4a4c3 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json @@ -0,0 +1,16 @@ +{ + "simulation": { + "addressmapping": "am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json", + "mcconfig": "fr_fcfs_grp.json", + "memspec": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json", + "simconfig": "ddr3.json", + "simulationid": "ddr3-example-dual-rank-json", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 533, + "name": "trace_test2.stl" + } + ] + } +} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json b/DRAMSys/tests/ddr4_bankgroups/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json new file mode 100644 index 00000000..be30b98f --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json @@ -0,0 +1,46 @@ +{ + "CONGEN": { + "BANKGROUP_BIT":[ + 30, + 31 + ], + "BANK_BIT": [ + 28, + 29 + ], + "BYTE_BIT": [ + 0, + 1, + 2 + ], + "COLUMN_BIT": [ + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12 + ], + "ROW_BIT": [ + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27 + ] + } +} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/mcconfigs/fr_fcfs.json b/DRAMSys/tests/ddr4_bankgroups/configs/mcconfigs/fr_fcfs.json new file mode 100644 index 00000000..2da01ceb --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/mcconfigs/fr_fcfs.json @@ -0,0 +1,12 @@ +{"mcconfig": { + "PagePolicy": "Open", + "Scheduler": "FrFcfs", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "Rankwise", + "RefreshMode": 1, + "RefreshMaxPostponed": 128, + "RefreshMaxPulledin": 128, + "PowerDownPolicy": "NoPowerDown", + "PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json new file mode 100644 index 00000000..11700aaf --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -0,0 +1,66 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 8, + "dataRate": 2, + "nbrOfBankGroups": 4, + "nbrOfBanks": 16, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfRows": 32768, + "width": 8 + }, + "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", + "memoryType": "DDR4", + "mempowerspec": { + "idd0": 56.25, + "idd02": 4.05, + "idd2n": 33.75, + "idd2p0": 17.0, + "idd2p1": 17.0, + "idd3n": 39.5, + "idd3p0": 22.5, + "idd3p1": 22.5, + "idd4r": 157.5, + "idd4w": 135.0, + "idd5": 118.0, + "idd6": 20.25, + "idd62": 2.6, + "vdd": 1.2, + "vdd2": 2.5 + }, + "memtimingspec": { + "AL": 0, + "CCD_L": 5, + "CCD_S": 4, + "CKE": 6, + "CKESR": 7, + "CL": 13, + "DQSCK": 2, + "FAW": 22, + "RAS": 32, + "RC": 45, + "RCD": 13, + "REFI": 3644, + "RFC": 243, + "RL": 13, + "RP": 13, + "RRD_L": 5, + "RRD_S": 4, + "RTP": 8, + "WL": 12, + "WR": 14, + "WTR_L": 7, + "WTR_S": 3, + "XP": 8, + "XPDLL": 255, + "XS": 252, + "XSDLL": 512, + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1, + "clkMhz": 933 + } + } +} \ No newline at end of file diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json b/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json new file mode 100644 index 00000000..8e62e680 --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json @@ -0,0 +1,21 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1, + "PowerAnalysis": false, + "SimulationName": "ddr4", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} \ No newline at end of file diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json new file mode 100644 index 00000000..b88ed84c --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json @@ -0,0 +1,15 @@ +{ + "thermalsimconfig": { + "TemperatureScale": "Celsius", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, + "ThermalSimUnit":"us", + "PowerInfoFile": "powerInfo.json", + "IceServerIp": "127.0.0.1", + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true + } +} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp new file mode 100755 index 00000000..e85e6801 --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp @@ -0,0 +1,45 @@ +CPUs : + + position 0, 0 ; + dimension 2750, 4300 ; + +GPU : + + position 3350, 0 ; + dimension 2750, 4000 ; + +BASEBAND1 : + + position 4250, 4000 ; + dimension 1850, 3300 ; + +BASEBAND2 : + + position 3350, 7300 ; + dimension 2750, 3300 ; + +LLCACHE : + + position 0, 4300 ; + dimension 1900, 3000 ; + +DRAMCTRL1 : + + position 1900, 4300 ; + dimension 850, 3000 ; + +DRAMCTRL2 : + + position 3350, 4000 ; + dimension 900, 3300 ; + +TSVS : + + position 2750, 2300 ; + dimension 600, 6000 ; + +ACELLERATORS : + + position 0, 7300 ; + dimension 2750, 3300 ; + diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp new file mode 100755 index 00000000..29d02254 --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp @@ -0,0 +1,16 @@ +channel0 : + position 150, 100 ; + dimension 2600, 5200 ; + +channel1 : + position 3350, 100 ; + dimension 2600, 5200 ; + +channel2 : + position 150, 5300 ; + dimension 2600, 5200 ; + +channel3 : + position 3350, 5300 ; + dimension 2600, 5200 ; + diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json new file mode 100644 index 00000000..524f690f --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json @@ -0,0 +1,20 @@ +{ + "powerInfo": { + "dram_die_channel0": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel1": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel2": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel3": { + "init_pow": 0, + "threshold": 1.0 + } + } +} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk new file mode 100755 index 00000000..ec74f020 --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk @@ -0,0 +1,49 @@ +material SILICON : + thermal conductivity 1.30e-4 ; + volumetric heat capacity 1.628e-12 ; + +material BEOL : + thermal conductivity 2.25e-6 ; + volumetric heat capacity 2.175e-12 ; + +material COPPER : + thermal conductivity 4.01e-04 ; + volumetric heat capacity 3.37e-12 ; + +top heat sink : + //sink height 1e03, area 100e06, material COPPER ; + //spreader height 0.5e03, area 70e06, material SILICON ; + heat transfer coefficient 1.3e-09 ; + temperature 318.15 ; +dimensions : + chip length 6100, width 10600 ; + cell length 100, width 100 ; + + +layer PCB : + height 10 ; + material BEOL ; + +die DRAM : + layer 58.5 SILICON ; + source 2 SILICON ; + layer 1.5 BEOL ; + layer 58.5 SILICON ; + + +stack: + die DRAM_DIE DRAM floorplan "./mem.flp" ; + layer CONN_TO_PCB PCB ; + +solver: + transient step 0.01, slot 0.05 ; + initial temperature 300.0 ; + +output: + Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); + Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); + Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); + Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); + Tmap (DRAM_DIE, "output1.txt", slot) ; + Pmap (DRAM_DIE, "output2.txt", slot) ; + diff --git a/DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql b/DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql new file mode 100644 index 00000000..7a127fac --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql @@ -0,0 +1,94 @@ +DROP TABLE IF EXISTS Phases; +DROP TABLE IF EXISTS GeneralInfo; +DROP TABLE IF EXISTS CommandLengths; +DROP TABLE IF EXISTS Comments; +DROP TABLE IF EXISTS ranges; +DROP TABLE IF EXISTS Transactions; +DROP TABLE IF EXISTS DebugMessages; +DROP TABLE IF EXISTS Power; + +CREATE TABLE Phases( + ID INTEGER PRIMARY KEY, + PhaseName TEXT, + PhaseBegin INTEGER, + PhaseEnd INTEGER, + Transact INTEGER +); + +CREATE TABLE GeneralInfo( + NumberOfTransactions INTEGER, + TraceEnd INTEGER, + NumberOfRanks INTEGER, + NumberOfBanks INTEGER, + clk INTEGER, + UnitOfTime TEXT, + MCconfig TEXT, + Memspec TEXT, + Traces TEXT, + WindowSize INTEGER, + FlexibleRefresh INTEGER, + MaxRefBurst INTEGER, + ControllerThread INTEGER +); + +CREATE TABLE CommandLengths( + ACT INTEGER, + PRE INTEGER, + PREA INTEGER, + RD INTEGER, + RDA INTEGER, + WR INTEGER, + WRA INTEGER, + REFA INTEGER, + REFB INTEGER, + PDEA INTEGER, + PDXA INTEGER, + PDEP INTEGER, + PDXP INTEGER, + SREFEN INTEGER, + SREFEX INTEGER +); + +CREATE TABLE Power( + time DOUBLE, + AveragePower DOUBLE +); + + +CREATE TABLE Comments( + Time INTEGER, + Text TEXT +); + +CREATE TABLE DebugMessages( + Time INTEGER, + Message TEXT +); + +-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) +CREATE VIRTUAL TABLE ranges USING rtree( + id, + begin, end +); + +CREATE TABLE Transactions( + ID INTEGER, + Range INTEGER, + Address INTEGER, + Burstlength INTEGER, + TThread INTEGER, + TChannel INTEGER, + TRank INTEGER, + TBankgroup INTEGER, + TBank INTEGER, + TRow INTEGER, + TColumn INTEGER, + DataStrobeBegin INTEGER, + DataStrobeEnd INTEGER, + TimeOfGeneration INTEGER, + Command TEXT + ); + +CREATE INDEX ranges_index ON Transactions(Range); +CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); +CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/ddr4_bankgroups/simulations/ddr4-example.json b/DRAMSys/tests/ddr4_bankgroups/simulations/ddr4-example.json new file mode 100644 index 00000000..d97481d9 --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/simulations/ddr4-example.json @@ -0,0 +1,16 @@ +{ + "simulation": { + "addressmapping": "am_ddr4_8x4Gbx8_dimm_p1KB_brc.json", + "mcconfig": "fr_fcfs.json", + "memspec": "MICRON_4Gb_DDR4-1866_8bit_A.json", + "simconfig": "ddr4.json", + "simulationid": "ddr4-bankgrp", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 933, + "name": "trace_test3.stl" + } + ] + } +} diff --git a/DRAMSys/tests/lpddr4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json b/DRAMSys/tests/lpddr4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json new file mode 100644 index 00000000..e9b3ac9f --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json @@ -0,0 +1,42 @@ +{ + "CONGEN": { + "BANK_BIT": [ + 27, + 28, + 29 + ], + "BYTE_BIT": [ + 0 + ], + "COLUMN_BIT": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10 + ], + "ROW_BIT": [ + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26 + ] + } +} \ No newline at end of file diff --git a/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json b/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json new file mode 100644 index 00000000..712e1c96 --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json @@ -0,0 +1,11 @@ +{"mcconfig": {"PagePolicy": "Open", +"Scheduler": "Fifo", +"RequestBufferSize": 8, +"CmdMux": "Oldest", +"RespQueue": "Fifo", +"RefreshPolicy": "Bankwise", +"RefreshMode": 1, +"RefreshMaxPostponed": 8, +"RefreshMaxPulledin": 8, +"PowerDownPolicy": "NoPowerDown", +"PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json new file mode 100644 index 00000000..97a8cc3e --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json @@ -0,0 +1,46 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 16, + "dataRate": 2, + "nbrOfBanks": 8, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfRows": 65536, + "width": 16 + }, + "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", + "memoryType": "LPDDR4", + "memtimingspec": { + "CCD": 8, + "CKE": 12, + "CMDCKE": 3, + "DQS2DQ": 2, + "DQSCK": 6, + "DQSS": 1, + "ESCKE": 3, + "FAW": 64, + "PPD": 4, + "RAS": 68, + "RCD": 29, + "REFI": 6246, + "REFIPB": 780, + "RFCAB": 448, + "RFCPB": 224, + "RL": 28, + "RPAB": 34, + "RPPB": 29, + "RPST": 0, + "RRD": 16, + "RTP": 12, + "SR": 24, + "WL": 14, + "WPRE": 2, + "WR": 29, + "WTR": 16, + "XP": 12, + "XSR": 460, + "clkMhz": 1600 + } + } +} \ No newline at end of file diff --git a/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json new file mode 100644 index 00000000..fd8fe855 --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json @@ -0,0 +1,21 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1, + "PowerAnalysis": false, + "SimulationName": "lpddr4", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} \ No newline at end of file diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/config.json b/DRAMSys/tests/lpddr4/configs/thermalsim/config.json new file mode 100644 index 00000000..b88ed84c --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/config.json @@ -0,0 +1,15 @@ +{ + "thermalsimconfig": { + "TemperatureScale": "Celsius", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, + "ThermalSimUnit":"us", + "PowerInfoFile": "powerInfo.json", + "IceServerIp": "127.0.0.1", + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true + } +} diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/core.flp b/DRAMSys/tests/lpddr4/configs/thermalsim/core.flp new file mode 100755 index 00000000..e85e6801 --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/core.flp @@ -0,0 +1,45 @@ +CPUs : + + position 0, 0 ; + dimension 2750, 4300 ; + +GPU : + + position 3350, 0 ; + dimension 2750, 4000 ; + +BASEBAND1 : + + position 4250, 4000 ; + dimension 1850, 3300 ; + +BASEBAND2 : + + position 3350, 7300 ; + dimension 2750, 3300 ; + +LLCACHE : + + position 0, 4300 ; + dimension 1900, 3000 ; + +DRAMCTRL1 : + + position 1900, 4300 ; + dimension 850, 3000 ; + +DRAMCTRL2 : + + position 3350, 4000 ; + dimension 900, 3300 ; + +TSVS : + + position 2750, 2300 ; + dimension 600, 6000 ; + +ACELLERATORS : + + position 0, 7300 ; + dimension 2750, 3300 ; + diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/mem.flp b/DRAMSys/tests/lpddr4/configs/thermalsim/mem.flp new file mode 100755 index 00000000..29d02254 --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/mem.flp @@ -0,0 +1,16 @@ +channel0 : + position 150, 100 ; + dimension 2600, 5200 ; + +channel1 : + position 3350, 100 ; + dimension 2600, 5200 ; + +channel2 : + position 150, 5300 ; + dimension 2600, 5200 ; + +channel3 : + position 3350, 5300 ; + dimension 2600, 5200 ; + diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/powerInfo.json b/DRAMSys/tests/lpddr4/configs/thermalsim/powerInfo.json new file mode 100644 index 00000000..524f690f --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/powerInfo.json @@ -0,0 +1,20 @@ +{ + "powerInfo": { + "dram_die_channel0": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel1": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel2": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel3": { + "init_pow": 0, + "threshold": 1.0 + } + } +} diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/stack.stk b/DRAMSys/tests/lpddr4/configs/thermalsim/stack.stk new file mode 100755 index 00000000..ec74f020 --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/stack.stk @@ -0,0 +1,49 @@ +material SILICON : + thermal conductivity 1.30e-4 ; + volumetric heat capacity 1.628e-12 ; + +material BEOL : + thermal conductivity 2.25e-6 ; + volumetric heat capacity 2.175e-12 ; + +material COPPER : + thermal conductivity 4.01e-04 ; + volumetric heat capacity 3.37e-12 ; + +top heat sink : + //sink height 1e03, area 100e06, material COPPER ; + //spreader height 0.5e03, area 70e06, material SILICON ; + heat transfer coefficient 1.3e-09 ; + temperature 318.15 ; +dimensions : + chip length 6100, width 10600 ; + cell length 100, width 100 ; + + +layer PCB : + height 10 ; + material BEOL ; + +die DRAM : + layer 58.5 SILICON ; + source 2 SILICON ; + layer 1.5 BEOL ; + layer 58.5 SILICON ; + + +stack: + die DRAM_DIE DRAM floorplan "./mem.flp" ; + layer CONN_TO_PCB PCB ; + +solver: + transient step 0.01, slot 0.05 ; + initial temperature 300.0 ; + +output: + Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); + Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); + Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); + Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); + Tmap (DRAM_DIE, "output1.txt", slot) ; + Pmap (DRAM_DIE, "output2.txt", slot) ; + diff --git a/DRAMSys/tests/lpddr4/scripts/createTraceDB.sql b/DRAMSys/tests/lpddr4/scripts/createTraceDB.sql new file mode 100644 index 00000000..7a127fac --- /dev/null +++ b/DRAMSys/tests/lpddr4/scripts/createTraceDB.sql @@ -0,0 +1,94 @@ +DROP TABLE IF EXISTS Phases; +DROP TABLE IF EXISTS GeneralInfo; +DROP TABLE IF EXISTS CommandLengths; +DROP TABLE IF EXISTS Comments; +DROP TABLE IF EXISTS ranges; +DROP TABLE IF EXISTS Transactions; +DROP TABLE IF EXISTS DebugMessages; +DROP TABLE IF EXISTS Power; + +CREATE TABLE Phases( + ID INTEGER PRIMARY KEY, + PhaseName TEXT, + PhaseBegin INTEGER, + PhaseEnd INTEGER, + Transact INTEGER +); + +CREATE TABLE GeneralInfo( + NumberOfTransactions INTEGER, + TraceEnd INTEGER, + NumberOfRanks INTEGER, + NumberOfBanks INTEGER, + clk INTEGER, + UnitOfTime TEXT, + MCconfig TEXT, + Memspec TEXT, + Traces TEXT, + WindowSize INTEGER, + FlexibleRefresh INTEGER, + MaxRefBurst INTEGER, + ControllerThread INTEGER +); + +CREATE TABLE CommandLengths( + ACT INTEGER, + PRE INTEGER, + PREA INTEGER, + RD INTEGER, + RDA INTEGER, + WR INTEGER, + WRA INTEGER, + REFA INTEGER, + REFB INTEGER, + PDEA INTEGER, + PDXA INTEGER, + PDEP INTEGER, + PDXP INTEGER, + SREFEN INTEGER, + SREFEX INTEGER +); + +CREATE TABLE Power( + time DOUBLE, + AveragePower DOUBLE +); + + +CREATE TABLE Comments( + Time INTEGER, + Text TEXT +); + +CREATE TABLE DebugMessages( + Time INTEGER, + Message TEXT +); + +-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) +CREATE VIRTUAL TABLE ranges USING rtree( + id, + begin, end +); + +CREATE TABLE Transactions( + ID INTEGER, + Range INTEGER, + Address INTEGER, + Burstlength INTEGER, + TThread INTEGER, + TChannel INTEGER, + TRank INTEGER, + TBankgroup INTEGER, + TBank INTEGER, + TRow INTEGER, + TColumn INTEGER, + DataStrobeBegin INTEGER, + DataStrobeEnd INTEGER, + TimeOfGeneration INTEGER, + Command TEXT + ); + +CREATE INDEX ranges_index ON Transactions(Range); +CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); +CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/lpddr4/simulations/lpddr4-example.json b/DRAMSys/tests/lpddr4/simulations/lpddr4-example.json new file mode 100644 index 00000000..30211e69 --- /dev/null +++ b/DRAMSys/tests/lpddr4/simulations/lpddr4-example.json @@ -0,0 +1,16 @@ +{ + "simulation": { + "addressmapping": "am_lpddr4_8Gbx16_brc.json", + "mcconfig": "fifo.json", + "memspec": "JEDEC_8Gb_LPDDR4-3200_16bit.json", + "simconfig": "lpddr4.json", + "simulationid": "lpddr4-example", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 1600, + "name": "trace_lpddr4.stl" + } + ] + } +} From a3592e15ba6646c4c149c758505d59f771033650 Mon Sep 17 00:00:00 2001 From: scorrea Date: Mon, 15 Jun 2020 18:24:16 +0200 Subject: [PATCH 03/53] Nr of channel and devices per DIMM at memspec file --- DRAMSys/library/src/common/AddressDecoder.cpp | 4 +- .../src/configuration/Configuration.cpp | 17 +--- .../library/src/configuration/Configuration.h | 2 - .../src/configuration/memspec/MemSpec.cpp | 4 + .../src/configuration/memspec/MemSpec.h | 2 + DRAMSys/library/src/controller/ControllerIF.h | 2 +- DRAMSys/library/src/simulation/Arbiter.cpp | 4 +- DRAMSys/library/src/simulation/DRAMSys.cpp | 6 +- .../src/simulation/DRAMSysRecordable.cpp | 8 +- DRAMSys/library/src/simulation/dram/Dram.cpp | 4 +- .../src/simulation/dram/DramRecordable.cpp | 8 +- ..._ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json | 51 ++++++++++ .../configs/mcconfigs/fr_fcfs_grp.json | 12 +++ .../MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 62 ++++++++++++ .../configs/simulator/ddr3.json | 19 ++++ .../configs/thermalsim/config.json | 15 +++ .../configs/thermalsim/core.flp | 45 +++++++++ .../configs/thermalsim/mem.flp | 16 ++++ .../configs/thermalsim/powerInfo.json | 20 ++++ .../configs/thermalsim/stack.stk | 49 ++++++++++ .../scripts/createTraceDB.sql | 94 +++++++++++++++++++ .../simulations/ddr3-example.json | 16 ++++ 22 files changed, 427 insertions(+), 33 deletions(-) create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/config.json create mode 100755 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp create mode 100755 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/powerInfo.json create mode 100755 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json diff --git a/DRAMSys/library/src/common/AddressDecoder.cpp b/DRAMSys/library/src/common/AddressDecoder.cpp index b454cec6..02980d4f 100644 --- a/DRAMSys/library/src/common/AddressDecoder.cpp +++ b/DRAMSys/library/src/common/AddressDecoder.cpp @@ -143,10 +143,10 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping) Configuration &config = Configuration::getInstance(); MemSpec *memSpec = config.memSpec; - if (config.numberOfMemChannels != channels || memSpec->numberOfRanks != ranks + if (memSpec->numberOfMemChannels != channels || memSpec->numberOfRanks != ranks || memSpec->numberOfBankGroups != bankgroups || memSpec->numberOfBanks != banks || memSpec->numberOfRows != rows || memSpec->numberOfColumns != columns - || config.numberOfDevicesOnDIMM * memSpec->bitWidth != bytes * 8) + || memSpec->numberOfDevicesOnDIMM * memSpec->bitWidth != bytes * 8) SC_REPORT_FATAL("AddressDecoder", "Memspec and address mapping do not match"); } diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index 3f8462ba..921c8c5c 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -121,20 +121,10 @@ void Configuration::setParameter(std::string name, nlohmann::json value) } else if (name == "Debug") debug = value; - else if (name == "NumberOfMemChannels") - numberOfMemChannels = value; else if (name == "ThermalSimulation") thermalSimulation = value; else if (name == "SimulationProgressBar") simulationProgressBar = value; - else if (name == "NumberOfDevicesOnDIMM") - { - numberOfDevicesOnDIMM = value; - if (numberOfDevicesOnDIMM == 0) - SC_REPORT_FATAL("Configuration", - ("Invalid value for parameter " + name + - ". This parameter must be at least one.").c_str()); - } else if (name == "AddressOffset") { #ifdef DRAMSYS_GEM5 @@ -209,12 +199,13 @@ std::uint64_t Configuration::getSimMemSizeInBytes() std::uint64_t rows = memSpec->numberOfRows; std::uint64_t columns = memSpec->numberOfColumns; std::uint64_t bitWidth = memSpec->bitWidth; + std::uint64_t devicesOnDIMM = memSpec->numberOfDevicesOnDIMM; // 2. Calculate size of one DRAM chip in bits std::uint64_t chipBitSize = banks * rows * columns * bitWidth; // 3. Calculate size of one DRAM chip in bytes std::uint64_t chipSize = chipBitSize / 8; // 4. Total memory size in Bytes of one DIMM (with only support of 1 rank on a DIMM) - std::uint64_t memorySize = chipSize * numberOfDevicesOnDIMM; + std::uint64_t memorySize = chipSize * memSpec->numberOfDevicesOnDIMM; std::cout << headline << std::endl; std::cout << "Per Channel Configuration:" << std::endl << std::endl; @@ -228,7 +219,7 @@ std::uint64_t Configuration::getSimMemSizeInBytes() std::cout << " Chip data bus width: " << bitWidth << std::endl; std::cout << " Chip size in bits: " << chipBitSize << std::endl; std::cout << " Chip Size in bytes: " << chipSize << std::endl; - std::cout << " Devices/Chips on DIMM: " << numberOfDevicesOnDIMM << std::endl; + std::cout << " Devices/Chips on DIMM: " << devicesOnDIMM << std::endl; std::cout << std::endl; assert(memorySize > 0); @@ -241,7 +232,7 @@ std::uint64_t Configuration::getSimMemSizeInBytes() // The bus width is given in bits, e.g., 64-bit data bus, 128-bit data bus, etc. unsigned int Configuration::getDataBusWidth() { - return memSpec->bitWidth * numberOfDevicesOnDIMM; + return memSpec->bitWidth * memSpec->numberOfDevicesOnDIMM; } // Returns the number of bytes transfered in a burst diff --git a/DRAMSys/library/src/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h index af0ffff9..0f850baa 100644 --- a/DRAMSys/library/src/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -88,10 +88,8 @@ public: bool enableWindowing = false; unsigned int windowSize = 1000; bool debug = false; - unsigned int numberOfMemChannels = 1; bool thermalSimulation = false; bool simulationProgressBar = false; - unsigned int numberOfDevicesOnDIMM = 8; bool checkTLM2Protocol = false; std::string ECCMode = "Disabled"; ECCBaseClass *pECC = nullptr; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 3022440c..3d7984f0 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -58,6 +58,10 @@ MemSpec::MemSpec(json &memspec, unsigned numberOfRanks, unsigned banksPerRank, dataRate(parseUint(memspec["memarchitecturespec"]["dataRate"],"dataRate")), bitWidth(parseUint(memspec["memarchitecturespec"]["width"],"width")), fCKMHz(parseUdouble(memspec["memtimingspec"]["clkMhz"], "clkMhz")), + numberOfDevicesOnDIMM(parseUint(memspec["memarchitecturespec"]["NumberOfDevicesOnDIMM"], + "numberOfDevicesOnDIMM")), + numberOfMemChannels(parseUint(memspec["memarchitecturespec"]["NumberOfMemChannels"], + "NumberOfMemChannels")), tCK(sc_time(1.0 / fCKMHz, SC_US)), burstDuration(tCK * (burstLength / dataRate)), memoryId(parseString(memspec["memoryId"], "memoryId")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 37185107..afa311e4 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -59,6 +59,8 @@ public: unsigned burstLength; unsigned dataRate; unsigned bitWidth; + unsigned int numberOfDevicesOnDIMM; + unsigned int numberOfMemChannels; // Clock double fCKMHz; diff --git a/DRAMSys/library/src/controller/ControllerIF.h b/DRAMSys/library/src/controller/ControllerIF.h index fbcf969f..965697c2 100644 --- a/DRAMSys/library/src/controller/ControllerIF.h +++ b/DRAMSys/library/src/controller/ControllerIF.h @@ -35,7 +35,7 @@ public: // BusWidth e.g. 8 or 64 * Configuration::getInstance().memSpec->bitWidth // Number of devices on a DIMM e.g. 8 - * Configuration::getInstance().numberOfDevicesOnDIMM ) / ( 1024 ); + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM ) / ( 1024 ); std::cout << name() << std::string(" Total Time: ") << sc_time_stamp().to_string() diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 098c6013..6b6c061b 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -49,7 +49,7 @@ Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) : // Anytime an transaction comes from a memory unity to the arbiter the "bw" callback is called. iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw); - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; ++i) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; ++i) { channelIsFree.push_back(true); pendingRequests.push_back(std::queue()); @@ -130,7 +130,7 @@ void Arbiter::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) // Check the valid range of thread ID and channel Id // TODO: thread ID not checked - assert(channelId < Configuration::getInstance().numberOfMemChannels); + assert(channelId < Configuration::getInstance().memSpec->numberOfMemChannels); // Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter) if (phase == BEGIN_REQ) diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index b210438d..7a9d8b8f 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -192,7 +192,7 @@ void DRAMSys::instantiateModules(const std::string &pathToResources, // Create controllers and DRAMs std::string memoryType = Configuration::getInstance().memSpec->memoryType; - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) { std::string str = "controller" + std::to_string(i); @@ -251,7 +251,7 @@ void DRAMSys::bindSockets() if (Configuration::getInstance().checkTLM2Protocol) { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket); @@ -260,7 +260,7 @@ void DRAMSys::bindSockets() } else { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) { arbiter->iSocket.bind(controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index 60e4dbd9..b55180a5 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -91,7 +91,7 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName, const std::string &pathToResources) { // Create TLM Recorders, one per channel. - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) { std::string sqlScriptURI = pathToResources + std::string("scripts/createTraceDB.sql"); @@ -140,7 +140,7 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName, // Create controllers and DRAMs std::string memoryType = Configuration::getInstance().memSpec->memoryType; - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) { std::string str = "controller" + std::to_string(i); @@ -199,7 +199,7 @@ void DRAMSysRecordable::bindSockets() if (Configuration::getInstance().checkTLM2Protocol) { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket); @@ -208,7 +208,7 @@ void DRAMSysRecordable::bindSockets() } else { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) { arbiter->iSocket.bind(controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index 16a76f98..845cbfbe 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -129,14 +129,14 @@ void Dram::reportPower() std::cout << name() << std::string(" Total Energy: ") << std::fixed << std::setprecision( 2 ) << DRAMPower->getEnergy().total_energy - * Configuration::getInstance().numberOfDevicesOnDIMM + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM << std::string(" pJ") << std::endl; std::cout << name() << std::string(" Average Power: ") << std::fixed << std::setprecision( 2 ) << DRAMPower->getPower().average_power - * Configuration::getInstance().numberOfDevicesOnDIMM + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM << std::string(" mW") << std::endl; } } diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index c2319ddb..96f2ddc2 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -67,7 +67,7 @@ void DramRecordable::reportPower() BaseDram::reportPower(); tlmRecorder->recordPower(sc_time_stamp().to_seconds(), this->DRAMPower->getPower().window_average_power - * Configuration::getInstance().numberOfDevicesOnDIMM); + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM); } template @@ -132,15 +132,15 @@ void DramRecordable::powerWindow() // Store the time (in seconds) and the current average power (in mW) into the database tlmRecorder->recordPower(sc_time_stamp().to_seconds(), this->DRAMPower->getPower().window_average_power - * Configuration::getInstance().numberOfDevicesOnDIMM); + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM); // Here considering that DRAMPower provides the energy in pJ and the power in mW PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Energy: \t") + std::to_string( this->DRAMPower->getEnergy().window_energy * - Configuration::getInstance().numberOfDevicesOnDIMM) + std::string("\t[pJ]")); + Configuration::getInstance().memSpec->numberOfDevicesOnDIMM) + std::string("\t[pJ]")); PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Average Power: \t") + std::to_string( this->DRAMPower->getPower().window_average_power * - Configuration::getInstance().numberOfDevicesOnDIMM) + std::string("\t[mW]")); + Configuration::getInstance().memSpec->numberOfDevicesOnDIMM) + std::string("\t[mW]")); } while (true); } diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json new file mode 100644 index 00000000..c82926c9 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json @@ -0,0 +1,51 @@ +{ + "CONGEN": { + "XOR":[ + { + "FIRST":13, + "SECOND":16 + } + ], + "BANK_BIT": [ + 13, + 14, + 15 + ], + "BYTE_BIT": [ + 0, + 1, + 2 + ], + "COLUMN_BIT": [ + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12 + ], + "ROW_BIT": [ + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29 + ], + "RANK_BIT": [ + 30 + ] + } +} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json new file mode 100644 index 00000000..4ac02e30 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json @@ -0,0 +1,12 @@ +{"mcconfig": + {"PagePolicy": "Open", + "Scheduler": "FrFcfsGrp", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "Rankwise", + "RefreshMode": 1, + "RefreshMaxPostponed": 0, + "RefreshMaxPulledin": 0, + "PowerDownPolicy": "Staggered", + "PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json new file mode 100644 index 00000000..d842bda2 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -0,0 +1,62 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 8, + "dataRate": 2, + "nbrOfBanks": 8, + "nbrOfColumns": 1024, + "nbrOfRanks": 2, + "nbrOfRows": 16384, + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 + }, + "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", + "memoryType": "DDR3", + "mempowerspec": { + "idd0": 720.0, + "idd2n": 400.0, + "idd2p0": 80.0, + "idd2p1": 200.0, + "idd3n": 440.0, + "idd3p0": 240.0, + "idd3p1": 240.0, + "idd4r": 1200.0, + "idd4w": 1200.0, + "idd5": 1760.0, + "idd6": 48.0, + "vdd": 1.5 + }, + "memtimingspec": { + "AL": 0, + "CCD": 4, + "CKE": 3, + "CKESR": 4, + "CL": 7, + "DQSCK": 0, + "FAW": 20, + "RAS": 20, + "RC": 27, + "RCD": 7, + "REFI": 4160, + "RFC": 59, + "RL": 7, + "RP": 7, + "RRD": 4, + "RTP": 4, + "WL": 6, + "WR": 8, + "WTR": 4, + "XP": 4, + "XPDLL": 13, + "XS": 64, + "XSDLL": 512, + "clkMhz": 533, + + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1 + } + } +} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json new file mode 100644 index 00000000..99ccdb45 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json @@ -0,0 +1,19 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "PowerAnalysis": false, + "SimulationName": "ddr3", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/config.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/config.json new file mode 100644 index 00000000..b88ed84c --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/config.json @@ -0,0 +1,15 @@ +{ + "thermalsimconfig": { + "TemperatureScale": "Celsius", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, + "ThermalSimUnit":"us", + "PowerInfoFile": "powerInfo.json", + "IceServerIp": "127.0.0.1", + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true + } +} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp new file mode 100755 index 00000000..e85e6801 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp @@ -0,0 +1,45 @@ +CPUs : + + position 0, 0 ; + dimension 2750, 4300 ; + +GPU : + + position 3350, 0 ; + dimension 2750, 4000 ; + +BASEBAND1 : + + position 4250, 4000 ; + dimension 1850, 3300 ; + +BASEBAND2 : + + position 3350, 7300 ; + dimension 2750, 3300 ; + +LLCACHE : + + position 0, 4300 ; + dimension 1900, 3000 ; + +DRAMCTRL1 : + + position 1900, 4300 ; + dimension 850, 3000 ; + +DRAMCTRL2 : + + position 3350, 4000 ; + dimension 900, 3300 ; + +TSVS : + + position 2750, 2300 ; + dimension 600, 6000 ; + +ACELLERATORS : + + position 0, 7300 ; + dimension 2750, 3300 ; + diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp new file mode 100755 index 00000000..29d02254 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp @@ -0,0 +1,16 @@ +channel0 : + position 150, 100 ; + dimension 2600, 5200 ; + +channel1 : + position 3350, 100 ; + dimension 2600, 5200 ; + +channel2 : + position 150, 5300 ; + dimension 2600, 5200 ; + +channel3 : + position 3350, 5300 ; + dimension 2600, 5200 ; + diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/powerInfo.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/powerInfo.json new file mode 100644 index 00000000..524f690f --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/powerInfo.json @@ -0,0 +1,20 @@ +{ + "powerInfo": { + "dram_die_channel0": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel1": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel2": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel3": { + "init_pow": 0, + "threshold": 1.0 + } + } +} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk new file mode 100755 index 00000000..ec74f020 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk @@ -0,0 +1,49 @@ +material SILICON : + thermal conductivity 1.30e-4 ; + volumetric heat capacity 1.628e-12 ; + +material BEOL : + thermal conductivity 2.25e-6 ; + volumetric heat capacity 2.175e-12 ; + +material COPPER : + thermal conductivity 4.01e-04 ; + volumetric heat capacity 3.37e-12 ; + +top heat sink : + //sink height 1e03, area 100e06, material COPPER ; + //spreader height 0.5e03, area 70e06, material SILICON ; + heat transfer coefficient 1.3e-09 ; + temperature 318.15 ; +dimensions : + chip length 6100, width 10600 ; + cell length 100, width 100 ; + + +layer PCB : + height 10 ; + material BEOL ; + +die DRAM : + layer 58.5 SILICON ; + source 2 SILICON ; + layer 1.5 BEOL ; + layer 58.5 SILICON ; + + +stack: + die DRAM_DIE DRAM floorplan "./mem.flp" ; + layer CONN_TO_PCB PCB ; + +solver: + transient step 0.01, slot 0.05 ; + initial temperature 300.0 ; + +output: + Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); + Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); + Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); + Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); + Tmap (DRAM_DIE, "output1.txt", slot) ; + Pmap (DRAM_DIE, "output2.txt", slot) ; + diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql b/DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql new file mode 100644 index 00000000..7a127fac --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql @@ -0,0 +1,94 @@ +DROP TABLE IF EXISTS Phases; +DROP TABLE IF EXISTS GeneralInfo; +DROP TABLE IF EXISTS CommandLengths; +DROP TABLE IF EXISTS Comments; +DROP TABLE IF EXISTS ranges; +DROP TABLE IF EXISTS Transactions; +DROP TABLE IF EXISTS DebugMessages; +DROP TABLE IF EXISTS Power; + +CREATE TABLE Phases( + ID INTEGER PRIMARY KEY, + PhaseName TEXT, + PhaseBegin INTEGER, + PhaseEnd INTEGER, + Transact INTEGER +); + +CREATE TABLE GeneralInfo( + NumberOfTransactions INTEGER, + TraceEnd INTEGER, + NumberOfRanks INTEGER, + NumberOfBanks INTEGER, + clk INTEGER, + UnitOfTime TEXT, + MCconfig TEXT, + Memspec TEXT, + Traces TEXT, + WindowSize INTEGER, + FlexibleRefresh INTEGER, + MaxRefBurst INTEGER, + ControllerThread INTEGER +); + +CREATE TABLE CommandLengths( + ACT INTEGER, + PRE INTEGER, + PREA INTEGER, + RD INTEGER, + RDA INTEGER, + WR INTEGER, + WRA INTEGER, + REFA INTEGER, + REFB INTEGER, + PDEA INTEGER, + PDXA INTEGER, + PDEP INTEGER, + PDXP INTEGER, + SREFEN INTEGER, + SREFEX INTEGER +); + +CREATE TABLE Power( + time DOUBLE, + AveragePower DOUBLE +); + + +CREATE TABLE Comments( + Time INTEGER, + Text TEXT +); + +CREATE TABLE DebugMessages( + Time INTEGER, + Message TEXT +); + +-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) +CREATE VIRTUAL TABLE ranges USING rtree( + id, + begin, end +); + +CREATE TABLE Transactions( + ID INTEGER, + Range INTEGER, + Address INTEGER, + Burstlength INTEGER, + TThread INTEGER, + TChannel INTEGER, + TRank INTEGER, + TBankgroup INTEGER, + TBank INTEGER, + TRow INTEGER, + TColumn INTEGER, + DataStrobeBegin INTEGER, + DataStrobeEnd INTEGER, + TimeOfGeneration INTEGER, + Command TEXT + ); + +CREATE INDEX ranges_index ON Transactions(Range); +CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); +CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json b/DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json new file mode 100644 index 00000000..e3d4a4c3 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json @@ -0,0 +1,16 @@ +{ + "simulation": { + "addressmapping": "am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json", + "mcconfig": "fr_fcfs_grp.json", + "memspec": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json", + "simconfig": "ddr3.json", + "simulationid": "ddr3-example-dual-rank-json", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 533, + "name": "trace_test2.stl" + } + ] + } +} From 4265ecc3c701c803df45dac19a9c48429b615ab6 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 16 Jun 2020 10:53:43 +0200 Subject: [PATCH 04/53] Adapted memspecs to nbrOfChannels and nbrOfDevicesOnDIMM. --- DRAMSys/library/CMakeLists.txt | 3 +++ DRAMSys/library/src/common/AddressDecoder.cpp | 2 +- .../src/configuration/memspec/MemSpec.cpp | 18 +++++++++--------- .../src/configuration/memspec/MemSpec.h | 10 ++++++---- .../src/configuration/memspec/MemSpecDDR3.cpp | 4 +++- .../src/configuration/memspec/MemSpecDDR4.cpp | 4 +++- .../src/configuration/memspec/MemSpecGDDR5.cpp | 4 +++- .../configuration/memspec/MemSpecGDDR5X.cpp | 4 +++- .../src/configuration/memspec/MemSpecGDDR6.cpp | 4 +++- .../src/configuration/memspec/MemSpecHBM2.cpp | 4 +++- .../configuration/memspec/MemSpecLPDDR4.cpp | 4 +++- .../configuration/memspec/MemSpecWideIO.cpp | 4 +++- .../configuration/memspec/MemSpecWideIO2.cpp | 4 +++- DRAMSys/library/src/simulation/Arbiter.cpp | 4 ++-- DRAMSys/library/src/simulation/DRAMSys.cpp | 6 +++--- .../src/simulation/DRAMSysRecordable.cpp | 8 ++++---- DRAMSys/tests/HBM2/configs/memspecs/HBM2.json | 1 + DRAMSys/tests/HBM2/configs/simulator/hbm2.json | 2 -- .../MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 8 +++++++- .../ddr3_multirank/configs/simulator/ddr3.json | 2 -- .../memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json | 4 +++- .../configs/simulator/ddr4.json | 2 -- .../memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json | 4 ++++ .../tests/lpddr4/configs/simulator/lpddr4.json | 2 -- 24 files changed, 70 insertions(+), 42 deletions(-) diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index 0b828857..d15862ed 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -172,6 +172,7 @@ add_library(DRAMSysLibrary resources/simulations/lpddr4-example.json resources/simulations/ranktest.json resources/simulations/wideio-example.json + resources/simulations/wideio-thermal.json # Address Mapping Config Files resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.json @@ -266,9 +267,11 @@ add_library(DRAMSysLibrary resources/configs/simulator/hbm2.json resources/configs/simulator/lpddr4.json resources/configs/simulator/wideio.json + resources/configs/simulator/wideio_thermal.json # Thermal Simulation Config Files resources/configs/thermalsim/config.json + resources/configs/thermalsim/powerInfo.json # Trace Files resources/traces/test_ecc.stl diff --git a/DRAMSys/library/src/common/AddressDecoder.cpp b/DRAMSys/library/src/common/AddressDecoder.cpp index 02980d4f..33e920c9 100644 --- a/DRAMSys/library/src/common/AddressDecoder.cpp +++ b/DRAMSys/library/src/common/AddressDecoder.cpp @@ -143,7 +143,7 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping) Configuration &config = Configuration::getInstance(); MemSpec *memSpec = config.memSpec; - if (memSpec->numberOfMemChannels != channels || memSpec->numberOfRanks != ranks + if (memSpec->numberOfChannels != channels || memSpec->numberOfRanks != ranks || memSpec->numberOfBankGroups != bankgroups || memSpec->numberOfBanks != banks || memSpec->numberOfRows != rows || memSpec->numberOfColumns != columns || memSpec->numberOfDevicesOnDIMM * memSpec->bitWidth != bytes * 8) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 3d7984f0..4cae3c73 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -43,29 +43,29 @@ using namespace tlm; using json = nlohmann::json; -MemSpec::MemSpec(json &memspec, unsigned numberOfRanks, unsigned banksPerRank, +MemSpec::MemSpec(json &memspec, unsigned numberOfChannels, + unsigned numberOfRanks, unsigned banksPerRank, unsigned groupsPerRank, unsigned banksPerGroup, - unsigned numberOfBanks, unsigned numberOfBankGroups) - : numberOfRanks(numberOfRanks), + unsigned numberOfBanks, unsigned numberOfBankGroups, + unsigned numberOfDevicesOnDIMM) + : numberOfChannels(numberOfChannels), + numberOfRanks(numberOfRanks), banksPerRank(banksPerRank), groupsPerRank(groupsPerRank), banksPerGroup(banksPerGroup), numberOfBanks(numberOfBanks), numberOfBankGroups(numberOfBankGroups), + numberOfDevicesOnDIMM(numberOfDevicesOnDIMM), numberOfRows(parseUint(memspec["memarchitecturespec"]["nbrOfRows"],"nbrOfRows")), numberOfColumns(parseUint(memspec["memarchitecturespec"]["nbrOfColumns"],"nbrOfColumns")), burstLength(parseUint(memspec["memarchitecturespec"]["burstLength"],"burstLength")), dataRate(parseUint(memspec["memarchitecturespec"]["dataRate"],"dataRate")), bitWidth(parseUint(memspec["memarchitecturespec"]["width"],"width")), fCKMHz(parseUdouble(memspec["memtimingspec"]["clkMhz"], "clkMhz")), - numberOfDevicesOnDIMM(parseUint(memspec["memarchitecturespec"]["NumberOfDevicesOnDIMM"], - "numberOfDevicesOnDIMM")), - numberOfMemChannels(parseUint(memspec["memarchitecturespec"]["NumberOfMemChannels"], - "NumberOfMemChannels")), tCK(sc_time(1.0 / fCKMHz, SC_US)), - burstDuration(tCK * (burstLength / dataRate)), memoryId(parseString(memspec["memoryId"], "memoryId")), - memoryType(parseString(memspec["memoryType"], "memoryType")) + memoryType(parseString(memspec["memoryType"], "memoryType")), + burstDuration(tCK * (burstLength / dataRate)) { commandLengthInCycles = std::vector(numberOfCommands(), 1); } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index afa311e4..785e52d7 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -48,19 +48,19 @@ class MemSpec { public: + unsigned numberOfChannels; unsigned numberOfRanks; unsigned banksPerRank; unsigned groupsPerRank; unsigned banksPerGroup; unsigned numberOfBanks; unsigned numberOfBankGroups; + unsigned numberOfDevicesOnDIMM; unsigned numberOfRows; unsigned numberOfColumns; unsigned burstLength; unsigned dataRate; unsigned bitWidth; - unsigned int numberOfDevicesOnDIMM; - unsigned int numberOfMemChannels; // Clock double fCKMHz; @@ -80,9 +80,11 @@ public: sc_time getCommandLength(Command) const; protected: - MemSpec(nlohmann::json &memspec, unsigned numberOfRanks, unsigned banksPerRank, + MemSpec(nlohmann::json &memspec, unsigned numberOfChannels, + unsigned numberOfRanks, unsigned banksPerRank, unsigned groupsPerRank, unsigned banksPerGroup, - unsigned numberOfBanks, unsigned numberOfBankGroups); + unsigned numberOfBanks, unsigned numberOfBankGroups, + unsigned numberOfDevicesOnDIMM); // Command lengths in cycles on bus, usually one clock cycle std::vector commandLengthInCycles; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 387ec6be..52fed95d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -40,13 +40,15 @@ using json = nlohmann::json; MemSpecDDR3::MemSpecDDR3(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), 1, parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + parseUint(memspec["memarchitecturespec"]["nbrOfDevicesOnDIMM"],"nbrOfDevicesOnDIMM")), tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), tPD (tCKE), tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index 5078ca0e..9e38241e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -41,6 +41,7 @@ using json = nlohmann::json; MemSpecDDR4::MemSpecDDR4(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -49,7 +50,8 @@ MemSpecDDR4::MemSpecDDR4(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + parseUint(memspec["memarchitecturespec"]["nbrOfDevicesOnDIMM"],"nbrOfDevicesOnDIMM")), tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), tPD (tCKE), tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp index 66bd7f7c..0572099a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp @@ -40,6 +40,7 @@ using json = nlohmann::json; MemSpecGDDR5::MemSpecGDDR5(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -48,7 +49,8 @@ MemSpecGDDR5::MemSpecGDDR5(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp index a2897967..90908bd9 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp @@ -40,6 +40,7 @@ using json = nlohmann::json; MemSpecGDDR5X::MemSpecGDDR5X(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -48,7 +49,8 @@ MemSpecGDDR5X::MemSpecGDDR5X(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp index 636a3351..b9a70d10 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp @@ -40,6 +40,7 @@ using json = nlohmann::json; MemSpecGDDR6::MemSpecGDDR6(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -48,7 +49,8 @@ MemSpecGDDR6::MemSpecGDDR6(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index c8afaa93..da1d77b1 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -40,6 +40,7 @@ using json = nlohmann::json; MemSpecHBM2::MemSpecHBM2(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -48,7 +49,8 @@ MemSpecHBM2::MemSpecHBM2(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index c16f9b50..6716744f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -40,13 +40,15 @@ using json = nlohmann::json; MemSpecLPDDR4::MemSpecLPDDR4(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), 1, parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")), tREFIpb (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")), tRFCab (tCK * parseUint(memspec["memtimingspec"]["RFCAB"], "RFCAB")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index ecbcb202..e4ccfadb 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -40,13 +40,15 @@ using json = nlohmann::json; MemSpecWideIO::MemSpecWideIO(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), 1, parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp index 91e27078..2f07fdcd 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -40,13 +40,15 @@ using json = nlohmann::json; MemSpecWideIO2::MemSpecWideIO2(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), 1, parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), tDQSS (tCK * parseUint(memspec["memtimingspec"]["DQSS"], "DQSS")), tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 6b6c061b..6a74396d 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -49,7 +49,7 @@ Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) : // Anytime an transaction comes from a memory unity to the arbiter the "bw" callback is called. iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw); - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; ++i) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; ++i) { channelIsFree.push_back(true); pendingRequests.push_back(std::queue()); @@ -130,7 +130,7 @@ void Arbiter::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) // Check the valid range of thread ID and channel Id // TODO: thread ID not checked - assert(channelId < Configuration::getInstance().memSpec->numberOfMemChannels); + assert(channelId < Configuration::getInstance().memSpec->numberOfChannels); // Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter) if (phase == BEGIN_REQ) diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 7a9d8b8f..5991560b 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -192,7 +192,7 @@ void DRAMSys::instantiateModules(const std::string &pathToResources, // Create controllers and DRAMs std::string memoryType = Configuration::getInstance().memSpec->memoryType; - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { std::string str = "controller" + std::to_string(i); @@ -251,7 +251,7 @@ void DRAMSys::bindSockets() if (Configuration::getInstance().checkTLM2Protocol) { - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket); @@ -260,7 +260,7 @@ void DRAMSys::bindSockets() } else { - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index b55180a5..c799d8c1 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -91,7 +91,7 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName, const std::string &pathToResources) { // Create TLM Recorders, one per channel. - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { std::string sqlScriptURI = pathToResources + std::string("scripts/createTraceDB.sql"); @@ -140,7 +140,7 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName, // Create controllers and DRAMs std::string memoryType = Configuration::getInstance().memSpec->memoryType; - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { std::string str = "controller" + std::to_string(i); @@ -199,7 +199,7 @@ void DRAMSysRecordable::bindSockets() if (Configuration::getInstance().checkTLM2Protocol) { - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket); @@ -208,7 +208,7 @@ void DRAMSysRecordable::bindSockets() } else { - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); diff --git a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json index efa8ee9e..7cf4004b 100644 --- a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json +++ b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json @@ -7,6 +7,7 @@ "nbrOfBanks": 16, "nbrOfColumns": 128, "nbrOfRanks": 2, + "nbrOfChannels": 1, "nbrOfRows": 32768, "width": 64 }, diff --git a/DRAMSys/tests/HBM2/configs/simulator/hbm2.json b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json index 9589611f..e6affb0b 100644 --- a/DRAMSys/tests/HBM2/configs/simulator/hbm2.json +++ b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "hbm2", "SimulationProgressBar": true, diff --git a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json index 13d9fef5..08e13043 100644 --- a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -6,8 +6,10 @@ "nbrOfBanks": 8, "nbrOfColumns": 1024, "nbrOfRanks": 2, + "nbrOfChannels": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", "memoryType": "DDR3", @@ -49,6 +51,10 @@ "XPDLL": 13, "XS": 64, "XSDLL": 512, + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1, "clkMhz": 533 } } diff --git a/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json index 4e9faadc..99ccdb45 100644 --- a/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json +++ b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "ddr3", "SimulationProgressBar": true, diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json index 11700aaf..adbfd117 100644 --- a/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -7,8 +7,10 @@ "nbrOfBanks": 16, "nbrOfColumns": 1024, "nbrOfRanks": 1, + "nbrOfChannels": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json b/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json index 8e62e680..81b72d43 100644 --- a/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json +++ b/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "ddr4", "SimulationProgressBar": true, diff --git a/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json index 97a8cc3e..223f064d 100644 --- a/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json +++ b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json @@ -6,6 +6,7 @@ "nbrOfBanks": 8, "nbrOfColumns": 1024, "nbrOfRanks": 1, + "nbrOfChannels": 1, "nbrOfRows": 65536, "width": 16 }, @@ -30,6 +31,8 @@ "RL": 28, "RPAB": 34, "RPPB": 29, + "RCAB": 102, + "RCPB": 97, "RPST": 0, "RRD": 16, "RTP": 12, @@ -40,6 +43,7 @@ "WTR": 16, "XP": 12, "XSR": 460, + "RTRS": 1, "clkMhz": 1600 } } diff --git a/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json index fd8fe855..0fae8a52 100644 --- a/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json +++ b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "lpddr4", "SimulationProgressBar": true, From b2b70d3771a412bde69fab0651613824bb894b88 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 16 Jun 2020 11:25:49 +0200 Subject: [PATCH 05/53] ci and test files modified/some old tests deleted --- .gitlab-ci_old.yml | 56 +++++++++++ DRAMSys/tests/DDR3/ci.yml | 83 ---------------- .../am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml | 34 ------- .../DDR3/configs/mcconfigs/fifoStrict.xml | 20 ---- .../tests/DDR3/configs/mcconfigs/fr_fcfs.xml | 20 ---- .../memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml | 55 ----------- .../simulator/ddr3-protocol_checker.xml | 29 ------ DRAMSys/tests/DDR3/configs/simulator/ddr3.xml | 29 ------ .../tests/DDR3/configs/thermalsim/config.xml | 14 --- .../DDR3/configs/thermalsim/powerInfo.xml | 8 -- .../tests/DDR3/simulations/ddr3-example.xml | 25 ----- .../tests/DDR3/simulations/ddr3-fr_fcfs.xml | 25 ----- .../simulations/ddr3-protocol_checker.xml | 25 ----- DRAMSys/tests/DDR4/ci.yml | 29 ++++++ .../am_ddr4_8x4Gbx8_dimm_p1KB_brc.json | 0 .../configs/mcconfigs/fr_fcfs.json | 0 .../memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json | 6 +- .../configs/simulator/ddr4.json | 4 +- .../configs/thermalsim/config.json | 0 .../configs/thermalsim/core.flp | 0 .../{DDR3 => DDR4}/configs/thermalsim/mem.flp | 0 .../configs/thermalsim/powerInfo.json | 0 .../configs/thermalsim/stack.stk | 0 .../{DDR3 => DDR4}/scripts/createTraceDB.sql | 0 .../simulations/ddr4-example.json | 0 DRAMSys/tests/HBM2/ci.yml | 29 ++++++ DRAMSys/tests/HBM2/configs/memspecs/HBM2.json | 6 +- .../tests/HBM2/configs/simulator/hbm2.json | 4 +- DRAMSys/tests/WIDEIO/ci.yml | 40 -------- .../configs/amconfigs/am_wideio_brc.xml | 8 -- .../configs/amconfigs/am_wideio_rbc.xml | 8 -- .../WIDEIO/configs/mcconfigs/fifoStrict.xml | 50 ---------- .../tests/WIDEIO/configs/memspecs/wideio.xml | 61 ------------ .../tests/WIDEIO/configs/simulator/wideio.xml | 24 ----- .../WIDEIO/configs/thermalsim/config.xml | 14 --- .../tests/WIDEIO/configs/thermalsim/core.flp | 45 --------- .../tests/WIDEIO/configs/thermalsim/mem.flp | 16 ---- .../WIDEIO/configs/thermalsim/powerInfo.xml | 8 -- .../tests/WIDEIO/configs/thermalsim/stack.stk | 49 ---------- .../tests/WIDEIO/scripts/createTraceDB.sql | 94 ------------------- .../WIDEIO/simulations/wideio-example.xml | 24 ----- DRAMSys/tests/WIDEIO/traces/generator.pl | 75 --------------- DRAMSys/tests/ddr3_multirank/ci.yml | 29 ++++++ .../MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 11 ++- .../configs/simulator/ddr3.json | 2 - .../simulations/ddr3-example.json | 2 +- ..._ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json | 51 ---------- .../configs/mcconfigs/fr_fcfs_grp.json | 12 --- .../MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 62 ------------ .../configs/simulator/ddr3.json | 19 ---- .../configs/thermalsim/core.flp | 45 --------- .../configs/thermalsim/mem.flp | 16 ---- .../configs/thermalsim/stack.stk | 49 ---------- .../scripts/createTraceDB.sql | 94 ------------------- .../simulations/ddr3-example.json | 16 ---- .../configs/thermalsim/config.json | 15 --- .../configs/thermalsim/core.flp | 45 --------- .../configs/thermalsim/mem.flp | 16 ---- .../configs/thermalsim/powerInfo.json | 20 ---- .../configs/thermalsim/stack.stk | 49 ---------- .../ddr4_bankgroups/scripts/createTraceDB.sql | 94 ------------------- DRAMSys/tests/lpddr4/ci.yml | 28 ++++++ .../memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json | 10 +- .../lpddr4/configs/simulator/lpddr4.json | 4 +- 64 files changed, 200 insertions(+), 1506 deletions(-) create mode 100644 .gitlab-ci_old.yml delete mode 100644 DRAMSys/tests/DDR3/ci.yml delete mode 100644 DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml delete mode 100644 DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml delete mode 100644 DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml delete mode 100644 DRAMSys/tests/DDR3/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml delete mode 100644 DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml delete mode 100644 DRAMSys/tests/DDR3/configs/simulator/ddr3.xml delete mode 100644 DRAMSys/tests/DDR3/configs/thermalsim/config.xml delete mode 100644 DRAMSys/tests/DDR3/configs/thermalsim/powerInfo.xml delete mode 100644 DRAMSys/tests/DDR3/simulations/ddr3-example.xml delete mode 100644 DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml delete mode 100644 DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml create mode 100644 DRAMSys/tests/DDR4/ci.yml rename DRAMSys/tests/{ddr4_bankgroups => DDR4}/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json (100%) rename DRAMSys/tests/{ddr4_bankgroups => DDR4}/configs/mcconfigs/fr_fcfs.json (100%) rename DRAMSys/tests/{ddr4_bankgroups => DDR4}/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json (94%) rename DRAMSys/tests/{ddr4_bankgroups => DDR4}/configs/simulator/ddr4.json (87%) rename DRAMSys/tests/{ddr3_parametersAtMemspec => DDR4}/configs/thermalsim/config.json (100%) rename DRAMSys/tests/{DDR3 => DDR4}/configs/thermalsim/core.flp (100%) rename DRAMSys/tests/{DDR3 => DDR4}/configs/thermalsim/mem.flp (100%) rename DRAMSys/tests/{ddr3_parametersAtMemspec => DDR4}/configs/thermalsim/powerInfo.json (100%) rename DRAMSys/tests/{DDR3 => DDR4}/configs/thermalsim/stack.stk (100%) rename DRAMSys/tests/{DDR3 => DDR4}/scripts/createTraceDB.sql (100%) rename DRAMSys/tests/{ddr4_bankgroups => DDR4}/simulations/ddr4-example.json (100%) create mode 100644 DRAMSys/tests/HBM2/ci.yml delete mode 100644 DRAMSys/tests/WIDEIO/ci.yml delete mode 100755 DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml delete mode 100755 DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml delete mode 100644 DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml delete mode 100644 DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml delete mode 100644 DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml delete mode 100644 DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml delete mode 100755 DRAMSys/tests/WIDEIO/configs/thermalsim/core.flp delete mode 100755 DRAMSys/tests/WIDEIO/configs/thermalsim/mem.flp delete mode 100644 DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml delete mode 100755 DRAMSys/tests/WIDEIO/configs/thermalsim/stack.stk delete mode 100644 DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql delete mode 100644 DRAMSys/tests/WIDEIO/simulations/wideio-example.xml delete mode 100644 DRAMSys/tests/WIDEIO/traces/generator.pl create mode 100644 DRAMSys/tests/ddr3_multirank/ci.yml delete mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json delete mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json delete mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json delete mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json delete mode 100755 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp delete mode 100755 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp delete mode 100755 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk delete mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql delete mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json delete mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json delete mode 100755 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp delete mode 100755 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp delete mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json delete mode 100755 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk delete mode 100644 DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql create mode 100644 DRAMSys/tests/lpddr4/ci.yml diff --git a/.gitlab-ci_old.yml b/.gitlab-ci_old.yml new file mode 100644 index 00000000..9011e4ab --- /dev/null +++ b/.gitlab-ci_old.yml @@ -0,0 +1,56 @@ +# vim: set ts=4 sw=4 expandtab: +image: gcc + +variables: + GIT_STRATEGY: clone + +stages: + - build + - dramsys-gem5-build + - WIDEIO + - DDR3 + - Coverage + +build: + stage: build + script: + - git submodule sync + - git submodule update --init --recursive + - rm -rf build + - mkdir -p build + - cd build + - cmake ../DRAMSys + - make -j16 + - find . -name "*.o" -type f -delete + - rm -rf ${CI_PROJECT_DIR}/coverage + - mkdir -p ${CI_PROJECT_DIR}/coverage + + cache: + key: build + paths: + - build/ + policy: push + + artifacts: + paths: + - coverage/ + +coverage: + stage: Coverage + coverage: '/Total:\|(\d+\.?\d+\%)/' + script: + # delete all empty files since they produce errors + - find coverage -size 0 -type f -delete + - ls coverage/ -lah + - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out + - lcov --list coverage/final.out + + artifacts: + paths: + - coverage/final.out + + +include: + - '/DRAMSys/tests/DDR3/ci.yml' + - '/DRAMSys/tests/WIDEIO/ci.yml' + #- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used diff --git a/DRAMSys/tests/DDR3/ci.yml b/DRAMSys/tests/DDR3/ci.yml deleted file mode 100644 index a5afa603..00000000 --- a/DRAMSys/tests/DDR3/ci.yml +++ /dev/null @@ -1,83 +0,0 @@ -# Standard DDR3 Test: -example_ddr3: - stage: DDR3 - script: - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-example.xml ../../DRAMSys/tests/DDR3/ - - ls -lah - - ls -lah ../../DRAMSys/tests/DDR3/expected/ - - sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb - - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3-example_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - # Run Code Coverage - - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out - - cache: - key: build - paths: - - build/ - policy: pull - - artifacts: - paths: - - build/simulator/ddr3-example_ddr3_ch0.tdb - - coverage/${CI_JOB_NAME}.out - expire_in: 2 days - -# Testing Reordering with FR_FCFS Scheduling Algorithm: -fr_fcfs: - stage: DDR3 - script: - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml ../../DRAMSys/tests/DDR3/ - - ls -lah - - ls -lah ../../DRAMSys/tests/DDR3/expected/ - - sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-fr_fcfs_ddr3_ch0.tdb ddr3-fr_fcfs_ddr3_ch0.tdb - - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-fr_fcfs_ddr3_ch0.tdb ddr3-fr_fcfs_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3-fr_fcfs_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - # Run Code Coverage - - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out - - cache: - key: build - paths: - - build/ - policy: pull - - allow_failure: true # TODO should be removed after first tests - - artifacts: - paths: - - build/simulator/ddr3-fr_fcfs_ddr3_ch0.tdb - - coverage/${CI_JOB_NAME}.out - expire_in: 2 days - -# Testing with TLM Protocol Checker -protocol_checker: - stage: DDR3 - script: - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml ../../DRAMSys/tests/DDR3/ > output.txt - - echo "TODO" - - ls -lah - # Run Code Coverage - - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out - - cache: - key: build - paths: - - build/ - policy: pull - - artifacts: - paths: - - coverage/${CI_JOB_NAME}.out - expire_in: 2 days diff --git a/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml b/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml deleted file mode 100644 index b2c3af48..00000000 --- a/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml +++ /dev/null @@ -1,34 +0,0 @@ - - - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - - \ No newline at end of file diff --git a/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml b/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml deleted file mode 100644 index 44bf294e..00000000 --- a/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml +++ /dev/null @@ -1,20 +0,0 @@ - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml b/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml deleted file mode 100644 index 7240485d..00000000 --- a/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml +++ /dev/null @@ -1,20 +0,0 @@ - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml b/DRAMSys/tests/DDR3/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml deleted file mode 100644 index 052f6773..00000000 --- a/DRAMSys/tests/DDR3/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml +++ /dev/null @@ -1,55 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml b/DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml deleted file mode 100644 index 3efbabe7..00000000 --- a/DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml +++ /dev/null @@ -1,29 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/simulator/ddr3.xml b/DRAMSys/tests/DDR3/configs/simulator/ddr3.xml deleted file mode 100644 index 1613737f..00000000 --- a/DRAMSys/tests/DDR3/configs/simulator/ddr3.xml +++ /dev/null @@ -1,29 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/config.xml b/DRAMSys/tests/DDR3/configs/thermalsim/config.xml deleted file mode 100644 index 4d32315e..00000000 --- a/DRAMSys/tests/DDR3/configs/thermalsim/config.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/powerInfo.xml b/DRAMSys/tests/DDR3/configs/thermalsim/powerInfo.xml deleted file mode 100644 index 192cb4ea..00000000 --- a/DRAMSys/tests/DDR3/configs/thermalsim/powerInfo.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/DRAMSys/tests/DDR3/simulations/ddr3-example.xml b/DRAMSys/tests/DDR3/simulations/ddr3-example.xml deleted file mode 100644 index c6140385..00000000 --- a/DRAMSys/tests/DDR3/simulations/ddr3-example.xml +++ /dev/null @@ -1,25 +0,0 @@ - - - - - - - - - - - - - - - - - ddr3_example.stl - - diff --git a/DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml b/DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml deleted file mode 100644 index a432321b..00000000 --- a/DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml +++ /dev/null @@ -1,25 +0,0 @@ - - - - - - - - - - - - - - - - - ddr3_example.stl - - diff --git a/DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml b/DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml deleted file mode 100644 index ececf822..00000000 --- a/DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml +++ /dev/null @@ -1,25 +0,0 @@ - - - - - - - - - - - - - - - - - ddr3_example.stl - - diff --git a/DRAMSys/tests/DDR4/ci.yml b/DRAMSys/tests/DDR4/ci.yml new file mode 100644 index 00000000..d6226908 --- /dev/null +++ b/DRAMSys/tests/DDR4/ci.yml @@ -0,0 +1,29 @@ +# DDR4 with 4 bank groups, flexible rankwise refresh and FrFcfs scheduler: +example_ddr4: + stage: DDR4 + script: + - export GCOV_PREFIX=$(pwd) + - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - cd build/simulator + - ./DRAMSys ../../DRAMSys/tests/DDR4/simulations/ddr4-example.json ../../DRAMSys/tests/DDR4/ + - ls -lah + - ls -lah ../../DRAMSys/tests/DDR4/expected/ + - sqldiff ../../DRAMSys/tests/DDR4/expected/ddr4-bankgrp_ddr4_ch0.tdb ddr4-bankgrp_ddr4_ch0.tdb + - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR4/expected/ddr4-bankgrp_ddr4_ch0.tdb ddr4-bankgrp_ddr4_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' + - cd ../traceAnalyzer + - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr4-bankgrp_ddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + # Run Code Coverage + - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out + + cache: + key: build + paths: + - build/ + policy: pull + + artifacts: + paths: + - build/simulator/ddr4-bankgrp_ddr4_ch0.tdb + - coverage/${CI_JOB_NAME}.out + expire_in: 2 days + diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json b/DRAMSys/tests/DDR4/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json similarity index 100% rename from DRAMSys/tests/ddr4_bankgroups/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json rename to DRAMSys/tests/DDR4/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/mcconfigs/fr_fcfs.json b/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json similarity index 100% rename from DRAMSys/tests/ddr4_bankgroups/configs/mcconfigs/fr_fcfs.json rename to DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json similarity index 94% rename from DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json rename to DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json index 11700aaf..abad7eab 100644 --- a/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -8,7 +8,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", @@ -63,4 +65,4 @@ "clkMhz": 933 } } -} \ No newline at end of file +} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json b/DRAMSys/tests/DDR4/configs/simulator/ddr4.json similarity index 87% rename from DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json rename to DRAMSys/tests/DDR4/configs/simulator/ddr4.json index 8e62e680..05cd86e2 100644 --- a/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json +++ b/DRAMSys/tests/DDR4/configs/simulator/ddr4.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "ddr4", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/config.json b/DRAMSys/tests/DDR4/configs/thermalsim/config.json similarity index 100% rename from DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/config.json rename to DRAMSys/tests/DDR4/configs/thermalsim/config.json diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/core.flp b/DRAMSys/tests/DDR4/configs/thermalsim/core.flp similarity index 100% rename from DRAMSys/tests/DDR3/configs/thermalsim/core.flp rename to DRAMSys/tests/DDR4/configs/thermalsim/core.flp diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/mem.flp b/DRAMSys/tests/DDR4/configs/thermalsim/mem.flp similarity index 100% rename from DRAMSys/tests/DDR3/configs/thermalsim/mem.flp rename to DRAMSys/tests/DDR4/configs/thermalsim/mem.flp diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/powerInfo.json b/DRAMSys/tests/DDR4/configs/thermalsim/powerInfo.json similarity index 100% rename from DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/powerInfo.json rename to DRAMSys/tests/DDR4/configs/thermalsim/powerInfo.json diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/stack.stk b/DRAMSys/tests/DDR4/configs/thermalsim/stack.stk similarity index 100% rename from DRAMSys/tests/DDR3/configs/thermalsim/stack.stk rename to DRAMSys/tests/DDR4/configs/thermalsim/stack.stk diff --git a/DRAMSys/tests/DDR3/scripts/createTraceDB.sql b/DRAMSys/tests/DDR4/scripts/createTraceDB.sql similarity index 100% rename from DRAMSys/tests/DDR3/scripts/createTraceDB.sql rename to DRAMSys/tests/DDR4/scripts/createTraceDB.sql diff --git a/DRAMSys/tests/ddr4_bankgroups/simulations/ddr4-example.json b/DRAMSys/tests/DDR4/simulations/ddr4-example.json similarity index 100% rename from DRAMSys/tests/ddr4_bankgroups/simulations/ddr4-example.json rename to DRAMSys/tests/DDR4/simulations/ddr4-example.json diff --git a/DRAMSys/tests/HBM2/ci.yml b/DRAMSys/tests/HBM2/ci.yml new file mode 100644 index 00000000..fb9474a1 --- /dev/null +++ b/DRAMSys/tests/HBM2/ci.yml @@ -0,0 +1,29 @@ +# HBM2 test with 4 bank groups, 2 trace players, fifo strict scheduler and closed pg policy.: +example_HBM2: + stage: HBM2 + script: + - export GCOV_PREFIX=$(pwd) + - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - cd build/simulator + - ./DRAMSys ../../DRAMSys/tests/HBM2/simulations/hbm2-example.json ../../DRAMSys/tests/HBM2/ + - ls -lah + - ls -lah ../../DRAMSys/tests/HBM2/expected/ + - sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb + - perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' + - cd ../traceAnalyzer + - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/hbm2-example_hbm2_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + # Run Code Coverage + - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out + + cache: + key: build + paths: + - build/ + policy: pull + + artifacts: + paths: + - build/simulator/hbm2-example_hbm2_ch0.tdb + - coverage/${CI_JOB_NAME}.out + expire_in: 2 days + diff --git a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json index efa8ee9e..b5985d10 100644 --- a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json +++ b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json @@ -8,7 +8,9 @@ "nbrOfColumns": 128, "nbrOfRanks": 2, "nbrOfRows": 32768, - "width": 64 + "width": 64, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1 }, "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", "memoryType": "HBM2", @@ -43,4 +45,4 @@ "clkMhz": 1000 } } -} \ No newline at end of file +} diff --git a/DRAMSys/tests/HBM2/configs/simulator/hbm2.json b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json index 9589611f..608aec41 100644 --- a/DRAMSys/tests/HBM2/configs/simulator/hbm2.json +++ b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "hbm2", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/tests/WIDEIO/ci.yml b/DRAMSys/tests/WIDEIO/ci.yml deleted file mode 100644 index e04215e0..00000000 --- a/DRAMSys/tests/WIDEIO/ci.yml +++ /dev/null @@ -1,40 +0,0 @@ -# vim: set ts=4 sw=4 expandtab: -example_wideio: - stage: WIDEIO - script: - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - # Generate specific traces for WIDEIO: - - cd DRAMSys/tests/WIDEIO/traces/ - - perl generator.pl - - cd - - # Run DRAMSys - - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/WIDEIO/simulations/wideio-example.xml ../../DRAMSys/tests/WIDEIO/ - - ls - # Run Traceanalyzer testing scripts: - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch1.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch2.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch3.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - # Run Code Coverage - - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out - - cache: - key: build - paths: - - build/ - policy: pull - - allow_failure: true # TODO: should be removed once the problems are fixed! - - artifacts: - paths: - - build/simulator/wideio-example_wideio_ch0.tdb - - build/simulator/wideio-example_wideio_ch1.tdb - - build/simulator/wideio-example_wideio_ch2.tdb - - build/simulator/wideio-example_wideio_ch3.tdb - - coverage/${CI_JOB_NAME}.out - expire_in: 2 days - diff --git a/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml b/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml deleted file mode 100755 index c6a33e71..00000000 --- a/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml b/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml deleted file mode 100755 index 511a7f0a..00000000 --- a/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml b/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml deleted file mode 100644 index ed869b57..00000000 --- a/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml +++ /dev/null @@ -1,50 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml b/DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml deleted file mode 100644 index fbe252d6..00000000 --- a/DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml +++ /dev/null @@ -1,61 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml b/DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml deleted file mode 100644 index acd95599..00000000 --- a/DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml +++ /dev/null @@ -1,24 +0,0 @@ - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml b/DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml deleted file mode 100644 index 4d32315e..00000000 --- a/DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/core.flp b/DRAMSys/tests/WIDEIO/configs/thermalsim/core.flp deleted file mode 100755 index e85e6801..00000000 --- a/DRAMSys/tests/WIDEIO/configs/thermalsim/core.flp +++ /dev/null @@ -1,45 +0,0 @@ -CPUs : - - position 0, 0 ; - dimension 2750, 4300 ; - -GPU : - - position 3350, 0 ; - dimension 2750, 4000 ; - -BASEBAND1 : - - position 4250, 4000 ; - dimension 1850, 3300 ; - -BASEBAND2 : - - position 3350, 7300 ; - dimension 2750, 3300 ; - -LLCACHE : - - position 0, 4300 ; - dimension 1900, 3000 ; - -DRAMCTRL1 : - - position 1900, 4300 ; - dimension 850, 3000 ; - -DRAMCTRL2 : - - position 3350, 4000 ; - dimension 900, 3300 ; - -TSVS : - - position 2750, 2300 ; - dimension 600, 6000 ; - -ACELLERATORS : - - position 0, 7300 ; - dimension 2750, 3300 ; - diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/mem.flp b/DRAMSys/tests/WIDEIO/configs/thermalsim/mem.flp deleted file mode 100755 index 29d02254..00000000 --- a/DRAMSys/tests/WIDEIO/configs/thermalsim/mem.flp +++ /dev/null @@ -1,16 +0,0 @@ -channel0 : - position 150, 100 ; - dimension 2600, 5200 ; - -channel1 : - position 3350, 100 ; - dimension 2600, 5200 ; - -channel2 : - position 150, 5300 ; - dimension 2600, 5200 ; - -channel3 : - position 3350, 5300 ; - dimension 2600, 5200 ; - diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml b/DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml deleted file mode 100644 index 192cb4ea..00000000 --- a/DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/stack.stk b/DRAMSys/tests/WIDEIO/configs/thermalsim/stack.stk deleted file mode 100755 index ec74f020..00000000 --- a/DRAMSys/tests/WIDEIO/configs/thermalsim/stack.stk +++ /dev/null @@ -1,49 +0,0 @@ -material SILICON : - thermal conductivity 1.30e-4 ; - volumetric heat capacity 1.628e-12 ; - -material BEOL : - thermal conductivity 2.25e-6 ; - volumetric heat capacity 2.175e-12 ; - -material COPPER : - thermal conductivity 4.01e-04 ; - volumetric heat capacity 3.37e-12 ; - -top heat sink : - //sink height 1e03, area 100e06, material COPPER ; - //spreader height 0.5e03, area 70e06, material SILICON ; - heat transfer coefficient 1.3e-09 ; - temperature 318.15 ; -dimensions : - chip length 6100, width 10600 ; - cell length 100, width 100 ; - - -layer PCB : - height 10 ; - material BEOL ; - -die DRAM : - layer 58.5 SILICON ; - source 2 SILICON ; - layer 1.5 BEOL ; - layer 58.5 SILICON ; - - -stack: - die DRAM_DIE DRAM floorplan "./mem.flp" ; - layer CONN_TO_PCB PCB ; - -solver: - transient step 0.01, slot 0.05 ; - initial temperature 300.0 ; - -output: - Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); - Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); - Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); - Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); - Tmap (DRAM_DIE, "output1.txt", slot) ; - Pmap (DRAM_DIE, "output2.txt", slot) ; - diff --git a/DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql b/DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql deleted file mode 100644 index 7a127fac..00000000 --- a/DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql +++ /dev/null @@ -1,94 +0,0 @@ -DROP TABLE IF EXISTS Phases; -DROP TABLE IF EXISTS GeneralInfo; -DROP TABLE IF EXISTS CommandLengths; -DROP TABLE IF EXISTS Comments; -DROP TABLE IF EXISTS ranges; -DROP TABLE IF EXISTS Transactions; -DROP TABLE IF EXISTS DebugMessages; -DROP TABLE IF EXISTS Power; - -CREATE TABLE Phases( - ID INTEGER PRIMARY KEY, - PhaseName TEXT, - PhaseBegin INTEGER, - PhaseEnd INTEGER, - Transact INTEGER -); - -CREATE TABLE GeneralInfo( - NumberOfTransactions INTEGER, - TraceEnd INTEGER, - NumberOfRanks INTEGER, - NumberOfBanks INTEGER, - clk INTEGER, - UnitOfTime TEXT, - MCconfig TEXT, - Memspec TEXT, - Traces TEXT, - WindowSize INTEGER, - FlexibleRefresh INTEGER, - MaxRefBurst INTEGER, - ControllerThread INTEGER -); - -CREATE TABLE CommandLengths( - ACT INTEGER, - PRE INTEGER, - PREA INTEGER, - RD INTEGER, - RDA INTEGER, - WR INTEGER, - WRA INTEGER, - REFA INTEGER, - REFB INTEGER, - PDEA INTEGER, - PDXA INTEGER, - PDEP INTEGER, - PDXP INTEGER, - SREFEN INTEGER, - SREFEX INTEGER -); - -CREATE TABLE Power( - time DOUBLE, - AveragePower DOUBLE -); - - -CREATE TABLE Comments( - Time INTEGER, - Text TEXT -); - -CREATE TABLE DebugMessages( - Time INTEGER, - Message TEXT -); - --- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) -CREATE VIRTUAL TABLE ranges USING rtree( - id, - begin, end -); - -CREATE TABLE Transactions( - ID INTEGER, - Range INTEGER, - Address INTEGER, - Burstlength INTEGER, - TThread INTEGER, - TChannel INTEGER, - TRank INTEGER, - TBankgroup INTEGER, - TBank INTEGER, - TRow INTEGER, - TColumn INTEGER, - DataStrobeBegin INTEGER, - DataStrobeEnd INTEGER, - TimeOfGeneration INTEGER, - Command TEXT - ); - -CREATE INDEX ranges_index ON Transactions(Range); -CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); -CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/WIDEIO/simulations/wideio-example.xml b/DRAMSys/tests/WIDEIO/simulations/wideio-example.xml deleted file mode 100644 index fea1f568..00000000 --- a/DRAMSys/tests/WIDEIO/simulations/wideio-example.xml +++ /dev/null @@ -1,24 +0,0 @@ - - - - - - - - - - - - - - - - - wideio.stl - - diff --git a/DRAMSys/tests/WIDEIO/traces/generator.pl b/DRAMSys/tests/WIDEIO/traces/generator.pl deleted file mode 100644 index 173a0248..00000000 --- a/DRAMSys/tests/WIDEIO/traces/generator.pl +++ /dev/null @@ -1,75 +0,0 @@ -#!/usr/bin/perl -w -use warnings; -use strict; - -# Width: 128 bit -# -# Mapping: -# 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 -# H | H B B B | R R R R | R R R R | R R R R | R C C C | C C C C | Y Y Y Y - - -open(OUT, "> wideio.stl"); - -my $length = 100000; -my $size = 0x10; -my $channelOffset = 0x8000000; -my $state = 0; -# state 0: reads only linear -# state 1: reads only random -# state 2: read and writes linear - -for(my $i=0; $i < $length; $i += 4) -{ - my $r = 0; - - if($state == 0) - { - print OUT ($i+0).": read ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n"; - print OUT ($i+1).": read ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n"; - print OUT ($i+2).": read ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n"; - print OUT ($i+3).": read ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n"; - } - elsif($state == 1) - { - $r = int(rand($channelOffset)); - print OUT ($i+0).": read ".sprintf("0x%x",($size*$r)+0*$channelOffset)."\n"; - $r = int(rand($channelOffset)); - print OUT ($i+1).": read ".sprintf("0x%x",($size*$r)+1*$channelOffset)."\n"; - $r = int(rand($channelOffset)); - print OUT ($i+2).": read ".sprintf("0x%x",($size*$r)+2*$channelOffset)."\n"; - $r = int(rand($channelOffset)); - print OUT ($i+3).": read ".sprintf("0x%x",($size*$r)+3*$channelOffset)."\n"; - } - elsif($state == 2) - { - my $rw = int(rand(2))%2; - if($rw == 0) - { - print OUT "$i: read ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n"; - print OUT "$i: read ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n"; - print OUT "$i: read ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n"; - print OUT "$i: read ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n"; - } - else - { - print OUT "$i: write ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n"; - print OUT "$i: write ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n"; - print OUT "$i: write ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n"; - print OUT "$i: write ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n"; - } - } - else - { - print "Error generating traces (".$state.")"; - exit(-1); - } - - if(($i != 0) && (($i % 1000) == 0)) - { - # GOTO next state every 1000st request: - $state = ($state + 1) % 3; - } -} - -close(OUT); diff --git a/DRAMSys/tests/ddr3_multirank/ci.yml b/DRAMSys/tests/ddr3_multirank/ci.yml new file mode 100644 index 00000000..da90393a --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/ci.yml @@ -0,0 +1,29 @@ +# DDR3 Dual Rank Test with Staggered Power Down Policy and Scheduler FrFcfsGrp +example_ddr3: + stage: DDR3 + script: + - export GCOV_PREFIX=$(pwd) + - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - cd build/simulator + - ./DRAMSys ../../DRAMSys/tests/ddr3_multirank/ddr3-example.json ../../DRAMSys/tests/ddr3_multirank/ + - ls -lah + - ls -lah ../../DRAMSys/tests/ddr3_multirank/expected/ + - sqldiff ../../DRAMSys/tests/ddr3_multirank/expected/ddr3-dual-rank_ddr3_ch0.tdb ddr3-dual-rank_ddr3_ch0.tdb + - perl -e 'if(`sqldiff ../../DRAMSys/tests/ddr3_multirank/expected/ddr3-dual-rank_ddr3_ch0.tdb ddr3-dual-rank_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' + - cd ../traceAnalyzer + - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3_multirank_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + # Run Code Coverage + - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out + + cache: + key: build + paths: + - build/ + policy: pull + + artifacts: + paths: + - build/simulator/ddr3_multirank_ddr3_ch0.tdb + - coverage/${CI_JOB_NAME}.out + expire_in: 2 days + diff --git a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json index 13d9fef5..d842bda2 100644 --- a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 2, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", "memoryType": "DDR3", @@ -49,7 +51,12 @@ "XPDLL": 13, "XS": 64, "XSDLL": 512, - "clkMhz": 533 + "clkMhz": 533, + + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1 } } } diff --git a/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json index 4e9faadc..99ccdb45 100644 --- a/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json +++ b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "ddr3", "SimulationProgressBar": true, diff --git a/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json b/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json index e3d4a4c3..b924da62 100644 --- a/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json +++ b/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json @@ -4,7 +4,7 @@ "mcconfig": "fr_fcfs_grp.json", "memspec": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json", "simconfig": "ddr3.json", - "simulationid": "ddr3-example-dual-rank-json", + "simulationid": "ddr3-dual-rank", "thermalconfig": "config.json", "tracesetup": [ { diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json deleted file mode 100644 index c82926c9..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json +++ /dev/null @@ -1,51 +0,0 @@ -{ - "CONGEN": { - "XOR":[ - { - "FIRST":13, - "SECOND":16 - } - ], - "BANK_BIT": [ - 13, - 14, - 15 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12 - ], - "ROW_BIT": [ - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28, - 29 - ], - "RANK_BIT": [ - 30 - ] - } -} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json deleted file mode 100644 index 4ac02e30..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json +++ /dev/null @@ -1,12 +0,0 @@ -{"mcconfig": - {"PagePolicy": "Open", - "Scheduler": "FrFcfsGrp", - "RequestBufferSize": 8, - "CmdMux": "Oldest", - "RespQueue": "Fifo", - "RefreshPolicy": "Rankwise", - "RefreshMode": 1, - "RefreshMaxPostponed": 0, - "RefreshMaxPulledin": 0, - "PowerDownPolicy": "Staggered", - "PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json deleted file mode 100644 index d842bda2..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ /dev/null @@ -1,62 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 2, - "nbrOfRows": 16384, - "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 - }, - "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 720.0, - "idd2n": 400.0, - "idd2p0": 80.0, - "idd2p1": 200.0, - "idd3n": 440.0, - "idd3p0": 240.0, - "idd3p1": 240.0, - "idd4r": 1200.0, - "idd4w": 1200.0, - "idd5": 1760.0, - "idd6": 48.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 20, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 59, - "RL": 7, - "RP": 7, - "RRD": 4, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 64, - "XSDLL": 512, - "clkMhz": 533, - - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1 - } - } -} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json deleted file mode 100644 index 99ccdb45..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json +++ /dev/null @@ -1,19 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "PowerAnalysis": false, - "SimulationName": "ddr3", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp deleted file mode 100755 index e85e6801..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp +++ /dev/null @@ -1,45 +0,0 @@ -CPUs : - - position 0, 0 ; - dimension 2750, 4300 ; - -GPU : - - position 3350, 0 ; - dimension 2750, 4000 ; - -BASEBAND1 : - - position 4250, 4000 ; - dimension 1850, 3300 ; - -BASEBAND2 : - - position 3350, 7300 ; - dimension 2750, 3300 ; - -LLCACHE : - - position 0, 4300 ; - dimension 1900, 3000 ; - -DRAMCTRL1 : - - position 1900, 4300 ; - dimension 850, 3000 ; - -DRAMCTRL2 : - - position 3350, 4000 ; - dimension 900, 3300 ; - -TSVS : - - position 2750, 2300 ; - dimension 600, 6000 ; - -ACELLERATORS : - - position 0, 7300 ; - dimension 2750, 3300 ; - diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp deleted file mode 100755 index 29d02254..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp +++ /dev/null @@ -1,16 +0,0 @@ -channel0 : - position 150, 100 ; - dimension 2600, 5200 ; - -channel1 : - position 3350, 100 ; - dimension 2600, 5200 ; - -channel2 : - position 150, 5300 ; - dimension 2600, 5200 ; - -channel3 : - position 3350, 5300 ; - dimension 2600, 5200 ; - diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk deleted file mode 100755 index ec74f020..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk +++ /dev/null @@ -1,49 +0,0 @@ -material SILICON : - thermal conductivity 1.30e-4 ; - volumetric heat capacity 1.628e-12 ; - -material BEOL : - thermal conductivity 2.25e-6 ; - volumetric heat capacity 2.175e-12 ; - -material COPPER : - thermal conductivity 4.01e-04 ; - volumetric heat capacity 3.37e-12 ; - -top heat sink : - //sink height 1e03, area 100e06, material COPPER ; - //spreader height 0.5e03, area 70e06, material SILICON ; - heat transfer coefficient 1.3e-09 ; - temperature 318.15 ; -dimensions : - chip length 6100, width 10600 ; - cell length 100, width 100 ; - - -layer PCB : - height 10 ; - material BEOL ; - -die DRAM : - layer 58.5 SILICON ; - source 2 SILICON ; - layer 1.5 BEOL ; - layer 58.5 SILICON ; - - -stack: - die DRAM_DIE DRAM floorplan "./mem.flp" ; - layer CONN_TO_PCB PCB ; - -solver: - transient step 0.01, slot 0.05 ; - initial temperature 300.0 ; - -output: - Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); - Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); - Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); - Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); - Tmap (DRAM_DIE, "output1.txt", slot) ; - Pmap (DRAM_DIE, "output2.txt", slot) ; - diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql b/DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql deleted file mode 100644 index 7a127fac..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql +++ /dev/null @@ -1,94 +0,0 @@ -DROP TABLE IF EXISTS Phases; -DROP TABLE IF EXISTS GeneralInfo; -DROP TABLE IF EXISTS CommandLengths; -DROP TABLE IF EXISTS Comments; -DROP TABLE IF EXISTS ranges; -DROP TABLE IF EXISTS Transactions; -DROP TABLE IF EXISTS DebugMessages; -DROP TABLE IF EXISTS Power; - -CREATE TABLE Phases( - ID INTEGER PRIMARY KEY, - PhaseName TEXT, - PhaseBegin INTEGER, - PhaseEnd INTEGER, - Transact INTEGER -); - -CREATE TABLE GeneralInfo( - NumberOfTransactions INTEGER, - TraceEnd INTEGER, - NumberOfRanks INTEGER, - NumberOfBanks INTEGER, - clk INTEGER, - UnitOfTime TEXT, - MCconfig TEXT, - Memspec TEXT, - Traces TEXT, - WindowSize INTEGER, - FlexibleRefresh INTEGER, - MaxRefBurst INTEGER, - ControllerThread INTEGER -); - -CREATE TABLE CommandLengths( - ACT INTEGER, - PRE INTEGER, - PREA INTEGER, - RD INTEGER, - RDA INTEGER, - WR INTEGER, - WRA INTEGER, - REFA INTEGER, - REFB INTEGER, - PDEA INTEGER, - PDXA INTEGER, - PDEP INTEGER, - PDXP INTEGER, - SREFEN INTEGER, - SREFEX INTEGER -); - -CREATE TABLE Power( - time DOUBLE, - AveragePower DOUBLE -); - - -CREATE TABLE Comments( - Time INTEGER, - Text TEXT -); - -CREATE TABLE DebugMessages( - Time INTEGER, - Message TEXT -); - --- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) -CREATE VIRTUAL TABLE ranges USING rtree( - id, - begin, end -); - -CREATE TABLE Transactions( - ID INTEGER, - Range INTEGER, - Address INTEGER, - Burstlength INTEGER, - TThread INTEGER, - TChannel INTEGER, - TRank INTEGER, - TBankgroup INTEGER, - TBank INTEGER, - TRow INTEGER, - TColumn INTEGER, - DataStrobeBegin INTEGER, - DataStrobeEnd INTEGER, - TimeOfGeneration INTEGER, - Command TEXT - ); - -CREATE INDEX ranges_index ON Transactions(Range); -CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); -CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json b/DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json deleted file mode 100644 index e3d4a4c3..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json", - "mcconfig": "fr_fcfs_grp.json", - "memspec": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json", - "simconfig": "ddr3.json", - "simulationid": "ddr3-example-dual-rank-json", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 533, - "name": "trace_test2.stl" - } - ] - } -} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json deleted file mode 100644 index b88ed84c..00000000 --- a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json +++ /dev/null @@ -1,15 +0,0 @@ -{ - "thermalsimconfig": { - "TemperatureScale": "Celsius", - "StaticTemperatureDefaultValue": 89, - "ThermalSimPeriod":100, - "ThermalSimUnit":"us", - "PowerInfoFile": "powerInfo.json", - "IceServerIp": "127.0.0.1", - "IceServerPort": 11880, - "SimPeriodAdjustFactor" : 10, - "NPowStableCyclesToIncreasePeriod": 5, - "GenerateTemperatureMap": true, - "GeneratePowerMap": true - } -} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp deleted file mode 100755 index e85e6801..00000000 --- a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp +++ /dev/null @@ -1,45 +0,0 @@ -CPUs : - - position 0, 0 ; - dimension 2750, 4300 ; - -GPU : - - position 3350, 0 ; - dimension 2750, 4000 ; - -BASEBAND1 : - - position 4250, 4000 ; - dimension 1850, 3300 ; - -BASEBAND2 : - - position 3350, 7300 ; - dimension 2750, 3300 ; - -LLCACHE : - - position 0, 4300 ; - dimension 1900, 3000 ; - -DRAMCTRL1 : - - position 1900, 4300 ; - dimension 850, 3000 ; - -DRAMCTRL2 : - - position 3350, 4000 ; - dimension 900, 3300 ; - -TSVS : - - position 2750, 2300 ; - dimension 600, 6000 ; - -ACELLERATORS : - - position 0, 7300 ; - dimension 2750, 3300 ; - diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp deleted file mode 100755 index 29d02254..00000000 --- a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp +++ /dev/null @@ -1,16 +0,0 @@ -channel0 : - position 150, 100 ; - dimension 2600, 5200 ; - -channel1 : - position 3350, 100 ; - dimension 2600, 5200 ; - -channel2 : - position 150, 5300 ; - dimension 2600, 5200 ; - -channel3 : - position 3350, 5300 ; - dimension 2600, 5200 ; - diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json deleted file mode 100644 index 524f690f..00000000 --- a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "powerInfo": { - "dram_die_channel0": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel1": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel2": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel3": { - "init_pow": 0, - "threshold": 1.0 - } - } -} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk deleted file mode 100755 index ec74f020..00000000 --- a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk +++ /dev/null @@ -1,49 +0,0 @@ -material SILICON : - thermal conductivity 1.30e-4 ; - volumetric heat capacity 1.628e-12 ; - -material BEOL : - thermal conductivity 2.25e-6 ; - volumetric heat capacity 2.175e-12 ; - -material COPPER : - thermal conductivity 4.01e-04 ; - volumetric heat capacity 3.37e-12 ; - -top heat sink : - //sink height 1e03, area 100e06, material COPPER ; - //spreader height 0.5e03, area 70e06, material SILICON ; - heat transfer coefficient 1.3e-09 ; - temperature 318.15 ; -dimensions : - chip length 6100, width 10600 ; - cell length 100, width 100 ; - - -layer PCB : - height 10 ; - material BEOL ; - -die DRAM : - layer 58.5 SILICON ; - source 2 SILICON ; - layer 1.5 BEOL ; - layer 58.5 SILICON ; - - -stack: - die DRAM_DIE DRAM floorplan "./mem.flp" ; - layer CONN_TO_PCB PCB ; - -solver: - transient step 0.01, slot 0.05 ; - initial temperature 300.0 ; - -output: - Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); - Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); - Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); - Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); - Tmap (DRAM_DIE, "output1.txt", slot) ; - Pmap (DRAM_DIE, "output2.txt", slot) ; - diff --git a/DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql b/DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql deleted file mode 100644 index 7a127fac..00000000 --- a/DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql +++ /dev/null @@ -1,94 +0,0 @@ -DROP TABLE IF EXISTS Phases; -DROP TABLE IF EXISTS GeneralInfo; -DROP TABLE IF EXISTS CommandLengths; -DROP TABLE IF EXISTS Comments; -DROP TABLE IF EXISTS ranges; -DROP TABLE IF EXISTS Transactions; -DROP TABLE IF EXISTS DebugMessages; -DROP TABLE IF EXISTS Power; - -CREATE TABLE Phases( - ID INTEGER PRIMARY KEY, - PhaseName TEXT, - PhaseBegin INTEGER, - PhaseEnd INTEGER, - Transact INTEGER -); - -CREATE TABLE GeneralInfo( - NumberOfTransactions INTEGER, - TraceEnd INTEGER, - NumberOfRanks INTEGER, - NumberOfBanks INTEGER, - clk INTEGER, - UnitOfTime TEXT, - MCconfig TEXT, - Memspec TEXT, - Traces TEXT, - WindowSize INTEGER, - FlexibleRefresh INTEGER, - MaxRefBurst INTEGER, - ControllerThread INTEGER -); - -CREATE TABLE CommandLengths( - ACT INTEGER, - PRE INTEGER, - PREA INTEGER, - RD INTEGER, - RDA INTEGER, - WR INTEGER, - WRA INTEGER, - REFA INTEGER, - REFB INTEGER, - PDEA INTEGER, - PDXA INTEGER, - PDEP INTEGER, - PDXP INTEGER, - SREFEN INTEGER, - SREFEX INTEGER -); - -CREATE TABLE Power( - time DOUBLE, - AveragePower DOUBLE -); - - -CREATE TABLE Comments( - Time INTEGER, - Text TEXT -); - -CREATE TABLE DebugMessages( - Time INTEGER, - Message TEXT -); - --- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) -CREATE VIRTUAL TABLE ranges USING rtree( - id, - begin, end -); - -CREATE TABLE Transactions( - ID INTEGER, - Range INTEGER, - Address INTEGER, - Burstlength INTEGER, - TThread INTEGER, - TChannel INTEGER, - TRank INTEGER, - TBankgroup INTEGER, - TBank INTEGER, - TRow INTEGER, - TColumn INTEGER, - DataStrobeBegin INTEGER, - DataStrobeEnd INTEGER, - TimeOfGeneration INTEGER, - Command TEXT - ); - -CREATE INDEX ranges_index ON Transactions(Range); -CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); -CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/lpddr4/ci.yml b/DRAMSys/tests/lpddr4/ci.yml new file mode 100644 index 00000000..40860f3f --- /dev/null +++ b/DRAMSys/tests/lpddr4/ci.yml @@ -0,0 +1,28 @@ +# LPDDR4 with Bankwise Flexible Refresh and FIFO Scheduler: +example_lpddr4: + stage: LPDDR4 + script: + - export GCOV_PREFIX=$(pwd) + - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - cd build/simulator + - ./DRAMSys ../../DRAMSys/tests/lpddr4/simulations/lpddr4-example.json ../../DRAMSys/tests/lpddr4/ + - ls -lah + - ls -lah ../../DRAMSys/tests/lpddr4/expected/ + - sqldiff ../../DRAMSys/tests/lpddr4/expected/lpddr4-example_lpddr4_ch0.tdb lpddr4-example_lpddr4_ch0.tdb + - perl -e 'if(`sqldiff ../../DRAMSys/tests/lpddr4/expected/lpddr4-example_lpddr4_ch0.tdb lpddr4-example_lpddr4_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' + - cd ../traceAnalyzer + - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/lpddr4-example_lpddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + # Run Code Coverage + - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out + + cache: + key: build + paths: + - build/ + policy: pull + + artifacts: + paths: + - build/simulator/lpddr4-example_lpddr4_ch0.tdb + - coverage/${CI_JOB_NAME}.out + expire_in: 2 days diff --git a/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json index 97a8cc3e..fce6c632 100644 --- a/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json +++ b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 65536, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1, }, "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", "memoryType": "LPDDR4", @@ -40,7 +42,11 @@ "WTR": 16, "XP": 12, "XSR": 460, + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1, "clkMhz": 1600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json index fd8fe855..6ea5b1bd 100644 --- a/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json +++ b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "lpddr4", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} From ab206aa68839e7c245be317c78cb53b98564f644 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 16 Jun 2020 11:50:11 +0200 Subject: [PATCH 06/53] ci.yml edited --- .gitlab-ci.yml | 11 +++++---- .gitlab-ci_old.yml | 56 ---------------------------------------------- 2 files changed, 7 insertions(+), 60 deletions(-) delete mode 100644 .gitlab-ci_old.yml diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 9011e4ab..800215b0 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -6,9 +6,10 @@ variables: stages: - build - - dramsys-gem5-build - - WIDEIO + - LPDDR4 - DDR3 + - DDR4 + - HBM2 - Coverage build: @@ -51,6 +52,8 @@ coverage: include: - - '/DRAMSys/tests/DDR3/ci.yml' - - '/DRAMSys/tests/WIDEIO/ci.yml' + - '/DRAMSys/tests/lpddr4/ci.yml' + - '/DRAMSys/tests/ddr3_multirank/ci.yml' + - '/DRAMSys/tests/DDR4/ci.yml' + - '/DRAMSys/tests/HBM2/ci.yml' #- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used diff --git a/.gitlab-ci_old.yml b/.gitlab-ci_old.yml deleted file mode 100644 index 9011e4ab..00000000 --- a/.gitlab-ci_old.yml +++ /dev/null @@ -1,56 +0,0 @@ -# vim: set ts=4 sw=4 expandtab: -image: gcc - -variables: - GIT_STRATEGY: clone - -stages: - - build - - dramsys-gem5-build - - WIDEIO - - DDR3 - - Coverage - -build: - stage: build - script: - - git submodule sync - - git submodule update --init --recursive - - rm -rf build - - mkdir -p build - - cd build - - cmake ../DRAMSys - - make -j16 - - find . -name "*.o" -type f -delete - - rm -rf ${CI_PROJECT_DIR}/coverage - - mkdir -p ${CI_PROJECT_DIR}/coverage - - cache: - key: build - paths: - - build/ - policy: push - - artifacts: - paths: - - coverage/ - -coverage: - stage: Coverage - coverage: '/Total:\|(\d+\.?\d+\%)/' - script: - # delete all empty files since they produce errors - - find coverage -size 0 -type f -delete - - ls coverage/ -lah - - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - - lcov --list coverage/final.out - - artifacts: - paths: - - coverage/final.out - - -include: - - '/DRAMSys/tests/DDR3/ci.yml' - - '/DRAMSys/tests/WIDEIO/ci.yml' - #- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used From 5f57c29224a27aa279d8b11cf632a636d1e7adb8 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 16 Jun 2020 13:24:20 +0200 Subject: [PATCH 07/53] Per-bank refresh fix. --- .../src/controller/checker/CheckerLPDDR4.cpp | 2 +- .../refresh/RefreshManagerBankwise.cpp | 25 ++++++++++++++----- .../refresh/RefreshManagerBankwise.h | 1 + 3 files changed, 21 insertions(+), 7 deletions(-) diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index 09adc6d1..98e304fc 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -164,7 +164,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank } else if (command == Command::ACT) { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][rank.ID()]; + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 349bef14..84429e4c 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -91,14 +91,17 @@ sc_time RefreshManagerBankwise::start() bool forcedRefresh = (flexibilityCounter == maxPostponed); bool allBanksBusy = true; - for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) + if (!skipSelection) { - if ((*it)->isIdle()) + for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) { - currentIterator = it; - currentBankMachine = *it; - allBanksBusy = false; - break; + if ((*it)->isIdle()) + { + currentIterator = it; + currentBankMachine = *it; + allBanksBusy = false; + break; + } } } @@ -113,7 +116,16 @@ sc_time RefreshManagerBankwise::start() if (currentBankMachine->getState() == BmState::Activated) nextCommand = Command::PRE; else + { nextCommand = Command::REFB; + + if (forcedRefresh) + { + currentBankMachine->block(); + skipSelection = true; + } + } + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, currentBankMachine->getBankGroup(), currentBankMachine->getBank()); return timeToSchedule; @@ -161,6 +173,7 @@ void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *p switch (command) { case Command::REFB: + skipSelection = false; remainingBankMachines.erase(currentIterator); if (remainingBankMachines.empty()) remainingBankMachines = allBankMachines; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 285329b5..252a4b9e 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -74,6 +74,7 @@ private: int maxPulledin = 0; bool sleeping = false; + bool skipSelection = false; }; #endif // REFRESHMANAGERBANKWISE_H From 295810ac1b69fe0da354e2f4131a28e810ae3779 Mon Sep 17 00:00:00 2001 From: scorrea Date: Thu, 18 Jun 2020 10:40:37 +0200 Subject: [PATCH 08/53] ci tests traces and memspec modified --- DRAMSys/library/resources/configs/memspecs/HBM2.json | 5 +++-- .../configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json | 5 +++-- .../configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json | 5 +++-- .../configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json | 6 ++++-- .../configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json | 6 ++++-- .../configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json | 5 +++-- .../configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json | 5 +++-- .../configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json | 5 +++-- .../configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json | 5 +++-- .../configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json | 5 +++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json | 4 +++- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json | 6 ++++-- .../memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json | 6 ++++-- .../memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 6 ++++-- .../memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json | 6 ++++-- .../memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json | 6 ++++-- .../memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json | 5 +++-- .../configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json | 5 +++-- .../configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json | 5 +++-- .../configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json | 5 +++-- .../configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json | 6 ++++-- .../configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json | 6 ++++-- .../configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json | 5 +++-- .../configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json | 5 +++-- .../configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json | 5 +++-- .../memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json | 6 ++++-- .../memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json | 6 ++++-- .../resources/configs/memspecs/memspec_ranktest.json | 5 +++-- .../resources/configs/simulator/ddr3-single-device.json | 4 +--- DRAMSys/library/resources/configs/simulator/ddr3.json | 2 -- .../resources/configs/simulator/ddr3_boot_linux.json | 4 +--- DRAMSys/library/resources/configs/simulator/ddr3_ecc.json | 4 +--- .../library/resources/configs/simulator/ddr3_gem5_se.json | 4 +--- DRAMSys/library/resources/configs/simulator/ddr4.json | 4 +--- DRAMSys/library/resources/configs/simulator/hbm2.json | 4 +--- DRAMSys/library/resources/configs/simulator/lpddr4.json | 3 +-- DRAMSys/library/resources/configs/simulator/wideio.json | 4 +--- DRAMSys/library/resources/configs/simulator/wideio_ecc.json | 4 +--- .../library/resources/configs/simulator/wideio_thermal.json | 4 +--- DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json | 4 ++-- DRAMSys/tests/HBM2/configs/memspecs/HBM2.json | 1 - .../memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 4 ++-- 62 files changed, 189 insertions(+), 131 deletions(-) diff --git a/DRAMSys/library/resources/configs/memspecs/HBM2.json b/DRAMSys/library/resources/configs/memspecs/HBM2.json index efa8ee9e..bc9faa23 100644 --- a/DRAMSys/library/resources/configs/memspecs/HBM2.json +++ b/DRAMSys/library/resources/configs/memspecs/HBM2.json @@ -8,7 +8,8 @@ "nbrOfColumns": 128, "nbrOfRanks": 2, "nbrOfRows": 32768, - "width": 64 + "width": 64, + "NumberOfMemChannels": 1 }, "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", "memoryType": "HBM2", @@ -43,4 +44,4 @@ "clkMhz": 1000 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json index 64256e3c..17630099 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 128, "nbrOfRanks": 1, "nbrOfRows": 4096, - "width": 128 + "width": 128, + "NumberOfMemChannels": 4 }, "memoryId": "JEDEC_256Mb_WIDEIO_SDR-200_128bit", "memoryType": "WIDEIO_SDR", @@ -62,4 +63,4 @@ "clkMhz": 200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json index c2d60cd9..7f576e12 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 128, "nbrOfRanks": 1, "nbrOfRows": 4096, - "width": 128 + "width": 128, + "NumberOfMemChannels": 4 }, "memoryId": "JEDEC_256Mb_WIDEIO_SDR-266_128bit", "memoryType": "WIDEIO_SDR", @@ -62,4 +63,4 @@ "clkMhz": 266 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json index c7c0e7a0..db212fc7 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json @@ -8,7 +8,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", @@ -65,4 +67,4 @@ "clkMhz": 933 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json index 51ac9635..9ea5ca87 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json @@ -8,7 +8,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A", "memoryType": "DDR4", @@ -65,4 +67,4 @@ "clkMhz": 1200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json index 65be78a0..29e9f3d6 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 512, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 64 + "width": 64, + "NumberOfMemChannels": 4 }, "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-400_64bit", "memoryType": "WIDEIO2", @@ -39,4 +40,4 @@ "clkMhz": 400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json index a01fedb0..16f3546f 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 512, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 64 + "width": 64, + "NumberOfMemChannels": 4 }, "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-533_64bit", "memoryType": "WIDEIO2", @@ -39,4 +40,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json index c41d427f..6504cd54 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 65536, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", "memoryType": "LPDDR4", @@ -93,4 +94,4 @@ "clkMhz": 1600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json index aaecf874..42692386 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR2-1066_16bit_H", "memoryType": "DDR2", @@ -52,4 +53,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json index 33f80da5..3cbdec2d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR2-800_16bit_H", "memoryType": "DDR2", @@ -52,4 +53,4 @@ "clkMhz": 400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json index 467c599b..0e15b9b3 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json index 6ff10023..f6557d3d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json index 9b4a0ad8..f8b477bb 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json index 9459ab49..fe0feff6 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json index 5dd17ce0..549f79ae 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json index 8f7e730b..fb5a2a58 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json index 315c3fce..378722ed 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json index ae39db63..a79e2ea0 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json index 3020b53b..fca362ca 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json index 6867118b..f193410e 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json index 2988bf90..69084ebe 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json index c6dabf1d..9515ac0d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json index 9aaa2c4c..eed0f3b5 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json index 0aef9bf9..9be74831 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-800_8bit_G", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json index b8cd6ba9..8d85c957 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 2, "nbrOfRows": 16384, - "width": 64 + "width": 64, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json index d19953e5..589c2ef7 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 2, "nbrOfRows": 16384, - "width": 64 + "width": 64, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_G_UDIMM", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json index 2b954795..4b665ba4 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 2, "nbrOfRows": 16384, - "width": 64 + "width": 64, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1333_64bit_D_SODIMM", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 666 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json index ef9a59b8..f52937e5 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 2, "nbrOfRows": 16384, - "width": 64 + "width": 64, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1600_64bit_G_UDIMM", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json index f135a2e6..8247a00d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json index 0cd99819..067f826b 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json index 647e8938..2fba0c69 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json index 1273f6e2..ada0ddbd 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json index a6a5a43a..c52f37bf 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json index 768b1cae..a0a6e4ea 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json index a5b3a676..14bf56fa 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json index a6b86516..2809f069 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json index a75ff24b..579d540d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 2048, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR-266_16bit_A", "memoryType": "LPDDR", @@ -51,4 +52,4 @@ "clkMhz": 133 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json index 8b17dc3f..6038029c 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 2048, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR-333_16bit_A", "memoryType": "LPDDR", @@ -51,4 +52,4 @@ "clkMhz": 166 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json index 8aadde0a..bb424df9 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR2-1066-S4_16bit_A", "memoryType": "LPDDR2", @@ -64,4 +65,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json index ebe11f7a..4b6dbcf8 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR2-800-S4_16bit_A", "memoryType": "LPDDR2", @@ -64,4 +65,4 @@ "clkMhz": 400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json index 11700aaf..9d837139 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -8,7 +8,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", @@ -63,4 +65,4 @@ "clkMhz": 933 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json index ed4906cd..b1160755 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json @@ -8,7 +8,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A", "memoryType": "DDR4", @@ -63,4 +65,4 @@ "clkMhz": 1200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json index 35e1fe35..025531d1 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 32 + "width": 32, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_4Gb_LPDDR3-1333_32bit_A", "memoryType": "LPDDR3", @@ -64,4 +65,4 @@ "clkMhz": 667 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json index 60d40c43..a9e32fdd 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 32 + "width": 32, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_4Gb_LPDDR3-1600_32bit_A", "memoryType": "LPDDR3", @@ -64,4 +65,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json index 17638bb1..9faeea25 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 49152, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_6Gb_LPDDR3-3200_16bit_A", "memoryType": "LPDDR4", @@ -92,4 +93,4 @@ "clkMhz": 1600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json index 41f5cef2..628077a9 100644 --- a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1, + "NumberOfDevicesOnDIMM": 1, }, "memoryId": "SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json index ca86b2d5..7cb2625c 100644 --- a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1 }, "memoryId": "SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json index 88044fdd..b7d49c2a 100644 --- a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json +++ b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 4, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", @@ -56,4 +57,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json b/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json index a1621422..de1a1bec 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json @@ -8,8 +8,6 @@ "EnableWindowing": true, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "ddr3_single_dev", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.json b/DRAMSys/library/resources/configs/simulator/ddr3.json index 4e9faadc..99ccdb45 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "ddr3", "SimulationProgressBar": true, diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json b/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json index fd35bdee..d885c677 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json @@ -8,8 +8,6 @@ "EnableWindowing": true, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "ddr3", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": true, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json b/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json index 2b813f99..e148c3aa 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json @@ -8,8 +8,6 @@ "EnableWindowing": true, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "ddr3", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json b/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json index 72ebcf9b..c0b12f97 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json @@ -8,8 +8,6 @@ "EnableWindowing": true, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "ddr3", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr4.json b/DRAMSys/library/resources/configs/simulator/ddr4.json index 8e62e680..05cd86e2 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr4.json +++ b/DRAMSys/library/resources/configs/simulator/ddr4.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "ddr4", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/hbm2.json b/DRAMSys/library/resources/configs/simulator/hbm2.json index 9589611f..608aec41 100644 --- a/DRAMSys/library/resources/configs/simulator/hbm2.json +++ b/DRAMSys/library/resources/configs/simulator/hbm2.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "hbm2", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/lpddr4.json b/DRAMSys/library/resources/configs/simulator/lpddr4.json index fd8fe855..ee38bd66 100644 --- a/DRAMSys/library/resources/configs/simulator/lpddr4.json +++ b/DRAMSys/library/resources/configs/simulator/lpddr4.json @@ -8,7 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "lpddr4", @@ -18,4 +17,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/wideio.json b/DRAMSys/library/resources/configs/simulator/wideio.json index 4a0bd0ee..0c285f79 100644 --- a/DRAMSys/library/resources/configs/simulator/wideio.json +++ b/DRAMSys/library/resources/configs/simulator/wideio.json @@ -7,8 +7,6 @@ "EnableWindowing": true, "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 4, "PowerAnalysis": true, "SimulationName": "wideio", "SimulationProgressBar": true, @@ -17,4 +15,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/wideio_ecc.json b/DRAMSys/library/resources/configs/simulator/wideio_ecc.json index 216d3623..80acc3be 100644 --- a/DRAMSys/library/resources/configs/simulator/wideio_ecc.json +++ b/DRAMSys/library/resources/configs/simulator/wideio_ecc.json @@ -7,8 +7,6 @@ "EnableWindowing": true, "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "wideio_ecc", "SimulationProgressBar": true, @@ -17,4 +15,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/wideio_thermal.json b/DRAMSys/library/resources/configs/simulator/wideio_thermal.json index 6a47ff5b..b37cda4f 100644 --- a/DRAMSys/library/resources/configs/simulator/wideio_thermal.json +++ b/DRAMSys/library/resources/configs/simulator/wideio_thermal.json @@ -7,8 +7,6 @@ "EnableWindowing": true, "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 4, "PowerAnalysis": true, "SimulationName": "wideio", "SimulationProgressBar": true, @@ -17,4 +15,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json b/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json index 2da01ceb..5eea8b88 100644 --- a/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json +++ b/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json @@ -6,7 +6,7 @@ "RespQueue": "Fifo", "RefreshPolicy": "Rankwise", "RefreshMode": 1, - "RefreshMaxPostponed": 128, - "RefreshMaxPulledin": 128, + "RefreshMaxPostponed": 8, + "RefreshMaxPulledin": 8, "PowerDownPolicy": "NoPowerDown", "PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json index 5014ff9a..933baeba 100644 --- a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json +++ b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json @@ -10,7 +10,6 @@ "nbrOfChannels": 1, "nbrOfRows": 32768, "width": 64, - "NumberOfDevicesOnDIMM": 1, "NumberOfMemChannels": 1 }, "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", diff --git a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json index 08e13043..0c90c3ca 100644 --- a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -8,8 +8,8 @@ "nbrOfRanks": 2, "nbrOfChannels": 1, "nbrOfRows": 16384, - "width": 8, - "nbrOfDevicesOnDIMM": 8 + "width": 64, + "nbrOfDevicesOnDIMM": 1 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", "memoryType": "DDR3", From 5cbfa36339d5b73788e0b330d490b3c30104784e Mon Sep 17 00:00:00 2001 From: scorrea Date: Thu, 18 Jun 2020 12:39:50 +0200 Subject: [PATCH 09/53] PAGE POLICIES AND TRACES MODIFIED --- DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json | 2 +- DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json b/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json index 5eea8b88..01603197 100644 --- a/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json +++ b/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json @@ -1,5 +1,5 @@ {"mcconfig": { - "PagePolicy": "Open", + "PagePolicy": "ClosedAdaptive", "Scheduler": "FrFcfs", "RequestBufferSize": 8, "CmdMux": "Oldest", diff --git a/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json b/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json index 712e1c96..59b55965 100644 --- a/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json +++ b/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json @@ -1,4 +1,4 @@ -{"mcconfig": {"PagePolicy": "Open", +{"mcconfig": {"PagePolicy": "OpenAdaptive", "Scheduler": "Fifo", "RequestBufferSize": 8, "CmdMux": "Oldest", From 81c67fb1d3491ba983029f949fa9e7d41f0bf7b1 Mon Sep 17 00:00:00 2001 From: scorrea Date: Thu, 18 Jun 2020 15:45:27 +0200 Subject: [PATCH 10/53] NumberOfMemChannels to nbrOfChannels --- DRAMSys/library/resources/configs/memspecs/HBM2.json | 2 +- .../configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json | 2 +- .../configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json | 2 +- .../configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json | 4 ++-- .../configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json | 4 ++-- .../configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json | 2 +- .../configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json | 2 +- .../configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json | 2 +- .../configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json | 2 +- .../configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json | 2 +- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json | 4 ++-- .../memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json | 4 ++-- .../configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 4 ++-- .../configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json | 4 ++-- .../configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json | 4 ++-- .../configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json | 2 +- .../configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json | 2 +- .../configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json | 2 +- .../configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json | 2 +- .../configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json | 4 ++-- .../configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json | 4 ++-- .../configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json | 2 +- .../configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json | 2 +- .../configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json | 2 +- .../memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json | 4 ++-- .../memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json | 4 ++-- .../library/resources/configs/memspecs/memspec_ranktest.json | 2 +- 48 files changed, 80 insertions(+), 80 deletions(-) diff --git a/DRAMSys/library/resources/configs/memspecs/HBM2.json b/DRAMSys/library/resources/configs/memspecs/HBM2.json index bc9faa23..0f60243d 100644 --- a/DRAMSys/library/resources/configs/memspecs/HBM2.json +++ b/DRAMSys/library/resources/configs/memspecs/HBM2.json @@ -9,7 +9,7 @@ "nbrOfRanks": 2, "nbrOfRows": 32768, "width": 64, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", "memoryType": "HBM2", diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json index 17630099..114a76fb 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 4096, "width": 128, - "NumberOfMemChannels": 4 + "nbrOfChannels": 4 }, "memoryId": "JEDEC_256Mb_WIDEIO_SDR-200_128bit", "memoryType": "WIDEIO_SDR", diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json index 7f576e12..8ef5ffe8 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 4096, "width": 128, - "NumberOfMemChannels": 4 + "nbrOfChannels": 4 }, "memoryId": "JEDEC_256Mb_WIDEIO_SDR-266_128bit", "memoryType": "WIDEIO_SDR", diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json index db212fc7..8343c6f8 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json @@ -9,8 +9,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json index 9ea5ca87..1e16ea82 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json @@ -9,8 +9,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A", "memoryType": "DDR4", diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json index 29e9f3d6..04886e6b 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 64, - "NumberOfMemChannels": 4 + "nbrOfChannels": 4 }, "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-400_64bit", "memoryType": "WIDEIO2", diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json index 16f3546f..fc6aab68 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 64, - "NumberOfMemChannels": 4 + "nbrOfChannels": 4 }, "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-533_64bit", "memoryType": "WIDEIO2", diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json index 6504cd54..03008970 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 65536, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", "memoryType": "LPDDR4", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json index 42692386..60ef5c90 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR2-1066_16bit_H", "memoryType": "DDR2", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json index 3cbdec2d..77317ff8 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR2-800_16bit_H", "memoryType": "DDR2", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json index 0e15b9b3..06f79649 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json index f6557d3d..dfd064bf 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_2s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json index f8b477bb..8a40d4d0 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_3s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json index fe0feff6..989c7697 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_mu", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json index 549f79ae..5a96131d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json index fb5a2a58..4ef0bc5b 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_2s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json index 378722ed..c28ed4b3 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_3s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json index a79e2ea0..16d6d572 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_mu", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json index fca362ca..9d4d682c 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json index f193410e..379cd55d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_2s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json index 69084ebe..e3a00e86 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_3s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json index 9515ac0d..fd672487 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json index eed0f3b5..061219e6 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_mu", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json index 9be74831..ceace84b 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-800_8bit_G", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json index 8d85c957..947f6aa4 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -8,8 +8,8 @@ "nbrOfRanks": 2, "nbrOfRows": 16384, "width": 64, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json index 589c2ef7..4a249d45 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json @@ -8,8 +8,8 @@ "nbrOfRanks": 2, "nbrOfRows": 16384, "width": 64, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_G_UDIMM", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json index 4b665ba4..c9927028 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json @@ -8,8 +8,8 @@ "nbrOfRanks": 2, "nbrOfRows": 16384, "width": 64, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1333_64bit_D_SODIMM", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json index f52937e5..cfca2ccd 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json @@ -8,8 +8,8 @@ "nbrOfRanks": 2, "nbrOfRows": 16384, "width": 64, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1600_64bit_G_UDIMM", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json index 8247a00d..bb451167 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json index 067f826b..7ac094bc 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_2s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json index 2fba0c69..f16c8d27 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_3s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json index ada0ddbd..e962654a 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_mu", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json index c52f37bf..d404eba9 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json index a0a6e4ea..949cd56e 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_2s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json index 14bf56fa..2da4909c 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_3s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json index 2809f069..dfc21103 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_mu", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json index 579d540d..f7c989f9 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR-266_16bit_A", "memoryType": "LPDDR", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json index 6038029c..2e271810 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR-333_16bit_A", "memoryType": "LPDDR", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json index bb424df9..638afb58 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR2-1066-S4_16bit_A", "memoryType": "LPDDR2", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json index 4b6dbcf8..fa1a357c 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR2-800-S4_16bit_A", "memoryType": "LPDDR2", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json index 9d837139..7afe6d81 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -9,8 +9,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json index b1160755..0406d803 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json @@ -9,8 +9,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A", "memoryType": "DDR4", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json index 025531d1..9bee9f8b 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 32, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_LPDDR3-1333_32bit_A", "memoryType": "LPDDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json index a9e32fdd..87f5047e 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 32, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_LPDDR3-1600_32bit_A", "memoryType": "LPDDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json index 9faeea25..1d61ae45 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 49152, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_6Gb_LPDDR3-3200_16bit_A", "memoryType": "LPDDR4", diff --git a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json index 628077a9..2706f93d 100644 --- a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, - "NumberOfMemChannels": 1, - "NumberOfDevicesOnDIMM": 1, + "nbrOfChannels": 1, + "nbrOfDevicesOnDIMM": 1, }, "memoryId": "SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json index 7cb2625c..a58d953a 100644 --- a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 16, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json index b7d49c2a..3faa3399 100644 --- a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json +++ b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json @@ -8,7 +8,7 @@ "nbrOfRanks": 4, "nbrOfRows": 16384, "width": 8, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", From 54f3285b17bebbf28580f00034edc6f36c653891 Mon Sep 17 00:00:00 2001 From: scorrea Date: Sat, 20 Jun 2020 16:12:35 +0200 Subject: [PATCH 11/53] HBM2 test to dual-channel/ DDR2 memspecs updated --- .../MICRON_1Gb_DDR2-1066_16bit_H.json | 1 + .../memspecs/MICRON_1Gb_DDR2-800_16bit_H.json | 1 + .../configs/amconfigs/am_hbm2_8Gb_pc_brc.json | 23 ++++++++++--------- DRAMSys/tests/HBM2/configs/memspecs/HBM2.json | 7 +++--- 4 files changed, 17 insertions(+), 15 deletions(-) diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json index 60ef5c90..0554838d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json @@ -8,6 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, + "nbrOfDevicesOnDIMM": 4, "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR2-1066_16bit_H", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json index 77317ff8..d54ddb75 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json @@ -8,6 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, + "nbrOfDevicesOnDIMM": 4, "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR2-800_16bit_H", diff --git a/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json b/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json index 354217a5..c9362ea4 100644 --- a/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json +++ b/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json @@ -1,32 +1,32 @@ { "CONGEN": { - "RANK_BIT":[ - 29 + "CHANNEL_BIT":[ + 30 ], "BANKGROUP_BIT":[ - 27, - 28 + 28, + 29 ], "BANK_BIT": [ - 25, - 26 + 26, + 27 ], "BYTE_BIT": [ 0, 1, - 2 + 2, + 3 ], "COLUMN_BIT": [ - 3, 4, 5, 6, 7, 8, - 9 + 9, + 10 ], "ROW_BIT": [ - 10, 11, 12, 13, @@ -40,7 +40,8 @@ 21, 22, 23, - 24 + 24, + 25 ] } } diff --git a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json index 933baeba..c10d1242 100644 --- a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json +++ b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json @@ -6,11 +6,10 @@ "nbrOfBankGroups": 4, "nbrOfBanks": 16, "nbrOfColumns": 128, - "nbrOfRanks": 2, - "nbrOfChannels": 1, + "nbrOfRanks": 1, + "nbrOfChannels": 2, "nbrOfRows": 32768, - "width": 64, - "NumberOfMemChannels": 1 + "width": 128 }, "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", "memoryType": "HBM2", From c016959d50498e706857fd70b51c5536c00eb5c5 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 23 Jun 2020 11:09:17 +0200 Subject: [PATCH 12/53] traceAnalyzer tests excluded from ci tests --- DRAMSys/tests/DDR4/ci.yml | 4 ++-- DRAMSys/tests/HBM2/ci.yml | 6 ++++-- DRAMSys/tests/ddr3_multirank/ci.yml | 4 ++-- DRAMSys/tests/lpddr4/ci.yml | 4 ++-- 4 files changed, 10 insertions(+), 8 deletions(-) diff --git a/DRAMSys/tests/DDR4/ci.yml b/DRAMSys/tests/DDR4/ci.yml index d6226908..94dc5d4c 100644 --- a/DRAMSys/tests/DDR4/ci.yml +++ b/DRAMSys/tests/DDR4/ci.yml @@ -10,8 +10,8 @@ example_ddr4: - ls -lah ../../DRAMSys/tests/DDR4/expected/ - sqldiff ../../DRAMSys/tests/DDR4/expected/ddr4-bankgrp_ddr4_ch0.tdb ddr4-bankgrp_ddr4_ch0.tdb - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR4/expected/ddr4-bankgrp_ddr4_ch0.tdb ddr4-bankgrp_ddr4_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr4-bankgrp_ddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + #- cd ../traceAnalyzer + #- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr4-bankgrp_ddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi # Run Code Coverage - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out diff --git a/DRAMSys/tests/HBM2/ci.yml b/DRAMSys/tests/HBM2/ci.yml index fb9474a1..80a4b981 100644 --- a/DRAMSys/tests/HBM2/ci.yml +++ b/DRAMSys/tests/HBM2/ci.yml @@ -10,8 +10,10 @@ example_HBM2: - ls -lah ../../DRAMSys/tests/HBM2/expected/ - sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb - perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/hbm2-example_hbm2_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + - sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb + - perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb` eq "") {exit(0)} else {exit(-1)}' + #- cd ../traceAnalyzer + #- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/hbm2-example_hbm2_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi # Run Code Coverage - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out diff --git a/DRAMSys/tests/ddr3_multirank/ci.yml b/DRAMSys/tests/ddr3_multirank/ci.yml index da90393a..941a2aee 100644 --- a/DRAMSys/tests/ddr3_multirank/ci.yml +++ b/DRAMSys/tests/ddr3_multirank/ci.yml @@ -10,8 +10,8 @@ example_ddr3: - ls -lah ../../DRAMSys/tests/ddr3_multirank/expected/ - sqldiff ../../DRAMSys/tests/ddr3_multirank/expected/ddr3-dual-rank_ddr3_ch0.tdb ddr3-dual-rank_ddr3_ch0.tdb - perl -e 'if(`sqldiff ../../DRAMSys/tests/ddr3_multirank/expected/ddr3-dual-rank_ddr3_ch0.tdb ddr3-dual-rank_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3_multirank_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + #- cd ../traceAnalyzer + #- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3_multirank_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi # Run Code Coverage - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out diff --git a/DRAMSys/tests/lpddr4/ci.yml b/DRAMSys/tests/lpddr4/ci.yml index 40860f3f..ff811142 100644 --- a/DRAMSys/tests/lpddr4/ci.yml +++ b/DRAMSys/tests/lpddr4/ci.yml @@ -10,8 +10,8 @@ example_lpddr4: - ls -lah ../../DRAMSys/tests/lpddr4/expected/ - sqldiff ../../DRAMSys/tests/lpddr4/expected/lpddr4-example_lpddr4_ch0.tdb lpddr4-example_lpddr4_ch0.tdb - perl -e 'if(`sqldiff ../../DRAMSys/tests/lpddr4/expected/lpddr4-example_lpddr4_ch0.tdb lpddr4-example_lpddr4_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/lpddr4-example_lpddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + #- cd ../traceAnalyzer + #- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/lpddr4-example_lpddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi # Run Code Coverage - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out From 26c2c7f66fe3aa78ca2adaa942edc5cb140d2684 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 23 Jun 2020 11:45:54 +0200 Subject: [PATCH 13/53] HBM2 ci.yml correction --- DRAMSys/tests/HBM2/ci.yml | 54 +++++++++++++++++---------------------- 1 file changed, 24 insertions(+), 30 deletions(-) diff --git a/DRAMSys/tests/HBM2/ci.yml b/DRAMSys/tests/HBM2/ci.yml index 80a4b981..1f34b6d1 100644 --- a/DRAMSys/tests/HBM2/ci.yml +++ b/DRAMSys/tests/HBM2/ci.yml @@ -1,31 +1,25 @@ -# HBM2 test with 4 bank groups, 2 trace players, fifo strict scheduler and closed pg policy.: -example_HBM2: - stage: HBM2 - script: - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/HBM2/simulations/hbm2-example.json ../../DRAMSys/tests/HBM2/ - - ls -lah - - ls -lah ../../DRAMSys/tests/HBM2/expected/ - - sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb - - perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb - - perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb` eq "") {exit(0)} else {exit(-1)}' - #- cd ../traceAnalyzer - #- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/hbm2-example_hbm2_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - # Run Code Coverage - - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out - - cache: - key: build - paths: - - build/ - policy: pull - - artifacts: - paths: - - build/simulator/hbm2-example_hbm2_ch0.tdb - - coverage/${CI_JOB_NAME}.out - expire_in: 2 days +example_HBM2: + artifacts: + expire_in: "2 days" + paths: + - build/simulator/hbm2-example_hbm2_ch0.tdb + - "coverage/${CI_JOB_NAME}.out" + cache: + key: build + paths: + - build/ + policy: pull + script: + - "export GCOV_PREFIX=$(pwd)" + - "export GCOV_PREFIX_STRIP=$(pwd | awk -F\"/\" '{print NF-1}')" + - "cd build/simulator" + - "./DRAMSys ../../DRAMSys/tests/HBM2/simulations/hbm2-example.json ../../DRAMSys/tests/HBM2/" + - "ls -lah" + - "ls -lah ../../DRAMSys/tests/HBM2/expected/" + - "sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb" + - "perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb` eq \"\") {exit(0)} else {exit(-1)}'" + - "sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb" + - "perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb` eq \"\") {exit(0)} else {exit(-1)}'" + - "lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out" + stage: HBM2 From 4cf1f2c0b4cebee0d80d81870e72247ba0627d19 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 23 Jun 2020 12:07:02 +0200 Subject: [PATCH 14/53] .tdb in expected folders excluded from gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 99b20805..118c019c 100644 --- a/.gitignore +++ b/.gitignore @@ -5,6 +5,7 @@ /dram/build *.user *.tdb +!/DRAMSys/tests/*/expected/*.tdb *.tdb-journal *.out /build-simulation From 2e5483e122f7b3b24b9fb2e8c750208bb057f22b Mon Sep 17 00:00:00 2001 From: scorrea Date: Wed, 24 Jun 2020 16:15:43 +0200 Subject: [PATCH 15/53] ddr3 ci.yml file corrected --- DRAMSys/tests/ddr3_multirank/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DRAMSys/tests/ddr3_multirank/ci.yml b/DRAMSys/tests/ddr3_multirank/ci.yml index 941a2aee..ea32584e 100644 --- a/DRAMSys/tests/ddr3_multirank/ci.yml +++ b/DRAMSys/tests/ddr3_multirank/ci.yml @@ -5,7 +5,7 @@ example_ddr3: - export GCOV_PREFIX=$(pwd) - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/ddr3_multirank/ddr3-example.json ../../DRAMSys/tests/ddr3_multirank/ + - ./DRAMSys ../../DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json ../../DRAMSys/tests/ddr3_multirank/ - ls -lah - ls -lah ../../DRAMSys/tests/ddr3_multirank/expected/ - sqldiff ../../DRAMSys/tests/ddr3_multirank/expected/ddr3-dual-rank_ddr3_ch0.tdb ddr3-dual-rank_ddr3_ch0.tdb From 542a7d9f3216f289ae6696f24a3df605cbb598fe Mon Sep 17 00:00:00 2001 From: scorrea Date: Wed, 24 Jun 2020 17:53:56 +0200 Subject: [PATCH 16/53] gcov option passed to GCC --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 800215b0..76dbafb4 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,7 +20,7 @@ build: - rm -rf build - mkdir -p build - cd build - - cmake ../DRAMSys + - cmake -Wl,-fprofile-arcs,-ftest-coverage ../DRAMSys - make -j16 - find . -name "*.o" -type f -delete - rm -rf ${CI_PROJECT_DIR}/coverage From 8ed64a85cfa05f161692a72b8bc882e77fbd7422 Mon Sep 17 00:00:00 2001 From: scorrea Date: Wed, 24 Jun 2020 18:05:01 +0200 Subject: [PATCH 17/53] --coverage option --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 76dbafb4..ae825116 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,7 +20,7 @@ build: - rm -rf build - mkdir -p build - cd build - - cmake -Wl,-fprofile-arcs,-ftest-coverage ../DRAMSys + - cmake --coverage ../DRAMSys - make -j16 - find . -name "*.o" -type f -delete - rm -rf ${CI_PROJECT_DIR}/coverage From 5a75a627609afa9263360747786ad9cf740b56a0 Mon Sep 17 00:00:00 2001 From: scorrea Date: Wed, 24 Jun 2020 18:35:50 +0200 Subject: [PATCH 18/53] coverage flags changed --- .gitlab-ci.yml | 2 +- DRAMSys/CMakeLists.txt | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index ae825116..800215b0 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,7 +20,7 @@ build: - rm -rf build - mkdir -p build - cd build - - cmake --coverage ../DRAMSys + - cmake ../DRAMSys - make -j16 - find . -name "*.o" -type f -delete - rm -rf ${CI_PROJECT_DIR}/coverage diff --git a/DRAMSys/CMakeLists.txt b/DRAMSys/CMakeLists.txt index 6a50c48c..f5cb1045 100644 --- a/DRAMSys/CMakeLists.txt +++ b/DRAMSys/CMakeLists.txt @@ -39,6 +39,11 @@ project(DRAMSys) set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows") +SET(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") +SET(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") +SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) +SET( CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") + # Add DRAMSysLibrary: add_subdirectory(library) @@ -54,3 +59,4 @@ add_subdirectory(simulator) if(DEFINED ENV{GEM5}) add_subdirectory(gem5) endif() + From 416b1bbcc717d8b447fbe76d16753b3ff0e44510 Mon Sep 17 00:00:00 2001 From: scorrea Date: Fri, 26 Jun 2020 09:43:13 +0200 Subject: [PATCH 19/53] coverage added to CMakelists --- DRAMSys/CMakeLists.txt | 2 +- DRAMSys/library/CMakeLists.txt | 6 ++++++ DRAMSys/simulator/CMakeLists.txt | 5 +++++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/DRAMSys/CMakeLists.txt b/DRAMSys/CMakeLists.txt index f5cb1045..ec99b946 100644 --- a/DRAMSys/CMakeLists.txt +++ b/DRAMSys/CMakeLists.txt @@ -38,12 +38,12 @@ project(DRAMSys) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows") - SET(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") SET(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) SET( CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") + # Add DRAMSysLibrary: add_subdirectory(library) diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index d15862ed..a8301da7 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -38,6 +38,12 @@ project(DRAMSysLibrary) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH="CMAKE_SH-NOTFOUND") +SET(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") +SET(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") +SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) +SET( CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") + + # Add DRAMPower: add_subdirectory(src/common/third_party/DRAMPower) diff --git a/DRAMSys/simulator/CMakeLists.txt b/DRAMSys/simulator/CMakeLists.txt index 23c68f3a..fad8af38 100644 --- a/DRAMSys/simulator/CMakeLists.txt +++ b/DRAMSys/simulator/CMakeLists.txt @@ -38,6 +38,11 @@ project(DRAMSysSimulator) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH="CMAKE_SH-NOTFOUND") +SET(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") +SET(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") +SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) +SET( CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") + if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/../library/src/simulation/DRAMSysRecordable.cpp) add_definitions(-DRECORDING) From 1751e0c6cd92a6f4171471a0e85607398e2967a8 Mon Sep 17 00:00:00 2001 From: scorrea Date: Fri, 26 Jun 2020 11:22:53 +0200 Subject: [PATCH 20/53] ci build and path updated --- .gitlab-ci.yml | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 800215b0..e77b5f89 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -25,6 +25,12 @@ build: - find . -name "*.o" -type f -delete - rm -rf ${CI_PROJECT_DIR}/coverage - mkdir -p ${CI_PROJECT_DIR}/coverage + - cd ${CI_PROJECT_DIR} + - export GCOV_PREFIX=$(pwd) + - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - lcov -q -c --initial --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR} -o ${CI_PROJECT_DIR}/coverage/base.out + + cache: key: build @@ -34,21 +40,28 @@ build: artifacts: paths: - - coverage/ + - coverage/base.out coverage: stage: Coverage coverage: '/Total:\|(\d+\.?\d+\%)/' script: - # delete all empty files since they produce errors + # delete all empty files since they produce errors - find coverage -size 0 -type f -delete - ls coverage/ -lah - - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - - lcov --list coverage/final.out + - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out + - lcov --remove coverage/final.out '*/systemc*/include/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out + - lcov --list coverage/final_dramsys.out + # Create html + - mkdir ${CI_PROJECT_DIR}/html + - genhtml --prefix ${CI_PROJECT_DIR} --ignore-errors source coverage/final_dramsys.out --legend --title "`git log | head | grep commit`" --output-directory=html/ + artifacts: paths: - coverage/final.out + - coverage/final_drasys.out + -html/ include: From 3c00374d39a81c15206f97275d4228b28798b885 Mon Sep 17 00:00:00 2001 From: scorrea Date: Fri, 26 Jun 2020 11:29:22 +0200 Subject: [PATCH 21/53] ci build and path updated --- .gitlab-ci.yml => gitlab-ci.yml | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) rename .gitlab-ci.yml => gitlab-ci.yml (89%) diff --git a/.gitlab-ci.yml b/gitlab-ci.yml similarity index 89% rename from .gitlab-ci.yml rename to gitlab-ci.yml index e77b5f89..5ca5a2f2 100644 --- a/.gitlab-ci.yml +++ b/gitlab-ci.yml @@ -20,18 +20,16 @@ build: - rm -rf build - mkdir -p build - cd build - - cmake ../DRAMSys - - make -j16 + - qmake ../DRAMSys/DRAMSys.pro + - make -j4 - find . -name "*.o" -type f -delete - - rm -rf ${CI_PROJECT_DIR}/coverage + # Create Base file to cover all lines - mkdir -p ${CI_PROJECT_DIR}/coverage - cd ${CI_PROJECT_DIR} - export GCOV_PREFIX=$(pwd) - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - lcov -q -c --initial --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR} -o ${CI_PROJECT_DIR}/coverage/base.out - - cache: key: build paths: @@ -41,12 +39,12 @@ build: artifacts: paths: - coverage/base.out - + coverage: stage: Coverage coverage: '/Total:\|(\d+\.?\d+\%)/' script: - # delete all empty files since they produce errors + # delete all empty files since they produce errors - find coverage -size 0 -type f -delete - ls coverage/ -lah - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out @@ -56,13 +54,11 @@ coverage: - mkdir ${CI_PROJECT_DIR}/html - genhtml --prefix ${CI_PROJECT_DIR} --ignore-errors source coverage/final_dramsys.out --legend --title "`git log | head | grep commit`" --output-directory=html/ - artifacts: paths: - coverage/final.out - - coverage/final_drasys.out - -html/ - + - coverage/final_dramsys.out + - html/ include: - '/DRAMSys/tests/lpddr4/ci.yml' From 79574c83ecf66fb0668b26a470e55fba9d519b05 Mon Sep 17 00:00:00 2001 From: scorrea Date: Fri, 26 Jun 2020 11:31:55 +0200 Subject: [PATCH 22/53] ci build and path updated2 --- gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gitlab-ci.yml b/gitlab-ci.yml index 5ca5a2f2..070986b1 100644 --- a/gitlab-ci.yml +++ b/gitlab-ci.yml @@ -65,4 +65,4 @@ include: - '/DRAMSys/tests/ddr3_multirank/ci.yml' - '/DRAMSys/tests/DDR4/ci.yml' - '/DRAMSys/tests/HBM2/ci.yml' - #- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used + #- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used From c97c3b87f69fd0d2ba7286ae4b4b1d8a3567e35f Mon Sep 17 00:00:00 2001 From: scorrea Date: Fri, 26 Jun 2020 11:34:35 +0200 Subject: [PATCH 23/53] ci build and path updated3 --- gitlab-ci.yml => .gitlab-ci.yml | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename gitlab-ci.yml => .gitlab-ci.yml (100%) diff --git a/gitlab-ci.yml b/.gitlab-ci.yml similarity index 100% rename from gitlab-ci.yml rename to .gitlab-ci.yml From bc8f2aaecaafb378f65f59e509938e4c98cf424e Mon Sep 17 00:00:00 2001 From: scorrea Date: Fri, 26 Jun 2020 11:44:10 +0200 Subject: [PATCH 24/53] ci build and path updated4 --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 070986b1..3acd0825 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,7 +20,7 @@ build: - rm -rf build - mkdir -p build - cd build - - qmake ../DRAMSys/DRAMSys.pro + - cmake ../DRAMSys - make -j4 - find . -name "*.o" -type f -delete # Create Base file to cover all lines From 066f22c798271321a945fbc04637b5598cfed0d6 Mon Sep 17 00:00:00 2001 From: scorrea Date: Fri, 26 Jun 2020 15:56:22 +0200 Subject: [PATCH 25/53] cov path modified --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 3acd0825..7d147bbc 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -25,7 +25,7 @@ build: - find . -name "*.o" -type f -delete # Create Base file to cover all lines - mkdir -p ${CI_PROJECT_DIR}/coverage - - cd ${CI_PROJECT_DIR} + - cd ${CI_PROJECT_DIR}/coverage - export GCOV_PREFIX=$(pwd) - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - lcov -q -c --initial --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR} -o ${CI_PROJECT_DIR}/coverage/base.out From 117937f4aaddeacbe47427f6958c3093b4e89512 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 30 Jun 2020 11:15:46 +0200 Subject: [PATCH 26/53] Includes flag for coverage build. --- .gitlab-ci.yml | 3 ++- DRAMSys/CMakeLists.txt | 12 +++++++----- DRAMSys/library/CMakeLists.txt | 12 ++++++------ DRAMSys/simulator/CMakeLists.txt | 11 ++++++----- DRAMSys/tests/ddr3_multirank/ci.yml | 2 +- 5 files changed, 22 insertions(+), 18 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 7d147bbc..8cee2556 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,8 +20,9 @@ build: - rm -rf build - mkdir -p build - cd build + - export COVERAGE=true - cmake ../DRAMSys - - make -j4 + - make -j 24 - find . -name "*.o" -type f -delete # Create Base file to cover all lines - mkdir -p ${CI_PROJECT_DIR}/coverage diff --git a/DRAMSys/CMakeLists.txt b/DRAMSys/CMakeLists.txt index ec99b946..ccb2df9f 100644 --- a/DRAMSys/CMakeLists.txt +++ b/DRAMSys/CMakeLists.txt @@ -38,11 +38,13 @@ project(DRAMSys) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows") -SET(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") -SET(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") -SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) -SET( CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") - +if(DEFINED ENV{COVERAGE}) + set(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") + set(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}") + set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") + message("-- Coverage check enabled") +endif() # Add DRAMSysLibrary: add_subdirectory(library) diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index a8301da7..a84e0f29 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -38,12 +38,12 @@ project(DRAMSysLibrary) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH="CMAKE_SH-NOTFOUND") -SET(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") -SET(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") -SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) -SET( CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") - - +if(DEFINED ENV{COVERAGE}) + set(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") + set(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}") + set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") +endif() # Add DRAMPower: add_subdirectory(src/common/third_party/DRAMPower) diff --git a/DRAMSys/simulator/CMakeLists.txt b/DRAMSys/simulator/CMakeLists.txt index fad8af38..3018a14f 100644 --- a/DRAMSys/simulator/CMakeLists.txt +++ b/DRAMSys/simulator/CMakeLists.txt @@ -38,11 +38,12 @@ project(DRAMSysSimulator) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH="CMAKE_SH-NOTFOUND") -SET(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") -SET(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") -SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) -SET( CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") - +if(DEFINED ENV{COVERAGE}) + set(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") + set(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}") + set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") +endif() if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/../library/src/simulation/DRAMSysRecordable.cpp) add_definitions(-DRECORDING) diff --git a/DRAMSys/tests/ddr3_multirank/ci.yml b/DRAMSys/tests/ddr3_multirank/ci.yml index ea32584e..254c0e62 100644 --- a/DRAMSys/tests/ddr3_multirank/ci.yml +++ b/DRAMSys/tests/ddr3_multirank/ci.yml @@ -23,7 +23,7 @@ example_ddr3: artifacts: paths: - - build/simulator/ddr3_multirank_ddr3_ch0.tdb + - build/simulator/ddr3-dual-rank_ddr3_ch0.tdb - coverage/${CI_JOB_NAME}.out expire_in: 2 days From 9241689b99552d2610bbf0fc02bb0a5cce28db24 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 12:33:12 +0200 Subject: [PATCH 27/53] cov test updated --- .gitlab-ci.yml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 7d147bbc..04fdd89e 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -47,18 +47,18 @@ coverage: # delete all empty files since they produce errors - find coverage -size 0 -type f -delete - ls coverage/ -lah - - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - - lcov --remove coverage/final.out '*/systemc*/include/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out + - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final_dramsys.out + - lcov --remove coverage/final.out '*/systemc*/include/*' '*/traceAnalyzer/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out - lcov --list coverage/final_dramsys.out # Create html - - mkdir ${CI_PROJECT_DIR}/html - - genhtml --prefix ${CI_PROJECT_DIR} --ignore-errors source coverage/final_dramsys.out --legend --title "`git log | head | grep commit`" --output-directory=html/ + #- mkdir ${CI_PROJECT_DIR}/html + #- genhtml --prefix ${CI_PROJECT_DIR} --ignore-errors source coverage/final_dramsys.out --legend --title "`git log | head | grep commit`" --output-directory=html/ artifacts: paths: - - coverage/final.out + #- coverage/final.out - coverage/final_dramsys.out - - html/ + #- html/ include: - '/DRAMSys/tests/lpddr4/ci.yml' From 5db27a8b17dbf1bd33fc5cd571485d6805547477 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 12:59:24 +0200 Subject: [PATCH 28/53] undone changes to cov test --- .gitlab-ci.yml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 83ae3ce9..72a8088a 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -48,18 +48,18 @@ coverage: # delete all empty files since they produce errors - find coverage -size 0 -type f -delete - ls coverage/ -lah - - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final_dramsys.out + - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - lcov --remove coverage/final.out '*/systemc*/include/*' '*/traceAnalyzer/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out - lcov --list coverage/final_dramsys.out # Create html - #- mkdir ${CI_PROJECT_DIR}/html - #- genhtml --prefix ${CI_PROJECT_DIR} --ignore-errors source coverage/final_dramsys.out --legend --title "`git log | head | grep commit`" --output-directory=html/ + - mkdir ${CI_PROJECT_DIR}/html + - genhtml --prefix ${CI_PROJECT_DIR} --ignore-errors source coverage/final_dramsys.out --legend --title "`git log | head | grep commit`" --output-directory=html/ artifacts: paths: - #- coverage/final.out + - coverage/final.out - coverage/final_dramsys.out - #- html/ + - html/ include: - '/DRAMSys/tests/lpddr4/ci.yml' From 153d68dee8fbbb0ab61a80d88dbe591a33ecf0b5 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 15:58:23 +0200 Subject: [PATCH 29/53] base file removed --- .gitlab-ci.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 72a8088a..a54fbd85 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -29,7 +29,6 @@ build: - cd ${CI_PROJECT_DIR}/coverage - export GCOV_PREFIX=$(pwd) - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - lcov -q -c --initial --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR} -o ${CI_PROJECT_DIR}/coverage/base.out cache: key: build From 6e8ea831c62701c2f620e9294a7eaad3969c721b Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 16:12:48 +0200 Subject: [PATCH 30/53] removed base.out before coverage eval --- .gitlab-ci.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index a54fbd85..0160fe3b 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -29,6 +29,7 @@ build: - cd ${CI_PROJECT_DIR}/coverage - export GCOV_PREFIX=$(pwd) - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - lcov -q -c --initial --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR} -o ${CI_PROJECT_DIR}/coverage/base.out cache: key: build @@ -46,6 +47,7 @@ coverage: script: # delete all empty files since they produce errors - find coverage -size 0 -type f -delete + - rm coverage/base.out - ls coverage/ -lah - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - lcov --remove coverage/final.out '*/systemc*/include/*' '*/traceAnalyzer/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out From f0d3a081c85287dd0097b4169d01232a3132dafa Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 17:07:51 +0200 Subject: [PATCH 31/53] .gitlab-ci.yml back to older version --- .gitlab-ci.yml | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 0160fe3b..30aa8890 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -24,12 +24,9 @@ build: - cmake ../DRAMSys - make -j 24 - find . -name "*.o" -type f -delete - # Create Base file to cover all lines + - rm -rf ${CI_PROJECT_DIR}/coverage - mkdir -p ${CI_PROJECT_DIR}/coverage - - cd ${CI_PROJECT_DIR}/coverage - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - lcov -q -c --initial --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR} -o ${CI_PROJECT_DIR}/coverage/base.out + cache: key: build @@ -39,7 +36,7 @@ build: artifacts: paths: - - coverage/base.out + - coverage/ coverage: stage: Coverage @@ -47,7 +44,6 @@ coverage: script: # delete all empty files since they produce errors - find coverage -size 0 -type f -delete - - rm coverage/base.out - ls coverage/ -lah - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - lcov --remove coverage/final.out '*/systemc*/include/*' '*/traceAnalyzer/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out From e98e1c49aaaf83815c1bb8416f6db30bc891af60 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 17:42:08 +0200 Subject: [PATCH 32/53] html removed --- .gitlab-ci.yml | 7 +- .../AddressDecoder.cpp.func-sort-c.html | 93 ++ .../src/common/AddressDecoder.cpp.func.html | 93 ++ .../src/common/AddressDecoder.cpp.gcov.html | 367 ++++++ .../common/AddressDecoder.h.func-sort-c.html | 81 ++ .../src/common/AddressDecoder.h.func.html | 81 ++ .../src/common/AddressDecoder.h.gcov.html | 144 +++ .../common/TlmRecorder.cpp.func-sort-c.html | 153 +++ .../src/common/TlmRecorder.cpp.func.html | 153 +++ .../src/common/TlmRecorder.cpp.gcov.html | 557 ++++++++ .../src/common/TlmRecorder.h.func-sort-c.html | 81 ++ .../src/common/TlmRecorder.h.func.html | 81 ++ .../src/common/TlmRecorder.h.gcov.html | 184 +++ .../dramExtensions.cpp.func-sort-c.html | 309 +++++ .../src/common/dramExtensions.cpp.func.html | 309 +++++ .../src/common/dramExtensions.cpp.gcov.html | 434 +++++++ .../common/dramExtensions.h.func-sort-c.html | 97 ++ .../src/common/dramExtensions.h.func.html | 97 ++ .../src/common/dramExtensions.h.gcov.html | 321 +++++ .../library/src/common/index-sort-f.html | 183 +++ .../library/src/common/index-sort-l.html | 183 +++ html/DRAMSys/library/src/common/index.html | 183 +++ ...2_base_protocol_checker.h.func-sort-c.html | 181 +++ .../tlm2_base_protocol_checker.h.func.html | 181 +++ .../tlm2_base_protocol_checker.h.gcov.html | 1128 +++++++++++++++++ .../src/common/utils.cpp.func-sort-c.html | 109 ++ .../library/src/common/utils.cpp.func.html | 109 ++ .../library/src/common/utils.cpp.gcov.html | 239 ++++ .../src/common/utils.h.func-sort-c.html | 85 ++ .../library/src/common/utils.h.func.html | 85 ++ .../library/src/common/utils.h.gcov.html | 187 +++ .../Configuration.cpp.func-sort-c.html | 113 ++ .../configuration/Configuration.cpp.func.html | 113 ++ .../configuration/Configuration.cpp.gcov.html | 397 ++++++ .../Configuration.h.func-sort-c.html | 93 ++ .../configuration/Configuration.h.func.html | 93 ++ .../configuration/Configuration.h.gcov.html | 147 +++ .../TemperatureSimConfig.h.func-sort-c.html | 85 ++ .../TemperatureSimConfig.h.func.html | 85 ++ .../TemperatureSimConfig.h.gcov.html | 207 +++ .../src/configuration/index-sort-f.html | 123 ++ .../src/configuration/index-sort-l.html | 123 ++ .../library/src/configuration/index.html | 123 ++ .../memspec/MemSpec.cpp.func-sort-c.html | 97 ++ .../memspec/MemSpec.cpp.func.html | 97 ++ .../memspec/MemSpec.cpp.gcov.html | 161 +++ .../memspec/MemSpec.h.func-sort-c.html | 89 ++ .../configuration/memspec/MemSpec.h.func.html | 89 ++ .../configuration/memspec/MemSpec.h.gcov.html | 157 +++ .../memspec/MemSpecDDR3.cpp.func-sort-c.html | 109 ++ .../memspec/MemSpecDDR3.cpp.func.html | 109 ++ .../memspec/MemSpecDDR3.cpp.gcov.html | 225 ++++ .../memspec/MemSpecDDR3.h.func-sort-c.html | 89 ++ .../memspec/MemSpecDDR3.h.func.html | 89 ++ .../memspec/MemSpecDDR3.h.gcov.html | 127 ++ .../memspec/MemSpecDDR4.cpp.func-sort-c.html | 105 ++ .../memspec/MemSpecDDR4.cpp.func.html | 105 ++ .../memspec/MemSpecDDR4.cpp.gcov.html | 242 ++++ .../memspec/MemSpecDDR4.h.func-sort-c.html | 89 ++ .../memspec/MemSpecDDR4.h.func.html | 89 ++ .../memspec/MemSpecDDR4.h.gcov.html | 127 ++ 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html/DRAMSys/simulator/index-sort-l.html create mode 100644 html/DRAMSys/simulator/index.html create mode 100644 html/DRAMSys/simulator/main.cpp.func-sort-c.html create mode 100644 html/DRAMSys/simulator/main.cpp.func.html create mode 100644 html/DRAMSys/simulator/main.cpp.gcov.html create mode 100644 html/gcov.css create mode 100644 html/index-sort-f.html create mode 100644 html/index-sort-l.html create mode 100644 html/index.html diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 30aa8890..bb478fa4 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,9 +20,8 @@ build: - rm -rf build - mkdir -p build - cd build - - export COVERAGE=true - cmake ../DRAMSys - - make -j 24 + - make -j 16 - find . -name "*.o" -type f -delete - rm -rf ${CI_PROJECT_DIR}/coverage - mkdir -p ${CI_PROJECT_DIR}/coverage @@ -48,15 +47,11 @@ coverage: - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - lcov --remove coverage/final.out '*/systemc*/include/*' '*/traceAnalyzer/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out - lcov --list coverage/final_dramsys.out - # Create html - - mkdir ${CI_PROJECT_DIR}/html - - genhtml --prefix ${CI_PROJECT_DIR} --ignore-errors source coverage/final_dramsys.out --legend --title "`git log | head | grep commit`" --output-directory=html/ artifacts: paths: - coverage/final.out - coverage/final_dramsys.out - - html/ include: - '/DRAMSys/tests/lpddr4/ci.yml' diff --git a/html/DRAMSys/library/src/common/AddressDecoder.cpp.func-sort-c.html b/html/DRAMSys/library/src/common/AddressDecoder.cpp.func-sort-c.html new file mode 100644 index 00000000..a49c5700 --- /dev/null +++ b/html/DRAMSys/library/src/common/AddressDecoder.cpp.func-sort-c.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/AddressDecoder.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - AddressDecoder.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11313782.5 %
Date:2020-06-30 17:34:44Functions:77100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN14AddressDecoder23getUnsignedAttrFromJsonEN8nlohmann10basic_jsonISt3mapSt6vectorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEblmdSaNS0_14adl_serializerEEES9_30
_Z41__static_initialization_and_destruction_0ii30
_ZN14AddressDecoder5printEv30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/AddressDecoder.cpp.func.html b/html/DRAMSys/library/src/common/AddressDecoder.cpp.func.html new file mode 100644 index 00000000..08e0325a --- /dev/null +++ b/html/DRAMSys/library/src/common/AddressDecoder.cpp.func.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/AddressDecoder.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - AddressDecoder.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11313782.5 %
Date:2020-06-30 17:34:44Functions:77100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN14AddressDecoder23getUnsignedAttrFromJsonEN8nlohmann10basic_jsonISt3mapSt6vectorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEblmdSaNS0_14adl_serializerEEES9_30
_Z41__static_initialization_and_destruction_0ii30
_ZN14AddressDecoder5printEv30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/AddressDecoder.cpp.gcov.html b/html/DRAMSys/library/src/common/AddressDecoder.cpp.gcov.html new file mode 100644 index 00000000..9316d48d --- /dev/null +++ b/html/DRAMSys/library/src/common/AddressDecoder.cpp.gcov.html @@ -0,0 +1,367 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/AddressDecoder.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - AddressDecoder.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11313782.5 %
Date:2020-06-30 17:34:44Functions:77100.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
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+
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+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/AddressDecoder.h.func-sort-c.html b/html/DRAMSys/library/src/common/AddressDecoder.h.func-sort-c.html new file mode 100644 index 00000000..6b6b1b19 --- /dev/null +++ b/html/DRAMSys/library/src/common/AddressDecoder.h.func-sort-c.html @@ -0,0 +1,81 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/AddressDecoder.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - AddressDecoder.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:2450.0 %
Date:2020-06-30 17:34:44Functions:00-
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + +

Function Name Sort by function nameHit count Sort by hit count
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/AddressDecoder.h.func.html b/html/DRAMSys/library/src/common/AddressDecoder.h.func.html new file mode 100644 index 00000000..a738edb3 --- /dev/null +++ b/html/DRAMSys/library/src/common/AddressDecoder.h.func.html @@ -0,0 +1,81 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/AddressDecoder.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - AddressDecoder.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:2450.0 %
Date:2020-06-30 17:34:44Functions:00-
Legend: Lines: + hit + not hit +
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+ +
+ + + + + + +

Function Name Sort by function nameHit count Sort by hit count
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/AddressDecoder.h.gcov.html b/html/DRAMSys/library/src/common/AddressDecoder.h.gcov.html new file mode 100644 index 00000000..46d860b8 --- /dev/null +++ b/html/DRAMSys/library/src/common/AddressDecoder.h.gcov.html @@ -0,0 +1,144 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/AddressDecoder.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - AddressDecoder.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:2450.0 %
Date:2020-06-30 17:34:44Functions:00-
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
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+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/TlmRecorder.cpp.func-sort-c.html b/html/DRAMSys/library/src/common/TlmRecorder.cpp.func-sort-c.html new file mode 100644 index 00000000..2f95ce2b --- /dev/null +++ b/html/DRAMSys/library/src/common/TlmRecorder.cpp.func-sort-c.html @@ -0,0 +1,153 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/TlmRecorder.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - TlmRecorder.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:25227791.0 %
Date:2020-06-30 17:34:44Functions:232688.5 %
Legend: Lines: + hit + not hit +
+
+ +
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Function Name Sort by function nameHit count Sort by hit count
_ZN11TlmRecorder11recordPowerEdd0
_ZN11TlmRecorder22insertDebugMessageInDBENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKN7sc_core7sc_timeE0
_GLOBAL__sub_I__ZN11TlmRecorderC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES5_S5_30
_Z41__static_initialization_and_destruction_0ii30
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_ZN11TlmRecorder17executeSqlCommandENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE37
_ZN11TlmRecorder17insertGeneralInfoEv37
_ZN11TlmRecorder20insertCommandLengthsEv37
_ZN11TlmRecorder20prepareSqlStatementsEv37
_ZN11TlmRecorder33setUpTransactionTerminatingPhasesEv37
_ZN11TlmRecorder6openDBENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE37
_ZN11TlmRecorder16updateDataStrobeERKN7sc_core7sc_timeES3_RN3tlm19tlm_generic_payloadE252938
_ZN11TlmRecorder15insertRangeInDBEjRKN7sc_core7sc_timeES3_254719
_ZN11TlmRecorder21insertTransactionInDBERNS_11TransactionE254719
_ZN11TlmRecorder27removeTransactionFromSystemERN3tlm19tlm_generic_payloadE254719
_ZN11TlmRecorder26introduceTransactionSystemERN3tlm19tlm_generic_payloadE254778
_ZN11TlmRecorder15insertPhaseInDBENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKN7sc_core7sc_timeES9_j924402
_ZN11TlmRecorder11Transaction11setPhaseEndENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEN7sc_core7sc_timeE924511
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/TlmRecorder.cpp.func.html b/html/DRAMSys/library/src/common/TlmRecorder.cpp.func.html new file mode 100644 index 00000000..df73c4c7 --- /dev/null +++ b/html/DRAMSys/library/src/common/TlmRecorder.cpp.func.html @@ -0,0 +1,153 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/TlmRecorder.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - TlmRecorder.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:25227791.0 %
Date:2020-06-30 17:34:44Functions:232688.5 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN11TlmRecorderC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES5_S5_30
_Z41__static_initialization_and_destruction_0ii30
_ZN11TlmRecorder11Transaction11setPhaseEndENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEN7sc_core7sc_timeE924511
_ZN11TlmRecorder11recordPowerEdd0
_ZN11TlmRecorder15closeConnectionEv37
_ZN11TlmRecorder15insertPhaseInDBENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKN7sc_core7sc_timeES9_j924402
_ZN11TlmRecorder15insertRangeInDBEjRKN7sc_core7sc_timeES3_254719
_ZN11TlmRecorder16updateDataStrobeERKN7sc_core7sc_timeES3_RN3tlm19tlm_generic_payloadE252938
_ZN11TlmRecorder17executeSqlCommandENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE37
_ZN11TlmRecorder17insertGeneralInfoEv37
_ZN11TlmRecorder20insertCommandLengthsEv37
_ZN11TlmRecorder20prepareSqlStatementsEv37
_ZN11TlmRecorder21insertTransactionInDBERNS_11TransactionE254719
_ZN11TlmRecorder22insertDebugMessageInDBENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKN7sc_core7sc_timeE0
_ZN11TlmRecorder26introduceTransactionSystemERN3tlm19tlm_generic_payloadE254778
_ZN11TlmRecorder27removeTransactionFromSystemERN3tlm19tlm_generic_payloadE254719
_ZN11TlmRecorder33setUpTransactionTerminatingPhasesEv37
_ZN11TlmRecorder6openDBENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE37
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/TlmRecorder.cpp.gcov.html b/html/DRAMSys/library/src/common/TlmRecorder.cpp.gcov.html new file mode 100644 index 00000000..076215c9 --- /dev/null +++ b/html/DRAMSys/library/src/common/TlmRecorder.cpp.gcov.html @@ -0,0 +1,557 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/TlmRecorder.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - TlmRecorder.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:25227791.0 %
Date:2020-06-30 17:34:44Functions:232688.5 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/TlmRecorder.h.func-sort-c.html b/html/DRAMSys/library/src/common/TlmRecorder.h.func-sort-c.html new file mode 100644 index 00000000..20ef8334 --- /dev/null +++ b/html/DRAMSys/library/src/common/TlmRecorder.h.func-sort-c.html @@ -0,0 +1,81 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/TlmRecorder.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - TlmRecorder.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:77100.0 %
Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + +

Function Name Sort by function nameHit count Sort by hit count
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/TlmRecorder.h.func.html b/html/DRAMSys/library/src/common/TlmRecorder.h.func.html new file mode 100644 index 00000000..fc659479 --- /dev/null +++ b/html/DRAMSys/library/src/common/TlmRecorder.h.func.html @@ -0,0 +1,81 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/TlmRecorder.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - TlmRecorder.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:77100.0 %
Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + +

Function Name Sort by function nameHit count Sort by hit count
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/TlmRecorder.h.gcov.html b/html/DRAMSys/library/src/common/TlmRecorder.h.gcov.html new file mode 100644 index 00000000..922d76d6 --- /dev/null +++ b/html/DRAMSys/library/src/common/TlmRecorder.h.gcov.html @@ -0,0 +1,184 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/TlmRecorder.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - TlmRecorder.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:77100.0 %
Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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+      99     3698184 : /* EOF */
+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/dramExtensions.cpp.func-sort-c.html b/html/DRAMSys/library/src/common/dramExtensions.cpp.func-sort-c.html new file mode 100644 index 00000000..728812fd --- /dev/null +++ b/html/DRAMSys/library/src/common/dramExtensions.cpp.func-sort-c.html @@ -0,0 +1,309 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/dramExtensions.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - dramExtensions.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4713235.6 %
Date:2020-06-30 17:34:44Functions:215736.8 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
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_ZN13DramExtension10getChannelERKN3tlm19tlm_generic_payloadE0
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_ZN13DramExtension12getPayloadIDERKN3tlm19tlm_generic_payloadE0
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_ZN13DramExtension9getColumnERKN3tlm19tlm_generic_payloadE0
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_ZN13DramExtension9getThreadERKN3tlm19tlm_generic_payloadE0
_ZN19GenerationExtension19getTimeOfGenerationEPKN3tlm19tlm_generic_payloadE0
_ZN19GenerationExtension19getTimeOfGenerationERKN3tlm19tlm_generic_payloadE0
_ZN19GenerationExtension9copy_fromERKN3tlm18tlm_extension_baseE0
_ZN3RowppEv0
_ZNK13DramExtension14getBurstlengthEv0
_ZNK13DramExtension5cloneEv0
_ZNK19GenerationExtension5cloneEv0
_ZeqRK4BankS1_0
_ZeqRK4RankS1_0
_ZeqRK6ColumnS1_0
_ZeqRK6ThreadS1_0
_ZeqRK7ChannelS1_0
_ZeqRK9BankGroupS1_0
_ZltRK4BankS1_0
_ZltRK6ThreadS1_0
_ZneRK3RowS1_0
_ZneRK4BankS1_0
_ZneRK4RankS1_0
_ZneRK6ColumnS1_0
_ZneRK6ThreadS1_0
_ZneRK7ChannelS1_0
_ZneRK9BankGroupS1_0
_GLOBAL__sub_I__ZN13DramExtensionC2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN13DramExtensionC2ERK6ThreadRK4RankRK9BankGroupRK4BankRK3RowRK6Columnjm136
_ZN13DramExtensionC2ERK6ThreadRK7ChannelRK4RankRK9BankGroupRK4BankRK3RowRK6Columnjm252938
_ZN19GenerationExtension12getExtensionEPKN3tlm19tlm_generic_payloadE252938
_ZNK13DramExtension7getRankEv254719
_ZN13DramExtensionC2Ev254778
_ZN13DramExtension12getBankGroupEPKN3tlm19tlm_generic_payloadE418705
_ZN13DramExtension7getRankEPKN3tlm19tlm_generic_payloadE671643
_ZNK13DramExtension12getPayloadIDEv1011722
_ZN13DramExtension7getBankEPKN3tlm19tlm_generic_payloadE1177519
_ZNK13DramExtension12getBankGroupEv1685146
_ZNK13DramExtension6getRowEv1685146
_ZNK13DramExtension7getBankEv1685146
_ZNK13DramExtension9getColumnEv1685146
_ZN13DramExtension12getPayloadIDEPKN3tlm19tlm_generic_payloadE2404567
_ZNK13DramExtension10getChannelEv2696868
_ZNK13DramExtension9getThreadEv2951646
_ZN13DramExtension12getExtensionERKN3tlm19tlm_generic_payloadE12127284
_ZeqRK3RowS1_18361423
_ZN13DramExtension6getRowEPKN3tlm19tlm_generic_payloadE18522627
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/dramExtensions.cpp.func.html b/html/DRAMSys/library/src/common/dramExtensions.cpp.func.html new file mode 100644 index 00000000..fc89e8a4 --- /dev/null +++ b/html/DRAMSys/library/src/common/dramExtensions.cpp.func.html @@ -0,0 +1,309 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/dramExtensions.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - dramExtensions.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4713235.6 %
Date:2020-06-30 17:34:44Functions:215736.8 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN13DramExtensionC2Ev30
_Z41__static_initialization_and_destruction_0ii30
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_ZN13DramExtension10getChannelERKN3tlm19tlm_generic_payloadE0
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_ZN13DramExtension12getExtensionERKN3tlm19tlm_generic_payloadE12127284
_ZN13DramExtension12getPayloadIDEPKN3tlm19tlm_generic_payloadE2404567
_ZN13DramExtension12getPayloadIDERKN3tlm19tlm_generic_payloadE0
_ZN13DramExtension12incrementRowEv0
_ZN13DramExtension6getRowEPKN3tlm19tlm_generic_payloadE18522627
_ZN13DramExtension6getRowERKN3tlm19tlm_generic_payloadE0
_ZN13DramExtension7getBankEPKN3tlm19tlm_generic_payloadE1177519
_ZN13DramExtension7getBankERKN3tlm19tlm_generic_payloadE0
_ZN13DramExtension7getRankEPKN3tlm19tlm_generic_payloadE671643
_ZN13DramExtension7getRankERKN3tlm19tlm_generic_payloadE0
_ZN13DramExtension9copy_fromERKN3tlm18tlm_extension_baseE0
_ZN13DramExtension9getColumnEPKN3tlm19tlm_generic_payloadE0
_ZN13DramExtension9getColumnERKN3tlm19tlm_generic_payloadE0
_ZN13DramExtension9getThreadEPKN3tlm19tlm_generic_payloadE0
_ZN13DramExtension9getThreadERKN3tlm19tlm_generic_payloadE0
_ZN13DramExtensionC2ERK6ThreadRK4RankRK9BankGroupRK4BankRK3RowRK6Columnjm136
_ZN13DramExtensionC2ERK6ThreadRK7ChannelRK4RankRK9BankGroupRK4BankRK3RowRK6Columnjm252938
_ZN13DramExtensionC2Ev254778
_ZN19GenerationExtension12getExtensionEPKN3tlm19tlm_generic_payloadE252938
_ZN19GenerationExtension19getTimeOfGenerationEPKN3tlm19tlm_generic_payloadE0
_ZN19GenerationExtension19getTimeOfGenerationERKN3tlm19tlm_generic_payloadE0
_ZN19GenerationExtension9copy_fromERKN3tlm18tlm_extension_baseE0
_ZN3RowppEv0
_ZNK13DramExtension10getChannelEv2696868
_ZNK13DramExtension12getBankGroupEv1685146
_ZNK13DramExtension12getPayloadIDEv1011722
_ZNK13DramExtension14getBurstlengthEv0
_ZNK13DramExtension5cloneEv0
_ZNK13DramExtension6getRowEv1685146
_ZNK13DramExtension7getBankEv1685146
_ZNK13DramExtension7getRankEv254719
_ZNK13DramExtension9getColumnEv1685146
_ZNK13DramExtension9getThreadEv2951646
_ZNK19GenerationExtension5cloneEv0
_ZeqRK3RowS1_18361423
_ZeqRK4BankS1_0
_ZeqRK4RankS1_0
_ZeqRK6ColumnS1_0
_ZeqRK6ThreadS1_0
_ZeqRK7ChannelS1_0
_ZeqRK9BankGroupS1_0
_ZltRK4BankS1_0
_ZltRK6ThreadS1_0
_ZneRK3RowS1_0
_ZneRK4BankS1_0
_ZneRK4RankS1_0
_ZneRK6ColumnS1_0
_ZneRK6ThreadS1_0
_ZneRK7ChannelS1_0
_ZneRK9BankGroupS1_0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/dramExtensions.cpp.gcov.html b/html/DRAMSys/library/src/common/dramExtensions.cpp.gcov.html new file mode 100644 index 00000000..24492eef --- /dev/null +++ b/html/DRAMSys/library/src/common/dramExtensions.cpp.gcov.html @@ -0,0 +1,434 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/dramExtensions.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - dramExtensions.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4713235.6 %
Date:2020-06-30 17:34:44Functions:215736.8 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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LCOV - code coverage report
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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_ZN9tlm_utils26tlm2_base_protocol_checkerILj32EE28nb_transport_response_checksERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeEPKcSB_SB_0
_ZN9tlm_utils26tlm2_base_protocol_checkerILj32EE29get_direct_mem_ptr_pre_checksERN3tlm19tlm_generic_payloadERNS2_7tlm_dmiE0
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_ZN9tlm_utils6path_tC2Ev0
+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/tlm2_base_protocol_checker.h.func.html b/html/DRAMSys/library/src/common/tlm2_base_protocol_checker.h.func.html new file mode 100644 index 00000000..c55a87b4 --- /dev/null +++ b/html/DRAMSys/library/src/common/tlm2_base_protocol_checker.h.func.html @@ -0,0 +1,181 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/tlm2_base_protocol_checker.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/common - tlm2_base_protocol_checker.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:14720.2 %
Date:2020-06-30 17:34:44Functions:0280.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/tlm2_base_protocol_checker.h.gcov.html b/html/DRAMSys/library/src/common/tlm2_base_protocol_checker.h.gcov.html new file mode 100644 index 00000000..b3cf78ce --- /dev/null +++ b/html/DRAMSys/library/src/common/tlm2_base_protocol_checker.h.gcov.html @@ -0,0 +1,1128 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/tlm2_base_protocol_checker.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - tlm2_base_protocol_checker.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:14720.2 %
Date:2020-06-30 17:34:44Functions:0280.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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Date:2020-06-30 17:34:44Functions:020.0 %
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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_ZN12MemSpecGDDR6D0Ev0
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h.gcov.html b/html/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h.gcov.html new file mode 100644 index 00000000..163bfb6c --- /dev/null +++ b/html/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h.gcov.html @@ -0,0 +1,127 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h + + + + + + + + + + + + + + +
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Date:2020-06-30 17:34:44Functions:020.0 %
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Date:2020-06-30 17:34:44Functions:020.0 %
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Date:2020-06-30 17:34:44Functions:020.0 %
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Date:2020-06-30 17:34:44Functions:6785.7 %
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Date:2020-06-30 17:34:44Functions:020.0 %
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Date:2020-06-30 17:34:44Functions:2728.6 %
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecWideIO2.h (source / functions)HitTotalCoverage
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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_ZN14MemSpecWideIO2D2Ev0
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecWideIO2.h (source / functions)HitTotalCoverage
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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Function Name Sort by function nameHit count Sort by hit count
_ZN14MemSpecWideIO2D0Ev0
_ZN14MemSpecWideIO2D2Ev0
+
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Generated by: LCOV version 1.13
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/configuration/memspec/index-sort-f.html b/html/DRAMSys/library/src/configuration/memspec/index-sort-f.html new file mode 100644 index 00000000..cd1f2b8f --- /dev/null +++ b/html/DRAMSys/library/src/configuration/memspec/index-sort-f.html @@ -0,0 +1,293 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/configuration/memspec + + + + + + + + + + + + + + +
LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:388743.7 %
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
MemSpecDDR3.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecLPDDR4.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecHBM2.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecGDDR5X.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpec.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecWideIO.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecGDDR6.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecWideIO2.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecGDDR5.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecDDR4.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecWideIO.cpp +
1.2%1.2%
+ 		1.2 %1 / 8428.6 %2 / 7
MemSpecWideIO2.cpp +
1.4%1.4%
+ 		1.4 %1 / 6928.6 %2 / 7
MemSpecGDDR6.cpp +
1.2%1.2%
+ 		1.2 %1 / 8128.6 %2 / 7
MemSpecGDDR5.cpp +
1.3%1.3%
+ 		1.3 %1 / 7928.6 %2 / 7
MemSpecGDDR5X.cpp +
1.3%1.3%
+ 		1.3 %1 / 7928.6 %2 / 7
MemSpecDDR3.cpp +
90.8%90.8%
+ 		90.8 %69 / 7685.7 %6 / 7
MemSpecDDR4.cpp +
91.4%91.4%
+ 		91.4 %85 / 9385.7 %6 / 7
MemSpecLPDDR4.cpp +
92.9%92.9%
+ 		92.9 %78 / 8485.7 %6 / 7
MemSpecHBM2.cpp +
89.0%89.0%
+ 		89.0 %65 / 7385.7 %6 / 7
MemSpec.cpp +
100.0%
+ 		100.0 %17 / 17100.0 %4 / 4
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/configuration/memspec/index-sort-l.html b/html/DRAMSys/library/src/configuration/memspec/index-sort-l.html new file mode 100644 index 00000000..1588841f --- /dev/null +++ b/html/DRAMSys/library/src/configuration/memspec/index-sort-l.html @@ -0,0 +1,293 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/configuration/memspec + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - /DRAMSys/library/src/configuration/memspecHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:31974542.8 %
Date:2020-06-30 17:34:44Functions:388743.7 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
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+ +
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
MemSpecDDR3.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecLPDDR4.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecHBM2.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecGDDR5X.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpec.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecWideIO.h +
0.0%
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MemSpecGDDR6.h +
0.0%
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MemSpecWideIO2.h +
0.0%
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MemSpecGDDR5.h +
0.0%
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MemSpecDDR4.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecWideIO.cpp +
1.2%1.2%
+ 		1.2 %1 / 8428.6 %2 / 7
MemSpecGDDR5.cpp +
1.3%1.3%
+ 		1.3 %1 / 7928.6 %2 / 7
MemSpecGDDR5X.cpp +
1.3%1.3%
+ 		1.3 %1 / 7928.6 %2 / 7
MemSpecGDDR6.cpp +
1.2%1.2%
+ 		1.2 %1 / 8128.6 %2 / 7
MemSpecWideIO2.cpp +
1.4%1.4%
+ 		1.4 %1 / 6928.6 %2 / 7
MemSpecHBM2.cpp +
89.0%89.0%
+ 		89.0 %65 / 7385.7 %6 / 7
MemSpecDDR3.cpp +
90.8%90.8%
+ 		90.8 %69 / 7685.7 %6 / 7
MemSpecDDR4.cpp +
91.4%91.4%
+ 		91.4 %85 / 9385.7 %6 / 7
MemSpecLPDDR4.cpp +
92.9%92.9%
+ 		92.9 %78 / 8485.7 %6 / 7
MemSpec.cpp +
100.0%
+ 		100.0 %17 / 17100.0 %4 / 4
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/configuration/memspec/index.html b/html/DRAMSys/library/src/configuration/memspec/index.html new file mode 100644 index 00000000..561d4bd6 --- /dev/null +++ b/html/DRAMSys/library/src/configuration/memspec/index.html @@ -0,0 +1,293 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/configuration/memspec + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - /DRAMSys/library/src/configuration/memspecHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:31974542.8 %
Date:2020-06-30 17:34:44Functions:388743.7 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
MemSpec.cpp +
100.0%
+ 		100.0 %17 / 17100.0 %4 / 4
MemSpec.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecDDR3.cpp +
90.8%90.8%
+ 		90.8 %69 / 7685.7 %6 / 7
MemSpecDDR3.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecDDR4.cpp +
91.4%91.4%
+ 		91.4 %85 / 9385.7 %6 / 7
MemSpecDDR4.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecGDDR5.cpp +
1.3%1.3%
+ 		1.3 %1 / 7928.6 %2 / 7
MemSpecGDDR5.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecGDDR5X.cpp +
1.3%1.3%
+ 		1.3 %1 / 7928.6 %2 / 7
MemSpecGDDR5X.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecGDDR6.cpp +
1.2%1.2%
+ 		1.2 %1 / 8128.6 %2 / 7
MemSpecGDDR6.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecHBM2.cpp +
89.0%89.0%
+ 		89.0 %65 / 7385.7 %6 / 7
MemSpecHBM2.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecLPDDR4.cpp +
92.9%92.9%
+ 		92.9 %78 / 8485.7 %6 / 7
MemSpecLPDDR4.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecWideIO.cpp +
1.2%1.2%
+ 		1.2 %1 / 8428.6 %2 / 7
MemSpecWideIO.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecWideIO2.cpp +
1.4%1.4%
+ 		1.4 %1 / 6928.6 %2 / 7
MemSpecWideIO2.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/BankMachine.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/BankMachine.cpp.func-sort-c.html new file mode 100644 index 00000000..81786ff7 --- /dev/null +++ b/html/DRAMSys/library/src/controller/BankMachine.cpp.func-sort-c.html @@ -0,0 +1,161 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/BankMachine.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller - BankMachine.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:14916689.8 %
Date:2020-06-30 17:34:44Functions:192095.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN11BankMachine7getRankEv0
_GLOBAL__sub_I__ZN11BankMachineC2EP11SchedulerIFP9CheckerIF4Bank30
_Z41__static_initialization_and_destruction_0ii30
_ZN15BankMachineOpenC2EP11SchedulerIFP9CheckerIF4Bank80
_ZN23BankMachineOpenAdaptiveC2EP11SchedulerIFP9CheckerIF4Bank96
_ZN25BankMachineClosedAdaptiveC2EP11SchedulerIFP9CheckerIF4Bank96
_ZN17BankMachineClosedC2EP11SchedulerIFP9CheckerIF4Bank224
_ZN11BankMachineC2EP11SchedulerIFP9CheckerIF4Bank496
_ZN11BankMachine6isIdleEv29802
_ZN15BankMachineOpen5startEv71650
_ZN11BankMachine12getBankGroupEv87408
_ZN11BankMachine5blockEv133592
_ZN11BankMachine11updateStateE7Command426310
_ZN11BankMachine10getOpenRowEv2541205
_ZN17BankMachineClosed5startEv3416112
_ZN23BankMachineOpenAdaptive5startEv4507416
_ZN25BankMachineClosedAdaptive5startEv5314560
_ZN11BankMachine8getStateEv5446696
_ZN11BankMachine14getNextCommandEv13032248
_ZN11BankMachine7getBankEv13390075
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/BankMachine.cpp.func.html b/html/DRAMSys/library/src/controller/BankMachine.cpp.func.html new file mode 100644 index 00000000..96b534a6 --- /dev/null +++ b/html/DRAMSys/library/src/controller/BankMachine.cpp.func.html @@ -0,0 +1,161 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/BankMachine.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller - BankMachine.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:14916689.8 %
Date:2020-06-30 17:34:44Functions:192095.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN11BankMachineC2EP11SchedulerIFP9CheckerIF4Bank30
_Z41__static_initialization_and_destruction_0ii30
_ZN11BankMachine10getOpenRowEv2541205
_ZN11BankMachine11updateStateE7Command426310
_ZN11BankMachine12getBankGroupEv87408
_ZN11BankMachine14getNextCommandEv13032248
_ZN11BankMachine5blockEv133592
_ZN11BankMachine6isIdleEv29802
_ZN11BankMachine7getBankEv13390075
_ZN11BankMachine7getRankEv0
_ZN11BankMachine8getStateEv5446696
_ZN11BankMachineC2EP11SchedulerIFP9CheckerIF4Bank496
_ZN15BankMachineOpen5startEv71650
_ZN15BankMachineOpenC2EP11SchedulerIFP9CheckerIF4Bank80
_ZN17BankMachineClosed5startEv3416112
_ZN17BankMachineClosedC2EP11SchedulerIFP9CheckerIF4Bank224
_ZN23BankMachineOpenAdaptive5startEv4507416
_ZN23BankMachineOpenAdaptiveC2EP11SchedulerIFP9CheckerIF4Bank96
_ZN25BankMachineClosedAdaptive5startEv5314560
_ZN25BankMachineClosedAdaptiveC2EP11SchedulerIFP9CheckerIF4Bank96
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/BankMachine.cpp.gcov.html b/html/DRAMSys/library/src/controller/BankMachine.cpp.gcov.html new file mode 100644 index 00000000..abffb038 --- /dev/null +++ b/html/DRAMSys/library/src/controller/BankMachine.cpp.gcov.html @@ -0,0 +1,413 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/BankMachine.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller - BankMachine.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:14916689.8 %
Date:2020-06-30 17:34:44Functions:192095.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
+       1             : /* EOF */
+       2             : /* EOF */
+       3             : /* EOF */
+       4             : /* EOF */
+       5             : /* EOF */
+       6             : /* EOF */
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+       8             : /* EOF */
+       9             : /* EOF */
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+      11             : /* EOF */
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:2424100.0 %
Date:2020-06-30 17:34:44Functions:00-
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Date:2020-06-30 17:34:44Functions:111573.3 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller - Controller.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:19222087.3 %
Date:2020-06-30 17:34:44Functions:111573.3 %
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Function Name Sort by function nameHit count Sort by hit count
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+
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller - Controller.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:19222087.3 %
Date:2020-06-30 17:34:44Functions:111573.3 %
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp.func-sort-c.html new file mode 100644 index 00000000..d2dc3dcd --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR3.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR3.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:25328289.7 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN11CheckerDDR3C2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN11CheckerDDR36insertE7Command4Rank9BankGroup4Bank2275
_ZNK11CheckerDDR324timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank54425
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp.func.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp.func.html new file mode 100644 index 00000000..4d7102cc --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR3.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR3.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:25328289.7 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN11CheckerDDR3C2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN11CheckerDDR36insertE7Command4Rank9BankGroup4Bank2275
_ZNK11CheckerDDR324timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank54425
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp.gcov.html new file mode 100644 index 00000000..a4df13eb --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp.gcov.html @@ -0,0 +1,516 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR3.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR3.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:25328289.7 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.func-sort-c.html new file mode 100644 index 00000000..6014d036 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.func-sort-c.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR3.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR3.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN11CheckerDDR3D0Ev5
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.func.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.func.html new file mode 100644 index 00000000..26d34832 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.func.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR3.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR3.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN11CheckerDDR3D0Ev5
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.gcov.html new file mode 100644 index 00000000..22766102 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.gcov.html @@ -0,0 +1,129 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR3.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR3.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.func-sort-c.html new file mode 100644 index 00000000..456641f3 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR4.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:18730860.7 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN11CheckerDDR4C2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN11CheckerDDR46insertE7Command4Rank9BankGroup4Bank166614
_ZNK11CheckerDDR424timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank5298882
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:18730860.7 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN11CheckerDDR4C2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN11CheckerDDR46insertE7Command4Rank9BankGroup4Bank166614
_ZNK11CheckerDDR424timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank5298882
+
+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.gcov.html new file mode 100644 index 00000000..dc96b501 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.gcov.html @@ -0,0 +1,547 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR4.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:18730860.7 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.func-sort-c.html new file mode 100644 index 00000000..808fa173 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.func-sort-c.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR4.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN11CheckerDDR4D0Ev6
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+
+ + + +
Generated by: LCOV version 1.13
+
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ +
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Function Name Sort by function nameHit count Sort by hit count
_ZN11CheckerDDR4D0Ev6
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.gcov.html new file mode 100644 index 00000000..d40679f5 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.gcov.html @@ -0,0 +1,129 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR4.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
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+
          Line data    Source code
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.func-sort-c.html new file mode 100644 index 00000000..d984585f --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13700.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN12CheckerGDDR56insertE7Command4Rank9BankGroup4Bank0
_ZNK12CheckerGDDR524timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank0
_GLOBAL__sub_I__ZN12CheckerGDDR5C2Ev30
_Z41__static_initialization_and_destruction_0ii30
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+
+ + + +
Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13700.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
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+ +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN12CheckerGDDR5C2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN12CheckerGDDR56insertE7Command4Rank9BankGroup4Bank0
_ZNK12CheckerGDDR524timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.gcov.html new file mode 100644 index 00000000..4f3a4c50 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.gcov.html @@ -0,0 +1,636 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13700.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
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_ZN12CheckerGDDR5D0Ev0
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Date:2020-06-30 17:34:44Functions:020.0 %
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Function Name Sort by function nameHit count Sort by hit count
_ZN12CheckerGDDR5D0Ev0
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Date:2020-06-30 17:34:44Functions:020.0 %
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Date:2020-06-30 17:34:44Functions:020.0 %
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_ZN13CheckerGDDR5XD0Ev0
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_ZN13CheckerGDDR5XD0Ev0
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.h.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.h.func-sort-c.html new file mode 100644 index 00000000..8f99fe25 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.h.func-sort-c.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR6.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR6.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN12CheckerGDDR6D0Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.h.func.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.h.func.html new file mode 100644 index 00000000..fa586287 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.h.func.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR6.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR6.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN12CheckerGDDR6D0Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.h.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.h.gcov.html new file mode 100644 index 00000000..0f5b2cc0 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.h.gcov.html @@ -0,0 +1,129 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR6.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR6.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
+       1             : /* EOF */
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+      44           0 : /* EOF */
+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp.func-sort-c.html new file mode 100644 index 00000000..42eed417 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerHBM2.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerHBM2.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:17633951.9 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN11CheckerHBM2C2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN11CheckerHBM26insertE7Command4Rank9BankGroup4Bank58380
_ZNK11CheckerHBM224timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank1250781
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp.func.html b/html/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp.func.html new file mode 100644 index 00000000..7ee12337 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerHBM2.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerHBM2.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:17633951.9 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN11CheckerHBM2C2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN11CheckerHBM26insertE7Command4Rank9BankGroup4Bank58380
_ZNK11CheckerHBM224timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank1250781
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp.gcov.html new file mode 100644 index 00000000..d62a5cbc --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp.gcov.html @@ -0,0 +1,601 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerHBM2.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerHBM2.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:17633951.9 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.func-sort-c.html new file mode 100644 index 00000000..68ec3d7b --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.func-sort-c.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerHBM2.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN11CheckerHBM2D0Ev14
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.func.html b/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.func.html new file mode 100644 index 00000000..45ac0a30 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.func.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerHBM2.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN11CheckerHBM2D0Ev14
+
+
+ + + +
Generated by: LCOV version 1.13
+
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
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+ + + + + + + + +

+
          Line data    Source code
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerLPDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:17734551.3 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN13CheckerLPDDR4C2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN13CheckerLPDDR46insertE7Command4Rank9BankGroup4Bank191436
_ZNK13CheckerLPDDR424timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank4496580
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerLPDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:17734551.3 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
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+ +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN13CheckerLPDDR4C2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN13CheckerLPDDR46insertE7Command4Rank9BankGroup4Bank191436
_ZNK13CheckerLPDDR424timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank4496580
+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp.gcov.html new file mode 100644 index 00000000..e590d42c --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp.gcov.html @@ -0,0 +1,600 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerLPDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:17734551.3 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:020.0 %
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_ZN14CheckerWideIO2D0Ev0
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:386360.3 %
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CheckerGDDR5X.cpp +
0.3%0.3%
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CheckerGDDR5.cpp +
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0.3%0.3%
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CheckerWideIO.cpp +
0.4%0.4%
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100.0%
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CheckerLPDDR4.h +
100.0%
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CheckerHBM2.h +
100.0%
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CheckerDDR3.h +
100.0%
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CheckerDDR4.cpp +
60.7%60.7%
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CheckerDDR3.cpp +
89.7%89.7%
+ 		89.7 %253 / 282100.0 %5 / 5
CheckerLPDDR4.cpp +
51.3%51.3%
+ 		51.3 %177 / 345100.0 %5 / 5
CheckerHBM2.cpp +
51.9%51.9%
+ 		51.9 %176 / 339100.0 %5 / 5
+
+
+ + + + +
Generated by: LCOV version 1.13
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
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CheckerGDDR5X.cpp +
0.3%0.3%
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0.3%0.3%
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CheckerGDDR6.cpp +
0.3%0.3%
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CheckerWideIO.cpp +
0.4%0.4%
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CheckerWideIO2.cpp +
0.3%0.3%
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CheckerLPDDR4.cpp +
51.3%51.3%
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CheckerHBM2.cpp +
51.9%51.9%
+ 		51.9 %176 / 339100.0 %5 / 5
CheckerDDR4.cpp +
60.7%60.7%
+ 		60.7 %187 / 308100.0 %5 / 5
CheckerDDR3.cpp +
89.7%89.7%
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CheckerDDR4.h +
100.0%
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CheckerLPDDR4.h +
100.0%
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CheckerHBM2.h +
100.0%
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CheckerDDR3.h +
100.0%
+ 		100.0 %1 / 1100.0 %2 / 2
+
+
+ + + + +
Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
CheckerDDR3.cpp +
89.7%89.7%
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100.0%
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60.7%60.7%
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100.0%
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CheckerGDDR5.cpp +
0.3%0.3%
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0.0%
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CheckerGDDR5X.cpp +
0.3%0.3%
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0.3%0.3%
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CheckerGDDR6.h +
0.0%
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CheckerHBM2.cpp +
51.9%51.9%
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CheckerHBM2.h +
100.0%
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CheckerLPDDR4.cpp +
51.3%51.3%
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CheckerLPDDR4.h +
100.0%
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CheckerWideIO.cpp +
0.4%0.4%
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0.0%
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CheckerWideIO2.cpp +
0.3%0.3%
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0.0%
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/cmdmux - CmdMuxOldest.cpp (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Current view:top level - /DRAMSys/library/src/controller/cmdmuxHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:2626100.0 %
Date:2020-06-30 17:34:44Functions:81080.0 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
CmdMuxStrict.h +
100.0%
+ 		100.0 %1 / 150.0 %1 / 2
CmdMuxOldest.h +
100.0%
+ 		100.0 %1 / 150.0 %1 / 2
CmdMuxOldest.cpp +
100.0%
+ 		100.0 %13 / 13100.0 %3 / 3
CmdMuxStrict.cpp +
100.0%
+ 		100.0 %11 / 11100.0 %3 / 3
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/cmdmux/index-sort-l.html b/html/DRAMSys/library/src/controller/cmdmux/index-sort-l.html new file mode 100644 index 00000000..31d6649e --- /dev/null +++ b/html/DRAMSys/library/src/controller/cmdmux/index-sort-l.html @@ -0,0 +1,133 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/cmdmux + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - /DRAMSys/library/src/controller/cmdmuxHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:2626100.0 %
Date:2020-06-30 17:34:44Functions:81080.0 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
CmdMuxStrict.h +
100.0%
+ 		100.0 %1 / 150.0 %1 / 2
CmdMuxOldest.h +
100.0%
+ 		100.0 %1 / 150.0 %1 / 2
CmdMuxStrict.cpp +
100.0%
+ 		100.0 %11 / 11100.0 %3 / 3
CmdMuxOldest.cpp +
100.0%
+ 		100.0 %13 / 13100.0 %3 / 3
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/cmdmux/index.html b/html/DRAMSys/library/src/controller/cmdmux/index.html new file mode 100644 index 00000000..affd16ff --- /dev/null +++ b/html/DRAMSys/library/src/controller/cmdmux/index.html @@ -0,0 +1,133 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/cmdmux + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - /DRAMSys/library/src/controller/cmdmuxHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:2626100.0 %
Date:2020-06-30 17:34:44Functions:81080.0 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
CmdMuxOldest.cpp +
100.0%
+ 		100.0 %13 / 13100.0 %3 / 3
CmdMuxOldest.h +
100.0%
+ 		100.0 %1 / 150.0 %1 / 2
CmdMuxStrict.cpp +
100.0%
+ 		100.0 %11 / 11100.0 %3 / 3
CmdMuxStrict.h +
100.0%
+ 		100.0 %1 / 150.0 %1 / 2
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/index-sort-f.html b/html/DRAMSys/library/src/controller/index-sort-f.html new file mode 100644 index 00000000..5e8e92df --- /dev/null +++ b/html/DRAMSys/library/src/controller/index-sort-f.html @@ -0,0 +1,173 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller + + + + + + + + + + + + + + +
LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:46151689.3 %
Date:2020-06-30 17:34:44Functions:557078.6 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
BankMachine.h +
100.0%
+ 		100.0 %4 / 450.0 %4 / 8
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100.0%
+ 		100.0 %3 / 366.7 %2 / 3
Controller.cpp +
87.3%87.3%
+ 		87.3 %192 / 22073.3 %11 / 15
ControllerIF.h +
100.0%
+ 		100.0 %46 / 4675.0 %3 / 4
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72.0%72.0%
+ 		72.0 %18 / 2576.9 %10 / 13
ControllerRecordable.cpp +
89.3%89.3%
+ 		89.3 %25 / 2885.7 %6 / 7
BankMachine.cpp +
89.8%89.8%
+ 		89.8 %149 / 16695.0 %19 / 20
Command.h +
100.0%
+ 		100.0 %24 / 24-0 / 0
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/index-sort-l.html b/html/DRAMSys/library/src/controller/index-sort-l.html new file mode 100644 index 00000000..6c75bb1e --- /dev/null +++ b/html/DRAMSys/library/src/controller/index-sort-l.html @@ -0,0 +1,173 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller + + + + + + + + + + + + + + +
LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:46151689.3 %
Date:2020-06-30 17:34:44Functions:557078.6 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
Command.cpp +
72.0%72.0%
+ 		72.0 %18 / 2576.9 %10 / 13
Controller.cpp +
87.3%87.3%
+ 		87.3 %192 / 22073.3 %11 / 15
ControllerRecordable.cpp +
89.3%89.3%
+ 		89.3 %25 / 2885.7 %6 / 7
BankMachine.cpp +
89.8%89.8%
+ 		89.8 %149 / 16695.0 %19 / 20
ControllerRecordable.h +
100.0%
+ 		100.0 %3 / 366.7 %2 / 3
BankMachine.h +
100.0%
+ 		100.0 %4 / 450.0 %4 / 8
Command.h +
100.0%
+ 		100.0 %24 / 24-0 / 0
ControllerIF.h +
100.0%
+ 		100.0 %46 / 4675.0 %3 / 4
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/index.html b/html/DRAMSys/library/src/controller/index.html new file mode 100644 index 00000000..9e93bbf5 --- /dev/null +++ b/html/DRAMSys/library/src/controller/index.html @@ -0,0 +1,173 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - /DRAMSys/library/src/controllerHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:46151689.3 %
Date:2020-06-30 17:34:44Functions:557078.6 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
BankMachine.cpp +
89.8%89.8%
+ 		89.8 %149 / 16695.0 %19 / 20
BankMachine.h +
100.0%
+ 		100.0 %4 / 450.0 %4 / 8
Command.cpp +
72.0%72.0%
+ 		72.0 %18 / 2576.9 %10 / 13
Command.h +
100.0%
+ 		100.0 %24 / 24-0 / 0
Controller.cpp +
87.3%87.3%
+ 		87.3 %192 / 22073.3 %11 / 15
ControllerIF.h +
100.0%
+ 		100.0 %46 / 4675.0 %3 / 4
ControllerRecordable.cpp +
89.3%89.3%
+ 		89.3 %25 / 2885.7 %6 / 7
ControllerRecordable.h +
100.0%
+ 		100.0 %3 / 366.7 %2 / 3
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp.func-sort-c.html new file mode 100644 index 00000000..0e700a88 --- /dev/null +++ b/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp.func-sort-c.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerDummy.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:55100.0 %
Date:2020-06-30 17:34:44Functions:44100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN21PowerDownManagerDummy14getNextCommandEv30
_ZN21PowerDownManagerDummy14getNextCommandEv1085867
_ZN21PowerDownManagerDummy5startEv2171734
+
+
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerDummy.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:55100.0 %
Date:2020-06-30 17:34:44Functions:44100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN21PowerDownManagerDummy14getNextCommandEv30
_ZN21PowerDownManagerDummy14getNextCommandEv1085867
_ZN21PowerDownManagerDummy5startEv2171734
+
+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp.gcov.html b/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp.gcov.html new file mode 100644 index 00000000..8ba6b502 --- /dev/null +++ b/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp.gcov.html @@ -0,0 +1,132 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerDummy.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:55100.0 %
Date:2020-06-30 17:34:44Functions:44100.0 %
Legend: Lines: + hit + not hit +
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+
          Line data    Source code
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+       1             : /* EOF */
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h.func-sort-c.html b/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h.func-sort-c.html new file mode 100644 index 00000000..540c25bb --- /dev/null +++ b/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h.func-sort-c.html @@ -0,0 +1,105 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerDummy.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:5683.3 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN21PowerDownManagerDummyD2Ev0
_ZN21PowerDownManagerDummyD0Ev32
_ZN21PowerDownManagerDummy11triggerExitEv50
_ZN21PowerDownManagerDummy12triggerEntryEv1400
_ZN21PowerDownManagerDummy19triggerInterruptionEv93042
_ZN21PowerDownManagerDummy11updateStateE7Command416430
+
+
+ + + +
Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h.func.html b/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h.func.html new file mode 100644 index 00000000..2e9392c4 --- /dev/null +++ b/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h.func.html @@ -0,0 +1,105 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerDummy.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:66100.0 %
Date:2020-06-30 17:34:44Functions:5683.3 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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_ZN21PowerDownManagerDummy11updateStateE7Command416430
_ZN21PowerDownManagerDummy12triggerEntryEv1400
_ZN21PowerDownManagerDummy19triggerInterruptionEv93042
_ZN21PowerDownManagerDummyD0Ev32
_ZN21PowerDownManagerDummyD2Ev0
+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h.gcov.html b/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h.gcov.html new file mode 100644 index 00000000..a73d5f0c --- /dev/null +++ b/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h.gcov.html @@ -0,0 +1,135 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerDummy.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:66100.0 %
Date:2020-06-30 17:34:44Functions:5683.3 %
Legend: Lines: + hit + not hit +
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          Line data    Source code
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:1250.0 %
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:1250.0 %
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:1250.0 %
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Generated by: LCOV version 1.13
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PowerDownManagerStaggered.h +
100.0%
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100.0%
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100.0%
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96.7%96.7%
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:192190.5 %
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PowerDownManagerStaggered.cpp +
96.7%96.7%
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100.0%
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100.0%
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100.0%
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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PowerDownManagerDummy.cpp +
100.0%
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100.0%
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96.7%96.7%
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100.0%
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerBankwise.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:829784.5 %
Date:2020-06-30 17:34:44Functions:66100.0 %
Legend: Lines: + hit + not hit +
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+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
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_Z41__static_initialization_and_destruction_0ii30
_ZN22RefreshManagerBankwise14getNextCommandEv548424
_ZN22RefreshManagerBankwise5startEv1096848
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp.func.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp.func.html new file mode 100644 index 00000000..4a4bced0 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerBankwise.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:829784.5 %
Date:2020-06-30 17:34:44Functions:66100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN22RefreshManagerBankwiseC2ERSt6vectorIP11BankMachineSaIS2_EEP18PowerDownManagerIF4RankP9CheckerIF30
_Z41__static_initialization_and_destruction_0ii30
_ZN22RefreshManagerBankwise14getNextCommandEv548424
_ZN22RefreshManagerBankwise5startEv1096848
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp.gcov.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp.gcov.html new file mode 100644 index 00000000..698fc885 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp.gcov.html @@ -0,0 +1,294 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerBankwise.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:829784.5 %
Date:2020-06-30 17:34:44Functions:66100.0 %
Legend: Lines: + hit + not hit +
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+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h.func-sort-c.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h.func-sort-c.html new file mode 100644 index 00000000..549375c0 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h.func-sort-c.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerBankwise.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
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Function Name Sort by function nameHit count Sort by hit count
_ZN22RefreshManagerBankwiseD0Ev12
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h.func.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h.func.html new file mode 100644 index 00000000..49c830d5 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h.func.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerBankwise.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN22RefreshManagerBankwiseD0Ev12
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h.gcov.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h.gcov.html new file mode 100644 index 00000000..4a144ee3 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h.gcov.html @@ -0,0 +1,131 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerBankwise.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp.func-sort-c.html new file mode 100644 index 00000000..ffb67bc1 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp.func-sort-c.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerDummy.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1520.0 %
Date:2020-06-30 17:34:44Functions:2450.0 %
Legend: Lines: + hit + not hit +
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+ +
+ + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN19RefreshManagerDummy14getNextCommandEv0
_ZN19RefreshManagerDummy5startEv0
_GLOBAL__sub_I__ZN19RefreshManagerDummy14getNextCommandEv30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp.func.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp.func.html new file mode 100644 index 00000000..4be609f1 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp.func.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerDummy.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1520.0 %
Date:2020-06-30 17:34:44Functions:2450.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN19RefreshManagerDummy14getNextCommandEv30
_ZN19RefreshManagerDummy14getNextCommandEv0
_ZN19RefreshManagerDummy5startEv0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp.gcov.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp.gcov.html new file mode 100644 index 00000000..862733fb --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp.gcov.html @@ -0,0 +1,132 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerDummy.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1520.0 %
Date:2020-06-30 17:34:44Functions:2450.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h.func-sort-c.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h.func-sort-c.html new file mode 100644 index 00000000..a81ee993 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h.func-sort-c.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerDummy.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:020.0 %
Date:2020-06-30 17:34:44Functions:030.0 %
Legend: Lines: + hit + not hit +
+
+ +
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Function Name Sort by function nameHit count Sort by hit count
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_ZN19RefreshManagerDummyD2Ev0
+
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerDummy.h (source / functions)HitTotalCoverage
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:020.0 %
Date:2020-06-30 17:34:44Functions:030.0 %
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Function Name Sort by function nameHit count Sort by hit count
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_ZN19RefreshManagerDummyD0Ev0
_ZN19RefreshManagerDummyD2Ev0
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerDummy.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:020.0 %
Date:2020-06-30 17:34:44Functions:030.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Date:2020-06-30 17:34:44Functions:66100.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Date:2020-06-30 17:34:44Functions:66100.0 %
Legend: Lines: + hit + not hit +
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+
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.func-sort-c.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.func-sort-c.html new file mode 100644 index 00000000..09a6172e --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerRankwise.h (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:1250.0 %
Legend: Lines: + hit + not hit +
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_ZN22RefreshManagerRankwiseD2Ev0
_ZN22RefreshManagerRankwiseD0Ev30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.func.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.func.html new file mode 100644 index 00000000..2c30bcdc --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.func.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerRankwise.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:1250.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN22RefreshManagerRankwiseD0Ev30
_ZN22RefreshManagerRankwiseD2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.gcov.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.gcov.html new file mode 100644 index 00000000..49d05306 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.gcov.html @@ -0,0 +1,129 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerRankwise.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:1250.0 %
Legend: Lines: + hit + not hit +
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+
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+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/index-sort-f.html b/html/DRAMSys/library/src/controller/refresh/index-sort-f.html new file mode 100644 index 00000000..3e870329 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/index-sort-f.html @@ -0,0 +1,153 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh + + + + + + + + + + + + + + +
LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:172373.9 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
RefreshManagerDummy.h +
0.0%
+ 		0.0 %0 / 20.0 %0 / 3
RefreshManagerRankwise.h +
100.0%
+ 		100.0 %1 / 150.0 %1 / 2
RefreshManagerDummy.cpp +
20.0%20.0%
+ 		20.0 %1 / 550.0 %2 / 4
RefreshManagerBankwise.h +
100.0%
+ 		100.0 %1 / 1100.0 %2 / 2
RefreshManagerRankwise.cpp +
97.5%97.5%
+ 		97.5 %79 / 81100.0 %6 / 6
RefreshManagerBankwise.cpp +
84.5%84.5%
+ 		84.5 %82 / 97100.0 %6 / 6
+
+
+ + + + +
Generated by: LCOV version 1.13
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84.5%84.5%
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97.5%97.5%
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100.0%
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100.0%
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Generated by: LCOV version 1.13
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
RefreshManagerBankwise.cpp +
84.5%84.5%
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100.0%
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20.0%20.0%
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0.0%
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97.5%97.5%
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100.0%
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:55100.0 %
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Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:2540.0 %
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_Z41__static_initialization_and_destruction_0ii30
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:080.0 %
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_ZN3ECC18CalculateParityBitE5CWordR4CBit0
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/error/ECC - ECC.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:080.0 %
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_ZN3ECC18CalculateParityBitE5CWordR4CBit0
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/error/ECC - ECC.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:0470.0 %
Date:2020-06-30 17:34:44Functions:080.0 %
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Current view:top level - DRAMSys/library/src/error/ECC - Word.cpp (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:1156.7 %
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:1156.7 %
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN5CWordC2Ej30
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_ZN5CWordD0Ev0
_ZN5CWordD2Ev0
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1741.4 %
Date:2020-06-30 17:34:44Functions:1156.7 %
Legend: Lines: + hit + not hit +
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Current view:top level - DRAMSys/library/src/error/ECC - Word.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:030.0 %
Date:2020-06-30 17:34:44Functions:00-
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Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:00-
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Date:2020-06-30 17:34:44Functions:2540.0 %
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:030.0 %
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Current view:top level - DRAMSys/library/src/error - errormodel.cpp (source / functions)HitTotalCoverage
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Generated by: LCOV version 1.13
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+
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+ + + diff --git a/html/DRAMSys/library/src/error/errormodel.h.func-sort-c.html b/html/DRAMSys/library/src/error/errormodel.h.func-sort-c.html new file mode 100644 index 00000000..5dab7392 --- /dev/null +++ b/html/DRAMSys/library/src/error/errormodel.h.func-sort-c.html @@ -0,0 +1,81 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/error/errormodel.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:030.0 %
Date:2020-06-30 17:34:44Functions:00-
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+ +
+ + + + + + +

Function Name Sort by function nameHit count Sort by hit count
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+
+ + + +
Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/error/errormodel.h.func.html b/html/DRAMSys/library/src/error/errormodel.h.func.html new file mode 100644 index 00000000..25de10f1 --- /dev/null +++ b/html/DRAMSys/library/src/error/errormodel.h.func.html @@ -0,0 +1,81 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/error/errormodel.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/error - errormodel.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:030.0 %
Date:2020-06-30 17:34:44Functions:00-
Legend: Lines: + hit + not hit +
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+ +
+ + + + + + +

Function Name Sort by function nameHit count Sort by hit count
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/error/errormodel.h.gcov.html b/html/DRAMSys/library/src/error/errormodel.h.gcov.html new file mode 100644 index 00000000..4331f785 --- /dev/null +++ b/html/DRAMSys/library/src/error/errormodel.h.gcov.html @@ -0,0 +1,209 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/error/errormodel.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/error - errormodel.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:030.0 %
Date:2020-06-30 17:34:44Functions:00-
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:22100.0 %
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Current view:top level - DRAMSys/library/src/simulation - DRAMSys.cpp (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:71258.3 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation - DRAMSys.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation - DRAMSys.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:71258.3 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation - DRAMSysRecordable.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:669073.3 %
Date:2020-06-30 17:34:44Functions:99100.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation - DRAMSysRecordable.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:669073.3 %
Date:2020-06-30 17:34:44Functions:99100.0 %
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp.gcov.html b/html/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp.gcov.html new file mode 100644 index 00000000..9019f01f --- /dev/null +++ b/html/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp.gcov.html @@ -0,0 +1,302 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/DRAMSysRecordable.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation - DRAMSysRecordable.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:669073.3 %
Date:2020-06-30 17:34:44Functions:99100.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/TemperatureController.cpp.func-sort-c.html b/html/DRAMSys/library/src/simulation/TemperatureController.cpp.func-sort-c.html new file mode 100644 index 00000000..485b1b6c --- /dev/null +++ b/html/DRAMSys/library/src/simulation/TemperatureController.cpp.func-sort-c.html @@ -0,0 +1,113 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/TemperatureController.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation - TemperatureController.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1442.3 %
Date:2020-06-30 17:34:44Functions:2825.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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_Z41__static_initialization_and_destruction_0ii30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/TemperatureController.cpp.func.html b/html/DRAMSys/library/src/simulation/TemperatureController.cpp.func.html new file mode 100644 index 00000000..b8db75d2 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/TemperatureController.cpp.func.html @@ -0,0 +1,113 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/TemperatureController.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation - TemperatureController.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1442.3 %
Date:2020-06-30 17:34:44Functions:2825.0 %
Legend: Lines: + hit + not hit +
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+ +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN21TemperatureController18temperatureConvertEd30
_Z41__static_initialization_and_destruction_0ii30
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_ZN21TemperatureController19checkPowerThresholdEi0
_ZN21TemperatureController22adjustThermalSimPeriodEv0
+
+
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Generated by: LCOV version 1.13
+
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation - TemperatureController.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1442.3 %
Date:2020-06-30 17:34:44Functions:2825.0 %
Legend: Lines: + hit + not hit +
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+
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+ + + + +
Generated by: LCOV version 1.13
+
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LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation - TemperatureController.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:113234.4 %
Date:2020-06-30 17:34:44Functions:3475.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN21TemperatureControllerD0Ev0
_ZN21TemperatureController11getInstanceEv30
_ZN21TemperatureControllerC2EN7sc_core14sc_module_nameE30
_ZN21TemperatureControllerD2Ev30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/TemperatureController.h.func.html b/html/DRAMSys/library/src/simulation/TemperatureController.h.func.html new file mode 100644 index 00000000..b09940f8 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/TemperatureController.h.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/TemperatureController.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation - TemperatureController.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:113234.4 %
Date:2020-06-30 17:34:44Functions:3475.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN21TemperatureController11getInstanceEv30
_ZN21TemperatureControllerC2EN7sc_core14sc_module_nameE30
_ZN21TemperatureControllerD0Ev0
_ZN21TemperatureControllerD2Ev30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/TemperatureController.h.gcov.html b/html/DRAMSys/library/src/simulation/TemperatureController.h.gcov.html new file mode 100644 index 00000000..66afd851 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/TemperatureController.h.gcov.html @@ -0,0 +1,198 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/TemperatureController.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation - TemperatureController.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:113234.4 %
Date:2020-06-30 17:34:44Functions:3475.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:5862.5 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Date:2020-06-30 17:34:44Functions:5862.5 %
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LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - Dram.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:22100.0 %
Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - Dram.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:22100.0 %
Date:2020-06-30 17:34:44Functions:00-
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - Dram.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:22100.0 %
Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramDDR3.cpp.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramDDR3.cpp.func-sort-c.html new file mode 100644 index 00000000..d2bdcdd5 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramDDR3.cpp.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramDDR3.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR3.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4834.8 %
Date:2020-06-30 17:34:44Functions:33100.0 %
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_Z41__static_initialization_and_destruction_0ii30
+
+
+ + + +
Generated by: LCOV version 1.13
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LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR3.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4834.8 %
Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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_Z41__static_initialization_and_destruction_0ii30
+
+
+ + + +
Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramDDR3.cpp.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramDDR3.cpp.gcov.html new file mode 100644 index 00000000..05737263 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramDDR3.cpp.gcov.html @@ -0,0 +1,229 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramDDR3.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR3.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4834.8 %
Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.func-sort-c.html new file mode 100644 index 00000000..381353ec --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramDDR3.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR3.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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_ZN8DramDDR3D0Ev0
_ZN8DramDDR3D2Ev0
+
+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.func.html b/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.func.html new file mode 100644 index 00000000..196059ef --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.func.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramDDR3.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR3.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN8DramDDR3D0Ev0
_ZN8DramDDR3D2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.gcov.html new file mode 100644 index 00000000..0d1cb033 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.gcov.html @@ -0,0 +1,132 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramDDR3.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR3.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
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+
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramDDR4.cpp.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramDDR4.cpp.func-sort-c.html new file mode 100644 index 00000000..15cee2e9 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramDDR4.cpp.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramDDR4.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4834.8 %
Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN8DramDDR4C2EN7sc_core14sc_module_nameE30
_Z41__static_initialization_and_destruction_0ii30
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+
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramDDR4.cpp.func.html b/html/DRAMSys/library/src/simulation/dram/DramDDR4.cpp.func.html new file mode 100644 index 00000000..281fa307 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramDDR4.cpp.func.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramDDR4.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4834.8 %
Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN8DramDDR4C2EN7sc_core14sc_module_nameE30
_Z41__static_initialization_and_destruction_0ii30
+
+
+ + + +
Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramDDR4.cpp.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramDDR4.cpp.gcov.html new file mode 100644 index 00000000..7473aba8 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramDDR4.cpp.gcov.html @@ -0,0 +1,229 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramDDR4.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4834.8 %
Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramDDR4.h.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramDDR4.h.func-sort-c.html new file mode 100644 index 00000000..eb8ac769 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramDDR4.h.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramDDR4.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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+ +
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_ZN8DramDDR4D0Ev0
_ZN8DramDDR4D2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramDDR4.h.func.html b/html/DRAMSys/library/src/simulation/dram/DramDDR4.h.func.html new file mode 100644 index 00000000..c0a1fb9d --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramDDR4.h.func.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramDDR4.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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+ +
+ + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN8DramDDR4D0Ev0
_ZN8DramDDR4D2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramDDR4.h.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramDDR4.h.gcov.html new file mode 100644 index 00000000..db16ecd0 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramDDR4.h.gcov.html @@ -0,0 +1,132 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramDDR4.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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+       2             : /* EOF */
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR6.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:2366.7 %
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR6.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:2366.7 %
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:2366.7 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR6.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR6.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR6.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramHBM2.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramHBM2.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramHBM2.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramHBM2.h.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramHBM2.h.func-sort-c.html new file mode 100644 index 00000000..c21a8b9c --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramHBM2.h.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramHBM2.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramHBM2.h.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramHBM2.h.gcov.html new file mode 100644 index 00000000..ad66f053 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramHBM2.h.gcov.html @@ -0,0 +1,132 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramHBM2.h + + + + + + + + + + + + + + +
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Current view:top level - DRAMSys/library/src/simulation/dram - DramHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.func-sort-c.html new file mode 100644 index 00000000..08117f53 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramLPDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4666.7 %
Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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_GLOBAL__sub_I__ZN10DramLPDDR4C2EN7sc_core14sc_module_nameE30
+
+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.func.html b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.func.html new file mode 100644 index 00000000..5717622b --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.func.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramLPDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4666.7 %
Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN10DramLPDDR4C2EN7sc_core14sc_module_nameE30
_ZN10DramLPDDR4C2EN7sc_core14sc_module_nameE12
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.gcov.html new file mode 100644 index 00000000..85777181 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.gcov.html @@ -0,0 +1,135 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramLPDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4666.7 %
Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.func-sort-c.html new file mode 100644 index 00000000..7346fb16 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramLPDDR4.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramLPDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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_ZN10DramLPDDR4D0Ev0
_ZN10DramLPDDR4D2Ev0
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+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.func.html b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.func.html new file mode 100644 index 00000000..ad07bbbd --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.func.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramLPDDR4.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramLPDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.gcov.html new file mode 100644 index 00000000..50773866 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.gcov.html @@ -0,0 +1,132 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramLPDDR4.h + + + + + + + + + + + + + + +
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Current view:top level - DRAMSys/library/src/simulation/dram - DramLPDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramRecordable.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Function Name Sort by function nameHit count Sort by hit count
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_Z41__static_initialization_and_destruction_0ii30
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+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.func.html b/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.func.html new file mode 100644 index 00000000..07eba4a0 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.func.html @@ -0,0 +1,269 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramRecordable.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramRecordable.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:233860.5 %
Date:2020-06-30 17:34:44Functions:144729.8 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I_DramRecordable.cpp30
_Z41__static_initialization_and_destruction_0ii30
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_ZN14DramRecordableI9DramGDDR5E11powerWindowEv0
_ZN14DramRecordableI9DramGDDR5E11recordPhaseERN3tlm19tlm_generic_payloadENS2_9tlm_phaseEN7sc_core7sc_timeE0
_ZN14DramRecordableI9DramGDDR5E11reportPowerEv0
_ZN14DramRecordableI9DramGDDR5E15nb_transport_fwERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeE0
_ZN14DramRecordableI9DramGDDR5EC2EN7sc_core14sc_module_nameEP11TlmRecorder0
_ZN14DramRecordableI9DramGDDR6E11powerWindowEv0
_ZN14DramRecordableI9DramGDDR6E11recordPhaseERN3tlm19tlm_generic_payloadENS2_9tlm_phaseEN7sc_core7sc_timeE0
_ZN14DramRecordableI9DramGDDR6E11reportPowerEv0
_ZN14DramRecordableI9DramGDDR6E15nb_transport_fwERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeE0
_ZN14DramRecordableI9DramGDDR6EC2EN7sc_core14sc_module_nameEP11TlmRecorder0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.gcov.html new file mode 100644 index 00000000..09eab6e2 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.gcov.html @@ -0,0 +1,241 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramRecordable.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramRecordable.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:233860.5 %
Date:2020-06-30 17:34:44Functions:144729.8 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.func-sort-c.html new file mode 100644 index 00000000..e8fbee4f --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.func-sort-c.html @@ -0,0 +1,189 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramRecordable.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramRecordable.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3560.0 %
Date:2020-06-30 17:34:44Functions:42714.8 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN14DramRecordableI10DramGDDR5XE7isEqualEddd0
_ZN14DramRecordableI10DramGDDR5XED0Ev0
_ZN14DramRecordableI10DramGDDR5XED2Ev0
_ZN14DramRecordableI10DramLPDDR4E7isEqualEddd0
_ZN14DramRecordableI10DramLPDDR4ED2Ev0
_ZN14DramRecordableI10DramWideIOE7isEqualEddd0
_ZN14DramRecordableI10DramWideIOED0Ev0
_ZN14DramRecordableI10DramWideIOED2Ev0
_ZN14DramRecordableI11DramWideIO2E7isEqualEddd0
_ZN14DramRecordableI11DramWideIO2ED0Ev0
_ZN14DramRecordableI11DramWideIO2ED2Ev0
_ZN14DramRecordableI8DramDDR3E7isEqualEddd0
_ZN14DramRecordableI8DramDDR3ED2Ev0
_ZN14DramRecordableI8DramDDR4E7isEqualEddd0
_ZN14DramRecordableI8DramDDR4ED2Ev0
_ZN14DramRecordableI8DramHBM2E7isEqualEddd0
_ZN14DramRecordableI8DramHBM2ED2Ev0
_ZN14DramRecordableI9DramGDDR5E7isEqualEddd0
_ZN14DramRecordableI9DramGDDR5ED0Ev0
_ZN14DramRecordableI9DramGDDR5ED2Ev0
_ZN14DramRecordableI9DramGDDR6E7isEqualEddd0
_ZN14DramRecordableI9DramGDDR6ED0Ev0
_ZN14DramRecordableI9DramGDDR6ED2Ev0
_ZN14DramRecordableI8DramDDR3ED0Ev5
_ZN14DramRecordableI8DramDDR4ED0Ev6
_ZN14DramRecordableI10DramLPDDR4ED0Ev12
_ZN14DramRecordableI8DramHBM2ED0Ev14
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.func.html b/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.func.html new file mode 100644 index 00000000..5e486f62 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.func.html @@ -0,0 +1,189 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramRecordable.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramRecordable.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3560.0 %
Date:2020-06-30 17:34:44Functions:42714.8 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN14DramRecordableI10DramGDDR5XE7isEqualEddd0
_ZN14DramRecordableI10DramGDDR5XED0Ev0
_ZN14DramRecordableI10DramGDDR5XED2Ev0
_ZN14DramRecordableI10DramLPDDR4E7isEqualEddd0
_ZN14DramRecordableI10DramLPDDR4ED0Ev12
_ZN14DramRecordableI10DramLPDDR4ED2Ev0
_ZN14DramRecordableI10DramWideIOE7isEqualEddd0
_ZN14DramRecordableI10DramWideIOED0Ev0
_ZN14DramRecordableI10DramWideIOED2Ev0
_ZN14DramRecordableI11DramWideIO2E7isEqualEddd0
_ZN14DramRecordableI11DramWideIO2ED0Ev0
_ZN14DramRecordableI11DramWideIO2ED2Ev0
_ZN14DramRecordableI8DramDDR3E7isEqualEddd0
_ZN14DramRecordableI8DramDDR3ED0Ev5
_ZN14DramRecordableI8DramDDR3ED2Ev0
_ZN14DramRecordableI8DramDDR4E7isEqualEddd0
_ZN14DramRecordableI8DramDDR4ED0Ev6
_ZN14DramRecordableI8DramDDR4ED2Ev0
_ZN14DramRecordableI8DramHBM2E7isEqualEddd0
_ZN14DramRecordableI8DramHBM2ED0Ev14
_ZN14DramRecordableI8DramHBM2ED2Ev0
_ZN14DramRecordableI9DramGDDR5E7isEqualEddd0
_ZN14DramRecordableI9DramGDDR5ED0Ev0
_ZN14DramRecordableI9DramGDDR5ED2Ev0
_ZN14DramRecordableI9DramGDDR6E7isEqualEddd0
_ZN14DramRecordableI9DramGDDR6ED0Ev0
_ZN14DramRecordableI9DramGDDR6ED2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.gcov.html new file mode 100644 index 00000000..6e959c25 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.gcov.html @@ -0,0 +1,155 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramRecordable.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramRecordable.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3560.0 %
Date:2020-06-30 17:34:44Functions:42714.8 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
+       1             : /* EOF */
+       2             : /* EOF */
+       3             : /* EOF */
+       4             : /* EOF */
+       5             : /* EOF */
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+      25             : /* EOF */
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+      42             : /* EOF */
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+      44             : /* EOF */
+      45             : /* EOF */
+      46          74 : /* EOF */
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+      48             : /* EOF */
+      49             : /* EOF */
+      50             : /* EOF */
+      51             : /* EOF */
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+      53             : /* EOF */
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+      55             : /* EOF */
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+      58             : /* EOF */
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+      62          37 : /* EOF */
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+      68           0 : /* EOF */
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+      70           0 : /* EOF */
+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramWideIO.cpp.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramWideIO.cpp.func-sort-c.html new file mode 100644 index 00000000..ab47771e --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramWideIO.cpp.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramWideIO.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramWideIO.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11190.8 %
Date:2020-06-30 17:34:44Functions:2633.3 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN10DramWideIO15nb_transport_fwERN3tlm19tlm_generic_payloadERNS0_9tlm_phaseERN7sc_core7sc_timeE0
_ZN10DramWideIOD0Ev0
_GLOBAL__sub_I__ZN10DramWideIOC2EN7sc_core14sc_module_nameE30
_Z41__static_initialization_and_destruction_0ii30
+
+
+ + + +
Generated by: LCOV version 1.13
+
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Date:2020-06-30 17:34:44Functions:2366.7 %
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
DramWideIO2.h +
0.0%
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DramDDR4.h +
100.0%
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DramHBM2.h +
100.0%
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DramLPDDR4.h +
100.0%
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DramGDDR6.h +
0.0%
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DramDDR3.h +
100.0%
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DramGDDR5.h +
0.0%
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DramGDDR5X.h +
0.0%
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DramRecordable.h +
60.0%60.0%
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DramRecordable.cpp +
60.5%60.5%
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DramWideIO.cpp +
0.8%0.8%
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Dram.cpp +
25.7%25.7%
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DramGDDR5X.cpp +
16.7%16.7%
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DramGDDR5.cpp +
16.7%16.7%
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DramGDDR6.cpp +
16.7%16.7%
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DramWideIO2.cpp +
16.7%16.7%
+ 		16.7 %1 / 666.7 %2 / 3
Dram.h +
100.0%
+ 		100.0 %2 / 2-0 / 0
DramDDR3.cpp +
4.8%4.8%
+ 		4.8 %4 / 83100.0 %3 / 3
DramDDR4.cpp +
4.8%4.8%
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DramHBM2.cpp +
66.7%66.7%
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DramLPDDR4.cpp +
66.7%66.7%
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+
+
+ + + + +
Generated by: LCOV version 1.13
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
DramWideIO2.h +
0.0%
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0.0%
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0.0%
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DramWideIO.cpp +
0.8%0.8%
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DramDDR3.cpp +
4.8%4.8%
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DramDDR4.cpp +
4.8%4.8%
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DramGDDR5X.cpp +
16.7%16.7%
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DramGDDR5.cpp +
16.7%16.7%
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DramGDDR6.cpp +
16.7%16.7%
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DramWideIO2.cpp +
16.7%16.7%
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Dram.cpp +
25.7%25.7%
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DramRecordable.h +
60.0%60.0%
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DramRecordable.cpp +
60.5%60.5%
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DramHBM2.cpp +
66.7%66.7%
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DramLPDDR4.cpp +
66.7%66.7%
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DramDDR4.h +
100.0%
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DramHBM2.h +
100.0%
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DramLPDDR4.h +
100.0%
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DramDDR3.h +
100.0%
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Dram.h +
100.0%
+ 		100.0 %2 / 2-0 / 0
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+
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Generated by: LCOV version 1.13
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
Dram.cpp +
25.7%25.7%
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Dram.h +
100.0%
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DramDDR3.cpp +
4.8%4.8%
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DramDDR3.h +
100.0%
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DramDDR4.cpp +
4.8%4.8%
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DramDDR4.h +
100.0%
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DramGDDR5.cpp +
16.7%16.7%
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DramGDDR5.h +
0.0%
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DramGDDR5X.cpp +
16.7%16.7%
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DramGDDR5X.h +
0.0%
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DramGDDR6.cpp +
16.7%16.7%
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DramGDDR6.h +
0.0%
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DramHBM2.cpp +
66.7%66.7%
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DramHBM2.h +
100.0%
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DramLPDDR4.cpp +
66.7%66.7%
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DramLPDDR4.h +
100.0%
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DramRecordable.cpp +
60.5%60.5%
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DramRecordable.h +
60.0%60.0%
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DramWideIO.cpp +
0.8%0.8%
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DramWideIO2.cpp +
16.7%16.7%
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DramWideIO2.h +
0.0%
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+
+
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Generated by: LCOV version 1.13
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:20737555.2 %
Date:2020-06-30 17:34:44Functions:304369.8 %
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
TemperatureController.cpp +
2.3%2.3%
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DRAMSys.cpp +
40.2%40.2%
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TemperatureController.h +
34.4%34.4%
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Arbiter.cpp +
89.0%89.0%
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Arbiter.h +
100.0%
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DRAMSysRecordable.cpp +
73.3%73.3%
+ 		73.3 %66 / 90100.0 %9 / 9
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/index-sort-l.html b/html/DRAMSys/library/src/simulation/index-sort-l.html new file mode 100644 index 00000000..6ca1a79a --- /dev/null +++ b/html/DRAMSys/library/src/simulation/index-sort-l.html @@ -0,0 +1,153 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation + + + + + + + + + + + + + + +
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:20737555.2 %
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
TemperatureController.cpp +
2.3%2.3%
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TemperatureController.h +
34.4%34.4%
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DRAMSys.cpp +
40.2%40.2%
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DRAMSysRecordable.cpp +
73.3%73.3%
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Arbiter.cpp +
89.0%89.0%
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Arbiter.h +
100.0%
+ 		100.0 %1 / 1100.0 %2 / 2
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/index.html b/html/DRAMSys/library/src/simulation/index.html new file mode 100644 index 00000000..e66e6881 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/index.html @@ -0,0 +1,153 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation + + + + + + + + + + + + + + +
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:20737555.2 %
Date:2020-06-30 17:34:44Functions:304369.8 %
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
Arbiter.cpp +
89.0%89.0%
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100.0%
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DRAMSys.cpp +
40.2%40.2%
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DRAMSysRecordable.cpp +
73.3%73.3%
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TemperatureController.cpp +
2.3%2.3%
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TemperatureController.h +
34.4%34.4%
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+
+ + + + +
Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/simulator/MemoryManager.cpp.func-sort-c.html b/html/DRAMSys/simulator/MemoryManager.cpp.func-sort-c.html new file mode 100644 index 00000000..2b15610b --- /dev/null +++ b/html/DRAMSys/simulator/MemoryManager.cpp.func-sort-c.html @@ -0,0 +1,109 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/MemoryManager.cpp - functions + + + + + + + + + + + + + + +
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:182475.0 %
Date:2020-06-30 17:34:44Functions:5771.4 %
Legend: Lines: + hit + not hit +
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_ZN13MemoryManager8allocateEv252938
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:182475.0 %
Date:2020-06-30 17:34:44Functions:5771.4 %
Legend: Lines: + hit + not hit +
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_ZN13MemoryManagerD2Ev0
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Generated by: LCOV version 1.13
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:182475.0 %
Date:2020-06-30 17:34:44Functions:5771.4 %
Legend: Lines: + hit + not hit +
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          Line data    Source code
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/StlPlayer.h.func-sort-c.html b/html/DRAMSys/simulator/StlPlayer.h.func-sort-c.html new file mode 100644 index 00000000..efbec1ae --- /dev/null +++ b/html/DRAMSys/simulator/StlPlayer.h.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/StlPlayer.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - StlPlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:486277.4 %
Date:2020-06-30 17:34:44Functions:2825.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN9StlPlayerILb0EED0Ev0
_ZN9StlPlayerILb0EED2Ev0
_ZN9StlPlayerILb1EED0Ev0
_ZN9StlPlayerILb1EED2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/StlPlayer.h.func.html b/html/DRAMSys/simulator/StlPlayer.h.func.html new file mode 100644 index 00000000..c8a95420 --- /dev/null +++ b/html/DRAMSys/simulator/StlPlayer.h.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/StlPlayer.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - StlPlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:486277.4 %
Date:2020-06-30 17:34:44Functions:2825.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN9StlPlayerILb0EED0Ev0
_ZN9StlPlayerILb0EED2Ev0
_ZN9StlPlayerILb1EED0Ev0
_ZN9StlPlayerILb1EED2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/StlPlayer.h.gcov.html b/html/DRAMSys/simulator/StlPlayer.h.gcov.html new file mode 100644 index 00000000..945ea4ec --- /dev/null +++ b/html/DRAMSys/simulator/StlPlayer.h.gcov.html @@ -0,0 +1,259 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/StlPlayer.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - StlPlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:486277.4 %
Date:2020-06-30 17:34:44Functions:2825.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TracePlayer.cpp.func-sort-c.html b/html/DRAMSys/simulator/TracePlayer.cpp.func-sort-c.html new file mode 100644 index 00000000..ac38a8c5 --- /dev/null +++ b/html/DRAMSys/simulator/TracePlayer.cpp.func-sort-c.html @@ -0,0 +1,125 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TracePlayer.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - TracePlayer.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:475388.7 %
Date:2020-06-30 17:34:44Functions:101190.9 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN11TracePlayer23setNumberOfTransactionsEj0
_GLOBAL__sub_I__ZN11TracePlayerC2EN7sc_core14sc_module_nameEP19TracePlayerListener30
_Z41__static_initialization_and_destruction_0ii30
_ZN11TracePlayer16getNumberOfLinesENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE37
_ZN11TracePlayer6finishEv37
_ZN11TracePlayer9terminateEv37
_ZN11TracePlayerC2EN7sc_core14sc_module_nameEP19TracePlayerListener37
_ZN11TracePlayer15allocatePayloadEv252938
_ZN11TracePlayer12sendToTargetERN3tlm19tlm_generic_payloadERKNS0_9tlm_phaseERKN7sc_core7sc_timeE505876
_ZN11TracePlayer15nb_transport_bwERN3tlm19tlm_generic_payloadERNS0_9tlm_phaseERN7sc_core7sc_timeE505876
_ZN11TracePlayer11peqCallbackERN3tlm19tlm_generic_payloadERKNS0_9tlm_phaseE758814
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TracePlayer.cpp.func.html b/html/DRAMSys/simulator/TracePlayer.cpp.func.html new file mode 100644 index 00000000..c4e8801f --- /dev/null +++ b/html/DRAMSys/simulator/TracePlayer.cpp.func.html @@ -0,0 +1,125 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TracePlayer.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - TracePlayer.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:475388.7 %
Date:2020-06-30 17:34:44Functions:101190.9 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN11TracePlayerC2EN7sc_core14sc_module_nameEP19TracePlayerListener30
_Z41__static_initialization_and_destruction_0ii30
_ZN11TracePlayer11peqCallbackERN3tlm19tlm_generic_payloadERKNS0_9tlm_phaseE758814
_ZN11TracePlayer12sendToTargetERN3tlm19tlm_generic_payloadERKNS0_9tlm_phaseERKN7sc_core7sc_timeE505876
_ZN11TracePlayer15allocatePayloadEv252938
_ZN11TracePlayer15nb_transport_bwERN3tlm19tlm_generic_payloadERNS0_9tlm_phaseERN7sc_core7sc_timeE505876
_ZN11TracePlayer16getNumberOfLinesENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE37
_ZN11TracePlayer23setNumberOfTransactionsEj0
_ZN11TracePlayer6finishEv37
_ZN11TracePlayer9terminateEv37
_ZN11TracePlayerC2EN7sc_core14sc_module_nameEP19TracePlayerListener37
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TracePlayer.cpp.gcov.html b/html/DRAMSys/simulator/TracePlayer.cpp.gcov.html new file mode 100644 index 00000000..915a4953 --- /dev/null +++ b/html/DRAMSys/simulator/TracePlayer.cpp.gcov.html @@ -0,0 +1,217 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TracePlayer.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - TracePlayer.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:475388.7 %
Date:2020-06-30 17:34:44Functions:101190.9 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
+       1             : /* EOF */
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TracePlayer.h.func-sort-c.html b/html/DRAMSys/simulator/TracePlayer.h.func-sort-c.html new file mode 100644 index 00000000..c10aea59 --- /dev/null +++ b/html/DRAMSys/simulator/TracePlayer.h.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TracePlayer.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - TracePlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN11TracePlayerD0Ev0
_ZN11TracePlayerD2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TracePlayer.h.func.html b/html/DRAMSys/simulator/TracePlayer.h.func.html new file mode 100644 index 00000000..77f8ef2e --- /dev/null +++ b/html/DRAMSys/simulator/TracePlayer.h.func.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TracePlayer.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - TracePlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TracePlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TracePlayerListener.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:00-
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TracePlayerListener.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:00-
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TracePlayerListener.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TraceSetup.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TraceSetup.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:374386.0 %
Date:2020-06-30 17:34:44Functions:55100.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TraceSetup.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:374386.0 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TraceSetup.h (source / functions)HitTotalCoverage
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+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TraceSetup.h.func.html b/html/DRAMSys/simulator/TraceSetup.h.func.html new file mode 100644 index 00000000..41a03ffb --- /dev/null +++ b/html/DRAMSys/simulator/TraceSetup.h.func.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TraceSetup.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TraceSetup.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
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+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TraceSetup.h.gcov.html b/html/DRAMSys/simulator/TraceSetup.h.gcov.html new file mode 100644 index 00000000..b3cc1626 --- /dev/null +++ b/html/DRAMSys/simulator/TraceSetup.h.gcov.html @@ -0,0 +1,141 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TraceSetup.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/simulator/index-sort-f.html b/html/DRAMSys/simulator/index-sort-f.html new file mode 100644 index 00000000..5485068d --- /dev/null +++ b/html/DRAMSys/simulator/index-sort-f.html @@ -0,0 +1,173 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator + + + + + + + + + + + + + + +
LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
TracePlayer.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
StlPlayer.h +
77.4%77.4%
+ 		77.4 %48 / 6225.0 %2 / 8
TraceSetup.h +
100.0%
+ 		100.0 %1 / 150.0 %1 / 2
MemoryManager.cpp +
75.0%75.0%
+ 		75.0 %18 / 2471.4 %5 / 7
main.cpp +
70.2%70.2%
+ 		70.2 %33 / 4783.3 %5 / 6
TracePlayer.cpp +
88.7%88.7%
+ 		88.7 %47 / 5390.9 %10 / 11
TracePlayerListener.h +
0.0%
+ 		0.0 %0 / 1-0 / 0
TraceSetup.cpp +
86.0%86.0%
+ 		86.0 %37 / 43100.0 %5 / 5
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/index-sort-l.html b/html/DRAMSys/simulator/index-sort-l.html new file mode 100644 index 00000000..410cace6 --- /dev/null +++ b/html/DRAMSys/simulator/index-sort-l.html @@ -0,0 +1,173 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - /DRAMSys/simulatorHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:18423279.3 %
Date:2020-06-30 17:34:44Functions:284168.3 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
TracePlayerListener.h +
0.0%
+ 		0.0 %0 / 1-0 / 0
TracePlayer.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
main.cpp +
70.2%70.2%
+ 		70.2 %33 / 4783.3 %5 / 6
MemoryManager.cpp +
75.0%75.0%
+ 		75.0 %18 / 2471.4 %5 / 7
StlPlayer.h +
77.4%77.4%
+ 		77.4 %48 / 6225.0 %2 / 8
TraceSetup.cpp +
86.0%86.0%
+ 		86.0 %37 / 43100.0 %5 / 5
TracePlayer.cpp +
88.7%88.7%
+ 		88.7 %47 / 5390.9 %10 / 11
TraceSetup.h +
100.0%
+ 		100.0 %1 / 150.0 %1 / 2
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/index.html b/html/DRAMSys/simulator/index.html new file mode 100644 index 00000000..6a4db168 --- /dev/null +++ b/html/DRAMSys/simulator/index.html @@ -0,0 +1,173 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - /DRAMSys/simulatorHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:18423279.3 %
Date:2020-06-30 17:34:44Functions:284168.3 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
MemoryManager.cpp +
75.0%75.0%
+ 		75.0 %18 / 2471.4 %5 / 7
StlPlayer.h +
77.4%77.4%
+ 		77.4 %48 / 6225.0 %2 / 8
TracePlayer.cpp +
88.7%88.7%
+ 		88.7 %47 / 5390.9 %10 / 11
TracePlayer.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
TracePlayerListener.h +
0.0%
+ 		0.0 %0 / 1-0 / 0
TraceSetup.cpp +
86.0%86.0%
+ 		86.0 %37 / 43100.0 %5 / 5
TraceSetup.h +
100.0%
+ 		100.0 %1 / 150.0 %1 / 2
main.cpp +
70.2%70.2%
+ 		70.2 %33 / 4783.3 %5 / 6
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/main.cpp.func-sort-c.html b/html/DRAMSys/simulator/main.cpp.func-sort-c.html new file mode 100644 index 00000000..a5c6f21a --- /dev/null +++ b/html/DRAMSys/simulator/main.cpp.func-sort-c.html @@ -0,0 +1,101 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/main.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - main.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:334770.2 %
Date:2020-06-30 17:34:44Functions:5683.3 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
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_Z41__static_initialization_and_destruction_0ii30
_Z41__static_initialization_and_destruction_1ii30
main30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/main.cpp.func.html b/html/DRAMSys/simulator/main.cpp.func.html new file mode 100644 index 00000000..462e064b --- /dev/null +++ b/html/DRAMSys/simulator/main.cpp.func.html @@ -0,0 +1,101 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/main.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - main.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:334770.2 %
Date:2020-06-30 17:34:44Functions:5683.3 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__Z10pathOfFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE30
_Z10pathOfFileNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE0
_Z41__static_initialization_and_destruction_0ii30
_Z41__static_initialization_and_destruction_1ii30
main30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/main.cpp.gcov.html b/html/DRAMSys/simulator/main.cpp.gcov.html new file mode 100644 index 00000000..97950faf --- /dev/null +++ b/html/DRAMSys/simulator/main.cpp.gcov.html @@ -0,0 +1,232 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/main.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - main.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:334770.2 %
Date:2020-06-30 17:34:44Functions:5683.3 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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+     147         150 : /* EOF */
+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/gcov.css b/html/gcov.css new file mode 100644 index 00000000..bfd0a83e --- /dev/null +++ b/html/gcov.css @@ -0,0 +1,519 @@ +/* All views: initial background and text color */ +body +{ + color: #000000; + background-color: #FFFFFF; +} + +/* All views: standard link format*/ +a:link +{ + color: #284FA8; + text-decoration: underline; +} + +/* All views: standard link - visited format */ +a:visited +{ + color: #00CB40; + text-decoration: underline; +} + +/* All views: standard link - activated format */ +a:active +{ + color: #FF0040; + text-decoration: underline; +} + +/* All views: main title format */ +td.title +{ + text-align: center; + padding-bottom: 10px; + font-family: sans-serif; + font-size: 20pt; + font-style: italic; + font-weight: bold; +} + +/* All views: header item format */ +td.headerItem +{ + text-align: right; + padding-right: 6px; + font-family: sans-serif; + font-weight: bold; + vertical-align: top; + white-space: nowrap; +} + +/* All views: header item value format */ +td.headerValue +{ + text-align: left; + color: #284FA8; + font-family: sans-serif; + font-weight: bold; + white-space: nowrap; +} + +/* All views: header item coverage table heading */ +td.headerCovTableHead +{ + text-align: center; + padding-right: 6px; + padding-left: 6px; + padding-bottom: 0px; + font-family: sans-serif; + font-size: 80%; + white-space: nowrap; +} + +/* All views: header item coverage table entry */ +td.headerCovTableEntry +{ + text-align: right; + color: #284FA8; + font-family: sans-serif; + font-weight: bold; + white-space: nowrap; + padding-left: 12px; + padding-right: 4px; + background-color: #DAE7FE; +} + +/* All views: header item coverage table entry for high coverage rate */ +td.headerCovTableEntryHi +{ + text-align: right; + color: #000000; + font-family: sans-serif; + font-weight: bold; + white-space: nowrap; + padding-left: 12px; + padding-right: 4px; + background-color: #A7FC9D; +} + +/* All views: header item coverage table entry for medium coverage rate */ +td.headerCovTableEntryMed +{ + text-align: right; + color: #000000; + font-family: sans-serif; + font-weight: bold; + white-space: nowrap; + padding-left: 12px; + padding-right: 4px; + background-color: #FFEA20; +} + +/* All views: header item coverage table entry for ow coverage rate */ +td.headerCovTableEntryLo +{ + text-align: right; + color: #000000; + font-family: sans-serif; + font-weight: bold; + white-space: nowrap; + padding-left: 12px; + padding-right: 4px; + background-color: #FF0000; +} + +/* All views: header legend value for legend entry */ +td.headerValueLeg +{ + text-align: left; + color: #000000; + font-family: sans-serif; + font-size: 80%; + white-space: nowrap; + padding-top: 4px; +} + +/* All views: color of horizontal ruler */ +td.ruler +{ + background-color: #6688D4; +} + +/* All views: version string format */ +td.versionInfo +{ + text-align: center; + padding-top: 2px; + font-family: sans-serif; + font-style: italic; +} + +/* Directory view/File view (all)/Test case descriptions: + table headline format */ +td.tableHead +{ + text-align: center; + color: #FFFFFF; + background-color: #6688D4; + font-family: sans-serif; + font-size: 120%; + font-weight: bold; + white-space: nowrap; + padding-left: 4px; + padding-right: 4px; +} + +span.tableHeadSort +{ + padding-right: 4px; +} + +/* Directory view/File view (all): filename entry format */ +td.coverFile +{ + text-align: left; + padding-left: 10px; + padding-right: 20px; + color: #284FA8; + background-color: #DAE7FE; + font-family: monospace; +} + +/* Directory view/File view (all): bar-graph entry format*/ +td.coverBar +{ + padding-left: 10px; + padding-right: 10px; + background-color: #DAE7FE; +} + +/* Directory view/File view (all): bar-graph outline color */ +td.coverBarOutline +{ + background-color: #000000; +} + +/* Directory view/File view (all): percentage entry for files with + high coverage rate */ +td.coverPerHi +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #A7FC9D; + font-weight: bold; + font-family: sans-serif; +} + +/* Directory view/File view (all): line count entry for files with + high coverage rate */ +td.coverNumHi +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #A7FC9D; + white-space: nowrap; + font-family: sans-serif; +} + +/* Directory view/File view (all): percentage entry for files with + medium coverage rate */ +td.coverPerMed +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #FFEA20; + font-weight: bold; + font-family: sans-serif; +} + +/* Directory view/File view (all): line count entry for files with + medium coverage rate */ +td.coverNumMed +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #FFEA20; + white-space: nowrap; + font-family: sans-serif; +} + +/* Directory view/File view (all): percentage entry for files with + low coverage rate */ +td.coverPerLo +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #FF0000; + font-weight: bold; + font-family: sans-serif; +} + +/* Directory view/File view (all): line count entry for files with + low coverage rate */ +td.coverNumLo +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #FF0000; + white-space: nowrap; + font-family: sans-serif; +} + +/* File view (all): "show/hide details" link format */ +a.detail:link +{ + color: #B8D0FF; + font-size:80%; +} + +/* File view (all): "show/hide details" link - visited format */ +a.detail:visited +{ + color: #B8D0FF; + font-size:80%; +} + +/* File view (all): "show/hide details" link - activated format */ +a.detail:active +{ + color: #FFFFFF; + font-size:80%; +} + +/* File view (detail): test name entry */ +td.testName +{ + text-align: right; + padding-right: 10px; + background-color: #DAE7FE; + font-family: sans-serif; +} + +/* File view (detail): test percentage entry */ +td.testPer +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #DAE7FE; + font-family: sans-serif; +} + +/* File view (detail): test lines count entry */ +td.testNum +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #DAE7FE; + font-family: sans-serif; +} + +/* Test case descriptions: test name format*/ +dt +{ + font-family: sans-serif; + font-weight: bold; +} + +/* Test case descriptions: description table body */ +td.testDescription +{ + padding-top: 10px; + padding-left: 30px; + padding-bottom: 10px; + padding-right: 30px; + background-color: #DAE7FE; +} + +/* Source code view: function entry */ +td.coverFn +{ + text-align: left; + padding-left: 10px; + padding-right: 20px; + color: #284FA8; + background-color: #DAE7FE; + font-family: monospace; +} + +/* Source code view: function entry zero count*/ +td.coverFnLo +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #FF0000; + font-weight: bold; + font-family: sans-serif; +} + +/* Source code view: function entry nonzero count*/ +td.coverFnHi +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #DAE7FE; + font-weight: bold; + font-family: sans-serif; +} + +/* Source code view: source code format */ +pre.source +{ + font-family: monospace; + white-space: pre; + margin-top: 2px; +} + +/* Source code view: line number format */ +span.lineNum +{ + background-color: #EFE383; +} + +/* Source code view: format for lines which were executed */ +td.lineCov, +span.lineCov +{ + background-color: #CAD7FE; +} + +/* Source code view: format for Cov legend */ +span.coverLegendCov +{ + padding-left: 10px; + padding-right: 10px; + padding-bottom: 2px; + background-color: #CAD7FE; +} + +/* Source code view: format for lines which were not executed */ +td.lineNoCov, +span.lineNoCov +{ + background-color: #FF6230; +} + +/* Source code view: format for NoCov legend */ +span.coverLegendNoCov +{ + padding-left: 10px; + padding-right: 10px; + padding-bottom: 2px; + background-color: #FF6230; +} + +/* Source code view (function table): standard link - visited format */ +td.lineNoCov > a:visited, +td.lineCov > a:visited +{ + color: black; + text-decoration: underline; +} + +/* Source code view: format for lines which were executed only in a + previous version */ +span.lineDiffCov +{ + background-color: #B5F7AF; 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+ background-color: #FFEA20; + font-size: 80%; +} + +/* All views: header legend value for hi rate */ +td.headerValueLegH +{ + font-family: sans-serif; + text-align: center; + white-space: nowrap; + padding-left: 2px; + padding-right: 4px; + background-color: #A7FC9D; + font-size: 80%; +} + +/* All views except source code view: legend format for low coverage */ +span.coverLegendCovLo +{ + padding-left: 10px; + padding-right: 10px; + padding-top: 2px; + background-color: #FF0000; +} + +/* All views except source code view: legend format for med coverage */ +span.coverLegendCovMed +{ + padding-left: 10px; + padding-right: 10px; + padding-top: 2px; + background-color: #FFEA20; +} + +/* All views except source code view: legend format for hi coverage */ +span.coverLegendCovHi +{ + padding-left: 10px; + padding-right: 10px; + padding-top: 2px; + background-color: #A7FC9D; +} diff --git a/html/index-sort-f.html b/html/index-sort-f.html new file mode 100644 index 00000000..d9eeb09a --- /dev/null +++ b/html/index-sort-f.html @@ -0,0 +1,243 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top levelHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3137765241.0 %
Date:2020-06-30 17:34:44Functions:40274753.8 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
/DRAMSys/library/src/error/ECC +
1.4%1.4%
+ 		1.4 %2 / 1427.1 %2 / 28
/DRAMSys/library/src/error +
0.7%0.7%
+ 		0.7 %3 / 40417.6 %6 / 34
/DRAMSys/library/src/simulation/dram +
16.1%16.1%
+ 		16.1 %72 / 44835.2 %45 / 128
/DRAMSys/library/src/configuration/memspec +
42.8%42.8%
+ 		42.8 %319 / 74543.7 %38 / 87
/DRAMSys/library/src/common +
44.1%44.1%
+ 		44.1 %500 / 113547.1 %65 / 138
/DRAMSys/library/src/controller/checker +
26.8%26.8%
+ 		26.8 %802 / 298760.3 %38 / 63
/DRAMSys/simulator +
79.3%79.3%
+ 		79.3 %184 / 23268.3 %28 / 41
/DRAMSys/library/src/simulation +
55.2%55.2%
+ 		55.2 %207 / 37569.8 %30 / 43
/DRAMSys/library/src/controller/respqueue +
50.0%50.0%
+ 		50.0 %17 / 3470.0 %7 / 10
/DRAMSys/library/src/controller/refresh +
87.7%87.7%
+ 		87.7 %164 / 18773.9 %17 / 23
/DRAMSys/library/src/controller +
89.3%89.3%
+ 		89.3 %461 / 51678.6 %55 / 70
/DRAMSys/library/src/controller/cmdmux +
100.0%
+ 		100.0 %26 / 2680.0 %8 / 10
/DRAMSys/library/src/controller/scheduler +
87.8%87.8%
+ 		87.8 %101 / 11581.8 %27 / 33
/DRAMSys/library/src/controller/powerdown +
97.1%97.1%
+ 		97.1 %101 / 10490.5 %19 / 21
/DRAMSys/library/src/configuration +
88.1%88.1%
+ 		88.1 %178 / 20294.4 %17 / 18
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/index-sort-l.html b/html/index-sort-l.html new file mode 100644 index 00000000..26f46bba --- /dev/null +++ b/html/index-sort-l.html @@ -0,0 +1,243 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top levelHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3137765241.0 %
Date:2020-06-30 17:34:44Functions:40274753.8 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
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+ +
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Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
/DRAMSys/library/src/error +
0.7%0.7%
+ 		0.7 %3 / 40417.6 %6 / 34
/DRAMSys/library/src/error/ECC +
1.4%1.4%
+ 		1.4 %2 / 1427.1 %2 / 28
/DRAMSys/library/src/simulation/dram +
16.1%16.1%
+ 		16.1 %72 / 44835.2 %45 / 128
/DRAMSys/library/src/controller/checker +
26.8%26.8%
+ 		26.8 %802 / 298760.3 %38 / 63
/DRAMSys/library/src/configuration/memspec +
42.8%42.8%
+ 		42.8 %319 / 74543.7 %38 / 87
/DRAMSys/library/src/common +
44.1%44.1%
+ 		44.1 %500 / 113547.1 %65 / 138
/DRAMSys/library/src/controller/respqueue +
50.0%50.0%
+ 		50.0 %17 / 3470.0 %7 / 10
/DRAMSys/library/src/simulation +
55.2%55.2%
+ 		55.2 %207 / 37569.8 %30 / 43
/DRAMSys/simulator +
79.3%79.3%
+ 		79.3 %184 / 23268.3 %28 / 41
/DRAMSys/library/src/controller/refresh +
87.7%87.7%
+ 		87.7 %164 / 18773.9 %17 / 23
/DRAMSys/library/src/controller/scheduler +
87.8%87.8%
+ 		87.8 %101 / 11581.8 %27 / 33
/DRAMSys/library/src/configuration +
88.1%88.1%
+ 		88.1 %178 / 20294.4 %17 / 18
/DRAMSys/library/src/controller +
89.3%89.3%
+ 		89.3 %461 / 51678.6 %55 / 70
/DRAMSys/library/src/controller/powerdown +
97.1%97.1%
+ 		97.1 %101 / 10490.5 %19 / 21
/DRAMSys/library/src/controller/cmdmux +
100.0%
+ 		100.0 %26 / 2680.0 %8 / 10
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/index.html b/html/index.html new file mode 100644 index 00000000..e46e0fb3 --- /dev/null +++ b/html/index.html @@ -0,0 +1,243 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top levelHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3137765241.0 %
Date:2020-06-30 17:34:44Functions:40274753.8 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
+
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Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
/DRAMSys/library/src/common +
44.1%44.1%
+ 		44.1 %500 / 113547.1 %65 / 138
/DRAMSys/library/src/configuration +
88.1%88.1%
+ 		88.1 %178 / 20294.4 %17 / 18
/DRAMSys/library/src/configuration/memspec +
42.8%42.8%
+ 		42.8 %319 / 74543.7 %38 / 87
/DRAMSys/library/src/controller +
89.3%89.3%
+ 		89.3 %461 / 51678.6 %55 / 70
/DRAMSys/library/src/controller/checker +
26.8%26.8%
+ 		26.8 %802 / 298760.3 %38 / 63
/DRAMSys/library/src/controller/cmdmux +
100.0%
+ 		100.0 %26 / 2680.0 %8 / 10
/DRAMSys/library/src/controller/powerdown +
97.1%97.1%
+ 		97.1 %101 / 10490.5 %19 / 21
/DRAMSys/library/src/controller/refresh +
87.7%87.7%
+ 		87.7 %164 / 18773.9 %17 / 23
/DRAMSys/library/src/controller/respqueue +
50.0%50.0%
+ 		50.0 %17 / 3470.0 %7 / 10
/DRAMSys/library/src/controller/scheduler +
87.8%87.8%
+ 		87.8 %101 / 11581.8 %27 / 33
/DRAMSys/library/src/error +
0.7%0.7%
+ 		0.7 %3 / 40417.6 %6 / 34
/DRAMSys/library/src/error/ECC +
1.4%1.4%
+ 		1.4 %2 / 1427.1 %2 / 28
/DRAMSys/library/src/simulation +
55.2%55.2%
+ 		55.2 %207 / 37569.8 %30 / 43
/DRAMSys/library/src/simulation/dram +
16.1%16.1%
+ 		16.1 %72 / 44835.2 %45 / 128
/DRAMSys/simulator +
79.3%79.3%
+ 		79.3 %184 / 23268.3 %28 / 41
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + From 072ae5960c8a4fbd725ccbc7064ab006d676f1a1 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 17:44:57 +0200 Subject: [PATCH 33/53] html files removed --- .../AddressDecoder.cpp.func-sort-c.html | 93 -- .../src/common/AddressDecoder.cpp.func.html | 93 -- .../src/common/AddressDecoder.cpp.gcov.html | 367 ------ .../common/AddressDecoder.h.func-sort-c.html | 81 -- .../src/common/AddressDecoder.h.func.html | 81 -- .../src/common/AddressDecoder.h.gcov.html | 144 --- .../common/TlmRecorder.cpp.func-sort-c.html | 153 --- .../src/common/TlmRecorder.cpp.func.html | 153 --- .../src/common/TlmRecorder.cpp.gcov.html | 557 -------- .../src/common/TlmRecorder.h.func-sort-c.html | 81 -- .../src/common/TlmRecorder.h.func.html | 81 -- .../src/common/TlmRecorder.h.gcov.html | 184 --- .../dramExtensions.cpp.func-sort-c.html | 309 ----- .../src/common/dramExtensions.cpp.func.html | 309 ----- .../src/common/dramExtensions.cpp.gcov.html | 434 ------- .../common/dramExtensions.h.func-sort-c.html | 97 -- .../src/common/dramExtensions.h.func.html | 97 -- .../src/common/dramExtensions.h.gcov.html | 321 ----- .../library/src/common/index-sort-f.html | 183 --- .../library/src/common/index-sort-l.html | 183 --- html/DRAMSys/library/src/common/index.html | 183 --- ...2_base_protocol_checker.h.func-sort-c.html | 181 --- .../tlm2_base_protocol_checker.h.func.html | 181 --- .../tlm2_base_protocol_checker.h.gcov.html | 1128 ----------------- .../src/common/utils.cpp.func-sort-c.html | 109 -- .../library/src/common/utils.cpp.func.html | 109 -- .../library/src/common/utils.cpp.gcov.html | 239 ---- .../src/common/utils.h.func-sort-c.html | 85 -- .../library/src/common/utils.h.func.html | 85 -- .../library/src/common/utils.h.gcov.html | 187 --- .../Configuration.cpp.func-sort-c.html | 113 -- .../configuration/Configuration.cpp.func.html | 113 -- .../configuration/Configuration.cpp.gcov.html | 397 ------ .../Configuration.h.func-sort-c.html | 93 -- .../configuration/Configuration.h.func.html | 93 -- .../configuration/Configuration.h.gcov.html | 147 --- .../TemperatureSimConfig.h.func-sort-c.html | 85 -- .../TemperatureSimConfig.h.func.html | 85 -- .../TemperatureSimConfig.h.gcov.html | 207 --- .../src/configuration/index-sort-f.html | 123 -- .../src/configuration/index-sort-l.html | 123 -- .../library/src/configuration/index.html | 123 -- .../memspec/MemSpec.cpp.func-sort-c.html | 97 -- .../memspec/MemSpec.cpp.func.html | 97 -- .../memspec/MemSpec.cpp.gcov.html | 161 --- .../memspec/MemSpec.h.func-sort-c.html | 89 -- .../configuration/memspec/MemSpec.h.func.html | 89 -- .../configuration/memspec/MemSpec.h.gcov.html | 157 --- .../memspec/MemSpecDDR3.cpp.func-sort-c.html | 109 -- .../memspec/MemSpecDDR3.cpp.func.html | 109 -- .../memspec/MemSpecDDR3.cpp.gcov.html | 225 ---- .../memspec/MemSpecDDR3.h.func-sort-c.html | 89 -- .../memspec/MemSpecDDR3.h.func.html | 89 -- .../memspec/MemSpecDDR3.h.gcov.html | 127 -- .../memspec/MemSpecDDR4.cpp.func-sort-c.html | 105 -- .../memspec/MemSpecDDR4.cpp.func.html | 105 -- .../memspec/MemSpecDDR4.cpp.gcov.html | 242 ---- .../memspec/MemSpecDDR4.h.func-sort-c.html | 89 -- .../memspec/MemSpecDDR4.h.func.html | 89 -- .../memspec/MemSpecDDR4.h.gcov.html | 127 -- .../memspec/MemSpecGDDR5.cpp.func-sort-c.html | 109 -- .../memspec/MemSpecGDDR5.cpp.func.html | 109 -- .../memspec/MemSpecGDDR5.cpp.gcov.html | 229 ---- .../memspec/MemSpecGDDR5.h.func-sort-c.html | 89 -- .../memspec/MemSpecGDDR5.h.func.html | 89 -- .../memspec/MemSpecGDDR5.h.gcov.html | 127 -- .../MemSpecGDDR5X.cpp.func-sort-c.html | 109 -- .../memspec/MemSpecGDDR5X.cpp.func.html | 109 -- .../memspec/MemSpecGDDR5X.cpp.gcov.html | 229 ---- .../memspec/MemSpecGDDR5X.h.func-sort-c.html | 89 -- .../memspec/MemSpecGDDR5X.h.func.html | 89 -- .../memspec/MemSpecGDDR5X.h.gcov.html | 127 -- .../memspec/MemSpecGDDR6.cpp.func-sort-c.html | 109 -- .../memspec/MemSpecGDDR6.cpp.func.html | 109 -- .../memspec/MemSpecGDDR6.cpp.gcov.html | 231 ---- .../memspec/MemSpecGDDR6.h.func-sort-c.html | 89 -- .../memspec/MemSpecGDDR6.h.func.html | 89 -- .../memspec/MemSpecGDDR6.h.gcov.html | 127 -- .../memspec/MemSpecHBM2.cpp.func-sort-c.html | 109 -- .../memspec/MemSpecHBM2.cpp.func.html | 109 -- .../memspec/MemSpecHBM2.cpp.gcov.html | 226 ---- .../memspec/MemSpecHBM2.h.func-sort-c.html | 89 -- .../memspec/MemSpecHBM2.h.func.html | 89 -- .../memspec/MemSpecHBM2.h.gcov.html | 127 -- .../MemSpecLPDDR4.cpp.func-sort-c.html | 109 -- .../memspec/MemSpecLPDDR4.cpp.func.html | 109 -- .../memspec/MemSpecLPDDR4.cpp.gcov.html | 233 ---- .../memspec/MemSpecLPDDR4.h.func-sort-c.html | 89 -- .../memspec/MemSpecLPDDR4.h.func.html | 89 -- .../memspec/MemSpecLPDDR4.h.gcov.html | 127 -- .../MemSpecWideIO.cpp.func-sort-c.html | 109 -- .../memspec/MemSpecWideIO.cpp.func.html | 109 -- .../memspec/MemSpecWideIO.cpp.gcov.html | 233 ---- .../memspec/MemSpecWideIO.h.func-sort-c.html | 89 -- .../memspec/MemSpecWideIO.h.func.html | 89 -- .../memspec/MemSpecWideIO.h.gcov.html | 127 -- .../MemSpecWideIO2.cpp.func-sort-c.html | 109 -- .../memspec/MemSpecWideIO2.cpp.func.html | 109 -- .../memspec/MemSpecWideIO2.cpp.gcov.html | 218 ---- .../memspec/MemSpecWideIO2.h.func-sort-c.html | 89 -- .../memspec/MemSpecWideIO2.h.func.html | 89 -- .../memspec/MemSpecWideIO2.h.gcov.html | 127 -- .../configuration/memspec/index-sort-f.html | 293 ----- .../configuration/memspec/index-sort-l.html | 293 ----- .../src/configuration/memspec/index.html | 293 ----- .../BankMachine.cpp.func-sort-c.html | 161 --- .../src/controller/BankMachine.cpp.func.html | 161 --- .../src/controller/BankMachine.cpp.gcov.html | 413 ------ .../controller/BankMachine.h.func-sort-c.html | 113 -- .../src/controller/BankMachine.h.func.html | 113 -- .../src/controller/BankMachine.h.gcov.html | 194 --- .../controller/Command.cpp.func-sort-c.html | 133 -- .../src/controller/Command.cpp.func.html | 133 -- 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LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:14720.2 %
Date:2020-06-30 17:34:44Functions:0280.0 %
Legend: Lines: - hit - not hit -
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13700.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5.h (source / functions)HitTotalCoverage
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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Function Name Sort by function nameHit count Sort by hit count
_ZN12CheckerGDDR5D0Ev0
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Generated by: LCOV version 1.13
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- - - diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.h.func.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.h.func.html deleted file mode 100644 index b92b3e8d..00000000 --- a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.h.func.html +++ /dev/null @@ -1,85 +0,0 @@ - - - - - - - LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 -commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5.h - functions - - - - - - - - - - - - - - -
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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Function Name Sort by function nameHit count Sort by hit count
_ZN12CheckerGDDR5D0Ev0
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation - DRAMSys.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:71258.3 %
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation - DRAMSysRecordable.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:669073.3 %
Date:2020-06-30 17:34:44Functions:99100.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Current view:top level - DRAMSys/library/src/simulation - DRAMSysRecordable.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:669073.3 %
Date:2020-06-30 17:34:44Functions:99100.0 %
Legend: Lines: - hit - not hit -
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN17DRAMSysRecordableC2EN7sc_core14sc_module_nameENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES7_30
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation - DRAMSysRecordable.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:669073.3 %
Date:2020-06-30 17:34:44Functions:99100.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation - TemperatureController.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1442.3 %
Date:2020-06-30 17:34:44Functions:2825.0 %
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Function Name Sort by function nameHit count Sort by hit count
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Current view:top level - /DRAMSys/library/src/simulation/dramHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:7244816.1 %
Date:2020-06-30 17:34:44Functions:4512835.2 %
Legend: Rating: - low: < 75 % - medium: >= 75 % - high: >= 90 % -
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
Dram.cpp -
25.7%25.7%
- 		25.7 %19 / 7462.5 %5 / 8
Dram.h -
100.0%
- 		100.0 %2 / 2-0 / 0
DramDDR3.cpp -
4.8%4.8%
- 		4.8 %4 / 83100.0 %3 / 3
DramDDR3.h -
100.0%
- 		100.0 %1 / 10.0 %0 / 2
DramDDR4.cpp -
4.8%4.8%
- 		4.8 %4 / 83100.0 %3 / 3
DramDDR4.h -
100.0%
- 		100.0 %1 / 10.0 %0 / 2
DramGDDR5.cpp -
16.7%16.7%
- 		16.7 %1 / 666.7 %2 / 3
DramGDDR5.h -
0.0%
- 		0.0 %0 / 10.0 %0 / 2
DramGDDR5X.cpp -
16.7%16.7%
- 		16.7 %1 / 666.7 %2 / 3
DramGDDR5X.h -
0.0%
- 		0.0 %0 / 10.0 %0 / 2
DramGDDR6.cpp -
16.7%16.7%
- 		16.7 %1 / 666.7 %2 / 3
DramGDDR6.h -
0.0%
- 		0.0 %0 / 10.0 %0 / 2
DramHBM2.cpp -
66.7%66.7%
- 		66.7 %4 / 6100.0 %3 / 3
DramHBM2.h -
100.0%
- 		100.0 %1 / 10.0 %0 / 2
DramLPDDR4.cpp -
66.7%66.7%
- 		66.7 %4 / 6100.0 %3 / 3
DramLPDDR4.h -
100.0%
- 		100.0 %1 / 10.0 %0 / 2
DramRecordable.cpp -
60.5%60.5%
- 		60.5 %23 / 3829.8 %14 / 47
DramRecordable.h -
60.0%60.0%
- 		60.0 %3 / 514.8 %4 / 27
DramWideIO.cpp -
0.8%0.8%
- 		0.8 %1 / 11933.3 %2 / 6
DramWideIO2.cpp -
16.7%16.7%
- 		16.7 %1 / 666.7 %2 / 3
DramWideIO2.h -
0.0%
- 		0.0 %0 / 10.0 %0 / 2
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - /DRAMSys/library/src/simulationHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:20737555.2 %
Date:2020-06-30 17:34:44Functions:304369.8 %
Legend: Rating: - low: < 75 % - medium: >= 75 % - high: >= 90 % -
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
TemperatureController.cpp -
2.3%2.3%
- 		2.3 %1 / 4425.0 %2 / 8
DRAMSys.cpp -
40.2%40.2%
- 		40.2 %47 / 11758.3 %7 / 12
TemperatureController.h -
34.4%34.4%
- 		34.4 %11 / 3275.0 %3 / 4
Arbiter.cpp -
89.0%89.0%
- 		89.0 %81 / 9187.5 %7 / 8
Arbiter.h -
100.0%
- 		100.0 %1 / 1100.0 %2 / 2
DRAMSysRecordable.cpp -
73.3%73.3%
- 		73.3 %66 / 90100.0 %9 / 9
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - /DRAMSys/library/src/simulationHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:20737555.2 %
Date:2020-06-30 17:34:44Functions:304369.8 %
Legend: Rating: - low: < 75 % - medium: >= 75 % - high: >= 90 % -
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
TemperatureController.cpp -
2.3%2.3%
- 		2.3 %1 / 4425.0 %2 / 8
TemperatureController.h -
34.4%34.4%
- 		34.4 %11 / 3275.0 %3 / 4
DRAMSys.cpp -
40.2%40.2%
- 		40.2 %47 / 11758.3 %7 / 12
DRAMSysRecordable.cpp -
73.3%73.3%
- 		73.3 %66 / 90100.0 %9 / 9
Arbiter.cpp -
89.0%89.0%
- 		89.0 %81 / 9187.5 %7 / 8
Arbiter.h -
100.0%
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - /DRAMSys/library/src/simulationHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:20737555.2 %
Date:2020-06-30 17:34:44Functions:304369.8 %
Legend: Rating: - low: < 75 % - medium: >= 75 % - high: >= 90 % -
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
Arbiter.cpp -
89.0%89.0%
- 		89.0 %81 / 9187.5 %7 / 8
Arbiter.h -
100.0%
- 		100.0 %1 / 1100.0 %2 / 2
DRAMSys.cpp -
40.2%40.2%
- 		40.2 %47 / 11758.3 %7 / 12
DRAMSysRecordable.cpp -
73.3%73.3%
- 		73.3 %66 / 90100.0 %9 / 9
TemperatureController.cpp -
2.3%2.3%
- 		2.3 %1 / 4425.0 %2 / 8
TemperatureController.h -
34.4%34.4%
- 		34.4 %11 / 3275.0 %3 / 4
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Generated by: LCOV version 1.13
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- - - diff --git a/html/DRAMSys/simulator/MemoryManager.cpp.func-sort-c.html b/html/DRAMSys/simulator/MemoryManager.cpp.func-sort-c.html deleted file mode 100644 index 2b15610b..00000000 --- a/html/DRAMSys/simulator/MemoryManager.cpp.func-sort-c.html +++ /dev/null @@ -1,109 +0,0 @@ - - - - - - - LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 -commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/MemoryManager.cpp - functions - - - - - - - - - - - - - - -
LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - MemoryManager.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:182475.0 %
Date:2020-06-30 17:34:44Functions:5771.4 %
Legend: Lines: - hit - not hit -
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Function Name Sort by function nameHit count Sort by hit count
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_ZN13MemoryManager8allocateEv252938
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - MemoryManager.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:182475.0 %
Date:2020-06-30 17:34:44Functions:5771.4 %
Legend: Lines: - hit - not hit -
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN13MemoryManagerC2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN13MemoryManager4freeEPN3tlm19tlm_generic_payloadE252908
_ZN13MemoryManager8allocateEv252938
_ZN13MemoryManagerC2Ev37
_ZN13MemoryManagerD0Ev0
_ZN13MemoryManagerD2Ev0
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - MemoryManager.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:182475.0 %
Date:2020-06-30 17:34:44Functions:5771.4 %
Legend: Lines: - hit - not hit -
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Generated by: LCOV version 1.13
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- - - diff --git a/html/DRAMSys/simulator/StlPlayer.h.func-sort-c.html b/html/DRAMSys/simulator/StlPlayer.h.func-sort-c.html deleted file mode 100644 index efbec1ae..00000000 --- a/html/DRAMSys/simulator/StlPlayer.h.func-sort-c.html +++ /dev/null @@ -1,97 +0,0 @@ - - - - - - - LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 -commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/StlPlayer.h - functions - - - - - - - - - - - - - - -
LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - StlPlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:486277.4 %
Date:2020-06-30 17:34:44Functions:2825.0 %
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Function Name Sort by function nameHit count Sort by hit count
_ZN9StlPlayerILb0EED0Ev0
_ZN9StlPlayerILb0EED2Ev0
_ZN9StlPlayerILb1EED0Ev0
_ZN9StlPlayerILb1EED2Ev0
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - StlPlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:486277.4 %
Date:2020-06-30 17:34:44Functions:2825.0 %
Legend: Lines: - hit - not hit -
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Function Name Sort by function nameHit count Sort by hit count
_ZN9StlPlayerILb0EED0Ev0
_ZN9StlPlayerILb0EED2Ev0
_ZN9StlPlayerILb1EED0Ev0
_ZN9StlPlayerILb1EED2Ev0
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Generated by: LCOV version 1.13
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- - - diff --git a/html/DRAMSys/simulator/StlPlayer.h.gcov.html b/html/DRAMSys/simulator/StlPlayer.h.gcov.html deleted file mode 100644 index 945ea4ec..00000000 --- a/html/DRAMSys/simulator/StlPlayer.h.gcov.html +++ /dev/null @@ -1,259 +0,0 @@ - - - - - - - LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 -commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/StlPlayer.h - - - - - - - - - - - - - - -
LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - StlPlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:486277.4 %
Date:2020-06-30 17:34:44Functions:2825.0 %
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Date:2020-06-30 17:34:44Functions:5683.3 %
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main30
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Current view:top level - DRAMSys/simulator - main.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:334770.2 %
Date:2020-06-30 17:34:44Functions:5683.3 %
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LCOV - code coverage report
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Current view:top levelHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3137765241.0 %
Date:2020-06-30 17:34:44Functions:40274753.8 %
Legend: Rating: - low: < 75 % - medium: >= 75 % - high: >= 90 % -
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Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
/DRAMSys/library/src/error/ECC -
1.4%1.4%
- 		1.4 %2 / 1427.1 %2 / 28
/DRAMSys/library/src/error -
0.7%0.7%
- 		0.7 %3 / 40417.6 %6 / 34
/DRAMSys/library/src/simulation/dram -
16.1%16.1%
- 		16.1 %72 / 44835.2 %45 / 128
/DRAMSys/library/src/configuration/memspec -
42.8%42.8%
- 		42.8 %319 / 74543.7 %38 / 87
/DRAMSys/library/src/common -
44.1%44.1%
- 		44.1 %500 / 113547.1 %65 / 138
/DRAMSys/library/src/controller/checker -
26.8%26.8%
- 		26.8 %802 / 298760.3 %38 / 63
/DRAMSys/simulator -
79.3%79.3%
- 		79.3 %184 / 23268.3 %28 / 41
/DRAMSys/library/src/simulation -
55.2%55.2%
- 		55.2 %207 / 37569.8 %30 / 43
/DRAMSys/library/src/controller/respqueue -
50.0%50.0%
- 		50.0 %17 / 3470.0 %7 / 10
/DRAMSys/library/src/controller/refresh -
87.7%87.7%
- 		87.7 %164 / 18773.9 %17 / 23
/DRAMSys/library/src/controller -
89.3%89.3%
- 		89.3 %461 / 51678.6 %55 / 70
/DRAMSys/library/src/controller/cmdmux -
100.0%
- 		100.0 %26 / 2680.0 %8 / 10
/DRAMSys/library/src/controller/scheduler -
87.8%87.8%
- 		87.8 %101 / 11581.8 %27 / 33
/DRAMSys/library/src/controller/powerdown -
97.1%97.1%
- 		97.1 %101 / 10490.5 %19 / 21
/DRAMSys/library/src/configuration -
88.1%88.1%
- 		88.1 %178 / 20294.4 %17 / 18
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top levelHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3137765241.0 %
Date:2020-06-30 17:34:44Functions:40274753.8 %
Legend: Rating: - low: < 75 % - medium: >= 75 % - high: >= 90 % -
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Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
/DRAMSys/library/src/error -
0.7%0.7%
- 		0.7 %3 / 40417.6 %6 / 34
/DRAMSys/library/src/error/ECC -
1.4%1.4%
- 		1.4 %2 / 1427.1 %2 / 28
/DRAMSys/library/src/simulation/dram -
16.1%16.1%
- 		16.1 %72 / 44835.2 %45 / 128
/DRAMSys/library/src/controller/checker -
26.8%26.8%
- 		26.8 %802 / 298760.3 %38 / 63
/DRAMSys/library/src/configuration/memspec -
42.8%42.8%
- 		42.8 %319 / 74543.7 %38 / 87
/DRAMSys/library/src/common -
44.1%44.1%
- 		44.1 %500 / 113547.1 %65 / 138
/DRAMSys/library/src/controller/respqueue -
50.0%50.0%
- 		50.0 %17 / 3470.0 %7 / 10
/DRAMSys/library/src/simulation -
55.2%55.2%
- 		55.2 %207 / 37569.8 %30 / 43
/DRAMSys/simulator -
79.3%79.3%
- 		79.3 %184 / 23268.3 %28 / 41
/DRAMSys/library/src/controller/refresh -
87.7%87.7%
- 		87.7 %164 / 18773.9 %17 / 23
/DRAMSys/library/src/controller/scheduler -
87.8%87.8%
- 		87.8 %101 / 11581.8 %27 / 33
/DRAMSys/library/src/configuration -
88.1%88.1%
- 		88.1 %178 / 20294.4 %17 / 18
/DRAMSys/library/src/controller -
89.3%89.3%
- 		89.3 %461 / 51678.6 %55 / 70
/DRAMSys/library/src/controller/powerdown -
97.1%97.1%
- 		97.1 %101 / 10490.5 %19 / 21
/DRAMSys/library/src/controller/cmdmux -
100.0%
- 		100.0 %26 / 2680.0 %8 / 10
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top levelHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3137765241.0 %
Date:2020-06-30 17:34:44Functions:40274753.8 %
Legend: Rating: - low: < 75 % - medium: >= 75 % - high: >= 90 % -
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Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
/DRAMSys/library/src/common -
44.1%44.1%
- 		44.1 %500 / 113547.1 %65 / 138
/DRAMSys/library/src/configuration -
88.1%88.1%
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/DRAMSys/library/src/configuration/memspec -
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/DRAMSys/library/src/controller -
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/DRAMSys/library/src/controller/checker -
26.8%26.8%
- 		26.8 %802 / 298760.3 %38 / 63
/DRAMSys/library/src/controller/cmdmux -
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/DRAMSys/library/src/controller/powerdown -
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- 		97.1 %101 / 10490.5 %19 / 21
/DRAMSys/library/src/controller/refresh -
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/DRAMSys/library/src/controller/respqueue -
50.0%50.0%
- 		50.0 %17 / 3470.0 %7 / 10
/DRAMSys/library/src/controller/scheduler -
87.8%87.8%
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/DRAMSys/library/src/error -
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/DRAMSys/library/src/error/ECC -
1.4%1.4%
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/DRAMSys/library/src/simulation -
55.2%55.2%
- 		55.2 %207 / 37569.8 %30 / 43
/DRAMSys/library/src/simulation/dram -
16.1%16.1%
- 		16.1 %72 / 44835.2 %45 / 128
/DRAMSys/simulator -
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- 		79.3 %184 / 23268.3 %28 / 41
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Generated by: LCOV version 1.13
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- - - From 56fa53b7848366ebe48daf4afec7df0a5835621e Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 19:02:22 +0200 Subject: [PATCH 34/53] export COVERAGE=true --- .gitlab-ci.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index bb478fa4..5540c9c6 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,6 +20,7 @@ build: - rm -rf build - mkdir -p build - cd build + - export COVERAGE=true - cmake ../DRAMSys - make -j 16 - find . -name "*.o" -type f -delete From b52cabf21ad5d3b87a0652d7369fdc3171b934f3 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 1 Jul 2020 15:41:20 +0200 Subject: [PATCH 35/53] Readme updates, separate gem5 readme. --- DRAMSys/gem5/README.md | 681 ++++++ DRAMSys/library/CMakeLists.txt | 4 +- DRAMSys/library/src/controller/Controller.cpp | 2 +- .../src/controller/respqueue/RespQueueIF.h | 1 + README.md | 1824 ++--------------- 5 files changed, 871 insertions(+), 1641 deletions(-) create mode 100644 DRAMSys/gem5/README.md diff --git a/DRAMSys/gem5/README.md b/DRAMSys/gem5/README.md new file mode 100644 index 00000000..d4966a95 --- /dev/null +++ b/DRAMSys/gem5/README.md @@ -0,0 +1,681 @@ +## DRAMSys with gem5 + +Install gem5 by following the instructions on the [gem5 wiki](http://gem5.org/Documentation#Getting_Started). +Optionally, use the scripts from [gem5.TnT] to install gem5, build it, get some benchmark programs and learn more about gem5. + +In order to understand the SystemC coupling with gem5 it is recommended to +read the documentation in the gem5 repository *util/tlm/README* and [12]. + +The main steps for building gem5 and libgem5 follow: + +```bash +scons build/ARM/gem5.opt +``` + +```bash +scons --with-cxx-config --without-python --without-tcmalloc build/ARM/libgem5_opt.so +``` + +For MacOS: + +```bash +scons --with-cxx-config --without-python --without-tcmalloc build/ARM/libgem5_opt.dylib +``` + +In order to use gem5 with DRAMSys set the **GEM5** environment variable to the +path to gem5, for example in the *QtCreator under Projects > Build +& Run > Build Environment*: + +``` +GEM5=/path/to/gem5/ +``` + +Example: + +``` +GEM5=$HOME/gem5_tnt/gem5 +``` + +Optionally, export environment variables in your **~/.bashrc** file or +equivalent and open a new terminal: + +```bash +# In this example gem5 is located at $HOME/gem5_tnt/gem5. +export GEM5=$HOME/gem5_tnt/gem5 + +# Add the folder containing libgem5_opt.so to the list where libraries should +# be searched for. +export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${GEM5}/build/ARM +``` + +The project file [DRAMSys.pro](DRAMSys/DRAMSys.pro) checks whether the +environment variable **GEM5** is defined or not and configures automatically +the corresponding build target **gem5** for QtCreator. + +In order to run gem5 with DRAMSys it is mandatory to run gem5 first without +DRAMSys and generate a configuration file **config.ini** which will be the +value of the second parameter passed to DRAMSys_gem5. + +### DRAMSys with gem5 traffic generator + +In the following we will run a simple example with a gem5 traffic generator: + +``` +Base System Architecture: ++-------------+ +------+ ^ +| System Port | | TGEN | | ++-------+-----+ +--+---+ | + | | | gem5 World + | +----+ | + | | | ++-------v------v-------+ | +| Membus | v ++---------------+------+ External Port (see sc_slave_port.*) + | ^ + +----v----+ | TLM World + | DRAMSys | | (see sc_target.*) + +---------+ v + +``` + +As mentioned before we first need to create a config.ini +that represents the gem5 configuration. We do so by starting gem5 with the +desired python configuration script. + +```bash +cd gem5/utils/tlm/ +../../build/ARM/gem5.opt conf/tlm_slave.py +``` + +**Ignore the message below.** +``` +"fatal: Can't find port handler type 'tlm_slave'" +``` + +The configuration file config.ini will be stored in the **m5out** directory. +Copy this configuration file to the building directory of DRAMSys where the +executable **DRAMSys_gem5** is located: + +``` +dram.sys/build-DRAMSys-Desktop_Qt_5_7_0_clang_64bit-Debug/gem5 +``` + +Also the traffic generatior configuration file (conf/tgen.cfg) must be stored +in a conf directory of this building directory. + +Then the simulation can be started with: + +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json config.ini 1 +``` + +Let the simulation run for some seconds and then stop it with **CTRL-C**. +Observe the output of the simulation in the trace analyzer. The trace database +can be found inside the gem5 directory in the building directory. + +### Gem5 SE mode and DRAMSys + +All essential files for some functional examples are provided. + +Execute a hello world application: + +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/configs/hello.ini 1 +``` + +A **Hello world!** message should be printed to the standard output. + +Execute applications: + +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/Oscar/config.ini 1 +``` + +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/Bubblesort/config.ini 1 +``` + +Wait some minutes for the application to finish. + +The hello application binary was copied from gem5 repository. + +Other applications were obtained with [gem5.TnT]. + +Command template for generating **.ini** configuration files follows: + +```bash +build/ARM/gem5.opt configs/example/se.py \ + -c --mem-size=512MB --mem-channels=1 \ + --caches --l2cache --mem-type=SimpleMemory \ + --cpu-type=TimingSimpleCPU --num-cpu=1 \ + --tlm-memory=transactor +``` + +An overview of the architcture being simulated is presented below: + +![arch](DRAMSys/docs/images/gem5_se_mode_arch.png) + +**Note**: this is a gem5 generated file, therefore DRAMSys is omitted. DRAMSys is +direct connected as external tlm slave. + +**Note**: workaround in se.py required: + +```python +... +if options.tlm_memory: + system.physmem = SimpleMemory() +MemConfig.config_mem(options, system) +... +``` + +A convenience script to execute several applications automatically +[**run.sh**](DRAMSys/gem5/gem5_se/run.sh) is provided . Take a look and learn +from it. + +### [PARSEC] FS Mode + +Full system simulation files for ARM available in [DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB](DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB). + +Choose the benchmark in [parsec_arm_minor_2c_8GB.rcS](DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/parsec_arm_minor_2c_8GB.rcS). + +Edit the paths in [config.ini](DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/config.ini). + +All files required to build DRAMSys_gem5 and execute the simulation (gem5 +library, benchmarks, disk image, etc.) can be obtained with [gem5.TnT]. + +Start a simulation. Example: + +```bash +dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json ../../DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/config.ini 1 +``` + +Optionally, open another terminal or tab and connect to gem5. + +```bash +$ telnet localhost 3456 +``` + +Note: the port may vary, gem5 prints it during initialization. Example: + +``` +system.terminal: Listening for connections on port 3456 +``` + +### [PARSEC] SE Mode + + +Binaries and gem5 SE configuration files for ARM available in [DRAMSys/gem5/gem5_se/parsec-arm](DRAMSys/gem5/gem5_se/parsec-arm). + +Use [gem5.TnT] to download parsec. Example: + +Go to your **gem5.TnT** folder. Then go to **arch/arm** folder. Execute the +script *build-parsec-serial.sh*. + +```bash +gem5.TnT/arch/arm$ ./build-parsec-serial.sh +``` + +Extract inputs files. Example: + +```bash +cd $HOME/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs +tar -xf input_simdev.tar +tar -xf input_test.tar +tar -xf input_simmedium.tar +tar -xf input_simsmall.tar +tar -xf input_native.tar +tar -xf input_simlarge.tar + +cd $HOME/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs +tar -xf input_simdev.tar +tar -xf input_test.tar +tar -xf input_native.tar +tar -xf input_simlarge.tar +tar -xf input_simmedium.tar +tar -xf input_simsmall.tar + +cd $HOME/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs +tar -xf input_simdev.tar +tar -xf input_test.tar +tar -xf input_native.tar +tar -xf input_simlarge.tar +tar -xf input_simmedium.tar +tar -xf input_simsmall.tar +``` + +Open [DRAMSys/gem5/gem5_se/parsec-arm/config.ini](DRAMSys/gem5/gem5_se/parsec-arm/config.ini) + +Edit **cmd=**. + +Edit **executable=**. + +Examples (**Replace USER. Use the correct path in your computer.**): + +``` +-- canneal -- + +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 5 100 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/10.nets 1 +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 100 300 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/100.nets 2 +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 10000 2000 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/100000.nets 32 +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 15000 2000 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/200000.nets 64 +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 15000 2000 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/400000.nets 128 + +executable=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal + +-- streamcluster -- + +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 2 5 1 10 10 5 none output.txt 1 +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 3 10 3 16 16 10 none output.txt 1 +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 32 4096 4096 1000 none output.txt 1 +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 64 8192 8192 1000 none output.txt 1 +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 128 16384 16384 1000 none output.txt 1 +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 128 1000000 200000 5000 none output.txt 1 + +executable=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster + +-- swaptions -- + +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 1 -sm 5 -nt 1 +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 3 -sm 50 -nt 1 +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 16 -sm 5000 -nt 1 +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 32 -sm 10000 -nt 1 +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 64 -sm 20000 -nt 1 + +executable=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions + +-- fluidanimate -- + +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_5K.fluid out.fluid +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 3 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_15K.fluid out.fluid +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 5 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_35K.fluid out.fluid +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 5 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_100K.fluid out.fluid +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 5 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_300K.fluid out.fluid + +executable=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate + +-- blackscholes -- + +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_4.txt prices.txt +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_16.txt prices.txt +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_4K.txt prices.txt +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_16K.txt prices.txt +cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_64K.txt prices.txt + +executable=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes + +``` + +Start a simulation. Example: + +```bash +dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-se.json ../../DRAMSys/gem5/gem5_se/parsec-arm/config.ini 1 +``` + +### Boot Linux with gem5 and DRAMSys + +The procedure is very similar to the traffic generator example above. + +First we have to generate the config.ini file by starting gem5 with the following configuration: + +```bash +build/ARM/gem5.opt configs/example/fs.py \ + --tlm-memory=transactor --cpu-type=TimingSimpleCPU --num-cpu=1 \ + --mem-type=SimpleMemory --mem-size=512MB --mem-channels=1 --caches \ + --l2cache --machine-type=VExpress_EMM \ + --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \ + --kernel=vmlinux.aarch32.ll_20131205.0-gem5 \ + --disk-image=linux-aarch32-ael.img +``` + +The config.ini should be copied again to the DRAMSys_gem5 build folder. + +The simconfig should be changed in order to support storage and address offsets: + +``` json +{ + "simconfig": { + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1, + "PowerAnalysis": false, + "SimulationName": "ddr3", + "SimulationProgressBar": true, + "ThermalSimulation": false, + "WindowSize": 1000, + + "StoreMode": "Store", + "AddressOffset": 2147483648, + "UseMalloc": true + } +} +``` + +Then start DRAMSys_gem5 with the following command: + +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json config.ini 1 +``` + +For further sophisticated address mappings or scenarios checkout the file DRAMSys/gem5/main.cpp + +#### Boot Linux with gem5 and DRAMSys Example + +**All essential files for a functional example are provided.** + +Unzip the disk image: + +```bash +tar -xaf DRAMSys/gem5/boot_linux/linux-aarch32-ael.img.tar.gz -C DRAMSys/gem5/boot_linux/ +``` + +Execute the example: + +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-boot-linux.json ../../DRAMSys/gem5/configs/boot_linux.ini 1 +``` + +Open a new terminal and connect to gem5: + +```bash +telnet localhost 3456 +``` + +Wait some minutes for the Linux boot process to complete then login. Username is +**root** no password required. + + +### DRAMSys with gem5 Elastic Traces + +For understanding elastic traces and their generation, study the [gem5 +wiki](http://gem5.org/TraceCPU) and the paper [13]. +Some predefined configs are stored [here](DRAMSys/gem5/configs) and the related +python files are stored [here](DRAMSys/gem5/examples). + +This is an example for running an elastic trace: + +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/singleElasticTraceReplay.ini 1 +``` + +An overview of the architcture being simulated is presented below: + +![arch](DRAMSys/docs/images/singleElasticTraceReplay.png) + +Note that the address offset is usually zero for elastic traces. + +Another example with L2 cache: + +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini 1 +``` + +If two elastic traces should be used run the simulation with the following example: + +``` +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/dualElasticTraceReplay.ini 2 +``` + +An overview of the architcture being simulated is presented below: + +![arch](DRAMSys/docs/images/dualElasticTraceReplay.png) + +For more spophisticated setups, even with l2 caches the proper ini file should be created. +If you need help please contact Matthias Jung. + +### DRAMSys + GEM5 Log Collector Scripts + +Users can profit of running multiple **DRAMSys + gem5** simulations +automatically with [gem5ilva.sh] for **gem5 syscall emulation (SE) mode** and +[gem5ilva_fs.sh] for **gem5 full system (FS) mode**. + +Normally you will have to push your changes before running the scripts. This +approach makes it easier to track back what exactly was tested by the scripts. + +The scripts provide variables that tell **git** where to get the source +code from (repository URL), user name to be used (your git account), +**branch** to checkout (your working branch), etc. They are: + +```bash +# Git info. +git_user="$USER" +git_branch="master" +git_url="git.eit.uni-kl.de:ems/astdm/dram.sys.git" +git_url_https="git.eit.uni-kl.de/ems/astdm/dram.sys.git" +``` + +The default values of the variables presented above assume that your git +account uses the same name as your user name in your PC. If that is not the +case, replace the value of the **git_user** variable with your git account +name. Similarly, replace the value of the variable **git_branch** with your +working branch name. There (in your working branch) you can push your changes +and/or new files before executing the scripts. + +Open the script in QtCreator or another text editor of your choice and set the +variables with values that fit your needs. + +Nevertheless, for some cases, you may want to have gem5 essential files out of +the main repository (usually because they are too big to be added to the +repository). + +For those cases uncomment and properly set the variable +**external_inifile_path** in [gem5ilva_fs.sh]. + +This allows you to use a gem5 **config.ini** file external to the repository. +Note, however, that in this case it is up to you to keep track of your +simulation setup. + +**Hint:** +[gem5.TnT] provides convenience scripts +to create gem5 disk images with benchmarking programs embedded. + + +### Coverage Check + +Coverage check is enabled by default and can be disabled with an environment +variable. + +```bash +export COVERAGE=true +``` + +### DRAMSys + GEM5 x86 + +Make sure you have built **gem5/build/X86/libgem5_opt.so**. If you build with +[gem5.TnT] you can check if the library exists as follows. + +```bash +$ ls $HOME/gem5_tnt/gem5/build/X86/libgem5_opt.so +``` + +Change your ~/.bashrc. + +```bash +# In this example gem5 is located at $HOME/gem5_tnt/gem5. +export GEM5=$HOME/gem5_tnt/gem5 + +# Add the folder containing libgem5_opt.so to the list where libraries should +# be searched for. +#export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${GEM5}/build/ARM +export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${GEM5}/build/X86 +``` + +After that close QtCreator and all terminals. + +Open a new terminal. + +Change the architecture in [DRAMSys/gem5/gem5.pro](DRAMSys/gem5/gem5.pro). + +``` +gem5_arch = 'X86' +``` + +Delete the file **DRAMSys/DRAMSys.pro.user** from the repository. + +```bash +$ rm DRAMSys/DRAMSys.pro.user +``` + +Open a new QtCreator. + +Build DRAMSys as usual. + +After building, go the the folder where *DRAMSys_gem5* is located. + +Test with a hello world application for X86. + +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/hello-x86/config.ini 1 +``` + +A **Hello world!** message should be printed to the standard output. + +### [MiBench] + +Applications for x86 and configuration files available in [DRAMSys/gem5/gem5_se/MiBench](DRAMSys/gem5/gem5_se/MiBench). + +Examples: + +**Automotive Applications** + +**Basicmath** +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/large/config.ini 1 +``` + +**Bitcount** +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/large/config.ini 1 +``` + +**Qsort** +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/large/config.ini 1 +``` + +**Susan** +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/corners/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/corners/config.ini 1 + +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/edges/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/edges/config.ini 1 + +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/smoothing/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/smoothing/config.ini 1 +``` + +**Network Applications** + +**Dijkstra** +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/large/config.ini 1 +``` + +**Patricia** +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/large/config.ini 1 +``` + +**Security Applications** + +**Blowfish Encode** +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/large/config.ini 1 +``` + +**Blowfish Decode** +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/large/config.ini 1 +``` + +**SHA** +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/large/config.ini 1 +``` + +**Telecom Applications** + +**CRC32** +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/large/config.ini 1 +``` + +**FFT** +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/large/config.ini 1 +``` + +**FFT-INV** +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/large/config.ini 1 +``` + +**GSM Encode** +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/large/config.ini 1 +``` + +**GSM Decode** +```bash +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/small/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/large/config.ini 1 +``` + +Check the folder [DRAMSys/gem5/gem5_se/MiBench](DRAMSys/gem5/gem5_se/MiBench) for all applications and configuration files. + +### More AARCH64 Apps + +Full system simulation files for ARM available in [DRAMSys/gem5/gem5_fs/arm64](DRAMSys/gem5/gem5_fs/arm64). + +You can edit [arm64.rcS](DRAMSys/gem5/gem5_fs/arm64/arm64.rcS) to start an application and call *m5 exit* when it finishes. + +Edit the paths in [config.ini](DRAMSys/gem5/gem5_fs/arm64/config.ini). + +All files required to build DRAMSys_gem5 and execute the simulation (gem5 +library, benchmarks, disk image, etc.) can be obtained with [gem5.TnT]. + +Start a simulation. Example: + +```bash +dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json ../../DRAMSys/gem5/gem5_fs/arm64/config.ini 1 +``` + +Optionally, open another terminal or tab and connect to gem5. + +```bash +$ telnet localhost 3456 +``` + +Note: the port may vary, gem5 prints it during initialization. Example: + +``` +system.terminal: Listening for connections on port 3456 +``` + +[gem5.TnT]: https://github.com/tukl-msd/gem5.TnT +[gem5ilva.sh]: DRAMSys/library/resources/scripts/DRAMSylva/gem5ilva.sh +[gem5ilva_fs.sh]: DRAMSys/library/resources/scripts/DRAMSylva/gem5ilva_fs.sh +[Elwetritsch]: https://elwe.rhrk.uni-kl.de/ +[DRAMSylva.sh]: DRAMSys/library/resources/scripts/DRAMSylva/DRAMSylva.sh +[DRAMSylva folder]: DRAMSys/library/resources/scripts/DRAMSylva +[configs_json]: DRAMSys/library/resources/scripts/DRAMSylva/configs_json +[MiBench]: http://vhosts.eecs.umich.edu/mibench/ +[PARSEC]: http://parsec.cs.princeton.edu/ \ No newline at end of file diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index a84e0f29..733c7f6e 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -288,8 +288,8 @@ add_library(DRAMSysLibrary resources/traces/chstone-adpcm_32.stl ) -if(DEFINED ENV{LIBTHREED_ICE_HOME} AND DEFINED ENV{LIBSUPERLU_HOME}) - message("-- 3D-ICE and SuperLU available") +if(DEFINED ENV{LIBTHREED_ICE_HOME}) + message("-- Thermal simulation available") add_definitions(-DTHERMALSIM) target_include_directories(DRAMSysLibrary PRIVATE $ENV{LIBTHREED_ICE_HOME}/include/ diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 137aa3db..79c68d25 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -341,7 +341,7 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, timeToAcquire = sc_time_stamp() + notificationDelay; beginReqEvent.notify(notificationDelay); } - else if (phase = END_RESP) + else if (phase == END_RESP) { timeToRelease = sc_time_stamp() + notificationDelay; endRespEvent.notify(notificationDelay); diff --git a/DRAMSys/library/src/controller/respqueue/RespQueueIF.h b/DRAMSys/library/src/controller/respqueue/RespQueueIF.h index 078ddb93..e4848b09 100644 --- a/DRAMSys/library/src/controller/respqueue/RespQueueIF.h +++ b/DRAMSys/library/src/controller/respqueue/RespQueueIF.h @@ -44,6 +44,7 @@ public: virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) = 0; virtual tlm::tlm_generic_payload *nextPayload() = 0; virtual sc_time getTriggerTime() const = 0; + virtual ~RespQueueIF() {} }; #endif // RESPQUEUEIF_H diff --git a/README.md b/README.md index 44bad0a1..a820de3c 100644 --- a/README.md +++ b/README.md @@ -1,186 +1,74 @@ -DRAMSys 4.0 +DRAMSys4.0 =========== -**DRAMSys** [1] is a flexible DRAM subsystem design space exploration -framework that consists of models reflecting the DRAM functionality, power -consumption, temperature behaviour and retention time errors. +**DRAMSys4.0** is a flexible DRAM subsystem design space exploration framework that consists of models reflecting the DRAM functionality, power consumption, temperature behavior and retention time errors. + +Pipeline Status: [![pipeline status](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/pipeline.svg)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master) -Pipeline Status: [![pipeline status](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/pipeline.svg)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master) [![Coverage report](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/coverage.svg?job=coverage)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master) + ## Basic Setup -Start using DRAMSys by cloning the current stable master branch: - -```bash -$ git clone --recursive https://git.eit.uni-kl.de/ems/astdm/dram.sys.git -``` - -The *--recursive* flag tells git to initialize all submodules within the -repository, namely **DRAMPower** [2], **SystemC** and **tinyxml**. - -Now you can implement, test, commit and push features into a **branch**. - -When you consider your work stable enough to be merged into the master branch -it is time to open a **merge request** using the web interface. - -Your changes will be reviewed and might be integrated into the master branch. - -After cloning go to the project directory. - -```bash -$ cd dram.sys -``` +Start using DRAMSys by cloning the repository. +Use the *--recursive* flag to initialize all submodules within the repository, namely **DRAMPower** [2], **SystemC** and **nlohmann json**. ### Dependencies -Make sure you have properly installed all the required libraries and -tools in your system. +DRAMSys is based on the SystemC library. SystemC is included as a submodule and will be build automatically with the DRAMSys project. If you want to use an external SystemC version you have to export the environment variables *SYSTEMC_HOME* (SystemC root directory), *SYSTEMC_TARGET_ARCH* (e.g. linux64) and add the path of the library to *LD_LIBRARY_PATH*. -- **General dependencies** +### Building DRAMSys +DRAMSys uses CMake for the build process, the minimum required version is **CMake 3.10**. -You may want to have a look on the convenience scripts that are located in the -[utils](./utils) folder. +To build the standalone simulator for running memory trace files, create a build folder in the project root directory, then run CMake and make: ```bash -$ cd utils -$ ls -``` - -You can use [utils/install_deb.sh](./utils/install_deb.sh) in order to install -dependencies. Type your password if required. - -```bash -$ ./install_deb.sh -``` - -### Coding Style - -Please read the [coding-style document](coding-style.md) before starting to -code. - -A script is provided to apply the coding style. -```bash -$ cd util -$ ./make_pretty.sh -``` - -### Buiding with QTCreator -Execute the *QTCreator*. - -```bash -$ qtcreator & -``` - -Use the menu bar and open the DRAMSys project. - -**File -> Open Project -> dram.sys/DRAMSys/CMakeLists.txt** - -When you open the project for the first time a configuration window pops-up. -Then click in **Configure Project** and after that **Build** the project. - -To speedup the building process one can use the additional **make** option -**-j[jobs]**. The command line below returns the number of CPUs on a Debian -Linux to be passed to make as the number of jobs that can run simultaneously to -improve the building time. - -```bash -$ cat /proc/cpuinfo | grep processor | wc -l -``` - -In the left bar go to **Projects -> Build & Run -> Build Steps -> Make**. -Click in **Details** then **Make arguments** and add **-j** followed by the -number you got. - -In case you face a problem related to the **Qt version** double check the **Qt -version** configuration shown in the image below. - -![Qt Creator Configuration](DRAMSys/docs/images/QtCreatorConfig.png) - -### Building without QTCreator - -In case you prefer a command line interface to the QTCreator GUI you can also -use **cmake** to generate a Makefile and then compile the project. - -```bash -$ cd dram.sys +$ cd DRAMSys $ mkdir build $ cd build $ cmake ../DRAMSys/ -$ make -j4 +$ make ``` -The compilation generates executable binary files **DRAMSys** and -**TraceAnalyzer** that can be found inside sub-directories. +If you plan to integrate DRAMSys into your own SystemC/TLM project you can build the DRAMSys library only: -From the build directory use the commands below to execute DRAMSys. +```bash +$ cd DRAMSys +$ mkdir build +$ cd build +$ cmake ../DRAMSys/library/ +$ make +``` + +To build DRAMSys on Windows 10 we recommend to use the *Windows Subsystem for Linux (WSL)*. + +### Executing DRAMSys + +From the build directory use the commands below to execute the DRAMSys standalone. ```bash $ cd simulator $ ./DRAMSys ``` -To run DRAMSys with a specific config: +The default base config file is `ddr3-example.json` and located in `DRAMSys/library/resources/simulations`, the default resource folder for all nested config files is `DRAMSys/library/resources`. + +To run DRAMSys with a specific base config file: + ```bash $ ./DRAMSys ../../DRAMSys/library/resources/simulations/ddr3-example.json ``` -To run DRAMSys with a specific config and a resource folder somewhere else to the standard: +To run DRAMSys with a specific base config file and a resource folder somewhere else to the standard: + ```bash $ ./DRAMSys ../../DRAMSys/tests/example_ddr3/simulations/ddr3-example.json ../../DRAMSys/tests/example_ddr3/ ``` -From the build directory use the commands below to execute the Trace Analyzer. - -```bash -$ cd traceAnalyzer -$ export QT_QPA_PLATFORMTHEME=qgnomeplatform -$ ./TraceAnalyzer -``` - -### Building on MacOS (Formerly OSX) -- Install XCode as a Compiler (or any other via Homebrew) -- Install the required python3 over homebrew: - -```bash -$ brew install python3 -``` - -- Install the QtCreator using offical setup file from [link](https://www.qt.io/download-open-source/#section-2) - -**Note:** You have later setup PATH for Qt5 and its tool if you install QtCreator manually, e.g: - -```bash -# Setting PATH for Qt5 and its tools -PATH="/Users//Qt5.7.0/5.7/clang_64/bin:${PATH}" -export PATH -``` - -- Install the QWT manually to /opt/qwt, then do: - -```bash -$ cd /Library/Frameworks -$ sudo ln -s /opt/qwt-6.1.2/lib/qwt.framework/ . -``` - -You compile DRAMSys also with QtCreator or CMAKE as described in the Linux -section. - -### Building on Windows 10 - -- DRAMSys can also run on Windows 10 with the *Windows Subsystem for Linux* (WSL) feature. You can install a linux distribution like Debian over the windows app store. - We refer to the following example [website](https://docs.microsoft.com/en-us/windows/wsl/install-win10). - Then DRAMSys can be installed as described above for Linux. - -- Native Windows 10 Implementation is currently under investigation - ### DRAMSys Configuration -The **DRAMSys** executable supports one argument which is a JSON file that -contains certain arguments and the path of other configuration files for the -desired simulation. If no argument is passed through the command line a default -configuration file will be loaded. +The DRAMSys executable supports one argument which is a JSON file that contains certain arguments and the path of other configuration files for the desired simulation. -The JSON code below shows a typic configuration: +The JSON code below shows an example configuration: ```json { @@ -191,185 +79,169 @@ The JSON code below shows a typic configuration: "memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json", "addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json", "mcconfig":"fifoStrict.json", - "tracesetup": [{ + "tracesetup": [ + { "clkMhz": 300, - "name": "ddr3_example.stl"}, - { + "name": "ddr3_example.stl" + }, + { "clkMhz": 400, - "name": "ddr3_example.stl"} - ] + "name": "ddr3_example.stl" + } + ] } } ``` Fields Description - "simulationid": Simulation file identifier - "simconfig": Configuration file for the DRAMSys Simulator - "thermalconfig": Temperature Simulator Configuration File - "memspec": Memory Device Specification File - "addressmapping": Addressmapping Configuration of the Memory Controller File. - "mcconfig": Memory Controller Configuration File. - "tracesetup": The trace setup is only used in standalone mode. - In library mode e.g. in Platform Architect the trace setup is ignored. - Each device should be addes as a json object inside the "tracesetup" array. -Each **tracesetup** device configuration consists of two parameters - clkMhz -(operation frequency for this device) - and a **trace file**. - -Some configuration fields reference other JSON files which contain more -specialized chunks of the configuration like memory specification, address -mapping and memory configurations +- "simulationid": Simulation file identifier -The JSON configuration files are parsed by the program and the configuration -details extracted are assigned to the correspondent attributes of the internal -configuration structure. +- "simconfig": Configuration file for the DRAMSys Simulator + +- "thermalconfig": Temperature Simulator Configuration File + +- "memspec": Memory Device Specification File + +- "addressmapping": Addressmapping Configuration of the Memory Controller File. + +- "mcconfig": Memory Controller Configuration File. + +- "tracesetup": The trace setup is only used in standalone mode. In library mode the trace setup is ignored. + + Each device should be added as a json object inside the "tracesetup" array. + +Each **trace setup** device configuration consists of two parameters, **clkMhz** (operation frequency of the **trace player**) and a trace file **name**. Most configuration fields reference other JSON files which contain more specialized chunks of the configuration like a memory specification, an address mapping and a memory controller configuration. -#### Trace files +#### Trace Files -A **trace file** is a pre-recorded file containing memory transactions. Each -memory transaction has a timestamp that tells the simulator when it shall -happen, a transaction type (read or write) and a memory address given in -hexadecimal. +A **trace file** is a prerecorded file containing memory transactions. Each memory transaction has a time stamp that tells the simulator when it shall happen, a transaction type (*read* or *write*) and a hexadecimal memory address. -There are two different kinds of trace files. They differ in their timing behaviour and are distingushed by their file extension. +There are two different kinds of trace files. They differ in their timing behavior and are distinguished by their file extension. ##### STL Trace (.stl) -The timestamp corresponds to the time the request is to be issued and it is -given in cycles of the bus master device. Example: the device is a FPGA with -frequency 200 MHz (clock period of 5 ns). If the timestamp is 10 it means that -the request is to be issued when time is 50 ns. +The times tamp corresponds to the time the request is to be issued and it is given in cycles of the bus master device. Example: the device is an FPGA with a frequency of 200 MHz (clock period of 5 ns). If the time stamp is 10 it means that the request is to be issued when time is 50 ns. Here is an example syntax: ``` # Comment lines begin with # -# [clock-cyle]: [write|read] [hex-address] +# [clock-cyle]: [write|read] [hex-address] [hex-data (optional)] 31: read 0x400140 33: read 0x400160 -56: write 0x7fff8000 +56: write 0x7fff8000 0x123456789abcdef 81: read 0x400180 ``` ##### Relative STL Traces (.rstl) -The timestamp corresponds to the time the request is to be issued relative to the end of the transaction before or the beginning of the trace. This results in a simulation in which the **trace player** is able to react to possible delays due to DRAM bottlenecks. +The time stamp corresponds to the time the request is to be issued relative to the end of the transaction before or the beginning of the trace. This results in a simulation in which the trace player is able to react to possible delays due to DRAM bottlenecks. Here is an example syntax: ``` # Comment lines begin with # -# [clock-cyle]: [write|read] [hex-address] +# [clock-cyle]: [write|read] [hex-address] [hex-data (optional)] 31: read 0x400140 2: read 0x400160 -23: write 0x7fff8000 +23: write 0x7fff8000 0x123456789abcdef 25: read 0x400180 ``` -#### Trace player +#### Trace Player -A **trace player** is **equivalent** to a bus master **device** -(processor, FPGA, etc.). It reads an input trace file and translates each line into -a new memory request. By adding a new device element into the trace setup section -one can specify a new trace player, its operating frequency and the trace file -for that trace player. +A **trace player** is **equivalent** to a bus master **device** (processor, FPGA, etc.). It reads an input trace file and translates each line into a new memory request. By adding a new device element into the trace setup section one can specify a new trace player, its operating frequency and the trace file for that trace player. #### Configuration File Sections -The main configuration file is divided into self-contained sections. Each of -these sections refers to sub-configuration files. +The main configuration file is divided into self-contained sections. Each of these sections refers to sub-configuration files. Below, the sub-configurations are listed and explained. -- **Simulator Configuration** +##### Simulator Configuration - The content of [ddr3.json](DRAMSys/library/resources/configs/simulator/ddr3.json) is presented below as an example. +The content of [ddr3.json](DRAMSys/library/resources/configs/simulator/ddr3.json) is presented below as an example. ```json { "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, + "SimulationName": "ddr3", "Debug": false, - "ECCControllerMode": "Disabled", + "DatabaseRecording": true, + "PowerAnalysis": false, "EnableWindowing": false, + "WindowSize": 1000, + "ThermalSimulation": false, + "SimulationProgressBar": true, + "CheckTLM2Protocol": false, + "ECCControllerMode": "Disabled", + "UseMalloc": false, + "AddressOffset": 0, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, - "PowerAnalysis": false, - "SimulationName": "ddr3", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 + "StoreMode": "NoStorage" } } ``` - *SimulationName* (boolean) - - - Give the name of the simulation for distingushing from other simulations. + - Give the name of the simulation for distinguishing from other simulations. - *Debug* (boolean) - - true: enables debug output on console + - true: enables debug output on console (only supported by a debug build) - false: disables debug output - *DatabaseRecording* (boolean) - - true: enables trace file recording for the trace analyser tool - - false: disables trace file recording + - true: enables output database recording for the Trace Analyzer tool + - false: disables output database recording - *PowerAnalysis* (boolean) - - true: enables live power analysis with the DRAMPower tool + - true: enables live power analysis with DRAMPower - false: disables power analysis - *EnableWindowing* (boolean) - true: enables temporal windowing - false: disables temporal windowing - - *WindowSize* (unisgned int) - + - *WindowSize* (unsigned int) - Size of the window in clock cycles used to evaluate average bandwidth and average power consumption - - *NumberOfMemChannels* (unsigned int) - - - Number of memory channels - - *ControllerCoreRefDisable* (boolean) - - true: disables refreshes - - false: normal operation (refreshes enabled) - - *ControllerCoreRGR* (boolean) - - true: enable row granular refresh - - false: normal operation - *ThermalSimulation* (boolean) - true: enables thermal simulation - false: static temperature during simulation - *SimulationProgressBar* (boolean) - true: enables the simulation progress bar - false: disables the simulation progress bar - - *NumberOfDevicesOnDIMM* (unsigned int) - - - Number of devices on dual inline memory module - *CheckTLM2Protocol* (boolean) - true: enables the TLM-2.0 Protocol Checking - false: disables the TLM-2.0 Protocol Checking - *ECCControllerMode* (string) - - "Disabled": No ECC Controller is used + - "Disabled": No ECC controller is used - "Hamming": Enables an ECC Controller with classic SECDED implementation using Hamming Code - *UseMalloc* (boolean) - false: model storage using mmap() (DEFAULT) - true: allocate memory for modeling storage using malloc() +- *AddressOffset* (unsigned int) + - Address offset of the DRAM subsystem (required for the gem5 coupling). +- *ErrorChipSeed* (unsigned int) + - Seed to initialize the random error generator. + - *ErrorCSVFile* (string) + - CSV file with error injection information. + - *StoreMode* (string) + - "NoStorage": no storage + - "Store": store data without error model + - "ErrorModel": store data with error model [6] -- **Temperature Simulator Configuration** +##### Temperature Simulator Configuration - The content of [config.json](DRAMSys/library/resources/configs/thermalsim/config.json) is presented below as an example. +The content of [config.json](DRAMSys/library/resources/configs/thermalsim/config.json) is presented below as an example. ```json { "thermalsimconfig": { "TemperatureScale": "Celsius", "StaticTemperatureDefaultValue": 89, - "ThermalSimPeriod":100, - "ThermalSimUnit":"us", + "ThermalSimPeriod": 100, + "ThermalSimUnit": "us", "PowerInfoFile": "powerInfo.json", "IceServerIp": "127.0.0.1", "IceServerPort": 11880, - "SimPeriodAdjustFactor" : 10, + "SimPeriodAdjustFactor": 10, "NPowStableCyclesToIncreasePeriod": 5, "GenerateTemperatureMap": true, "GeneratePowerMap": true @@ -398,10 +270,10 @@ Below, the sub-configurations are listed and explained. - File containing power related information: devices identifiers, initial power values and power thresholds. - *IceServerIp* (string) - - 3D-Ice server IP address + - 3D-ICE server IP address - *IceServerPort* (unsigned int) - - 3D-Ice server port + - 3D-ICE server port - *SimPeriodAdjustFactor* (unsigned int) - When substantial changes in power occur (i.e., changes that exceed the thresholds), then the simulation period will be divided by this number causing the thermal simulation to be executed more often. @@ -415,74 +287,49 @@ Below, the sub-configurations are listed and explained. - true: generate power map files during thermal simulation - false: do not generate power map files during thermal simulation -- **Memory Specification** - A file with memory specifications. This information comes from datasheets and - measurements, and usually does not change. +##### Memory Specification - The fields inside "mempowerspec" can be written directly as a **double** type. "memoryId" and "memoryType" are **string**. The others are **unsigned int** as it can be checked in the files at . +A file with memory specifications. Timings and currents come from data sheets and measurements, and usually do not change. +The fields inside "mempowerspec" can be written directly as a **double** type. "memoryId" and "memoryType" are **string**. The others are **unsigned int**. -- **Address Mapping** +##### Address Mapping - Currently the CONGEN format is supported. It provides bit-wise granularity. It also provides the possibility of XOR address bits in order to map page misses to different banks and reduce latencies. - There is an optional field called **SOLUTION**. If added it will look for the solution with the field "ID" equals to 0. - Example with "SOLUTION" field at: - Example without "SOLUTION" field at: +DRAMSys uses the **ConGen** [TODO congen source] format for address mappings. It provides bit-wise granularity. It also provides the possibility to XOR address bits in order to map page misses to different banks and reduce latencies. +Used fields: -- **ConGen XML file format** - - This file format is generated by ConGen. - - The format delivers more information than needed for an address mapping. - Optional data (unused): - - - "NAME": Name of the trace file which was used by ConGen -- "COSTS": Number of row misses which this configuration produces while playing the trace. - - - "CONFIG": Gives you information about the ConGen configuration - - Used data: - - - "SOLUTION": (OBS.:Different solutions should be added as json objects inside the "SOLUTION" array) - - "ID": Unique identifier for this solution. It is used to specify a certain solution. - - "XOR": Defines an xor connection of a bank and row bit - - "BYTE_BIT": Address bits that are connected to the byte bits in ascending order - - "COLUMN_BIT": Address bits that are connected to the column bits in ascending order - - "ROW_BIT": Address bits that are connected to the row bits in ascending order - - "BANK_BIT": Address bits that are connected to the bank bits in ascending order - - "BANKGROUP_BIT": Address bits that are connected to the bankgroup bits in ascending order - - "RANK_BIT": Address bits that are connected to the rank bits in ascending order - - "CHANNEL_BIT": Address bits that are connected to the channel bits in ascending order +- "XOR": Defines an XOR connection of a "FIRST" and a "SECOND" bit +- "BYTE_BIT": Address bits that are connected to the byte bits in ascending order +- "COLUMN_BIT": Address bits that are connected to the column bits in ascending order +- "ROW_BIT": Address bits that are connected to the row bits in ascending order +- "BANK_BIT": Address bits that are connected to the bank bits in ascending order +- "BANKGROUP_BIT": Address bits that are connected to the bank group bits in ascending order +- "RANK_BIT": Address bits that are connected to the rank bits in ascending order +- "CHANNEL_BIT": Address bits that are connected to the channel bits in ascending order ```json { "CONGEN": { - "SOLUTION": [ + "XOR": [ { - "ID": 0, - "XOR": [ - { - "FIRST": 13, - "SECOND": 16 - } - ], - "BYTE_BIT": [0,1,2], - "COLUMN_BIT": [3,4,5,6,7,8,9,10,11,12], - "BANK_BIT": [13,14,15], - "ROW_BIT": [16,17,18,19,20,21,22,23,24,25,26,27,28,29] + "FIRST": 13, + "SECOND": 16 } - ] - } + ], + "BYTE_BIT": [0,1,2], + "COLUMN_BIT": [3,4,5,6,7,8,9,10,11,12], + "BANK_BIT": [13,14,15], + "ROW_BIT": [16,17,18,19,20,21,22,23,24,25,26,27,28,29] + } } ``` +##### Memory Controller Configuration -- **Memory Controller Configuration** - - An example follows. +An example follows. ```json { @@ -502,504 +349,49 @@ Below, the sub-configurations are listed and explained. } ``` - - *BankwiseLogic* (boolean) - - true: perform bankwise-refresh [3] and bankwise-powerdown [4] - - false: do not perform bankwise operations - - *OpenPagePolicy* (boolean) - - true: use open page precharge policy - - false: do not use open page precharge policy - - *MaxNrOfTransactions* (unsigned int) - - Maximum number of transactions. + - *PagePolicy* (string) + - "Open" + - "OpenAdaptive" + - "Closed" + - "ClosedAdaptive" - *Scheduler* (string) - "Fifo": first in, first out - - "FifoStrict": out-of-order treatment of queue elements not allowed - - "FrFcfs": first ready first-come-first-served - - "FrFcfsRp": first ready first-come-first-served read priority - - "FrFcfsGrp": first ready first-come-first-served grouper - - "Grp": grouper - - "SMS": will be removed - - *Capsize* (unsigned int) - - Capacitor cell size. - - *PowerDownMode* (enum EPowerDownMode) - - "NoPowerDown": no power down mode (active idle) + - "FrFcfs": first-ready - first-come, first-served + - "FrFcfsGrp": first-ready - first-come, first-served with grouping of read and write requests + - RequestBufferSize (unsigned int) + - buffer size of the scheduler + - *CmdMux* (string) + - "Oldest": oldest payload has the highest priority + - "Strict": read and write commands are issued in the same order as their corresponding requests arrived at the channel controller (can only be combined with "Fifo" scheduler) + - *RespQueue* (string) + - "Strict": outgoing responses are not reordered + - "Reorder": outgoing responses are reordered + - *RefreshPolicy* (string) + - "NoRefresh": refresh disabled + - "Rankwise": all-bank refresh commands, issued per rank + - "Bankwise": per-bank refresh commands (only supported by LPDDR4, Wide I/O 2, GDDR5/5X/6, HBM2) + - *RefreshMode* (unsigned int) [TODO: move refresh mode to memspec] + - special refresh modes of DDR4, 1 ≙ x1, 2 ≙ x2, 4 ≙ x4 + - *RefreshMaxPostponed* + - maximum number of refresh commands that can be postponed (usually 8, with per-bank refresh the number is automatically multiplied by the number of banks) + - *RefreshMaxPulledin* + - maximum number of refresh commands that can be pulled in (usually 8, with per-bank refresh the number is automatically multiplied by the number of banks) + - *PowerDownPolicy* (string) + - "NoPowerDown": power down disabled - "Staggered": staggered power down policy [5] - - "TimeoutPDN": precharge idle - - "TimeoutSREF": self refresh - - *ReadWriteGrouping* (boolean) - - true: enable read writing grouping - - false: disable read writing grouping - - *ReorderBuffer* (boolean) - - true: use reordering buffer - - false: do not use reordering buffer - - *ErrorChipSeed* (unsigned int) - - Seed to initialize the random error generator. - - *ErrorCSVFile* (string) - - CSV file with error injection information. - - *StoreMode* (enum StorageMode) - - "NoStorage": no storage - - "Store": store data without error model - - "ErrorModel": store data with error model [6] - - *ControllerCoreRefDisable* (boolean) - - true: disables refreshes - - false: normal operation (refreshes enabled) - - ControllerCoreRefMode (unsigned int) - - Refresh mode. 1: 1X, 2: 2X, 4: 4X. Refresh period is tREFI, tREFI/2, - tREFI/4, respectively. Number of rows per refresh is affected. Maximum - values for pull-in and postpone are affected. There are different values - of tRFC for each mode that come from memory specifications. - - *ControllerCoreRefForceMaxPostponeBurst* (boolean) - - true: always postpone, resulting in a ControllerCoreRefMaxPostponed burst - - false: normal operation - - *ControllerCoreRefEnablePostpone* (boolean) - - true: enables the postpone refresh feature - - false: normal operation - - *ControllerCoreRefEnablePullIn* (boolean) - - true: enables the pull-in refresh feature - - false: normal operation - - *ControllerCoreRefMaxPostponed* (unsigned int) - - Max AR commands to be postponed. Refresh mode affects this config. - - *ControllerCoreRefMaxPulledIn* (unsigned int) - - Max AR commands to be pulled-in. Refresh mode affects this config. - - *ControllerCoreRGR* (boolean) - - true: enables row granular refresh feature (RGR) - - false: normal operation - - *ControllerCoreRefNumARCmdsIntREFI* (unsigned int) - - Number of AR commands to to be issued in a refresh period tREFI in 1X - mode - - *ControllerCoreRGRRowInc* (unsigned int) - - Row increment for each AR command (selective refresh) - - *ControllerCoreRGRB0* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB1* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB2* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB3* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB4* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB5* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB6* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB7* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB8* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB9* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB10* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB11* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB12* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB13* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB14* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRB15* (boolean) - - true: RGR this bank - - false: skip this bank - - *ControllerCoreRGRtRASBInClkCycles* (unsigned int) - - Timing can be changed to explore optimum row granular refresh (ORGR) - - *ControllerCoreRGRtRRDB_LInClkCycles* (unsigned int) - - Timing can be changed to explore optimum row granular refresh (ORGR) - - *ControllerCoreRGRtRRDB_SInClkCycles* (unsigned int) - - Timing can be changed to explore optimum row granular refresh (ORGR) - - *ControllerCoreRGRtRPBInClkCycles* (unsigned int) - - Timing can be changed to explore optimum row granular refresh (ORGR) - - *ControllerCoreRGRtRCBInClkCycles* (unsigned int) - - Timing can be changed to explore optimum row granular refresh (ORGR) - - *ControllerCoreRGRtFAWBInClkCycles* (unsigned int) - - Timing can be changed to explore optimum row granular refresh (ORGR) +- PowerDownTimeout (unsigned int) + - currently unused - -**Refresh modes** - -The default refresh mode is fixed 1X mode where refresh commands should be -issued with the normal rate, i.e., tREFI. The duration of each refresh command -is the normal refresh cycle time tRFC. In 2X mode Refresh commands are issued -to the DRAM at the double frequency (tREFI/2). In 4X mode Refresh commands are -issued to the DRAM at the quadruple frequency (tREFI/4). There are different -values of tRFC for each mode that come from memory specifications. - -The number of refresh commands in a tREFI is multiplied by two in 2X mode and -by four in 4X mode. The maximum number of refresh commands that can be -postponed or pulled-in is affected in the same manner. The number of rows per -refresh command is divided by two and by four in 2X and 4X mode respectively. - -The nomenclature tREFIx is used to denote the refresh interval which value -changes accordingly to the operation mode, e.g., in 2X mode tREFIx corresponds -to tREFI/2. Similarly tRFCx denotes the refresh cycle time which value changes -accordingly to the operation mode. Nevertheless, the values of tRFCx must be -obtained from memory specifications, estimated, measured, etc. - -**Flexible Refresh** - -The feature can be used together with regular refresh, bankwise refresh and -also with row granular refresh (RGR) non-bankwise and bankwise. Combinations -with all refresh modes are possible. - -**Pull-In Refresh** - -A pull-in starts when a refresh is triggered (in a multiple of tREFIx) and -there are no pending requests in the memory controller's buffer. This can be -done in order to prepare for possible accesses that might happen in the -future. When a burst of REF commands is initiated a REF command is issued (due -to the current tREFIx) followed by one or more REF commands separated in time -by tRFCx. The burst is interrupted if requests arrive, meaning that the -maximum additional delay for a request (considering the worst case scenario in -which a request arrives at the same time a REF is issued) is a refresh cycle -time (tRFCx). - -The advantage of pulling-in refreshes is that they will not be issued in the -near future, i.e., in their actual times multiples of tREFIx, allowing for -more efficient accesses to the memory. - -**Postpone Refresh** - -Similarly, the decision to postpone a refresh is done if by the time of a -refresh due (multiple of tREFIx) there are pending requests on the memory -controller's buffer. Buffered requests may generate row-hits, so postponing -refreshes may be beneficial for it avoids breaking row-hit sequences what -reduces the number of commands (e.g., ACT, PRE) to carry out the memory -accesses and improves the overall system preformance because accesses that are -row-hits consume less time. After postponing refreshes, if there are no -pending requests in the next refresh interval (tREFIx) a burst is issued for -the same number of REF commands postponed plus the actual refresh for that -tREFIx. When the maximum number of postponed refreshes is reached a burst is -issued in the next tREFIx despite the state of the memory controller's buffer -(empty or not). A burst of postponed refreshes cannot be interrupted. - -**The Flexible Refresh FSM** - -![Flexible](DRAMSys/docs/images/flexreffsm.png) - - -- **Trace Setups** - - *clkMhz* (unsigned int) - - Speed of the trace player - - *trace file* - - A pre-recorded file containing memory transactions to be executed by a - trace player. - -Some attributes are self-explanatory while others require some previous -knowhow of memory technologies. - -Resources of the simulator are available inside of the **resources** directory -and its sub-directories. - -```bash -$ cd DRAMSys/library/resources -``` - -A description of the content each directory follows. - -- **resources** - - **configs**: JSON files that specify details of the simulation. - - amconfigs: address mapping configs. - - mcconfigs: memory controller configs. - - memspecs: memory specification files (technology dependent). - - simulator: simulator configs. - - **scripts**: useful tools. - - **simulations**: main configuration files. - - **traces**: pre-recorded trace files that may be used as stimuli in simulations. - - -### Log Collector Script - -Users can profit of running multiple simulations automatically with -[DRAMSylva.sh]. - -Every time you run the script you get a new folder with the name containing -the execution time: dram.sys\_YYYY\_MM\_DD-HH.MM.SS. - -Example on how to run the script: - -```bash -$ cd DRAMSys/library/resources/scripts/DRAMSylva -$ bash DRAMSylva.sh -``` - -To see the generated plots and CSV files: - -```bash -$ nautilus dram.sys_YYYY_MM_DD-HH.MM.SS/build/simulator -``` - -In that folder you will find plots as PDF files and CSV files with the output -data used to generate the plots. The CSV files are: - -- **out.csv** (energy, average power, bandwidth, etc.) - -- **metrics.csv** (DRAMSys metrics like average response latency, memory - utilization and many others) - -Use the command below to find all generated CSV files: - -```bash -$ ls -l dram.sys_YYYY_MM_DD-HH.MM.SS/build/simulator/*.csv -``` - -The generated CSV files can be open in a spreadsheet program for further -manipulation. - -Set the variable **create_comparison_plots** to **yes** in order to get plots -for quick comparison from the CSV files generated. - -```bash -create_comparison_plots="yes" -``` - -Additionally, the database files (\*.tdb) generated will be available and can -be open with the traceAnalyzer tool for debugging, plot generation, etc. - -Set the variable **create_analyzer_plots** to **yes** in order to get plots -generated from the trace databases (the same plots generated by the trace -analyzer tool). **Note**: enabling this option may incur extra time for -database manipulation and plot generation. Depending on the size and amount of -database files it may take long to finish. - -```bash -create_analyzer_plots="yes" -``` - -A DRAMSys simulation is defined by the main configuration file passed to the -simulator. The main configuration file includes other files which contain -specifc configs. -You can change what is going to be simulated by the script by editing it. -There is a list of main configuration files on the top of the script: - -```bash -sim_files=" -ddr3-example.json -ddr3-single-device.json -wideio-example.json -" -``` - -Simulation files are expected to be available (already commited and pushed to -be available after cloning) in the [simulation folder](DRAMSys/library/resources/simulations). - -Set the variable **use_trace_list** to **yes** in order to use all traces in -the **trace list** with all simulation files. Each pair generates a new simulation -with the original trace specified in the simulation file replaced by a trace -from the list. Otherwise it runs a simulation per simulation file using the -trace specified in the simulation file. Files are expected to be available -(already commited and pushed to be available after cloning) in the -[traces folder](DRAMSys/library/resources/traces). - -```bash -use_trace_list="yes" -``` - -```bash -trace_list=" -chstone-bf_32.stl -chstone-jpeg_32.stl -chstone-adpcm_32.stl -mediabench-unepic_32.stl -" -``` - -The script runs one instance of DRAMSys for each of the files in the list. -**The multiple instances run in parallel**. - -If some traces in trace_list are compressed in a tar.gz and require -decompression before execution the option **tgz_traces** can be set to -**yes**. The tarball is specified by the variable **tgz_file** and it is -expected to be available (already commited and pushed to be available after -cloning) in the [trace folder](DRAMSys/library/resources/traces). -[DRAMSylva.sh] will uncompress the tarball extracting the traces before using -them. - -```bash -tgz_traces="yes" -tgz_file="rgr_traces_flauer_ddr4_8b.tar.gz" -``` - -Set the variable **use_json_cfg** to **yes** in order to override sim_files -with new simulation files generated from a JSON description. Otherwise the -simulation files are the ones specified by sim_files. Files are expected to be -available (already commited and pushed to be available after cloning) in -[configs_json]. - -```bash -use_json_cfg="yes" -``` - -All the essential simuation files are auto generated accordingly to each of -the JSON descriptions provided in **json_cfg_list**. Several examples of JSON -configuration files are provided in [configs_json]. - -+ Insert the desired simulation data in one or multiple JSON files following - any of the examples provided, e.g., - [**configs.json**](DRAMSys/library/resources/scripts/DRAMSylva/configs_json/configs.json). - Multiple arrays are allowed and encouraged. Each array corresponds to a full - simulation setup. - -+ Add your JSON files to **json_cfg_list** in [DRAMSylva.sh]. - -```bash -json_cfg_list=" -ref.json -ref_bw.json -" -``` - -+ Commit and push your changes. - -+ Run **[DRAMSylva.sh]** as previously described. All generated files will be - inside the output folder, so it will be possible to keep a perfect track of - all simulations. - -For more information check the documentation inside [DRAMSylva folder]. - -### Trace Generator Script - -The [trace_gen](DRAMSys/library/resources/scripts/trace_gen.py) script for -generating input traces for simple tests is provided. - -Example on how to run the script: - -```bash -$ cd DRAMSys/library/resources/scripts -$ ./trace_gen.py > trace.stl -``` - -Now change your configuration file to use the new generated trace file and run -your simulation. - -The script can be easily changed and provides a way to quickly generate -accesses to all channels, all bank groups, all banks, all rows and all columns -of a memory. - -**Be aware that a trace which covers all rows and all columns may be huge -(several gigabytes) depending on your memory.** - -The defaul values in the script serve as an example. They consider the address -mapping that follows. - -``` -DDR3-SDRAM DIMM Characteristics: -Byte Offset (Y): 8 [0:2] (8-byte-wide memory module, i.e., 64-bit-wide data bus) -> 3 bit -Cols (C): 1K [3:12] (A0 - A9) -> 10 bit -Rows (R): 128K [13:29] (A0 - A16) -> 17 bit -Bank (B): 8 [30:32] (BA0 - BA2) -> 3 bit - -3 3 3 | 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1 -2 1 0 | 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0 -B B B | R R R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y -``` - -The parameters for the address mapping just described are presented below. - -``` -# Channel information. -num_ch = 1 # Number of channels -ch_shift = 34 # Shift to reach the frist bit reserved for channels in the address -ch_mask = 0x1 # Mask for all channel bits in the address - -# Bank group information. -num_bank_groups = 1 # Number of bank groups -bgroup_shift = 33 # Shift to reach the frist bit reserved for bank groups in the address -bgroup_mask = 0x1 # Mask for all bits in the address related to bank groups - -# Bank information -num_banks = 8 # Number of banks -bank_shift = 30 # Shift to reach the frist bit reserved for banks in the address -bank_mask = 0x7 # Mask for all bank bits in the address - -# Row information -num_rows = 128 * 1024 # Number of rows -row_shift = 13 # Shift to reach the frist bit reserved for rows in the address -row_mask = 0x1ffff # Mask for all row bits in the address - -# Column information -num_col = 1 * 1024 # Number of columns -col_shift = 3 # Shift to reach the frist bit reserved for columns in the address -col_mask = 0x3ff # Mask for all column bits in the address - -# Burst length -burst_len = 8 -``` - -Open the script with a text editor and change some parameters to fit your -needs. - -#### DRAMsys Diagrams - -- **TLM Approximately Timed (AT)** - - The figure below shows a cheat sheet with the possibilities that the TLM AT protocol - offers. The annotated references [X,Y] are placed into the source code for a better - orientation. - - ![TLM AT Cheat Sheet](DRAMSys/docs/images/tlmATCheatSheet.png) - - -- **Payload Extension information** - - GenerationExtension is added in TracePlayer and DramExtension is added in Arbiter. - - DramExtension indicates the decoded address (channel, bank, colums, row) and - the socket id (thread) of a payload. It is added in the Arbiter and is sent - to the Controller. - ![Payload Extension information](DRAMSys/docs/images/PayloadExtension.png) - -- **Transaction object with Memory Manager** - - The TracePlayer allocates the memory for the transaction object by calling allocatePayload method. - - The acquire method is called before passing the transaction object in TracePlayer, Arbiter and Controller. - - The release method is called after each component is done with the transaction object. After the final call of release method, the free method of the memory manager is called to free the transaction object. - - ![Payload Memory Manager](DRAMSys/docs/images/PayloadMemoryManager.png) - -- **Architecture of the backend TLM model** - - The below figure shows our custom TLM protocol between the Controller and the Dram. A new transaction enters the Controller with the BEGIN_REQ phase is stored in frontendPEQ. The callback function of the frontendPEQ is called and send the payload to the Scheduler. - - The Scheduler checks the address of payload and the current state to determine proper command (Active, Precharge, Read or Write). Then the ControllerCore sends the payload with the corresponding phase (BEGIN_ACT, BEGIN_PRE, BEGIN_RD or BEGIN_WR) to the Dram by calling nb_transport_fw method. - - The Dram receives the transaction then send back to the Controller by calling nb_transport_bw with appropriate END phase (END_ACT, END_PRE, END_RD or END_WR). - - ![Architecture backend TLM](DRAMSys/docs/images/TransactionPhase.png) - -### DRAMSys Thermal Simulation +### DRAMSys with Thermal Simulation The thermal simulation is performed by a **3D-ICE** [8] server accessed through the network. Therefore users interested in thermal simulation during their DRAMSys simulations need to make sure they have a 3D-ICE server up and -running before starting. For more information about 3D-ICE visit the [official website](http://esl.epfl.ch/3D-ICE). +running before starting. For more information about 3D-ICE visit the [official website](https://www.epfl.ch/labs/esl/open-source-software-projects/3d-ice/). -#### Installing the lastest 3D-ICE version +#### Installing 3D-ICE -[Download](https://www.epfl.ch/labs/esl/open-source-software-projects/3d-ice/3d-ice-download/) the lastest version. Make sure you got version 2.2.6 or greater: - -```bash -$ wget https://www.epfl.ch/labs/esl/wp-content/uploads/2018/12/3d-ice-latest.zip -$ unzip 3d-ice-latest.zip -``` - -Install [SuperLU](http://crd-legacy.lbl.gov/~xiaoye/SuperLU/superlu_5.2.1.tar.gz) dependencies: +Install SuperLU dependencies: ```bash $ sudo apt-get install build-essential git bison flex libblas-dev @@ -1014,8 +406,7 @@ $ cd SuperLU_4.3/ $ cp MAKE_INC/make.linux make.inc ``` -Make sure the SuperLUroot variable in ./make.inc is properly set. For example, -if you downloaded it to your home folder set as follows. +Make sure the *SuperLUroot* variable in *make.inc* is properly set. For example, if you downloaded it to your home folder set as follows: ```bash SuperLUroot = $(HOME)/SuperLU_4.3 @@ -1038,889 +429,56 @@ $ make $ sudo make install ``` -Go to the 3d-ice directory: +[Download](https://www.epfl.ch/labs/esl/open-source-software-projects/3d-ice/3d-ice-download/) the lastest version of 3D-ICE. Make sure you got version 2.2.6 or greater. + +Unzip the archive and go to the 3D-ICE directory: ```bash -$ cd 3d-ice-2.2.6 +$ unzip 3d-ice-latest.zip +$ cd 3d-ice-latest/3d-ice-2.2.6 ``` -Open the file makefile.def and set some variables. Set the correct path to the -SuperLU library you just compiled. +Open the file makefile.def and set some variables. ```bash SLU_MAIN = $(HOME)/SuperLU_$(SLU_VERSION) -``` - -Set the YACC variable to bison-2.4.1: - -```bash YACC = bison-2.4.1 -``` - -Set the following variables with proper values. - -```bash SYSTEMC_ARCH = linux64 -SYSTEMC_MAIN = $(HOME)/systemc-2.3.1a +SYSTEMC_MAIN = $(HOME)/systemc-2.3.3 ``` Compile 3D-ICE with SystemC TLM-2.0 support: ```bash -$ make clean $ make SYSTEMC_WRAPPER=y ``` -Users interested in thermal simulation can also add some extra environment -variables: +Export the environment variable *LIBTHREED_ICE_HOME*: ```bash -# Necessary for thermal simulation -export LIBTHREED_ICE_HOME= -export LIBSUPERLU_HOME= +export LIBTHREED_ICE_HOME=${HOME}/3d-ice-latest/3d-ice-2.2.6 ``` #### Running DRAMSys with Thermal Simulation -Before starting make sure you have a **clean repository** without any previous -automatic generated Makefiles. One way to ensure this is by running the -command below inside your DRAMSys repository, but keep in mind that -**untracked files and directories will be removed** from the repository. +In order to run DRAMSys with thermal simulation you have to rerun CMake and rebuild the project. + +Before starting DRAMSys it is necessary to run the 3D-ICE server passing to it two arguments: a suitable configuration file and a socket port number. And then wait until the server is ready to receive requests. ```bash -$ git clean -fdx -``` - -This feature can be enabled via an environment variable. - -```bash -$ export THERMALSIM=true -$ qtcreator & -``` - -or - -```bash -$ mkdir build -$ cd build -$ export THERMALSIM=true -$ qmake ../DRAMSys/DRAMSys.pro -$ make -``` - -Before starting DRAMSys it is necessary to run the 3D-ICE server passing to it -two arguments: a suitable configuration file and an Internet socket port -number. And then wait until the server is ready to receive requests. - -```bash -$ 3D-ICE-Server +$ cd DRAMSys/DRAMSys/library/resources/configs/thermalsim +$ ~/3d-ice-latest/3d-ice-2.2.6/bin/3D-ICE-Server stack.stk 11880 Preparing stk data ... done ! Preparing thermal data ... done ! Creating socket ... done ! -Waiting for client ... done ! +Waiting for client ... ``` -The IP address and the port number related to the server shall be informed in -DRAMSys' configuration to subsequent use by DRAMSys to access the thermal -simulation server. - -#### Usage Example with Thermal Simulation - -Generate the input trace file for DRAMSys. +In another terminal or terminal tab start DRAMSys with the special thermal simulation config: ```bash -$ cd DRAMSys/tests/error/ -$ ./generateErrorTest.pl > test_error.stl -``` - -Start the 3D-ICE server providing the stack file and the port number. - -```bash -$ cd DRAMSys/library/resources/configs/thermalsim -$ 3D-ICE-Server stack.stk 11880 -``` - -In another terminal or terminal tab start DRAMSys. Here the program's output -is redirected to a file. - -```bash -$ cd build/simulator/ -$ ./DRAMSys > output -``` - -## DRAMSys with gem5 - -Install gem5 by following the instructions on the [gem5 wiki](http://gem5.org/Documentation#Getting_Started). -Optionally, use the scripts from [gem5.TnT] to install gem5, build it, get some benchmark programs and learn more about gem5. - -In order to understand the SystemC coupling with gem5 it is recommended to -read the documentation in the gem5 repository *util/tlm/README* and [12]. - -The main steps for building gem5 and libgem5 follow: - -```bash -scons build/ARM/gem5.opt -``` - -```bash -scons --with-cxx-config --without-python --without-tcmalloc build/ARM/libgem5_opt.so -``` - -For MacOS: - -```bash -scons --with-cxx-config --without-python --without-tcmalloc build/ARM/libgem5_opt.dylib -``` - -In order to use gem5 with DRAMSys set the **GEM5** environment variable to the -path to gem5, for example in the *QtCreator under Projects > Build -& Run > Build Environment*: - -``` -GEM5=/path/to/gem5/ -``` - -Example: - -``` -GEM5=$HOME/gem5_tnt/gem5 -``` - -Optionally, export environment variables in your **~/.bashrc** file or -equivalent and open a new terminal: - -```bash -# In this example gem5 is located at $HOME/gem5_tnt/gem5. -export GEM5=$HOME/gem5_tnt/gem5 - -# Add the folder containing libgem5_opt.so to the list where libraries should -# be searched for. -export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${GEM5}/build/ARM -``` - -The project file [DRAMSys.pro](DRAMSys/DRAMSys.pro) checks whether the -environment variable **GEM5** is defined or not and configures automatically -the corresponding build target **gem5** for QtCreator. - -In order to run gem5 with DRAMSys it is mandatory to run gem5 first without -DRAMSys and generate a configuration file **config.ini** which will be the -value of the second parameter passed to DRAMSys_gem5. - -### DRAMSys with gem5 traffic generator - -In the following we will run a simple example with a gem5 traffic generator: - -``` -Base System Architecture: -+-------------+ +------+ ^ -| System Port | | TGEN | | -+-------+-----+ +--+---+ | - | | | gem5 World - | +----+ | - | | | -+-------v------v-------+ | -| Membus | v -+---------------+------+ External Port (see sc_slave_port.*) - | ^ - +----v----+ | TLM World - | DRAMSys | | (see sc_target.*) - +---------+ v - -``` - -As mentioned before we first need to create a config.ini -that represents the gem5 configuration. We do so by starting gem5 with the -desired python configuration script. - -```bash -cd gem5/utils/tlm/ -../../build/ARM/gem5.opt conf/tlm_slave.py -``` - -**Ignore the message below.** -``` -"fatal: Can't find port handler type 'tlm_slave'" -``` - -The configuration file config.ini will be stored in the **m5out** directory. -Copy this configuration file to the building directory of DRAMSys where the -executable **DRAMSys_gem5** is located: - -``` -dram.sys/build-DRAMSys-Desktop_Qt_5_7_0_clang_64bit-Debug/gem5 -``` - -Also the traffic generatior configuration file (conf/tgen.cfg) must be stored -in a conf directory of this building directory. - -Then the simulation can be started with: - -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json config.ini 1 -``` - -Let the simulation run for some seconds and then stop it with **CTRL-C**. -Observe the output of the simulation in the trace analyzer. The trace database -can be found inside the gem5 directory in the building directory. - -### Gem5 SE mode and DRAMSys - -All essential files for some functional examples are provided. - -Execute a hello world application: - -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/configs/hello.ini 1 -``` - -A **Hello world!** message should be printed to the standard output. - -Execute applications: - -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/Oscar/config.ini 1 -``` - -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/Bubblesort/config.ini 1 -``` - -Wait some minutes for the application to finish. - -The hello application binary was copied from gem5 repository. - -Other applications were obtained with [gem5.TnT]. - -Command template for generating **.ini** configuration files follows: - -```bash -build/ARM/gem5.opt configs/example/se.py \ - -c --mem-size=512MB --mem-channels=1 \ - --caches --l2cache --mem-type=SimpleMemory \ - --cpu-type=TimingSimpleCPU --num-cpu=1 \ - --tlm-memory=transactor -``` - -An overview of the architcture being simulated is presented below: - -![arch](DRAMSys/docs/images/gem5_se_mode_arch.png) - -**Note**: this is a gem5 generated file, therefore DRAMSys is omitted. DRAMSys is -direct connected as external tlm slave. - -**Note**: workaround in se.py required: - -```python -... -if options.tlm_memory: - system.physmem = SimpleMemory() -MemConfig.config_mem(options, system) -... -``` - -A convenience script to execute several applications automatically -[**run.sh**](DRAMSys/gem5/gem5_se/run.sh) is provided . Take a look and learn -from it. - -### [PARSEC] FS Mode - -Full system simulation files for ARM available in [DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB](DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB). - -Choose the benchmark in [parsec_arm_minor_2c_8GB.rcS](DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/parsec_arm_minor_2c_8GB.rcS). - -Edit the paths in [config.ini](DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/config.ini). - -All files required to build DRAMSys_gem5 and execute the simulation (gem5 -library, benchmarks, disk image, etc.) can be obtained with [gem5.TnT]. - -Start a simulation. Example: - -```bash -dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json ../../DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/config.ini 1 -``` - -Optionally, open another terminal or tab and connect to gem5. - -```bash -$ telnet localhost 3456 -``` - -Note: the port may vary, gem5 prints it during initialization. Example: - -``` -system.terminal: Listening for connections on port 3456 -``` - -### [PARSEC] SE Mode - - -Binaries and gem5 SE configuration files for ARM available in [DRAMSys/gem5/gem5_se/parsec-arm](DRAMSys/gem5/gem5_se/parsec-arm). - -Use [gem5.TnT] to download parsec. Example: - -Go to your **gem5.TnT** folder. Then go to **arch/arm** folder. Execute the -script *build-parsec-serial.sh*. - -```bash -gem5.TnT/arch/arm$ ./build-parsec-serial.sh -``` - -Extract inputs files. Example: - -```bash -cd $HOME/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs -tar -xf input_simdev.tar -tar -xf input_test.tar -tar -xf input_simmedium.tar -tar -xf input_simsmall.tar -tar -xf input_native.tar -tar -xf input_simlarge.tar - -cd $HOME/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs -tar -xf input_simdev.tar -tar -xf input_test.tar -tar -xf input_native.tar -tar -xf input_simlarge.tar -tar -xf input_simmedium.tar -tar -xf input_simsmall.tar - -cd $HOME/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs -tar -xf input_simdev.tar -tar -xf input_test.tar -tar -xf input_native.tar -tar -xf input_simlarge.tar -tar -xf input_simmedium.tar -tar -xf input_simsmall.tar -``` - -Open [DRAMSys/gem5/gem5_se/parsec-arm/config.ini](DRAMSys/gem5/gem5_se/parsec-arm/config.ini) - -Edit **cmd=**. - -Edit **executable=**. - -Examples (**Replace USER. Use the correct path in your computer.**): - -``` --- canneal -- - -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 5 100 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/10.nets 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 100 300 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/100.nets 2 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 10000 2000 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/100000.nets 32 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 15000 2000 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/200000.nets 64 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 15000 2000 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/400000.nets 128 - -executable=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal - --- streamcluster -- - -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 2 5 1 10 10 5 none output.txt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 3 10 3 16 16 10 none output.txt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 32 4096 4096 1000 none output.txt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 64 8192 8192 1000 none output.txt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 128 16384 16384 1000 none output.txt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 128 1000000 200000 5000 none output.txt 1 - -executable=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster - --- swaptions -- - -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 1 -sm 5 -nt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 3 -sm 50 -nt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 16 -sm 5000 -nt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 32 -sm 10000 -nt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 64 -sm 20000 -nt 1 - -executable=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions - --- fluidanimate -- - -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_5K.fluid out.fluid -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 3 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_15K.fluid out.fluid -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 5 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_35K.fluid out.fluid -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 5 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_100K.fluid out.fluid -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 5 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_300K.fluid out.fluid - -executable=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate - --- blackscholes -- - -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_4.txt prices.txt -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_16.txt prices.txt -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_4K.txt prices.txt -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_16K.txt prices.txt -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_64K.txt prices.txt - -executable=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes - -``` - -Start a simulation. Example: - -```bash -dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-se.json ../../DRAMSys/gem5/gem5_se/parsec-arm/config.ini 1 -``` - -### Boot Linux with gem5 and DRAMSys - -The procedure is very similar to the traffic generator example above. - -First we have to generate the config.ini file by starting gem5 with the following configuration: - -```bash -build/ARM/gem5.opt configs/example/fs.py \ - --tlm-memory=transactor --cpu-type=TimingSimpleCPU --num-cpu=1 \ - --mem-type=SimpleMemory --mem-size=512MB --mem-channels=1 --caches \ - --l2cache --machine-type=VExpress_EMM \ - --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \ - --kernel=vmlinux.aarch32.ll_20131205.0-gem5 \ - --disk-image=linux-aarch32-ael.img -``` - -The config.ini should be copied again to the DRAMSys_gem5 build folder. - -The simconfig should be changed in order to support storage and address offsets: - -``` json -{ - "simconfig": { - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, - "PowerAnalysis": false, - "SimulationName": "ddr3", - "SimulationProgressBar": true, - "ThermalSimulation": false, - "WindowSize": 1000, - - "StoreMode": "Store", - "AddressOffset": 2147483648, - "UseMalloc": true - } -} -``` - -Then start DRAMSys_gem5 with the following command: - -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json config.ini 1 -``` - -For further sophisticated address mappings or scenarios checkout the file DRAMSys/gem5/main.cpp - -#### Boot Linux with gem5 and DRAMSys Example - -**All essential files for a functional example are provided.** - -Unzip the disk image: - -```bash -tar -xaf DRAMSys/gem5/boot_linux/linux-aarch32-ael.img.tar.gz -C DRAMSys/gem5/boot_linux/ -``` - -Execute the example: - -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-boot-linux.json ../../DRAMSys/gem5/configs/boot_linux.ini 1 -``` - -Open a new terminal and connect to gem5: - -```bash -telnet localhost 3456 -``` - -Wait some minutes for the Linux boot process to complete then login. Username is -**root** no password required. - - -### DRAMSys with gem5 Elastic Traces - -For understanding elastic traces and their generation, study the [gem5 -wiki](http://gem5.org/TraceCPU) and the paper [13]. -Some predefined configs are stored [here](DRAMSys/gem5/configs) and the related -python files are stored [here](DRAMSys/gem5/examples). - -This is an example for running an elastic trace: - -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/singleElasticTraceReplay.ini 1 -``` - -An overview of the architcture being simulated is presented below: - -![arch](DRAMSys/docs/images/singleElasticTraceReplay.png) - -Note that the address offset is usually zero for elastic traces. - -Another example with L2 cache: - -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini 1 -``` - -If two elastic traces should be used run the simulation with the following example: - -``` -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/dualElasticTraceReplay.ini 2 -``` - -An overview of the architcture being simulated is presented below: - -![arch](DRAMSys/docs/images/dualElasticTraceReplay.png) - -For more spophisticated setups, even with l2 caches the proper ini file should be created. -If you need help please contact Matthias Jung. - -### DRAMSys + GEM5 Log Collector Scripts - -Users can profit of running multiple **DRAMSys + gem5** simulations -automatically with [gem5ilva.sh] for **gem5 syscall emulation (SE) mode** and -[gem5ilva_fs.sh] for **gem5 full system (FS) mode**. - -Normally you will have to push your changes before running the scripts. This -approach makes it easier to track back what exactly was tested by the scripts. - -The scripts provide variables that tell **git** where to get the source -code from (repository URL), user name to be used (your git account), -**branch** to checkout (your working branch), etc. They are: - -```bash -# Git info. -git_user="$USER" -git_branch="master" -git_url="git.eit.uni-kl.de:ems/astdm/dram.sys.git" -git_url_https="git.eit.uni-kl.de/ems/astdm/dram.sys.git" -``` - -The default values of the variables presented above assume that your git -account uses the same name as your user name in your PC. If that is not the -case, replace the value of the **git_user** variable with your git account -name. Similarly, replace the value of the variable **git_branch** with your -working branch name. There (in your working branch) you can push your changes -and/or new files before executing the scripts. - -Open the script in QtCreator or another text editor of your choice and set the -variables with values that fit your needs. - -Nevertheless, for some cases, you may want to have gem5 essential files out of -the main repository (usually because they are too big to be added to the -repository). - -For those cases uncomment and properly set the variable -**external_inifile_path** in [gem5ilva_fs.sh]. - -This allows you to use a gem5 **config.ini** file external to the repository. -Note, however, that in this case it is up to you to keep track of your -simulation setup. - -**Hint:** -[gem5.TnT] provides convenience scripts -to create gem5 disk images with benchmarking programs embedded. - -### Notes for [Elwetritsch] Users - -Firstly, take a look at [High Performance Computing at the TU Kaiserslautern](https://elwe.rhrk.uni-kl.de/). - -After that, please give yourself a change to learn a bit about [Batch Usage at -RHRK TU Kaiserslautern](https://elwe.rhrk.uni-kl.de/elwetritsch/batch.shtml). -This will probably save you some time later on. - -When using DRAMSys + gem5 on the [Elwetritsch] gem5 can be installed with -convenience scripts provided by [gem5.TnT]. - -[gem5.TnT] also provides convenience scripts -to create gem5 disk images with benchmarking programs embedded. The creation -of disk images for gem5 requires superuser privilege. A solution is to copy -(e.g., using scp or mounting a folder, etc.) the locally created disk images -to [Elwetritsch]. Since there is no compilation involved, copying disk images -created in one machine to another machine should not incur in incompatibility -problems. - -On [gem5.TnT] repository open a [gem5.TnT] config file. - -```bash -$ vim common/defaults.in -``` - -Note the variable **ROOTDIR**. Its default value is *ROOTDIR=$HOME/gem5_tnt*. -That means that [gem5.TnT] will download to *$HOME/gem5_tnt*. - -Currently the space one can use in its Elwetrich *$HOME* folder is limited to -a few tens of GiB. Nevertheless, a directory **/scratch/$USER** is provided -with less space restrictions. - -One can create a symlink pointing to **/scratch/$USER/gem5_tnt**. - -```bash -$ cd $SCRATCH -$ mkdir gem5_tnt -$ cd -$ ln -s /scratch/$USER/gem5_tnt -``` - -On [gem5.TnT] repository use the commands below to get files and build gem5: - -```bash -$ ./get_essential_fs.sh -$ ./get_benchmarks.sh -$ ./get_extra_fs.sh -$ ./build_gem5.sh -``` - -To get DRAMSys installed follow the traditional setup instructions described -in this document. - -For building DRAMSys one can profit from using [DRAMSylva.sh] which loads the -modules that are necessary for building DRAMSys on [Elwetritsch]. - -Regarding dependencies for building DRAMSys and DRAMSys + gem5, the scripts -provided inside the [DRAMSylva folder], when running on [Elwetritsch], will -load the required modules automatically. - -As usual, one may export environment variables from his/her **~/.bashrc** file -on Elwetritch. Some segments extracted from a functional ~/.bashrc file are -presented below to be used as reference. Note that you may have to adapt it, -for example, changing paths to point to the place you installed some of the -libraries. - -```bash -# User specific aliases and functions -# SystemC home -export SYSTEMC_HOME=$HOME/systemc-2.3.1a -# SystemC target architecture -export SYSTEMC_TARGET_ARCH=linux64 - -# Qwt lib -export LIBQWT_HOME=$HOME/qwt-6.1/lib -export LIBQWT_HEADERS=$HOME/qwt-6.1/src -export LD_LIBRARY_PATH=${LD_LIBRARY_PATH:+${LD_LIBRARY_PATH}:}$LIBQWT_HOME - -# Python lib -export LIBPYTHON_VERSION="3.6m" -export PYTHON_HOME=/usr/lib64 -export PYTHON_HEADERS=/usr/include/python3.6m - -# Gem5 + DRAMsys -export GEM5=$HOME/gem5_tnt/gem5 - -# Gem5 SystemC TLM-2.0 coupling (see also: $HOME/gem5_tnt/gem5/util/tlm/README) -export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${GEM5}/build/ARM -export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${SYSTEMC_HOME}/lib-$SYSTEMC_TARGET_ARCH -export PKG_CONFIG_PATH=${PKG_CONFIG_PATH}:${SYSTEMC_HOME}/lib-$SYSTEMC_TARGET_ARCH/pkgconfig - -# M5_PATH for gem5 -export M5_PATH=$HOME/gem5_tnt/full_system/arm/aarch-system-20180409 - -# Do not close my terminal when inactive after a timeout -unset TMOUT -``` - -[SLURM](https://slurm.schedmd.com/overview.html) **job scripts** are available -inside the [DRAMSylva folder]. They can be used directly without changes or as -examples on how to start jobs using nodes of the [Elwetritsch] cluster. Of -course, one can create his/her own job scripts. - - -### Coverage Check - -Coverage check is enabled by default and can be disabled with an environment -variable. - -```bash -export DRAMSYS_DISABLE_COVERAGE_CHECK=1 -``` - -### DRAMSys + GEM5 x86 - -Make sure you have built **gem5/build/X86/libgem5_opt.so**. If you build with -[gem5.TnT] you can check if the library exists as follows. - -```bash -$ ls $HOME/gem5_tnt/gem5/build/X86/libgem5_opt.so -``` - -Change your ~/.bashrc. - -```bash -# In this example gem5 is located at $HOME/gem5_tnt/gem5. -export GEM5=$HOME/gem5_tnt/gem5 - -# Add the folder containing libgem5_opt.so to the list where libraries should -# be searched for. -#export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${GEM5}/build/ARM -export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${GEM5}/build/X86 -``` - -After that close QtCreator and all terminals. - -Open a new terminal. - -Change the architecture in [DRAMSys/gem5/gem5.pro](DRAMSys/gem5/gem5.pro). - -``` -gem5_arch = 'X86' -``` - -Delete the file **DRAMSys/DRAMSys.pro.user** from the repository. - -```bash -$ rm DRAMSys/DRAMSys.pro.user -``` - -Open a new QtCreator. - -Build DRAMSys as usual. - -After building, go the the folder where *DRAMSys_gem5* is located. - -Test with a hello world application for X86. - -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/hello-x86/config.ini 1 -``` - -A **Hello world!** message should be printed to the standard output. - -### [MiBench] - -Applications for x86 and configuration files available in [DRAMSys/gem5/gem5_se/MiBench](DRAMSys/gem5/gem5_se/MiBench). - -Examples: - -**Automotive Applications** - -**Basicmath** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/large/config.ini 1 -``` - -**Bitcount** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/large/config.ini 1 -``` - -**Qsort** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/large/config.ini 1 -``` - -**Susan** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/corners/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/corners/config.ini 1 - -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/edges/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/edges/config.ini 1 - -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/smoothing/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/smoothing/config.ini 1 -``` - -**Network Applications** - -**Dijkstra** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/large/config.ini 1 -``` - -**Patricia** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/large/config.ini 1 -``` - -**Security Applications** - -**Blowfish Encode** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/large/config.ini 1 -``` - -**Blowfish Decode** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/large/config.ini 1 -``` - -**SHA** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/large/config.ini 1 -``` - -**Telecom Applications** - -**CRC32** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/large/config.ini 1 -``` - -**FFT** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/large/config.ini 1 -``` - -**FFT-INV** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/large/config.ini 1 -``` - -**GSM Encode** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/large/config.ini 1 -``` - -**GSM Decode** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/large/config.ini 1 -``` - -Check the folder [DRAMSys/gem5/gem5_se/MiBench](DRAMSys/gem5/gem5_se/MiBench) for all applications and configuration files. - -### More AARCH64 Apps - -Full system simulation files for ARM available in [DRAMSys/gem5/gem5_fs/arm64](DRAMSys/gem5/gem5_fs/arm64). - -You can edit [arm64.rcS](DRAMSys/gem5/gem5_fs/arm64/arm64.rcS) to start an application and call *m5 exit* when it finishes. - -Edit the paths in [config.ini](DRAMSys/gem5/gem5_fs/arm64/config.ini). - -All files required to build DRAMSys_gem5 and execute the simulation (gem5 -library, benchmarks, disk image, etc.) can be obtained with [gem5.TnT]. - -Start a simulation. Example: - -```bash -dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json ../../DRAMSys/gem5/gem5_fs/arm64/config.ini 1 -``` - -Optionally, open another terminal or tab and connect to gem5. - -```bash -$ telnet localhost 3456 -``` - -Note: the port may vary, gem5 prints it during initialization. Example: - -``` -system.terminal: Listening for connections on port 3456 +$ cd DRAMSys/build/simulator/ +$ ./DRAMSys ../../DRAMSys/library/resources/simulations/wideio-thermal.json ``` ## References @@ -1971,14 +529,4 @@ Conference on Embedded Computer Systems Architectures Modeling and Simulation [13] Exploring System Performance using Elastic Traces: Fast, Accurate and Portable Radhika Jagtap, Stephan Diestelhorst, Andreas Hansson, Matthias Jung and Norbert Wehn, IEEE International Conference on Embedded Computer Systems -Architectures Modeling and Simulation (SAMOS), 2016, Samos Island, Greece. - -[gem5.TnT]: https://github.com/tukl-msd/gem5.TnT -[gem5ilva.sh]: DRAMSys/library/resources/scripts/DRAMSylva/gem5ilva.sh -[gem5ilva_fs.sh]: DRAMSys/library/resources/scripts/DRAMSylva/gem5ilva_fs.sh -[Elwetritsch]: https://elwe.rhrk.uni-kl.de/ -[DRAMSylva.sh]: DRAMSys/library/resources/scripts/DRAMSylva/DRAMSylva.sh -[DRAMSylva folder]: DRAMSys/library/resources/scripts/DRAMSylva -[configs_json]: DRAMSys/library/resources/scripts/DRAMSylva/configs_json -[MiBench]: http://vhosts.eecs.umich.edu/mibench/ -[PARSEC]: http://parsec.cs.princeton.edu/ +Architectures Modeling and Simulation (SAMOS), 2016, Samos Island, Greece. \ No newline at end of file From 3d3c9c2799f2598e8bf8690b96cca416ef0765d2 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 1 Jul 2020 16:11:52 +0200 Subject: [PATCH 36/53] Update resources. --- DRAMSys/gem5/README.md | 14 +++++++++-- README.md | 56 ++++++++++-------------------------------- 2 files changed, 25 insertions(+), 45 deletions(-) diff --git a/DRAMSys/gem5/README.md b/DRAMSys/gem5/README.md index d4966a95..31cff150 100644 --- a/DRAMSys/gem5/README.md +++ b/DRAMSys/gem5/README.md @@ -4,7 +4,7 @@ Install gem5 by following the instructions on the [gem5 wiki](http://gem5.org/Do Optionally, use the scripts from [gem5.TnT] to install gem5, build it, get some benchmark programs and learn more about gem5. In order to understand the SystemC coupling with gem5 it is recommended to -read the documentation in the gem5 repository *util/tlm/README* and [12]. +read the documentation in the gem5 repository *util/tlm/README* and [1]. The main steps for building gem5 and libgem5 follow: @@ -393,7 +393,7 @@ Wait some minutes for the Linux boot process to complete then login. Username is ### DRAMSys with gem5 Elastic Traces For understanding elastic traces and their generation, study the [gem5 -wiki](http://gem5.org/TraceCPU) and the paper [13]. +wiki](http://gem5.org/TraceCPU) and the paper [2]. Some predefined configs are stored [here](DRAMSys/gem5/configs) and the related python files are stored [here](DRAMSys/gem5/examples). @@ -670,6 +670,16 @@ Note: the port may vary, gem5 prints it during initialization. Example: system.terminal: Listening for connections on port 3456 ``` +[1] System Simulation with gem5 and SystemC: The Keystone for Full +Interoperability C. Menard, M. Jung, J. Castrillon, N. Wehn. IEEE International +Conference on Embedded Computer Systems Architectures Modeling and Simulation +(SAMOS), July, 2017, Samos Island, Greece. + +[2] Exploring System Performance using Elastic Traces: Fast, Accurate and +Portable Radhika Jagtap, Stephan Diestelhorst, Andreas Hansson, Matthias Jung +and Norbert Wehn, IEEE International Conference on Embedded Computer Systems +Architectures Modeling and Simulation (SAMOS), 2016, Samos Island, Greece. + [gem5.TnT]: https://github.com/tukl-msd/gem5.TnT [gem5ilva.sh]: DRAMSys/library/resources/scripts/DRAMSylva/gem5ilva.sh [gem5ilva_fs.sh]: DRAMSys/library/resources/scripts/DRAMSylva/gem5ilva_fs.sh diff --git a/README.md b/README.md index a820de3c..b82d0749 100644 --- a/README.md +++ b/README.md @@ -1,20 +1,19 @@ DRAMSys4.0 =========== -**DRAMSys4.0** is a flexible DRAM subsystem design space exploration framework that consists of models reflecting the DRAM functionality, power consumption, temperature behavior and retention time errors. +**DRAMSys4.0** [1] [2] [3] is a flexible DRAM subsystem design space exploration framework that consists of models reflecting the DRAM functionality, power consumption, temperature behavior and retention time errors. Pipeline Status: [![pipeline status](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/pipeline.svg)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master) - [![Coverage report](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/coverage.svg?job=coverage)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master) ## Basic Setup Start using DRAMSys by cloning the repository. -Use the *--recursive* flag to initialize all submodules within the repository, namely **DRAMPower** [2], **SystemC** and **nlohmann json**. +Use the *--recursive* flag to initialize all submodules within the repository, namely **DRAMPower** [4], **SystemC** and **nlohmann json**. ### Dependencies -DRAMSys is based on the SystemC library. SystemC is included as a submodule and will be build automatically with the DRAMSys project. If you want to use an external SystemC version you have to export the environment variables *SYSTEMC_HOME* (SystemC root directory), *SYSTEMC_TARGET_ARCH* (e.g. linux64) and add the path of the library to *LD_LIBRARY_PATH*. +DRAMSys is based on the SystemC library. SystemC is included as a submodule and will be build automatically with the DRAMSys project. If you want to use an external SystemC version you have to export the environment variables `SYSTEMC_HOME` (SystemC root directory), `SYSTEMC_TARGET_ARCH` (e.g. linux64) and add the path of the library to `LD_LIBRARY_PATH`. ### Building DRAMSys DRAMSys uses CMake for the build process, the minimum required version is **CMake 3.10**. @@ -486,47 +485,18 @@ $ ./DRAMSys ../../DRAMSys/library/resources/simulations/wideio-thermal.json [1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin. -[2] DRAMPower: Open-source DRAM Power & Energy Estimation Tool -Karthik Chandrasekar, Christian Weis, Yonghui Li, Sven Goossens, Matthias Jung, Omar Naji, Benny Akesson, Norbert Wehn, and Kees Goossens +[2] DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework +M. Jung, C. Weis, N. Wehn. IPSJ Transactions on System LSI Design Methodology (T-SLDM), October, 2015. + +[3] DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator +L. Steiner, M. Jung, F. S. Prado, K. Bykov, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July, 2020, Samos Island, Greece. + +[4] DRAMPower: Open-source DRAM Power & Energy Estimation Tool +K. Chandrasekar, C. Weis, Y. Li, S. Goossens, M. Jung, O. Naji, B. Akesson, N. Wehn, K. Goossens URL: http://www.drampower.info -[3] Energy Optimization in 3D MPSoCs with Wide-I/O DRAM -M. Sadri, M. Jung, C. Weis, N. Wehn, L. Benini. Conference Design, Automation and Test in Europe (DATE), March, 2014, Dresden, Germany. - -[4] DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework -M. Jung, C. Weis, N. Wehn. Accepted for publication, IPSJ Transactions on System LSI Design Methodology (T-SLDM), October, 2015. - [5] Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs -M. Jung, M. Sadri, C. Weis, N. Wehn, L. Benini., VLSI-SoC, October, 2014, Playa del Carmen, Mexico. +M. Jung, M. Sadri, C. Weis, N. Wehn, L. Benini. VLSI-SoC, October, 2014, Playa del Carmen, Mexico. [6] Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs -C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. Accepted for publication, IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France - -[7] http://www.uni-kl.de/3d-dram/publications/ - -[8] A Sridhar, A Vincenzi, D Atienza, T Brunschwiler, 3D-ICE: a compact -thermal model for early-stage design of liquid-cooled ICs, IEEE Transactions -on Computers (TC 2013, accepted for publication). - -[9] A Sridhar, A Vincenzi, M Ruggiero, T Brunschwiler, D Atienza, 3D-ICE: Fast -compact transient thermal modeling for 3D-ICs with inter-tier liquid cooling, -Proceedings of the 2010 International Conference on Computer-Aided Design -(ICCAD 2010), San Jose, CA, USA, November 7-11 2010. - -[10] A Sridhar, A Vincenzi, M Ruggiero, T Brunschwiler, D Atienza, Compact -transient thermal model for 3D ICs with liquid cooling via enhanced heat -transfer cavity geometries, Proceedings of the 16th International Workshop on -Thermal Investigations of ICs and Systems (THERMINIC'10), Barcelona, Spain, -6-8 October, 2010. - -[11] http://esl.epfl.ch/3D-ICE - -[12] System Simulation with gem5 and SystemC: The Keystone for Full -Interoperability C. Menard, M. Jung, J. Castrillon, N. Wehn. IEEE International -Conference on Embedded Computer Systems Architectures Modeling and Simulation -(SAMOS), July, 2017, Samos Island, Greece. - -[13] Exploring System Performance using Elastic Traces: Fast, Accurate and -Portable Radhika Jagtap, Stephan Diestelhorst, Andreas Hansson, Matthias Jung -and Norbert Wehn, IEEE International Conference on Embedded Computer Systems -Architectures Modeling and Simulation (SAMOS), 2016, Samos Island, Greece. \ No newline at end of file +C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France From 92c32fdf15ed16212d0c379080cd297f96bc8a30 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 1 Jul 2020 16:31:01 +0200 Subject: [PATCH 37/53] Removed old images of readme. --- DRAMSys/docs/doxyCfg.cfg | 1228 ----- DRAMSys/docs/images/PayloadExtension.svg | 2449 --------- DRAMSys/docs/images/PayloadMemoryManager.svg | 4866 ----------------- DRAMSys/docs/images/TransactionPhase.svg | 2038 ------- DRAMSys/docs/images/am_sample1.svg | 1809 ------ DRAMSys/docs/images/am_sample2.svg | 1868 ------- DRAMSys/docs/images/am_wideio_brc.svg | 1734 ------ DRAMSys/docs/images/am_wideio_rbc.svg | 1748 ------ .../images/gem5_se_mode_arch.svg | 0 README.md | 52 +- 10 files changed, 26 insertions(+), 17766 deletions(-) delete mode 100644 DRAMSys/docs/doxyCfg.cfg delete mode 100644 DRAMSys/docs/images/PayloadExtension.svg delete mode 100644 DRAMSys/docs/images/PayloadMemoryManager.svg delete mode 100644 DRAMSys/docs/images/TransactionPhase.svg delete mode 100644 DRAMSys/docs/images/am_sample1.svg delete mode 100644 DRAMSys/docs/images/am_sample2.svg delete mode 100644 DRAMSys/docs/images/am_wideio_brc.svg delete mode 100644 DRAMSys/docs/images/am_wideio_rbc.svg rename DRAMSys/{docs => gem5}/images/gem5_se_mode_arch.svg (100%) diff --git a/DRAMSys/docs/doxyCfg.cfg b/DRAMSys/docs/doxyCfg.cfg deleted file mode 100644 index ea4940db..00000000 --- a/DRAMSys/docs/doxyCfg.cfg +++ /dev/null @@ -1,1228 +0,0 @@ -# Doxyfile 1.4.4 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = DRAMSys - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = doxygen - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Brazilian, Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, -# Dutch, Finnish, French, German, Greek, Hungarian, Italian, Japanese, -# Japanese-en (Japanese with English messages), Korean, Korean-en, Norwegian, -# Polish, Portuguese, Romanian, Russian, Serbian, Slovak, Slovene, Spanish, -# Swedish, and Ukrainian. - -OUTPUT_LANGUAGE = English - -# This tag can be used to specify the encoding used in the generated output. -# The encoding is not always determined by the language that is chosen, -# but also whether or not the output is meant for Windows or non-Windows users. -# In case there is a difference, setting the USE_WINDOWS_ENCODING tag to YES -# forces the Windows encoding (this is the default for the Windows binary), -# whereas setting the tag to NO uses a Unix-style encoding (the default for -# all platforms other than Windows). - -USE_WINDOWS_ENCODING = NO - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = YES - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like the Qt-style comments (thus requiring an -# explicit @brief command for a brief description. - -JAVADOC_AUTOBRIEF = YES - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the DETAILS_AT_TOP tag is set to YES then Doxygen -# will output the detailed description near the top, like JavaDoc. -# If set to NO, the detailed description appears after the member -# documentation. - -DETAILS_AT_TOP = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES = - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = NO - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java sources -# only. Doxygen will then generate output that is more tailored for Java. -# For instance, namespaces will be presented as packages, qualified scopes -# will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = YES - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = NO - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = YES - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = YES - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is YES. - -SHOW_DIRECTORIES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from the -# version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the progam writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = NO - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = ../ - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm - -FILE_PATTERNS = - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = YES - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = NO - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = NO - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES (the default) -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES (the default) -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = YES - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compressed HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 4 - -# If the GENERATE_TREEVIEW tag is set to YES, a side panel will be -# generated containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (for instance Mozilla 1.0+, -# Netscape 6.0+, Internet explorer 5.0+, or Konqueror). Windows users are -# probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = rtf - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = NO - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. This is useful -# if you want to understand what is going on. On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = NO - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_PREDEFINED tags. - -EXPAND_ONLY_PREDEF = NO - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = NO - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = NO - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = NO - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT tags are set to YES then doxygen will -# generate a call dependency graph for every global function or class method. -# Note that enabling this option will significantly increase the time of a run. -# So in most cases it will be better to enable call graphs for selected -# functions only using the \callgraph command. - -CALL_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = png - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The MAX_DOT_GRAPH_WIDTH tag can be used to set the maximum allowed width -# (in pixels) of the graphs generated by dot. If a graph becomes larger than -# this value, doxygen will try to truncate the graph, so that it fits within -# the specified constraint. Beware that most browsers cannot cope with very -# large images. - -MAX_DOT_GRAPH_WIDTH = 1024 - -# The MAX_DOT_GRAPH_HEIGHT tag can be used to set the maximum allows height -# (in pixels) of the graphs generated by dot. If a graph becomes larger than -# this value, doxygen will try to truncate the graph, so that it fits within -# the specified constraint. Beware that most browsers cannot cope with very -# large images. - -MAX_DOT_GRAPH_HEIGHT = 1024 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that a graph may be further truncated if the graph's -# image dimensions are not sufficient to fit the graph (see MAX_DOT_GRAPH_WIDTH -# and MAX_DOT_GRAPH_HEIGHT). If 0 is used for the depth value (the default), -# the graph is not depth-constrained. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, which results in a white background. -# Warning: Depending on the platform used, enabling this option may lead to -# badly anti-aliased labels on the edges of a graph (i.e. they become hard to -# read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = NO - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to the search engine -#--------------------------------------------------------------------------- - -# The SEARCHENGINE tag specifies whether or not a search engine should be -# used. If set to NO the values of all tags below this one will be ignored. - -SEARCHENGINE = NO diff --git a/DRAMSys/docs/images/PayloadExtension.svg b/DRAMSys/docs/images/PayloadExtension.svg deleted file mode 100644 index fd0cb966..00000000 --- a/DRAMSys/docs/images/PayloadExtension.svg +++ /dev/null @@ -1,2449 +0,0 @@ - - - -Trace -file n -Trace -file -1 -Trace Player -1 -Trace Player n -Arbiter -Controller -Scheduler -ControllerCore -Controller -Scheduler -ControllerCore -DRAM -DRAM -GenerationExtension -sc -_ -time -( -timeOfGeneration -) -Generic Payload -Command -Address -Data pointer -Data length -Byte enable pointer -Byte enable length -Streaming width -DMI hint -Response status -Generic Payload -Command -Address -Data pointer -Data length -Byte enable pointer -Byte enable length -Streaming width -DMI hint -Response status -GenerationExtension -sc -_ -time -( -timeOfGeneration -) -DramExtension -Thread -Chanel -Bank -BankGroup -Row -Column -Burstlength -Generic Payload -Command -Address -Data pointer -Data length -Byte enable pointer -Byte enable length -Streaming width -DMI hint -Response status -GenerationExtension -sc -_ -time -( -timeOfGeneration -) -DramExtension -Thread -Chanel -Bank -BankGroup -Row -Column -Burstlength -Generic Payload -Command -Address -Data pointer -Data length -Byte enable pointer -Byte enable length -Streaming width -DMI hint -Response status -GenerationExtension -sc -_ -time -( -timeOfGeneration -) -DramExtension -Thread -Chanel -Bank -BankGroup -Row -Column -Burstlength - \ No newline at end of file diff --git a/DRAMSys/docs/images/PayloadMemoryManager.svg b/DRAMSys/docs/images/PayloadMemoryManager.svg deleted file mode 100644 index fc237c0c..00000000 --- a/DRAMSys/docs/images/PayloadMemoryManager.svg +++ /dev/null @@ -1,4866 +0,0 @@ - - - - - - image/svg+xml - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SystemC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SystemC - - - - - - - - - - - - - - - - - - - - - - - - - - - SystemC - - - - - - - - - interrupt - jjjjjjjjjjjjjj - - - - - - - - - - - - - - - - - - - - - - - SystemC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SystemC - - - - - - - - - - - - - - - -