derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Replace deprecated headers "systemc.h" and "tlm.h".

Browse Source
This commit is contained in:
Lukas Steiner
2021-08-17 16:26:01 +02:00
parent 545e0ab168
commit aba8398a2d
158 changed files with 1204 additions and 1076 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
DRAMSys/library/src/common/DebugManager.cpp
View File

@@ -40,7 +40,9 @@
#include "../configuration/Configuration.h"
void DebugManager::printDebugMessage(const std::string &sender, const std::string &message)
using namespace sc_core;
void DebugManager::printDebugMessage(const std::string &sender, const std::string &message) const
{
if (Configuration::getInstance().debug)
{
@@ -64,8 +66,8 @@ void DebugManager::openDebugFile(const std::string &filename)
debugFile.open(filename);
}
DebugManager::DebugManager() :
writeToConsole(false), writeToFile(false)
DebugManager::DebugManager()
: writeToConsole(false), writeToFile(false)
{
}

7
DRAMSys/library/src/common/DebugManager.h
View File

@@ -50,10 +50,7 @@
#else
#define PRINTDEBUGMESSAGE(sender, message) DebugManager::getInstance().printDebugMessage(sender, message)
#include <systemc.h>
#include <string>
#include <set>
#include "utils.h"
class DebugManager
{
@@ -74,12 +71,12 @@ public:
bool writeToConsole;
bool writeToFile;
void printDebugMessage(const std::string &sender, const std::string &message);
void printDebugMessage(const std::string &sender, const std::string &message) const;
static void printMessage(const std::string &sender, const std::string &message);
void openDebugFile(const std::string &filename);
private:
ofstream debugFile;
std::ofstream debugFile;
};
#endif

7
DRAMSys/library/src/common/TlmRecorder.cpp
View File

@@ -36,13 +36,14 @@
* Eder F. Zulian
*/
#include <iostream>
#include <algorithm>
#include <fstream>
#include "TlmRecorder.h"
#include "dramExtensions.h"
#include "DebugManager.h"
#include "../controller/Command.h"
#include "../configuration/Configuration.h"
using namespace sc_core;
using namespace tlm;
TlmRecorder::TlmRecorder(const std::string &name, const std::string &dbName) :

40
DRAMSys/library/src/common/TlmRecorder.h
View File

@@ -39,18 +39,15 @@
#ifndef TLMRECORDER_H
#define TLMRECORDER_H
#include <iostream>
#include <ostream>
#include <string>
#include <unordered_map>
#include <algorithm>
#include <fstream>
#include <cerrno>
#include <vector>
#include <thread>
#include <tlm.h>
#include <systemc.h>
#include <systemc>
#include <tlm>
#include "sqlite3.h"
#include "DebugManager.h"
#include "dramExtensions.h"
#include "utils.h"
class TlmRecorder
@@ -61,30 +58,30 @@ public:
void recordMcConfig(std::string _mcconfig)
{
mcconfig = _mcconfig;
mcconfig = std::move(_mcconfig);
}
void recordMemspec(std::string _memspec)
{
memspec = _memspec;
memspec = std::move(_memspec);
}
void recordTraceNames(std::string _traces)
{
traces = _traces;
traces = std::move(_traces);
}
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_time &time);
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &time);
void recordPower(double timeInSeconds, double averagePower);
void recordBufferDepth(double timeInSeconds, const std::vector<double> &averageBufferDepth);
void recordBandwidth(double timeInSeconds, double averageBandwidth);
void recordDebugMessage(const std::string &message, const sc_time &time);
void updateDataStrobe(const sc_time &begin, const sc_time &end,
void recordDebugMessage(const std::string &message, const sc_core::sc_time &time);
void updateDataStrobe(const sc_core::sc_time &begin, const sc_core::sc_time &end,
tlm::tlm_generic_payload &trans);
void closeConnection();
private:
struct Transaction
{
Transaction() {}
Transaction() = default;
Transaction(uint64_t id) : id(id) {}
uint64_t id;
@@ -92,12 +89,13 @@ private:
unsigned int burstLength;
char cmd;
DramExtension dramExtension;
sc_time timeOfGeneration;
sc_core::sc_time timeOfGeneration;
TimeInterval timeOnDataStrobe;
struct Phase
{
Phase(std::string name, sc_time begin): name(name), interval(begin, SC_ZERO_TIME) {}
Phase(std::string name, const sc_core::sc_time& begin): name(std::move(name)),
interval(begin, sc_core::SC_ZERO_TIME) {}
std::string name;
TimeInterval interval;
};
@@ -122,10 +120,10 @@ private:
void insertGeneralInfo();
void insertCommandLengths();
void insertTransactionInDB(Transaction &recordingData);
void insertRangeInDB(uint64_t id, const sc_time &begin, const sc_time &end);
void insertPhaseInDB(const std::string &phaseName, const sc_time &begin, const sc_time &end,
void insertRangeInDB(uint64_t id, const sc_core::sc_time &begin, const sc_core::sc_time &end);
void insertPhaseInDB(const std::string &phaseName, const sc_core::sc_time &begin, const sc_core::sc_time &end,
uint64_t transactionID);
void insertDebugMessageInDB(const std::string &message, const sc_time &time);
void insertDebugMessageInDB(const std::string &message, const sc_core::sc_time &time);
static constexpr unsigned transactionCommitRate = 8192;
std::array<std::vector<Transaction>, 2> recordingDataBuffer;
@@ -136,7 +134,7 @@ private:
std::unordered_map<tlm::tlm_generic_payload *, Transaction> currentTransactionsInSystem;
uint64_t totalNumTransactions;
sc_time simulationTimeCoveredByRecording;
sc_core::sc_time simulationTimeCoveredByRecording;
sqlite3 *db = nullptr;
sqlite3_stmt *insertTransactionStatement, *insertRangeStatement,

15
DRAMSys/library/src/common/dramExtensions.cpp
View File

@@ -37,9 +37,8 @@
#include "dramExtensions.h"
#include "../configuration/Configuration.h"
#include "map"
#include "utils.h"
using namespace sc_core;
using namespace tlm;
DramExtension::DramExtension() :
@@ -55,7 +54,7 @@ DramExtension::DramExtension(Thread thread, Channel channel, Rank rank,
row(row), column(column), burstLength(burstLength),
threadPayloadID(threadPayloadID), channelPayloadID(channelPayloadID) {}
void DramExtension::setExtension(tlm::tlm_generic_payload *payload,
void DramExtension::setExtension(tlm_generic_payload *payload,
Thread thread, Channel channel, Rank rank,
BankGroup bankGroup, Bank bank, Row row,
Column column, unsigned int burstLength,
@@ -86,7 +85,7 @@ void DramExtension::setExtension(tlm::tlm_generic_payload *payload,
}
}
void DramExtension::setExtension(tlm::tlm_generic_payload &payload,
void DramExtension::setExtension(tlm_generic_payload &payload,
Thread thread, Channel channel, Rank rank,
BankGroup bankGroup, Bank bank, Row row,
Column column, unsigned int burstLength,
@@ -97,7 +96,7 @@ void DramExtension::setExtension(tlm::tlm_generic_payload &payload,
threadPayloadID, channelPayloadID);
}
void DramExtension::setPayloadIDs(tlm::tlm_generic_payload *payload, uint64_t threadPayloadID, uint64_t channelPayloadID)
void DramExtension::setPayloadIDs(tlm_generic_payload *payload, uint64_t threadPayloadID, uint64_t channelPayloadID)
{
DramExtension *extension;
payload->get_extension(extension);
@@ -105,7 +104,7 @@ void DramExtension::setPayloadIDs(tlm::tlm_generic_payload *payload, uint64_t th
extension->channelPayloadID = channelPayloadID;
}
void DramExtension::setPayloadIDs(tlm::tlm_generic_payload &payload, uint64_t threadPayloadID, uint64_t channelPayloadID)
void DramExtension::setPayloadIDs(tlm_generic_payload &payload, uint64_t threadPayloadID, uint64_t channelPayloadID)
{
DramExtension::setPayloadIDs(&payload, threadPayloadID, channelPayloadID);
}
@@ -310,7 +309,7 @@ void GenerationExtension::copy_from(const tlm_extension_base &ext)
}
void GenerationExtension::setExtension(tlm::tlm_generic_payload *payload, const sc_time &timeOfGeneration)
void GenerationExtension::setExtension(tlm_generic_payload *payload, const sc_time &timeOfGeneration)
{
GenerationExtension *extension = nullptr;
payload->get_extension(extension);
@@ -326,7 +325,7 @@ void GenerationExtension::setExtension(tlm::tlm_generic_payload *payload, const
}
}
void GenerationExtension::setExtension(tlm::tlm_generic_payload &payload, const sc_time &timeOfGeneration)
void GenerationExtension::setExtension(tlm_generic_payload &payload, const sc_time &timeOfGeneration)
{
GenerationExtension::setExtension(&payload, timeOfGeneration);
}

26
DRAMSys/library/src/common/dramExtensions.h
View File

@@ -37,9 +37,10 @@
#ifndef DRAMEXTENSIONS_H
#define DRAMEXTENSIONS_H
#include <tlm.h>
#include <iostream>
#include <systemc.h>
#include <systemc>
#include <tlm>
class Thread
{
@@ -100,19 +101,14 @@ private:
class Bank
{
public:
Bank(unsigned int id) : id(id) {}
explicit Bank(unsigned int id) : id(id) {}
unsigned int ID() const
{
return id;
}
unsigned int getStartAddress()
{
return 0;
}
std::string toString()
std::string toString() const
{
return std::to_string(id);
}
@@ -245,19 +241,19 @@ private:
class GenerationExtension : public tlm::tlm_extension<GenerationExtension>
{
public:
GenerationExtension(sc_time timeOfGeneration)
explicit GenerationExtension(const sc_core::sc_time &timeOfGeneration)
: timeOfGeneration(timeOfGeneration) {}
tlm::tlm_extension_base *clone() const override;
void copy_from(const tlm::tlm_extension_base &ext) override;
static void setExtension(tlm::tlm_generic_payload *payload, const sc_time &timeOfGeneration);
static void setExtension(tlm::tlm_generic_payload &payload, const sc_time &timeOfGeneration);
static void setExtension(tlm::tlm_generic_payload *payload, const sc_core::sc_time &timeOfGeneration);
static void setExtension(tlm::tlm_generic_payload &payload, const sc_core::sc_time &timeOfGeneration);
static GenerationExtension &getExtension(const tlm::tlm_generic_payload *payload);
static GenerationExtension &getExtension(const tlm::tlm_generic_payload &payload);
static sc_time getTimeOfGeneration(const tlm::tlm_generic_payload *payload);
static sc_time getTimeOfGeneration(const tlm::tlm_generic_payload &payload);
static sc_core::sc_time getTimeOfGeneration(const tlm::tlm_generic_payload *payload);
static sc_core::sc_time getTimeOfGeneration(const tlm::tlm_generic_payload &payload);
private:
sc_time timeOfGeneration;
sc_core::sc_time timeOfGeneration;
};

11
DRAMSys/library/src/common/utils.cpp
View File

@@ -36,13 +36,12 @@
* Luiza Correa
*/
#include "utils.h"
#include <string>
#include <tlm.h>
#include <fstream>
#include "dramExtensions.h"
#include <sstream>
#include <fstream>
#include "utils.h"
using namespace sc_core;
using namespace tlm;
using json = nlohmann::json;
@@ -141,7 +140,7 @@ std::string parseString(json &obj, const std::string &name)
void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank)
{
payload.set_address(bank.getStartAddress());
payload.set_address(0);
payload.set_command(TLM_IGNORE_COMMAND);
payload.set_data_length(0);
payload.set_response_status(TLM_OK_RESPONSE);

20
DRAMSys/library/src/common/utils.h
View File

@@ -39,26 +39,22 @@
#ifndef UTILS_H
#define UTILS_H
#include <systemc.h>
#include <map>
#include <string>
#include <ostream>
#include <tlm.h>
#include <iomanip>
#include <systemc>
#include <tlm>
#include "dramExtensions.h"
#include <fstream>
#include <sstream>
#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
class TimeInterval
{
public:
sc_time start, end;
TimeInterval() : start(SC_ZERO_TIME), end(SC_ZERO_TIME) {}
TimeInterval(sc_time start, sc_time end) : start(start), end(end) {}
sc_core::sc_time start, end;
TimeInterval() : start(sc_core::SC_ZERO_TIME), end(sc_core::SC_ZERO_TIME) {}
TimeInterval(const sc_core::sc_time& start, const sc_core::sc_time& end) : start(start), end(end) {}
sc_time getLength() const;
bool timeIsInInterval(const sc_time &time) const;
sc_core::sc_time getLength() const;
bool timeIsInInterval(const sc_core::sc_time &time) const;
bool intersects(const TimeInterval &other) const;
};

1
DRAMSys/library/src/configuration/Configuration.cpp
View File

@@ -53,6 +53,7 @@
#include "memspec/MemSpecGDDR6.h"
#include "memspec/MemSpecSTTMRAM.h"
using namespace sc_core;
using json = nlohmann::json;
std::string Configuration::memspecUri;

22
DRAMSys/library/src/configuration/Configuration.h
View File

@@ -41,14 +41,12 @@
#ifndef CONFIGURATION_H
#define CONFIGURATION_H
#include <systemc.h>
#include <string>
#include <cstdint>
#include "memspec/MemSpec.h"
#include "TemperatureSimConfig.h"
#include "../common/utils.h"
#include <systemc>
#include "memspec/MemSpec.h"
#include "../error/eccbaseclass.h"
#include "TemperatureSimConfig.h"
class Configuration
{
@@ -59,7 +57,7 @@ public:
return _instance;
}
private:
Configuration() {}
Configuration() = default;
Configuration(const Configuration &);
Configuration &operator = (const Configuration &);
@@ -82,12 +80,12 @@ public:
enum class PowerDownPolicy {NoPowerDown, Staggered} powerDownPolicy;
unsigned int powerDownTimeout = 3;
unsigned int maxActiveTransactions = 64;
sc_time arbitrationDelayFw = SC_ZERO_TIME;
sc_time arbitrationDelayBw = SC_ZERO_TIME;
sc_time thinkDelayFw = SC_ZERO_TIME;
sc_time thinkDelayBw = SC_ZERO_TIME;
sc_time phyDelayFw = SC_ZERO_TIME;
sc_time phyDelayBw = SC_ZERO_TIME;
sc_core::sc_time arbitrationDelayFw = sc_core::SC_ZERO_TIME;
sc_core::sc_time arbitrationDelayBw = sc_core::SC_ZERO_TIME;
sc_core::sc_time thinkDelayFw = sc_core::SC_ZERO_TIME;
sc_core::sc_time thinkDelayBw = sc_core::SC_ZERO_TIME;
sc_core::sc_time phyDelayFw = sc_core::SC_ZERO_TIME;
sc_core::sc_time phyDelayBw = sc_core::SC_ZERO_TIME;
// SimConfig
std::string simulationName = "default";

15
DRAMSys/library/src/configuration/TemperatureSimConfig.h
View File

@@ -38,11 +38,12 @@
#ifndef TEMPERATURESIMCONFIG_H
#define TEMPERATURESIMCONFIG_H
#include <systemc.h>
#include <iostream>
#include <string>
#include <vector>
#include <systemc>
#include <utility>
#include "../common/DebugManager.h"
#include "../common/utils.h"
struct TemperatureSimConfig
{
@@ -52,7 +53,7 @@ struct TemperatureSimConfig
void setPathToResources(std::string path)
{
pathToResources = path;
pathToResources = std::move(path);
}
// Static Temperature Simulation parameters
@@ -60,7 +61,7 @@ struct TemperatureSimConfig
// Thermal Simulation parameters
double thermalSimPeriod;
enum sc_time_unit thermalSimUnit;
enum sc_core::sc_time_unit thermalSimUnit;
std::string iceServerIp;
unsigned int iceServerPort;
unsigned int simPeriodAdjustFactor;
@@ -93,10 +94,10 @@ struct TemperatureSimConfig
}
else
{
for (auto it : powInfoElem["powerInfo"].items())
for (const auto& it : powInfoElem["powerInfo"].items())
{
// Load initial power values for all devices
auto value= it.value();
auto value = it.value();
float pow = value["init_pow"];
powerInitialValues.push_back(pow);

6
DRAMSys/library/src/configuration/memspec/MemSpec.cpp
View File

@@ -35,11 +35,7 @@
#include "MemSpec.h"
#include <systemc.h>
#include <tlm.h>
#include "../../controller/Command.h"
#include "../Configuration.h"
using namespace sc_core;
using namespace tlm;
using json = nlohmann::json;

22
DRAMSys/library/src/configuration/memspec/MemSpec.h
View File

@@ -38,12 +38,14 @@
#ifndef MEMSPEC_H
#define MEMSPEC_H
#include <systemc.h>
#include <vector>
#include "../../common/dramExtensions.h"
#include "../../controller/Command.h"
#include <string>
#include <systemc>
#include <tlm>
#include "../../common/utils.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
#include "../../controller/Command.h"
class MemSpec
{
@@ -66,7 +68,7 @@ public:
// Clock
const double fCKMHz;
const sc_time tCK;
const sc_core::sc_time tCK;
const std::string memoryId;
const enum class MemoryType {DDR3, DDR4, DDR5, LPDDR4, WideIO,
@@ -74,16 +76,16 @@ public:
virtual ~MemSpec() = default;
virtual sc_time getRefreshIntervalAB() const;
virtual sc_time getRefreshIntervalPB() const;
virtual sc_time getRefreshIntervalSB() const;
virtual sc_core::sc_time getRefreshIntervalAB() const;
virtual sc_core::sc_time getRefreshIntervalPB() const;
virtual sc_core::sc_time getRefreshIntervalSB() const;
virtual bool hasRasAndCasBus() const;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const = 0;
virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const = 0;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const = 0;
sc_time getCommandLength(Command) const;
sc_core::sc_time getCommandLength(Command) const;
uint64_t getSimMemSizeInBytes() const;
protected:
@@ -96,7 +98,7 @@ protected:
// Command lengths in cycles on bus, usually one clock cycle
std::vector<unsigned> commandLengthInCycles;
sc_time burstDuration;
sc_core::sc_time burstDuration;
uint64_t memorySizeBytes;
};

6
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
View File

@@ -33,8 +33,12 @@
* Lukas Steiner
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecDDR3.h"
using namespace sc_core;
using namespace tlm;
using json = nlohmann::json;
@@ -139,7 +143,7 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload
}
}
TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const
TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL, tRL + burstDuration};

59
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
View File

@@ -36,6 +36,7 @@
#ifndef MEMSPECDDR3_H
#define MEMSPECDDR3_H
#include <systemc>
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
@@ -45,33 +46,33 @@ public:
explicit MemSpecDDR3(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tCKE;
const sc_time tPD;
const sc_time tCKESR;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCD;
const sc_time tRL;
const sc_time tRTP;
const sc_time tWL;
const sc_time tWR;
const sc_time tXP;
const sc_time tXS;
const sc_time tREFI;
const sc_time tRFC;
const sc_time tRP;
const sc_time tDQSCK;
const sc_time tCCD;
const sc_time tFAW;
const sc_time tRRD;
const sc_time tWTR;
const sc_time tXPDLL;
const sc_time tXSDLL;
const sc_time tAL;
const sc_time tACTPDEN;
const sc_time tPRPDEN;
const sc_time tREFPDEN;
const sc_time tRTRS;
const sc_core::sc_time tCKE;
const sc_core::sc_time tPD;
const sc_core::sc_time tCKESR;
const sc_core::sc_time tRAS;
const sc_core::sc_time tRC;
const sc_core::sc_time tRCD;
const sc_core::sc_time tRL;
const sc_core::sc_time tRTP;
const sc_core::sc_time tWL;
const sc_core::sc_time tWR;
const sc_core::sc_time tXP;
const sc_core::sc_time tXS;
const sc_core::sc_time tREFI;
const sc_core::sc_time tRFC;
const sc_core::sc_time tRP;
const sc_core::sc_time tDQSCK;
const sc_core::sc_time tCCD;
const sc_core::sc_time tFAW;
const sc_core::sc_time tRRD;
const sc_core::sc_time tWTR;
const sc_core::sc_time tXPDLL;
const sc_core::sc_time tXSDLL;
const sc_core::sc_time tAL;
const sc_core::sc_time tACTPDEN;
const sc_core::sc_time tPRPDEN;
const sc_core::sc_time tREFPDEN;
const sc_core::sc_time tRTRS;
// Currents and Voltages:
const double iDD0;
@@ -87,9 +88,9 @@ public:
const double iDD3P0;
const double iDD3P1;
sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalAB() const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};

7
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
View File

@@ -33,9 +33,12 @@
* Lukas Steiner
*/
#include "MemSpecDDR4.h"
#include "../Configuration.h"
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecDDR4.h"
using namespace sc_core;
using namespace tlm;
using json = nlohmann::json;

69
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
View File

@@ -36,6 +36,7 @@
#ifndef MEMSPECDDR4_H
#define MEMSPECDDR4_H
#include <systemc>
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
@@ -45,38 +46,38 @@ public:
explicit MemSpecDDR4(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tCKE;
const sc_time tPD;
const sc_time tCKESR;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCD;
const sc_time tRL;
const sc_time tRPRE;
const sc_time tRTP;
const sc_time tWL;
const sc_time tWPRE;
const sc_time tWR;
const sc_time tXP;
const sc_time tXS;
const sc_time tREFI;
const sc_time tRFC;
const sc_time tRP;
const sc_time tDQSCK;
const sc_time tCCD_S;
const sc_time tCCD_L;
const sc_time tFAW;
const sc_time tRRD_S;
const sc_time tRRD_L;
const sc_time tWTR_S;
const sc_time tWTR_L;
const sc_time tAL;
const sc_time tXPDLL;
const sc_time tXSDLL;
const sc_time tACTPDEN;
const sc_time tPRPDEN;
const sc_time tREFPDEN;
const sc_time tRTRS;
const sc_core::sc_time tCKE;
const sc_core::sc_time tPD;
const sc_core::sc_time tCKESR;
const sc_core::sc_time tRAS;
const sc_core::sc_time tRC;
const sc_core::sc_time tRCD;
const sc_core::sc_time tRL;
const sc_core::sc_time tRPRE;
const sc_core::sc_time tRTP;
const sc_core::sc_time tWL;
const sc_core::sc_time tWPRE;
const sc_core::sc_time tWR;
const sc_core::sc_time tXP;
const sc_core::sc_time tXS;
const sc_core::sc_time tREFI;
const sc_core::sc_time tRFC;
const sc_core::sc_time tRP;
const sc_core::sc_time tDQSCK;
const sc_core::sc_time tCCD_S;
const sc_core::sc_time tCCD_L;
const sc_core::sc_time tFAW;
const sc_core::sc_time tRRD_S;
const sc_core::sc_time tRRD_L;
const sc_core::sc_time tWTR_S;
const sc_core::sc_time tWTR_L;
const sc_core::sc_time tAL;
const sc_core::sc_time tXPDLL;
const sc_core::sc_time tXSDLL;
const sc_core::sc_time tACTPDEN;
const sc_core::sc_time tPRPDEN;
const sc_core::sc_time tREFPDEN;
const sc_core::sc_time tRTRS;
// Currents and Voltages:
const double iDD0;
@@ -95,9 +96,9 @@ public:
const double iDD62;
const double vDD2;
sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalAB() const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};

7
DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
View File

@@ -33,9 +33,12 @@
* Lukas Steiner
*/
#include "MemSpecDDR5.h"
#include "../Configuration.h"
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecDDR5.h"
using namespace sc_core;
using namespace tlm;
using json = nlohmann::json;

105
DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h
View File

@@ -36,6 +36,7 @@
#ifndef MEMSPECDDR5_H
#define MEMSPECDDR5_H
#include <systemc>
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
@@ -53,66 +54,66 @@ public:
const unsigned refMode;
// Memspec Variables:
const sc_time tRCD;
const sc_time tPPD;
const sc_time tRP;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRL;
const sc_time tRTP;
const sc_time tRPRE;
const sc_time tRPST;
const sc_time tRDDQS;
const sc_time tWL;
const sc_time tWPRE;
const sc_time tWPST;
const sc_time tWR;
const sc_time tCCD_L_slr;
const sc_time tCCD_L_WR_slr;
const sc_time tCCD_L_WR2_slr;
const sc_time tCCD_S_slr;
const sc_time tCCD_S_WR_slr;
const sc_time tCCD_dlr;
const sc_time tCCD_WR_dlr;
const sc_time tCCD_WR_dpr;
const sc_time tRRD_L_slr;
const sc_time tRRD_S_slr;
const sc_time tRRD_dlr;
const sc_time tFAW_slr;
const sc_time tFAW_dlr;
const sc_time tWTR_L;
const sc_time tWTR_S;
const sc_time tRFC_slr;
const sc_time tRFC_dlr;
const sc_time tRFC_dpr;
const sc_time tRFCsb_slr;
const sc_time tRFCsb_dlr;
const sc_time tREFI;
const sc_time tREFIsb;
const sc_time tREFSBRD_slr;
const sc_time tREFSBRD_dlr;
const sc_time tRTRS;
const sc_core::sc_time tRCD;
const sc_core::sc_time tPPD;
const sc_core::sc_time tRP;
const sc_core::sc_time tRAS;
const sc_core::sc_time tRC;
const sc_core::sc_time tRL;
const sc_core::sc_time tRTP;
const sc_core::sc_time tRPRE;
const sc_core::sc_time tRPST;
const sc_core::sc_time tRDDQS;
const sc_core::sc_time tWL;
const sc_core::sc_time tWPRE;
const sc_core::sc_time tWPST;
const sc_core::sc_time tWR;
const sc_core::sc_time tCCD_L_slr;
const sc_core::sc_time tCCD_L_WR_slr;
const sc_core::sc_time tCCD_L_WR2_slr;
const sc_core::sc_time tCCD_S_slr;
const sc_core::sc_time tCCD_S_WR_slr;
const sc_core::sc_time tCCD_dlr;
const sc_core::sc_time tCCD_WR_dlr;
const sc_core::sc_time tCCD_WR_dpr;
const sc_core::sc_time tRRD_L_slr;
const sc_core::sc_time tRRD_S_slr;
const sc_core::sc_time tRRD_dlr;
const sc_core::sc_time tFAW_slr;
const sc_core::sc_time tFAW_dlr;
const sc_core::sc_time tWTR_L;
const sc_core::sc_time tWTR_S;
const sc_core::sc_time tRFC_slr;
const sc_core::sc_time tRFC_dlr;
const sc_core::sc_time tRFC_dpr;
const sc_core::sc_time tRFCsb_slr;
const sc_core::sc_time tRFCsb_dlr;
const sc_core::sc_time tREFI;
const sc_core::sc_time tREFIsb;
const sc_core::sc_time tREFSBRD_slr;
const sc_core::sc_time tREFSBRD_dlr;
const sc_core::sc_time tRTRS;
const sc_time tCPDED;
const sc_time tPD;
const sc_time tXP;
const sc_time tACTPDEN;
const sc_time tPRPDEN;
const sc_time tREFPDEN;
const sc_core::sc_time tCPDED;
const sc_core::sc_time tPD;
const sc_core::sc_time tXP;
const sc_core::sc_time tACTPDEN;
const sc_core::sc_time tPRPDEN;
const sc_core::sc_time tREFPDEN;
const sc_time shortCmdOffset;
const sc_time longCmdOffset;
const sc_core::sc_time shortCmdOffset;
const sc_core::sc_time longCmdOffset;
const sc_time tBURST16;
const sc_time tBURST32;
const sc_core::sc_time tBURST16;
const sc_core::sc_time tBURST32;
// Currents and Voltages:
// TODO: to be completed
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalSB() const override;
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalSB() const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};

4
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
View File

@@ -33,8 +33,12 @@
* Lukas Steiner
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecGDDR5.h"
using namespace sc_core;
using namespace tlm;
using json = nlohmann::json;

75
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h
View File

@@ -36,6 +36,7 @@
#ifndef MEMSPECGDDR5_H
#define MEMSPECGDDR5_H
#include <systemc>
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
@@ -45,50 +46,50 @@ public:
explicit MemSpecGDDR5(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tRP;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCDRD;
const sc_time tRCDWR;
const sc_time tRTP;
const sc_time tRRDS;
const sc_time tRRDL;
const sc_time tCCDS;
const sc_time tCCDL;
const sc_time tCL;
const sc_time tWCK2CKPIN;
const sc_time tWCK2CK;
const sc_time tWCK2DQO;
const sc_time tRTW;
const sc_time tWL;
const sc_time tWCK2DQI;
const sc_time tWR;
const sc_time tWTRS;
const sc_time tWTRL;
const sc_time tCKE;
const sc_time tPD;
const sc_time tXPN;
const sc_time tREFI;
const sc_time tREFIPB;
const sc_time tRFC;
const sc_time tRFCPB;
const sc_time tRREFD;
const sc_time tXS;
const sc_time tFAW;
const sc_time t32AW;
const sc_core::sc_time tRP;
const sc_core::sc_time tRAS;
const sc_core::sc_time tRC;
const sc_core::sc_time tRCDRD;
const sc_core::sc_time tRCDWR;
const sc_core::sc_time tRTP;
const sc_core::sc_time tRRDS;
const sc_core::sc_time tRRDL;
const sc_core::sc_time tCCDS;
const sc_core::sc_time tCCDL;
const sc_core::sc_time tCL;
const sc_core::sc_time tWCK2CKPIN;
const sc_core::sc_time tWCK2CK;
const sc_core::sc_time tWCK2DQO;
const sc_core::sc_time tRTW;
const sc_core::sc_time tWL;
const sc_core::sc_time tWCK2DQI;
const sc_core::sc_time tWR;
const sc_core::sc_time tWTRS;
const sc_core::sc_time tWTRL;
const sc_core::sc_time tCKE;
const sc_core::sc_time tPD;
const sc_core::sc_time tXPN;
const sc_core::sc_time tREFI;
const sc_core::sc_time tREFIPB;
const sc_core::sc_time tRFC;
const sc_core::sc_time tRFCPB;
const sc_core::sc_time tRREFD;
const sc_core::sc_time tXS;
const sc_core::sc_time tFAW;
const sc_core::sc_time t32AW;
// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK;
// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK;
const sc_time tPPD;
const sc_time tLK;
const sc_time tRTRS;
const sc_core::sc_time tPPD;
const sc_core::sc_time tLK;
const sc_core::sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};

3
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
View File

@@ -32,9 +32,12 @@
* Authors:
* Lukas Steiner
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecGDDR5X.h"
using namespace sc_core;
using namespace tlm;
using json = nlohmann::json;

75
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h
View File

@@ -36,6 +36,7 @@
#ifndef MEMSPECGDDR5X_H
#define MEMSPECGDDR5X_H
#include <systemc>
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
@@ -45,50 +46,50 @@ public:
explicit MemSpecGDDR5X(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tRP;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCDRD;
const sc_time tRCDWR;
const sc_time tRTP;
const sc_time tRRDS;
const sc_time tRRDL;
const sc_time tCCDS;
const sc_time tCCDL;
const sc_time tRL;
const sc_time tWCK2CKPIN;
const sc_time tWCK2CK;
const sc_time tWCK2DQO;
const sc_time tRTW;
const sc_time tWL;
const sc_time tWCK2DQI;
const sc_time tWR;
const sc_time tWTRS;
const sc_time tWTRL;
const sc_time tCKE;
const sc_time tPD;
const sc_time tXP;
const sc_time tREFI;
const sc_time tREFIPB;
const sc_time tRFC;
const sc_time tRFCPB;
const sc_time tRREFD;
const sc_time tXS;
const sc_time tFAW;
const sc_time t32AW;
const sc_core::sc_time tRP;
const sc_core::sc_time tRAS;
const sc_core::sc_time tRC;
const sc_core::sc_time tRCDRD;
const sc_core::sc_time tRCDWR;
const sc_core::sc_time tRTP;
const sc_core::sc_time tRRDS;
const sc_core::sc_time tRRDL;
const sc_core::sc_time tCCDS;
const sc_core::sc_time tCCDL;
const sc_core::sc_time tRL;
const sc_core::sc_time tWCK2CKPIN;
const sc_core::sc_time tWCK2CK;
const sc_core::sc_time tWCK2DQO;
const sc_core::sc_time tRTW;
const sc_core::sc_time tWL;
const sc_core::sc_time tWCK2DQI;
const sc_core::sc_time tWR;
const sc_core::sc_time tWTRS;
const sc_core::sc_time tWTRL;
const sc_core::sc_time tCKE;
const sc_core::sc_time tPD;
const sc_core::sc_time tXP;
const sc_core::sc_time tREFI;
const sc_core::sc_time tREFIPB;
const sc_core::sc_time tRFC;
const sc_core::sc_time tRFCPB;
const sc_core::sc_time tRREFD;
const sc_core::sc_time tXS;
const sc_core::sc_time tFAW;
const sc_core::sc_time t32AW;
// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK;
// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK;
const sc_time tPPD;
const sc_time tLK;
const sc_time tRTRS;
const sc_core::sc_time tPPD;
const sc_core::sc_time tLK;
const sc_core::sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};

4
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
View File

@@ -33,8 +33,12 @@
* Lukas Steiner
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecGDDR6.h"
using namespace sc_core;
using namespace tlm;
using json = nlohmann::json;

79
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h
View File

@@ -36,6 +36,7 @@
#ifndef MEMSPECGDDR6_H
#define MEMSPECGDDR6_H
#include <systemc>
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
@@ -45,52 +46,52 @@ public:
explicit MemSpecGDDR6(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tRP;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCDRD;
const sc_time tRCDWR;
const sc_time tRTP;
const sc_time tRRDS;
const sc_time tRRDL;
const sc_time tCCDS;
const sc_time tCCDL;
const sc_time tRL;
const sc_time tWCK2CKPIN;
const sc_time tWCK2CK;
const sc_time tWCK2DQO;
const sc_time tRTW;
const sc_time tWL;
const sc_time tWCK2DQI;
const sc_time tWR;
const sc_time tWTRS;
const sc_time tWTRL;
const sc_time tPD;
const sc_time tCKESR;
const sc_time tXP;
const sc_time tREFI;
const sc_time tREFIPB;
const sc_time tRFC;
const sc_time tRFCPB;
const sc_time tRREFD;
const sc_time tXS;
const sc_time tFAW;
const sc_core::sc_time tRP;
const sc_core::sc_time tRAS;
const sc_core::sc_time tRC;
const sc_core::sc_time tRCDRD;
const sc_core::sc_time tRCDWR;
const sc_core::sc_time tRTP;
const sc_core::sc_time tRRDS;
const sc_core::sc_time tRRDL;
const sc_core::sc_time tCCDS;
const sc_core::sc_time tCCDL;
const sc_core::sc_time tRL;
const sc_core::sc_time tWCK2CKPIN;
const sc_core::sc_time tWCK2CK;
const sc_core::sc_time tWCK2DQO;
const sc_core::sc_time tRTW;
const sc_core::sc_time tWL;
const sc_core::sc_time tWCK2DQI;
const sc_core::sc_time tWR;
const sc_core::sc_time tWTRS;
const sc_core::sc_time tWTRL;
const sc_core::sc_time tPD;
const sc_core::sc_time tCKESR;
const sc_core::sc_time tXP;
const sc_core::sc_time tREFI;
const sc_core::sc_time tREFIPB;
const sc_core::sc_time tRFC;
const sc_core::sc_time tRFCPB;
const sc_core::sc_time tRREFD;
const sc_core::sc_time tXS;
const sc_core::sc_time tFAW;
// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK;
// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK;
const sc_time tPPD;
const sc_time tLK;
const sc_time tACTPDE;
const sc_time tPREPDE;
const sc_time tREFPDE;
const sc_time tRTRS;
const sc_core::sc_time tPPD;
const sc_core::sc_time tLK;
const sc_core::sc_time tACTPDE;
const sc_core::sc_time tPREPDE;
const sc_core::sc_time tREFPDE;
const sc_core::sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};

4
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
View File

@@ -33,8 +33,12 @@
* Lukas Steiner
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecHBM2.h"
using namespace sc_core;
using namespace tlm;
using json = nlohmann::json;

65
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h
View File

@@ -36,6 +36,7 @@
#ifndef MEMSPECHBM2_H
#define MEMSPECHBM2_H
#include <systemc>
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
@@ -45,47 +46,47 @@ public:
explicit MemSpecHBM2(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tDQSCK;
const sc_core::sc_time tDQSCK;
// sc_time tDQSQ; // TODO: check actual value of this parameter
const sc_time tRC;
const sc_time tRAS;
const sc_time tRCDRD;
const sc_time tRCDWR;
const sc_time tRRDL;
const sc_time tRRDS;
const sc_time tFAW;
const sc_time tRTP;
const sc_time tRP;
const sc_time tRL;
const sc_time tWL;
const sc_time tPL;
const sc_time tWR;
const sc_time tCCDL;
const sc_time tCCDS;
const sc_core::sc_time tRC;
const sc_core::sc_time tRAS;
const sc_core::sc_time tRCDRD;
const sc_core::sc_time tRCDWR;
const sc_core::sc_time tRRDL;
const sc_core::sc_time tRRDS;
const sc_core::sc_time tFAW;
const sc_core::sc_time tRTP;
const sc_core::sc_time tRP;
const sc_core::sc_time tRL;
const sc_core::sc_time tWL;
const sc_core::sc_time tPL;
const sc_core::sc_time tWR;
const sc_core::sc_time tCCDL;
const sc_core::sc_time tCCDS;
// sc_time tCCDR; // TODO: consecutive reads to different stack IDs
const sc_time tWTRL;
const sc_time tWTRS;
const sc_time tRTW;
const sc_time tXP;
const sc_time tCKE;
const sc_time tPD; // = tCKE;
const sc_time tCKESR; // = tCKE + tCK;
const sc_time tXS;
const sc_time tRFC;
const sc_time tRFCSB;
const sc_time tRREFD;
const sc_time tREFI;
const sc_time tREFISB;
const sc_core::sc_time tWTRL;
const sc_core::sc_time tWTRS;
const sc_core::sc_time tRTW;
const sc_core::sc_time tXP;
const sc_core::sc_time tCKE;
const sc_core::sc_time tPD; // = tCKE;
const sc_core::sc_time tCKESR; // = tCKE + tCK;
const sc_core::sc_time tXS;
const sc_core::sc_time tRFC;
const sc_core::sc_time tRFCSB;
const sc_core::sc_time tRREFD;
const sc_core::sc_time tREFI;
const sc_core::sc_time tREFISB;
// Currents and Voltages:
// TODO: to be completed
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
bool hasRasAndCasBus() const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};

4
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
View File

@@ -33,8 +33,12 @@
* Lukas Steiner
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecLPDDR4.h"
using namespace sc_core;
using namespace tlm;
using json = nlohmann::json;

69
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h
View File

@@ -36,6 +36,7 @@
#ifndef MEMSPECLPDDR4_H
#define MEMSPECLPDDR4_H
#include <systemc>
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
@@ -45,45 +46,45 @@ public:
explicit MemSpecLPDDR4(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tREFI;
const sc_time tREFIpb;
const sc_time tRFCab;
const sc_time tRFCpb;
const sc_time tRAS;
const sc_time tRPab;
const sc_time tRPpb;
const sc_time tRCpb;
const sc_time tRCab;
const sc_time tPPD;
const sc_time tRCD;
const sc_time tFAW;
const sc_time tRRD;
const sc_time tCCD;
const sc_time tRL;
const sc_time tRPST;
const sc_time tDQSCK;
const sc_time tRTP;
const sc_time tWL;
const sc_time tDQSS;
const sc_time tDQS2DQ;
const sc_time tWR;
const sc_time tWPRE;
const sc_time tWTR;
const sc_time tXP;
const sc_time tSR;
const sc_time tXSR;
const sc_time tESCKE;
const sc_time tCKE;
const sc_time tCMDCKE;
const sc_time tRTRS;
const sc_core::sc_time tREFI;
const sc_core::sc_time tREFIpb;
const sc_core::sc_time tRFCab;
const sc_core::sc_time tRFCpb;
const sc_core::sc_time tRAS;
const sc_core::sc_time tRPab;
const sc_core::sc_time tRPpb;
const sc_core::sc_time tRCpb;
const sc_core::sc_time tRCab;
const sc_core::sc_time tPPD;
const sc_core::sc_time tRCD;
const sc_core::sc_time tFAW;
const sc_core::sc_time tRRD;
const sc_core::sc_time tCCD;
const sc_core::sc_time tRL;
const sc_core::sc_time tRPST;
const sc_core::sc_time tDQSCK;
const sc_core::sc_time tRTP;
const sc_core::sc_time tWL;
const sc_core::sc_time tDQSS;
const sc_core::sc_time tDQS2DQ;
const sc_core::sc_time tWR;
const sc_core::sc_time tWPRE;
const sc_core::sc_time tWTR;
const sc_core::sc_time tXP;
const sc_core::sc_time tSR;
const sc_core::sc_time tXSR;
const sc_core::sc_time tESCKE;
const sc_core::sc_time tCKE;
const sc_core::sc_time tCMDCKE;
const sc_core::sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};

4
DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp
View File

@@ -33,8 +33,12 @@
* Lukas Steiner
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecSTTMRAM.h"
using namespace sc_core;
using namespace tlm;
using json = nlohmann::json;

51
DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h
View File

@@ -36,6 +36,7 @@
#ifndef MEMSPECSTTMRAM_H
#define MEMSPECSTTMRAM_H
#include <systemc>
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
@@ -45,35 +46,35 @@ public:
explicit MemSpecSTTMRAM(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tCKE;
const sc_time tPD;
const sc_time tCKESR;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCD;
const sc_time tRL;
const sc_time tRTP;
const sc_time tWL;
const sc_time tWR;
const sc_time tXP;
const sc_time tXS;
const sc_time tRP;
const sc_time tDQSCK;
const sc_time tCCD;
const sc_time tFAW;
const sc_time tRRD;
const sc_time tWTR;
const sc_time tXPDLL;
const sc_time tXSDLL;
const sc_time tAL;
const sc_time tACTPDEN;
const sc_time tPRPDEN;
const sc_time tRTRS;
const sc_core::sc_time tCKE;
const sc_core::sc_time tPD;
const sc_core::sc_time tCKESR;
const sc_core::sc_time tRAS;
const sc_core::sc_time tRC;
const sc_core::sc_time tRCD;
const sc_core::sc_time tRL;
const sc_core::sc_time tRTP;
const sc_core::sc_time tWL;
const sc_core::sc_time tWR;
const sc_core::sc_time tXP;
const sc_core::sc_time tXS;
const sc_core::sc_time tRP;
const sc_core::sc_time tDQSCK;
const sc_core::sc_time tCCD;
const sc_core::sc_time tFAW;
const sc_core::sc_time tRRD;
const sc_core::sc_time tWTR;
const sc_core::sc_time tXPDLL;
const sc_core::sc_time tXSDLL;
const sc_core::sc_time tAL;
const sc_core::sc_time tACTPDEN;
const sc_core::sc_time tPRPDEN;
const sc_core::sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};

4
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -33,8 +33,12 @@
* Lukas Steiner
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecWideIO.h"
using namespace sc_core;
using namespace tlm;
using json = nlohmann::json;

47
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h
View File

@@ -36,6 +36,7 @@
#ifndef MEMSPECWIDEIO_H
#define MEMSPECWIDEIO_H
#include <systemc>
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
@@ -45,27 +46,27 @@ public:
explicit MemSpecWideIO(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tCKE;
const sc_time tCKESR;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCD;
const sc_time tRL;
const sc_time tWL;
const sc_time tWR;
const sc_time tXP;
const sc_time tXSR;
const sc_time tREFI;
const sc_time tRFC;
const sc_time tRP;
const sc_time tDQSCK;
const sc_time tAC;
const sc_time tCCD_R;
const sc_time tCCD_W;
const sc_time tRRD;
const sc_time tTAW;
const sc_time tWTR;
const sc_time tRTRS;
const sc_core::sc_time tCKE;
const sc_core::sc_time tCKESR;
const sc_core::sc_time tRAS;
const sc_core::sc_time tRC;
const sc_core::sc_time tRCD;
const sc_core::sc_time tRL;
const sc_core::sc_time tWL;
const sc_core::sc_time tWR;
const sc_core::sc_time tXP;
const sc_core::sc_time tXSR;
const sc_core::sc_time tREFI;
const sc_core::sc_time tRFC;
const sc_core::sc_time tRP;
const sc_core::sc_time tDQSCK;
const sc_core::sc_time tAC;
const sc_core::sc_time tCCD_R;
const sc_core::sc_time tCCD_W;
const sc_core::sc_time tRRD;
const sc_core::sc_time tTAW;
const sc_core::sc_time tWTR;
const sc_core::sc_time tRTRS;
// Currents and Voltages:
const double iDD0;
@@ -93,9 +94,9 @@ public:
const double iDD62;
const double vDD2;
sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalAB() const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};

4
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
View File

@@ -33,8 +33,12 @@
* Lukas Steiner
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecWideIO2.h"
using namespace sc_core;
using namespace tlm;
using json = nlohmann::json;

57
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h
View File

@@ -36,6 +36,7 @@
#ifndef MEMSPECWIDEIO2_H
#define MEMSPECWIDEIO2_H
#include <systemc>
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
@@ -45,39 +46,39 @@ public:
explicit MemSpecWideIO2(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tDQSCK;
const sc_time tDQSS;
const sc_time tCKE;
const sc_time tRL;
const sc_time tWL;
const sc_time tRCpb;
const sc_time tRCab;
const sc_time tCKESR;
const sc_time tXSR;
const sc_time tXP;
const sc_time tCCD;
const sc_time tRTP;
const sc_time tRCD;
const sc_time tRPpb;
const sc_time tRPab;
const sc_time tRAS;
const sc_time tWR;
const sc_time tWTR;
const sc_time tRRD;
const sc_time tFAW;
const sc_time tREFI;
const sc_time tREFIpb;
const sc_time tRFCab;
const sc_time tRFCpb;
const sc_time tRTRS;
const sc_core::sc_time tDQSCK;
const sc_core::sc_time tDQSS;
const sc_core::sc_time tCKE;
const sc_core::sc_time tRL;
const sc_core::sc_time tWL;
const sc_core::sc_time tRCpb;
const sc_core::sc_time tRCab;
const sc_core::sc_time tCKESR;
const sc_core::sc_time tXSR;
const sc_core::sc_time tXP;
const sc_core::sc_time tCCD;
const sc_core::sc_time tRTP;
const sc_core::sc_time tRCD;
const sc_core::sc_time tRPpb;
const sc_core::sc_time tRPab;
const sc_core::sc_time tRAS;
const sc_core::sc_time tWR;
const sc_core::sc_time tWTR;
const sc_core::sc_time tRRD;
const sc_core::sc_time tFAW;
const sc_core::sc_time tREFI;
const sc_core::sc_time tREFIpb;
const sc_core::sc_time tRFCab;
const sc_core::sc_time tRFCpb;
const sc_core::sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};

3
DRAMSys/library/src/controller/BankMachine.cpp
View File

@@ -32,9 +32,12 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "BankMachine.h"
#include "../configuration/Configuration.h"
using namespace sc_core;
using namespace tlm;
BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, Bank bank)

17
DRAMSys/library/src/controller/BankMachine.h
View File

@@ -35,9 +35,8 @@
#ifndef BANKMACHINE_H
#define BANKMACHINE_H
#include <systemc.h>
#include <tlm.h>
#include <utility>
#include <systemc>
#include <tlm>
#include "../common/dramExtensions.h"
#include "Command.h"
#include "scheduler/SchedulerIF.h"
@@ -47,7 +46,7 @@ class BankMachine
{
public:
virtual ~BankMachine() = default;
virtual sc_time start() = 0;
virtual sc_core::sc_time start() = 0;
CommandTuple::Type getNextCommand();
void updateState(Command);
void block();
@@ -69,7 +68,7 @@ protected:
Command nextCommand = Command::NOP;
State state = State::Precharged;
Row openRow;
sc_time timeToSchedule = sc_max_time();
sc_core::sc_time timeToSchedule = sc_core::sc_max_time();
Rank rank = Rank(0);
BankGroup bankgroup = BankGroup(0);
Bank bank;
@@ -81,28 +80,28 @@ class BankMachineOpen final : public BankMachine
{
public:
BankMachineOpen(SchedulerIF *, CheckerIF *, Bank);
sc_time start() override;
sc_core::sc_time start() override;
};
class BankMachineClosed final : public BankMachine
{
public:
BankMachineClosed(SchedulerIF *, CheckerIF *, Bank);
sc_time start() override;
sc_core::sc_time start() override;
};
class BankMachineOpenAdaptive final : public BankMachine
{
public:
BankMachineOpenAdaptive(SchedulerIF *, CheckerIF *, Bank);
sc_time start() override;
sc_core::sc_time start() override;
};
class BankMachineClosedAdaptive final : public BankMachine
{
public:
BankMachineClosedAdaptive(SchedulerIF *, CheckerIF *, Bank);
sc_time start() override;
sc_core::sc_time start() override;
};
#endif // BANKMACHINE_H

2
DRAMSys/library/src/controller/Command.cpp
View File

@@ -35,8 +35,8 @@
* Matthias Jung
*/
#include <array>
#include "Command.h"
#include <systemc.h>
using namespace tlm;
using namespace DRAMPower;

11
DRAMSys/library/src/controller/Command.h
View File

@@ -38,11 +38,10 @@
#include <string>
#include <vector>
#include <list>
#include <algorithm>
#include <array>
#include <systemc.h>
#include <tlm.h>
#include <tuple>
#include <systemc>
#include <tlm>
#include "../common/third_party/DRAMPower/src/MemCommand.h"
// DO NOT CHANGE THE ORDER!
@@ -137,7 +136,7 @@ tlm::tlm_phase getEndPhase(tlm::tlm_phase);
struct CommandTuple
{
using Type = std::tuple<::Command, tlm::tlm_generic_payload *, sc_time>;
using Type = std::tuple<::Command, tlm::tlm_generic_payload *, sc_core::sc_time>;
enum Accessor
{
Command = 0,

3
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -36,7 +36,7 @@
#include "../configuration/Configuration.h"
#include "../common/dramExtensions.h"
#include "Command.h"
#include "checker/CheckerDDR3.h"
#include "checker/CheckerDDR4.h"
#include "checker/CheckerDDR5.h"
@@ -62,6 +62,7 @@
#include "powerdown/PowerDownManagerStaggered.h"
#include "powerdown/PowerDownManagerDummy.h"
using namespace sc_core;
using namespace tlm;
Controller::Controller(const sc_module_name &name) :

41
DRAMSys/library/src/controller/Controller.h
View File

@@ -35,19 +35,14 @@
#ifndef CONTROLLER_H
#define CONTROLLER_H
#include <queue>
#include <vector>
#include <utility>
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <systemc>
#include <tlm>
#include "ControllerIF.h"
#include "../common/dramExtensions.h"
#include "BankMachine.h"
#include "Command.h"
#include "cmdmux/CmdMuxIF.h"
#include "scheduler/SchedulerIF.h"
#include "../common/DebugManager.h"
#include "checker/CheckerIF.h"
#include "refresh/RefreshManagerIF.h"
#include "powerdown/PowerDownManagerIF.h"
@@ -60,27 +55,29 @@ class PowerDownManagerStaggered;
class Controller : public ControllerIF
{
public:
explicit Controller(const sc_module_name &name);
explicit Controller(const sc_core::sc_module_name &name);
SC_HAS_PROCESS(Controller);
~Controller() override;
protected:
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase,
sc_core::sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase,
sc_core::sc_time &delay) override;
unsigned int transport_dbg(tlm::tlm_generic_payload &trans) override;
virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_time);
virtual void sendToDram(Command, tlm::tlm_generic_payload *, sc_time);
virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_core::sc_time);
virtual void sendToDram(Command, tlm::tlm_generic_payload *, sc_core::sc_time);
virtual void controllerMethod();
SchedulerIF *scheduler;
const MemSpec *memSpec;
sc_time thinkDelayFw;
sc_time thinkDelayBw;
sc_time phyDelayFw;
sc_time phyDelayBw;
sc_core::sc_time thinkDelayFw;
sc_core::sc_time thinkDelayBw;
sc_core::sc_time phyDelayFw;
sc_core::sc_time phyDelayBw;
private:
unsigned totalNumberOfPayloads = 0;
@@ -98,13 +95,13 @@ private:
struct Transaction
{
tlm::tlm_generic_payload *payload = nullptr;
sc_time time = sc_max_time();
sc_core::sc_time time = sc_core::sc_max_time();
} transToAcquire, transToRelease;
void manageResponses();
void manageRequests(const sc_time &delay);
void manageRequests(const sc_core::sc_time &delay);
sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent;
sc_core::sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent;
};
#endif // CONTROLLER_H

64
DRAMSys/library/src/controller/ControllerIF.h
View File

@@ -37,15 +37,17 @@
#ifndef CONTROLLERIF_H
#define CONTROLLERIF_H
#include <systemc.h>
#include <tlm.h>
#include <iomanip>
#include <systemc>
#include <tlm>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include "../configuration/Configuration.h"
// Utiliy class to pass around the DRAMSys, without having to propagate the template defintions
// throughout all classes
class ControllerIF : public sc_module
class ControllerIF : public sc_core::sc_module
{
public:
// Already create and bind sockets to the virtual functions
@@ -53,14 +55,14 @@ public:
tlm_utils::simple_initiator_socket<ControllerIF> iSocket; // DRAM side
// Destructor
virtual ~ControllerIF()
~ControllerIF() override
{
sc_time activeTime = numberOfBeatsServed
/ Configuration::getInstance().memSpec->dataRate
* Configuration::getInstance().memSpec->tCK;
sc_core::sc_time activeTime = numberOfBeatsServed
/ Configuration::getInstance().memSpec->dataRate
* Configuration::getInstance().memSpec->tCK;
double bandwidth = activeTime / sc_time_stamp();
double bandwidthWoIdle = activeTime / (sc_time_stamp() - idleTimeCollector.getIdleTime());
double bandwidth = activeTime / sc_core::sc_time_stamp();
double bandwidthWoIdle = activeTime / (sc_core::sc_time_stamp() - idleTimeCollector.getIdleTime());
double maxBandwidth = (
// fCK in GHz e.g. 1 [GHz] (tCK in ps):
@@ -73,28 +75,28 @@ public:
* Configuration::getInstance().memSpec->numberOfDevicesOnDIMM );
std::cout << name() << std::string(" Total Time: ")
<< sc_time_stamp().to_string()
<< std::endl;
<< sc_core::sc_time_stamp().to_string()
<< std::endl;
std::cout << name() << std::string(" AVG BW: ")
<< std::fixed << std::setprecision(2)
<< (bandwidth * maxBandwidth)
<< " Gb/s (" << (bandwidth * 100) << " %)"
<< std::endl;
<< std::fixed << std::setprecision(2)
<< (bandwidth * maxBandwidth)
<< " Gb/s (" << (bandwidth * 100) << " %)"
<< std::endl;
std::cout << name() << std::string(" AVG BW\\IDLE: ")
<< std::fixed << std::setprecision(2)
<< (bandwidthWoIdle * maxBandwidth)
<< " Gb/s (" << (bandwidthWoIdle * 100) << " %)"
<< endl;
<< std::fixed << std::setprecision(2)
<< (bandwidthWoIdle * maxBandwidth)
<< " Gb/s (" << (bandwidthWoIdle * 100) << " %)"
<< std::endl;
std::cout << name() << std::string(" MAX BW: ")
<< std::fixed << std::setprecision(2)
<< maxBandwidth << " Gb/s"
<< std::endl;
<< std::fixed << std::setprecision(2)
<< maxBandwidth << " Gb/s"
<< std::endl;
}
protected:
// Bind sockets with virtual functions
ControllerIF(const sc_module_name &name) :
sc_module(name), tSocket("tSocket"), iSocket("iSocket")
explicit ControllerIF(const sc_core::sc_module_name &name)
: sc_core::sc_module(name), tSocket("tSocket"), iSocket("iSocket")
{
tSocket.register_nb_transport_fw(this, &ControllerIF::nb_transport_fw);
tSocket.register_transport_dbg(this, &ControllerIF::transport_dbg);
@@ -103,9 +105,9 @@ protected:
SC_HAS_PROCESS(ControllerIF);
// Virtual transport functions
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) = 0;
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_core::sc_time &) = 0;
virtual unsigned int transport_dbg(tlm::tlm_generic_payload &) = 0;
virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) = 0;
virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_core::sc_time &) = 0;
// Bandwidth related
class IdleTimeCollector
@@ -116,7 +118,7 @@ protected:
if (!isIdle)
{
PRINTDEBUGMESSAGE("IdleTimeCollector", "IDLE start");
idleStart = sc_time_stamp();
idleStart = sc_core::sc_time_stamp();
isIdle = true;
}
}
@@ -126,20 +128,20 @@ protected:
if (isIdle)
{
PRINTDEBUGMESSAGE("IdleTimeCollector", "IDLE end");
idleTime += sc_time_stamp() - idleStart;
idleTime += sc_core::sc_time_stamp() - idleStart;
isIdle = false;
}
}
sc_time getIdleTime()
sc_core::sc_time getIdleTime()
{
return idleTime;
}
private:
bool isIdle = false;
sc_time idleTime = SC_ZERO_TIME;
sc_time idleStart;
sc_core::sc_time idleTime = sc_core::SC_ZERO_TIME;
sc_core::sc_time idleStart;
} idleTimeCollector;
uint64_t numberOfBeatsServed = 0;

6
DRAMSys/library/src/controller/ControllerRecordable.cpp
View File

@@ -34,7 +34,9 @@
#include "ControllerRecordable.h"
#include "../configuration/Configuration.h"
#include "scheduler/SchedulerIF.h"
using namespace sc_core;
using namespace tlm;
ControllerRecordable::ControllerRecordable(const sc_module_name &name, TlmRecorder *tlmRecorder)
@@ -112,7 +114,7 @@ void ControllerRecordable::controllerMethod()
lastTimeCalled = sc_time_stamp();
const std::vector<unsigned> &bufferDepth = scheduler->getBufferDepth();
for (size_t index = 0; index < slidingAverageBufferDepth.size(); index++)
for (std::size_t index = 0; index < slidingAverageBufferDepth.size(); index++)
slidingAverageBufferDepth[index] += bufferDepth[index] * timeDiff;
if (sc_time_stamp() == nextWindowEventTime)
@@ -120,7 +122,7 @@ void ControllerRecordable::controllerMethod()
windowEvent.notify(windowSizeTime);
nextWindowEventTime += windowSizeTime;
for (size_t index = 0; index < slidingAverageBufferDepth.size(); index++)
for (std::size_t index = 0; index < slidingAverageBufferDepth.size(); index++)
{
windowAverageBufferDepth[index] = slidingAverageBufferDepth[index] / windowSizeTime;
slidingAverageBufferDepth[index] = SC_ZERO_TIME;

32
DRAMSys/library/src/controller/ControllerRecordable.h
View File

@@ -35,40 +35,42 @@
#ifndef CONTROLLERRECORDABLE_H
#define CONTROLLERRECORDABLE_H
#include <systemc>
#include <tlm>
#include "Controller.h"
#include "../common/TlmRecorder.h"
class ControllerRecordable final : public Controller
{
public:
ControllerRecordable(const sc_module_name &name, TlmRecorder *tlmRecorder);
ControllerRecordable(const sc_core::sc_module_name &name, TlmRecorder *tlmRecorder);
~ControllerRecordable() override = default;
protected:
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans,
tlm::tlm_phase &phase, sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans,
tlm::tlm_phase &phase, sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase,
sc_core::sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase,
sc_core::sc_time &delay) override;
void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_time) override;
void sendToDram(Command, tlm::tlm_generic_payload *, sc_time) override;
void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_core::sc_time) override;
void sendToDram(Command, tlm::tlm_generic_payload *, sc_core::sc_time) override;
void controllerMethod() override;
private:
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_time &delay);
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &delay);
TlmRecorder *tlmRecorder;
sc_event windowEvent;
sc_time windowSizeTime;
sc_time nextWindowEventTime;
std::vector<sc_time> slidingAverageBufferDepth;
sc_core::sc_event windowEvent;
sc_core::sc_time windowSizeTime;
sc_core::sc_time nextWindowEventTime;
std::vector<sc_core::sc_time> slidingAverageBufferDepth;
std::vector<double> windowAverageBufferDepth;
sc_time lastTimeCalled = SC_ZERO_TIME;
sc_core::sc_time lastTimeCalled = sc_core::SC_ZERO_TIME;
uint64_t lastNumberOfBeatsServed = 0;
sc_time activeTimeMultiplier = Configuration::getInstance().memSpec->tCK
/ Configuration::getInstance().memSpec->dataRate;
sc_core::sc_time activeTimeMultiplier = Configuration::getInstance().memSpec->tCK
/ Configuration::getInstance().memSpec->dataRate;
};
#endif // CONTROLLERRECORDABLE_H

3
DRAMSys/library/src/controller/checker/CheckerDDR3.cpp
View File

@@ -32,8 +32,11 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerDDR3.h"
using namespace sc_core;
using namespace tlm;
CheckerDDR3::CheckerDDR3()

33
DRAMSys/library/src/controller/checker/CheckerDDR3.h
View File

@@ -35,9 +35,10 @@
#ifndef CHECKERDDR3_H
#define CHECKERDDR3_H
#include "CheckerIF.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecDDR3.h"
#include "../../configuration/Configuration.h"
@@ -45,29 +46,29 @@ class CheckerDDR3 final : public CheckerIF
{
public:
CheckerDDR3();
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecDDR3 *memSpec;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_time> lastScheduledByCommand;
sc_time lastCommandOnBus;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnBus;
// Four activate window
std::vector<std::queue<sc_time>> last4Activates;
std::vector<std::queue<sc_core::sc_time>> last4Activates;
sc_time tBURST;
sc_time tRDWR;
sc_time tRDWR_R;
sc_time tWRRD;
sc_time tWRPRE;
sc_time tWRRD_R;
sc_time tRDPDEN;
sc_time tWRPDEN;
sc_time tWRAPDEN;
sc_core::sc_time tBURST;
sc_core::sc_time tRDWR;
sc_core::sc_time tRDWR_R;
sc_core::sc_time tWRRD;
sc_core::sc_time tWRPRE;
sc_core::sc_time tWRRD_R;
sc_core::sc_time tRDPDEN;
sc_core::sc_time tWRPDEN;
sc_core::sc_time tWRAPDEN;
};
#endif // CHECKERDDR3_H

3
DRAMSys/library/src/controller/checker/CheckerDDR4.cpp
View File

@@ -32,8 +32,11 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerDDR4.h"
using namespace sc_core;
using namespace tlm;
CheckerDDR4::CheckerDDR4()

41
DRAMSys/library/src/controller/checker/CheckerDDR4.h
View File

@@ -35,9 +35,10 @@
#ifndef CHECKERDDR4_H
#define CHECKERDDR4_H
#include "CheckerIF.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecDDR4.h"
#include "../../configuration/Configuration.h"
@@ -45,33 +46,33 @@ class CheckerDDR4 final : public CheckerIF
{
public:
CheckerDDR4();
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecDDR4 *memSpec;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_time> lastScheduledByCommand;
sc_time lastCommandOnBus;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnBus;
// Four activate window
std::vector<std::queue<sc_time>> last4Activates;
std::vector<std::queue<sc_core::sc_time>> last4Activates;
sc_time tBURST;
sc_time tRDWR;
sc_time tRDWR_R;
sc_time tWRRD_S;
sc_time tWRRD_L;
sc_time tWRRD_R;
sc_time tRDAACT;
sc_time tWRPRE;
sc_time tWRAACT;
sc_time tRDPDEN;
sc_time tWRPDEN;
sc_time tWRAPDEN;
sc_core::sc_time tBURST;
sc_core::sc_time tRDWR;
sc_core::sc_time tRDWR_R;
sc_core::sc_time tWRRD_S;
sc_core::sc_time tWRRD_L;
sc_core::sc_time tWRRD_R;
sc_core::sc_time tRDAACT;
sc_core::sc_time tWRPRE;
sc_core::sc_time tWRAACT;
sc_core::sc_time tRDPDEN;
sc_core::sc_time tWRPDEN;
sc_core::sc_time tWRAPDEN;
};
#endif // CHECKERDDR4_H

3
DRAMSys/library/src/controller/checker/CheckerDDR5.cpp
View File

@@ -32,8 +32,11 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerDDR5.h"
using namespace sc_core;
using namespace tlm;
CheckerDDR5::CheckerDDR5()

75
DRAMSys/library/src/controller/checker/CheckerDDR5.h
View File

@@ -35,9 +35,10 @@
#ifndef CHECKERDDR5_H
#define CHECKERDDR5_H
#include "CheckerIF.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecDDR5.h"
#include "../../configuration/Configuration.h"
#include "../../common/utils.h"
@@ -46,25 +47,25 @@ class CheckerDDR5 final : public CheckerIF
{
public:
CheckerDDR5();
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecDDR5 *memSpec;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndDimmRank;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndPhysicalRank;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndLogicalRank;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBank;
std::vector<sc_time> lastScheduledByCommand;
sc_time lastCommandOnBus;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndDimmRank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndPhysicalRank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndLogicalRank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnBus;
TimeInterval dummyCommandOnBus;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBankInGroup;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBankInGroup;
std::vector<std::queue<sc_time>> last4ActivatesPhysical;
std::vector<std::queue<sc_time>> last4ActivatesLogical;
std::vector<std::queue<sc_core::sc_time>> last4ActivatesPhysical;
std::vector<std::queue<sc_core::sc_time>> last4ActivatesLogical;
std::vector<std::vector<uint8_t>> lastBurstLengthByCommandAndDimmRank;
std::vector<std::vector<uint8_t>> lastBurstLengthByCommandAndPhysicalRank;
@@ -77,32 +78,32 @@ private:
// TODO: store BL of last RD and WR globally or for each hierarchy?
sc_time cmdLengthDiff;
sc_core::sc_time cmdLengthDiff;
sc_time tBURST16;
sc_time tBURST32;
sc_time tWTRA;
sc_time tWRRDA;
sc_time tWRPRE;
sc_time tRDAACT;
sc_time tWRAACT;
sc_time tCCD_L_RTW_slr;
sc_time tCCD_S_RTW_slr;
sc_time tCCD_RTW_dlr;
sc_time tRDRD_dpr;
sc_time tRDRD_ddr;
sc_time tRDWR_dpr;
sc_time tRDWR_ddr;
sc_time tCCD_L_WTR_slr;
sc_time tCCD_S_WTR_slr;
sc_time tCCD_WTR_dlr;
sc_time tWRWR_dpr;
sc_time tWRWR_ddr;
sc_time tWRRD_dpr;
sc_time tWRRD_ddr;
sc_time tRDPDEN;
sc_time tWRPDEN;
sc_time tWRAPDEN;
sc_core::sc_time tBURST16;
sc_core::sc_time tBURST32;
sc_core::sc_time tWTRA;
sc_core::sc_time tWRRDA;
sc_core::sc_time tWRPRE;
sc_core::sc_time tRDAACT;
sc_core::sc_time tWRAACT;
sc_core::sc_time tCCD_L_RTW_slr;
sc_core::sc_time tCCD_S_RTW_slr;
sc_core::sc_time tCCD_RTW_dlr;
sc_core::sc_time tRDRD_dpr;
sc_core::sc_time tRDRD_ddr;
sc_core::sc_time tRDWR_dpr;
sc_core::sc_time tRDWR_ddr;
sc_core::sc_time tCCD_L_WTR_slr;
sc_core::sc_time tCCD_S_WTR_slr;
sc_core::sc_time tCCD_WTR_dlr;
sc_core::sc_time tWRWR_dpr;
sc_core::sc_time tWRWR_ddr;
sc_core::sc_time tWRRD_dpr;
sc_core::sc_time tWRRD_ddr;
sc_core::sc_time tRDPDEN;
sc_core::sc_time tWRPDEN;
sc_core::sc_time tWRAPDEN;
};
#endif // CHECKERDDR5_H

3
DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp
View File

@@ -32,8 +32,11 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerGDDR5.h"
using namespace sc_core;
using namespace tlm;
CheckerGDDR5::CheckerGDDR5()

35
DRAMSys/library/src/controller/checker/CheckerGDDR5.h
View File

@@ -35,9 +35,10 @@
#ifndef CHECKERGDDR5_H
#define CHECKERGDDR5_H
#include "CheckerIF.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecGDDR5.h"
#include "../../configuration/Configuration.h"
@@ -45,33 +46,33 @@ class CheckerGDDR5 final : public CheckerIF
{
public:
CheckerGDDR5();
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecGDDR5 *memSpec;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_time> lastScheduledByCommand;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_time lastCommandOnBus;
sc_core::sc_time lastCommandOnBus;
// 4 and 32 activate window
std::vector<std::queue<sc_time>> last4Activates;
std::vector<std::queue<sc_time>> last32Activates;
std::vector<std::queue<sc_core::sc_time>> last4Activates;
std::vector<std::queue<sc_core::sc_time>> last32Activates;
std::vector<unsigned> bankwiseRefreshCounter;
sc_time tBURST;
sc_time tRDSRE;
sc_time tWRSRE;
sc_time tRDWR_R;
sc_time tWRRD_S;
sc_time tWRRD_L;
sc_time tWRRD_R;
sc_time tWRPRE;
sc_core::sc_time tBURST;
sc_core::sc_time tRDSRE;
sc_core::sc_time tWRSRE;
sc_core::sc_time tRDWR_R;
sc_core::sc_time tWRRD_S;
sc_core::sc_time tWRRD_L;
sc_core::sc_time tWRRD_R;
sc_core::sc_time tWRPRE;
};
#endif // CHECKERGDDR5_H

3
DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp
View File

@@ -32,8 +32,11 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerGDDR5X.h"
using namespace sc_core;
using namespace tlm;
CheckerGDDR5X::CheckerGDDR5X()

35
DRAMSys/library/src/controller/checker/CheckerGDDR5X.h
View File

@@ -35,9 +35,10 @@
#ifndef CHECKERGDDR5X_H
#define CHECKERGDDR5X_H
#include "CheckerIF.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecGDDR5X.h"
#include "../../configuration/Configuration.h"
@@ -45,33 +46,33 @@ class CheckerGDDR5X final : public CheckerIF
{
public:
CheckerGDDR5X();
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecGDDR5X *memSpec;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_time> lastScheduledByCommand;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_time lastCommandOnBus;
sc_core::sc_time lastCommandOnBus;
// 4 and 32 activate window
std::vector<std::queue<sc_time>> last4Activates;
std::vector<std::queue<sc_time>> last32Activates;
std::vector<std::queue<sc_core::sc_time>> last4Activates;
std::vector<std::queue<sc_core::sc_time>> last32Activates;
std::vector<unsigned> bankwiseRefreshCounter;
sc_time tBURST;
sc_time tRDSRE;
sc_time tWRSRE;
sc_time tRDWR_R;
sc_time tWRRD_S;
sc_time tWRRD_L;
sc_time tWRRD_R;
sc_time tWRPRE;
sc_core::sc_time tBURST;
sc_core::sc_time tRDSRE;
sc_core::sc_time tWRSRE;
sc_core::sc_time tRDWR_R;
sc_core::sc_time tWRRD_S;
sc_core::sc_time tWRRD_L;
sc_core::sc_time tWRRD_R;
sc_core::sc_time tWRPRE;
};
#endif // CHECKERGDDR5X_H

3
DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp
View File

@@ -32,8 +32,11 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerGDDR6.h"
using namespace sc_core;
using namespace tlm;
CheckerGDDR6::CheckerGDDR6()

33
DRAMSys/library/src/controller/checker/CheckerGDDR6.h
View File

@@ -35,9 +35,10 @@
#ifndef CHECKERGDDR6_H
#define CHECKERGDDR6_H
#include "CheckerIF.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecGDDR6.h"
#include "../../configuration/Configuration.h"
@@ -45,31 +46,31 @@ class CheckerGDDR6 final : public CheckerIF
{
public:
CheckerGDDR6();
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecGDDR6 *memSpec;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_time> lastScheduledByCommand;
sc_time lastCommandOnBus;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnBus;
// four activate window
std::vector<std::queue<sc_time>> last4Activates;
std::vector<std::queue<sc_core::sc_time>> last4Activates;
std::vector<unsigned> bankwiseRefreshCounter;
sc_time tBURST;
sc_time tRDSRE;
sc_time tWRSRE;
sc_time tRDWR_R;
sc_time tWRRD_S;
sc_time tWRRD_L;
sc_time tWRRD_R;
sc_time tWRPRE;
sc_core::sc_time tBURST;
sc_core::sc_time tRDSRE;
sc_core::sc_time tWRSRE;
sc_core::sc_time tRDWR_R;
sc_core::sc_time tWRRD_S;
sc_core::sc_time tWRRD_L;
sc_core::sc_time tWRRD_R;
sc_core::sc_time tWRPRE;
};
#endif // CHECKERGDDR6_H

3
DRAMSys/library/src/controller/checker/CheckerHBM2.cpp
View File

@@ -32,8 +32,11 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerHBM2.h"
using namespace sc_core;
using namespace tlm;
CheckerHBM2::CheckerHBM2()

39
DRAMSys/library/src/controller/checker/CheckerHBM2.h
View File

@@ -35,9 +35,10 @@
#ifndef CHECKERHBM2_H
#define CHECKERHBM2_H
#include "CheckerIF.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecHBM2.h"
#include "../../configuration/Configuration.h"
@@ -45,34 +46,34 @@ class CheckerHBM2 final : public CheckerIF
{
public:
CheckerHBM2();
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecHBM2 *memSpec;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_time> lastScheduledByCommand;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_time lastCommandOnRasBus;
sc_time lastCommandOnCasBus;
sc_core::sc_time lastCommandOnRasBus;
sc_core::sc_time lastCommandOnCasBus;
// Four activate window
std::vector<std::queue<sc_time>> last4Activates;
std::vector<std::queue<sc_core::sc_time>> last4Activates;
std::vector<unsigned> bankwiseRefreshCounter;
sc_time tBURST;
sc_time tRDPDE;
sc_time tRDSRE;
sc_time tWRPRE;
sc_time tWRPDE;
sc_time tWRAPDE;
sc_time tRTWR;
sc_time tWRRDS;
sc_time tWRRDL;
sc_time tWRRDR;
sc_core::sc_time tBURST;
sc_core::sc_time tRDPDE;
sc_core::sc_time tRDSRE;
sc_core::sc_time tWRPRE;
sc_core::sc_time tWRPDE;
sc_core::sc_time tWRAPDE;
sc_core::sc_time tRTWR;
sc_core::sc_time tWRRDS;
sc_core::sc_time tWRRDL;
sc_core::sc_time tWRRDR;
};
#endif // CHECKERHBM2_H

7
DRAMSys/library/src/controller/checker/CheckerIF.h
View File

@@ -35,18 +35,15 @@
#ifndef CHECKERIF_H
#define CHECKERIF_H
#include <systemc.h>
#include <vector>
#include <systemc>
#include "../Command.h"
#include "../../common/dramExtensions.h"
#include "../../common/DebugManager.h"
class CheckerIF
{
public:
virtual ~CheckerIF() = default;
virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const = 0;
virtual sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const = 0;
virtual void insert(Command command, tlm::tlm_generic_payload *payload) = 0;
};

3
DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp
View File

@@ -32,8 +32,11 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerLPDDR4.h"
using namespace sc_core;
using namespace tlm;
CheckerLPDDR4::CheckerLPDDR4()

49
DRAMSys/library/src/controller/checker/CheckerLPDDR4.h
View File

@@ -35,9 +35,10 @@
#ifndef CHECKERLPDDR4_H
#define CHECKERLPDDR4_H
#include "CheckerIF.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecLPDDR4.h"
#include "../../configuration/Configuration.h"
@@ -45,37 +46,37 @@ class CheckerLPDDR4 final : public CheckerIF
{
public:
CheckerLPDDR4();
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecLPDDR4 *memSpec;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_time> lastScheduledByCommand;
sc_time lastCommandOnBus;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnBus;
// Four activate window
std::vector<std::queue<sc_time>> last4Activates;
std::vector<std::queue<sc_core::sc_time>> last4Activates;
sc_time tBURST;
sc_time tRDWR;
sc_time tRDWR_R;
sc_time tWRRD;
sc_time tWRRD_R;
sc_time tRDPRE;
sc_time tRDAPRE;
sc_time tRDAACT;
sc_time tWRPRE;
sc_time tWRAPRE;
sc_time tWRAACT;
sc_time tACTPDEN;
sc_time tPRPDEN;
sc_time tRDPDEN;
sc_time tWRPDEN;
sc_time tWRAPDEN;
sc_time tREFPDEN;
sc_core::sc_time tBURST;
sc_core::sc_time tRDWR;
sc_core::sc_time tRDWR_R;
sc_core::sc_time tWRRD;
sc_core::sc_time tWRRD_R;
sc_core::sc_time tRDPRE;
sc_core::sc_time tRDAPRE;
sc_core::sc_time tRDAACT;
sc_core::sc_time tWRPRE;
sc_core::sc_time tWRAPRE;
sc_core::sc_time tWRAACT;
sc_core::sc_time tACTPDEN;
sc_core::sc_time tPRPDEN;
sc_core::sc_time tRDPDEN;
sc_core::sc_time tWRPDEN;
sc_core::sc_time tWRAPDEN;
sc_core::sc_time tREFPDEN;
};
#endif // CHECKERLPDDR4_H

3
DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp
View File

@@ -32,8 +32,11 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerSTTMRAM.h"
using namespace sc_core;
using namespace tlm;
CheckerSTTMRAM::CheckerSTTMRAM()

33
DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h
View File

@@ -35,9 +35,10 @@
#ifndef CHECKERSTTMRAM_H
#define CHECKERSTTMRAM_H
#include "CheckerIF.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecSTTMRAM.h"
#include "../../configuration/Configuration.h"
@@ -45,29 +46,29 @@ class CheckerSTTMRAM final : public CheckerIF
{
public:
CheckerSTTMRAM();
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecSTTMRAM *memSpec;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_time> lastScheduledByCommand;
sc_time lastCommandOnBus;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnBus;
// Four activate window
std::vector<std::queue<sc_time>> last4Activates;
std::vector<std::queue<sc_core::sc_time>> last4Activates;
sc_time tBURST;
sc_time tRDWR;
sc_time tRDWR_R;
sc_time tWRRD;
sc_time tWRPRE;
sc_time tWRRD_R;
sc_time tRDPDEN;
sc_time tWRPDEN;
sc_time tWRAPDEN;
sc_core::sc_time tBURST;
sc_core::sc_time tRDWR;
sc_core::sc_time tRDWR_R;
sc_core::sc_time tWRRD;
sc_core::sc_time tWRPRE;
sc_core::sc_time tWRRD_R;
sc_core::sc_time tRDPDEN;
sc_core::sc_time tWRPDEN;
sc_core::sc_time tWRAPDEN;
};
#endif // CHECKERSTTMRAM_H

3
DRAMSys/library/src/controller/checker/CheckerWideIO.cpp
View File

@@ -32,8 +32,11 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerWideIO.h"
using namespace sc_core;
using namespace tlm;
CheckerWideIO::CheckerWideIO()

33
DRAMSys/library/src/controller/checker/CheckerWideIO.h
View File

@@ -35,9 +35,10 @@
#ifndef CHECKERWIDEIO_H
#define CHECKERWIDEIO_H
#include "CheckerIF.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecWideIO.h"
#include "../../configuration/Configuration.h"
@@ -45,29 +46,29 @@ class CheckerWideIO final : public CheckerIF
{
public:
CheckerWideIO();
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecWideIO *memSpec;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_time> lastScheduledByCommand;
sc_time lastCommandOnBus;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnBus;
// Four activate window
std::vector<std::queue<sc_time>> last2Activates;
std::vector<std::queue<sc_core::sc_time>> last2Activates;
sc_time tBURST;
sc_time tRDWR;
sc_time tRDWR_R;
sc_time tWRPRE;
sc_time tWRRD;
sc_time tWRRD_R;
sc_time tRDPDEN;
sc_time tWRPDEN;
sc_time tWRAPDEN;
sc_core::sc_time tBURST;
sc_core::sc_time tRDWR;
sc_core::sc_time tRDWR_R;
sc_core::sc_time tWRPRE;
sc_core::sc_time tWRRD;
sc_core::sc_time tWRRD_R;
sc_core::sc_time tRDPDEN;
sc_core::sc_time tWRPDEN;
sc_core::sc_time tWRAPDEN;
};
#endif // CHECKERWIDEIO_H

3
DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp
View File

@@ -32,8 +32,11 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerWideIO2.h"
using namespace sc_core;
using namespace tlm;
CheckerWideIO2::CheckerWideIO2()

35
DRAMSys/library/src/controller/checker/CheckerWideIO2.h
View File

@@ -35,9 +35,10 @@
#ifndef CHECKERWIDEIO2_H
#define CHECKERWIDEIO2_H
#include "CheckerIF.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecWideIO2.h"
#include "../../configuration/Configuration.h"
@@ -45,30 +46,30 @@ class CheckerWideIO2 final : public CheckerIF
{
public:
CheckerWideIO2();
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecWideIO2 *memSpec;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_time> lastScheduledByCommand;
sc_time lastCommandOnBus;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnBus;
// Four activate window
std::vector<std::queue<sc_time>> last4Activates;
std::vector<std::queue<sc_core::sc_time>> last4Activates;
sc_time tBURST;
sc_time tRDPRE;
sc_time tRDPDEN;
sc_time tRDWR;
sc_time tRDWR_R;
sc_time tWRPRE;
sc_time tWRPDEN;
sc_time tWRAPDEN;
sc_time tWRRD;
sc_time tWRRD_R;
sc_core::sc_time tBURST;
sc_core::sc_time tRDPRE;
sc_core::sc_time tRDPDEN;
sc_core::sc_time tRDWR;
sc_core::sc_time tRDWR_R;
sc_core::sc_time tWRPRE;
sc_core::sc_time tWRPDEN;
sc_core::sc_time tWRAPDEN;
sc_core::sc_time tWRRD;
sc_core::sc_time tWRRD_R;
};
#endif // CHECKERWIDEIO2_H

4
DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h
View File

@@ -35,10 +35,6 @@
#ifndef CMDMUXIF_H
#define CMDMUXIF_H
#include <systemc.h>
#include <tlm.h>
#include <utility>
#include <list>
#include "../Command.h"
class CmdMuxIF

4
DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp
View File

@@ -32,11 +32,11 @@
* Author: Lukas Steiner
*/
#include <systemc>
#include "CmdMuxOldest.h"
#include "../../common/dramExtensions.h"
using namespace tlm;
using namespace sc_core;
CmdMuxOldest::CmdMuxOldest() : memSpec(Configuration::getInstance().memSpec) {}

4
DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp
View File

@@ -32,11 +32,11 @@
* Author: Lukas Steiner
*/
#include <systemc>
#include "CmdMuxStrict.h"
#include "../../common/dramExtensions.h"
using namespace tlm;
using namespace sc_core;
CmdMuxStrict::CmdMuxStrict() : memSpec(Configuration::getInstance().memSpec) {}

2
DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp
View File

@@ -32,8 +32,10 @@
* Author: Lukas Steiner
*/
#include "../Command.h"
#include "PowerDownManagerDummy.h"
using namespace sc_core;
using namespace tlm;
CommandTuple::Type PowerDownManagerDummy::getNextCommand()

2
DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h
View File

@@ -48,7 +48,7 @@ public:
CommandTuple::Type getNextCommand() override;
void updateState(Command) override {}
sc_time start() override;
sc_core::sc_time start() override;
};
#endif // POWERDOWNMANAGERDUMMY_H

6
DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h
View File

@@ -35,9 +35,7 @@
#ifndef POWERDOWNMANAGERIF_H
#define POWERDOWNMANAGERIF_H
#include <utility>
#include <systemc.h>
#include <tlm.h>
#include <systemc>
#include "../Command.h"
class PowerDownManagerIF
@@ -51,7 +49,7 @@ public:
virtual CommandTuple::Type getNextCommand() = 0;
virtual void updateState(Command) = 0;
virtual sc_time start() = 0;
virtual sc_core::sc_time start() = 0;
};
#endif // POWERDOWNMANAGERIF_H

1
DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp
View File

@@ -35,6 +35,7 @@
#include "PowerDownManagerStaggered.h"
#include "../../common/utils.h"
using namespace sc_core;
using namespace tlm;
PowerDownManagerStaggered::PowerDownManagerStaggered(std::vector<BankMachine *> &bankMachinesOnRank,

5
DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h
View File

@@ -35,6 +35,7 @@
#ifndef POWERDOWNMANAGERSTAGGERED_H
#define POWERDOWNMANAGERSTAGGERED_H
#include <systemc>
#include "PowerDownManagerIF.h"
#include "../BankMachine.h"
#include "../checker/CheckerIF.h"
@@ -50,7 +51,7 @@ public:
CommandTuple::Type getNextCommand() override;
void updateState(Command) override;
sc_time start() override;
sc_core::sc_time start() override;
private:
enum class State {Idle, ActivePdn, PrechargePdn, SelfRefresh, ExtraRefresh} state = State::Idle;
@@ -58,7 +59,7 @@ private:
std::vector<BankMachine *> &bankMachinesOnRank;
CheckerIF *checker;
sc_time timeToSchedule = sc_max_time();
sc_core::sc_time timeToSchedule = sc_core::sc_max_time();
Command nextCommand = Command::NOP;
bool controllerIdle = true;

1
DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp
View File

@@ -37,6 +37,7 @@
#include "../../configuration/Configuration.h"
#include "../../common/utils.h"
using namespace sc_core;
using namespace tlm;
RefreshManagerAllBank::RefreshManagerAllBank(std::vector<BankMachine *> &bankMachinesOnRank,

10
DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.h
View File

@@ -35,6 +35,10 @@
#ifndef REFRESHMANAGERALLBANK_H
#define REFRESHMANAGERALLBANK_H
#include <vector>
#include <systemc>
#include <tlm>
#include "RefreshManagerIF.h"
#include "../../configuration/memspec/MemSpec.h"
#include "../BankMachine.h"
@@ -47,7 +51,7 @@ public:
RefreshManagerAllBank(std::vector<BankMachine *> &, PowerDownManagerIF *, Rank, CheckerIF *);
CommandTuple::Type getNextCommand() override;
sc_time start() override;
sc_core::sc_time start() override;
void updateState(Command) override;
private:
@@ -56,8 +60,8 @@ private:
std::vector<BankMachine *> &bankMachinesOnRank;
PowerDownManagerIF *powerDownManager;
tlm::tlm_generic_payload refreshPayload;
sc_time timeForNextTrigger = sc_max_time();
sc_time timeToSchedule = sc_max_time();
sc_core::sc_time timeForNextTrigger = sc_core::sc_max_time();
sc_core::sc_time timeToSchedule = sc_core::sc_max_time();
CheckerIF *checker;
Command nextCommand = Command::NOP;

1
DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp
View File

@@ -34,6 +34,7 @@
#include "RefreshManagerDummy.h"
using namespace sc_core;
using namespace tlm;
CommandTuple::Type RefreshManagerDummy::getNextCommand()

7
DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h
View File

@@ -35,17 +35,14 @@
#ifndef REFRESHMANAGERDUMMY_H
#define REFRESHMANAGERDUMMY_H
#include <systemc.h>
#include <tlm.h>
#include <utility>
#include <systemc>
#include "RefreshManagerIF.h"
#include "../Command.h"
class RefreshManagerDummy final : public RefreshManagerIF
{
public:
CommandTuple::Type getNextCommand() override;
sc_time start() override;
sc_core::sc_time start() override;
void updateState(Command) override {}
};

15
DRAMSys/library/src/controller/refresh/RefreshManagerIF.h
View File

@@ -35,9 +35,9 @@
#ifndef REFRESHMANAGERIF_H
#define REFRESHMANAGERIF_H
#include <systemc.h>
#include <tlm.h>
#include <utility>
#include <cmath>
#include <systemc>
#include "../Command.h"
#include "../../configuration/Configuration.h"
@@ -47,11 +47,12 @@ public:
virtual ~RefreshManagerIF() = default;
virtual CommandTuple::Type getNextCommand() = 0;
virtual sc_time start() = 0;
virtual sc_core::sc_time start() = 0;
virtual void updateState(Command) = 0;
protected:
static sc_time getTimeForFirstTrigger(const sc_time &refreshInterval, Rank rank, unsigned numberOfRanks)
static sc_core::sc_time getTimeForFirstTrigger(const sc_core::sc_time &refreshInterval,
Rank rank, unsigned numberOfRanks)
{
// Calculate bit-reversal rank ID
unsigned rankID = rank.ID();
@@ -72,8 +73,8 @@ protected:
}
// Use bit-reversal order for refreshes on ranks
sc_time timeForFirstTrigger = refreshInterval - reverseRankID * (refreshInterval / numberOfRanks);
sc_time tCK = Configuration::getInstance().memSpec->tCK;
sc_core::sc_time timeForFirstTrigger = refreshInterval - reverseRankID * (refreshInterval / numberOfRanks);
sc_core::sc_time tCK = Configuration::getInstance().memSpec->tCK;
timeForFirstTrigger = std::ceil(timeForFirstTrigger / tCK) * tCK;
return timeForFirstTrigger;

1
DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp
View File

@@ -37,6 +37,7 @@
#include "../../common/utils.h"
#include "../../common/dramExtensions.h"
using namespace sc_core;
using namespace tlm;
RefreshManagerPerBank::RefreshManagerPerBank(std::vector<BankMachine *> &bankMachinesOnRank,

14
DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.h
View File

@@ -35,13 +35,15 @@
#ifndef REFRESHMANAGERPERBANK_H
#define REFRESHMANAGERPERBANK_H
#include <vector>
#include <list>
#include <systemc>
#include <tlm>
#include "RefreshManagerIF.h"
#include "../../configuration/memspec/MemSpec.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
#include <vector>
#include <utility>
#include <list>
class RefreshManagerPerBank final : public RefreshManagerIF
{
@@ -49,7 +51,7 @@ public:
RefreshManagerPerBank(std::vector<BankMachine *> &, PowerDownManagerIF *, Rank, CheckerIF *);
CommandTuple::Type getNextCommand() override;
sc_time start() override;
sc_core::sc_time start() override;
void updateState(Command) override;
private:
@@ -57,8 +59,8 @@ private:
const MemSpec *memSpec;
PowerDownManagerIF *powerDownManager;
std::vector<tlm::tlm_generic_payload> refreshPayloads;
sc_time timeForNextTrigger = sc_max_time();
sc_time timeToSchedule = sc_max_time();
sc_core::sc_time timeForNextTrigger = sc_core::sc_max_time();
sc_core::sc_time timeToSchedule = sc_core::sc_max_time();
CheckerIF *checker;
Command nextCommand = Command::NOP;

1
DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp
View File

@@ -37,6 +37,7 @@
#include "../../common/utils.h"
#include "../../common/dramExtensions.h"
using namespace sc_core;
using namespace tlm;
RefreshManagerSameBank::RefreshManagerSameBank(std::vector<BankMachine *> &bankMachinesOnRank,

14
DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.h
View File

@@ -35,13 +35,15 @@
#ifndef REFRESHMANAGERSAMEBANK_H
#define REFRESHMANAGERSAMEBANK_H
#include <vector>
#include <list>
#include <systemc>
#include <tlm>
#include "RefreshManagerIF.h"
#include "../../configuration/memspec/MemSpec.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
#include <vector>
#include <utility>
#include <list>
class RefreshManagerSameBank final : public RefreshManagerIF
{
@@ -49,7 +51,7 @@ public:
RefreshManagerSameBank(std::vector<BankMachine *> &, PowerDownManagerIF *, Rank, CheckerIF *);
CommandTuple::Type getNextCommand() override;
sc_time start() override;
sc_core::sc_time start() override;
void updateState(Command) override;
private:
@@ -57,8 +59,8 @@ private:
const MemSpec *memSpec;
PowerDownManagerIF *powerDownManager;
std::vector<tlm::tlm_generic_payload> refreshPayloads;
sc_time timeForNextTrigger = sc_max_time();
sc_time timeToSchedule = sc_max_time();
sc_core::sc_time timeForNextTrigger = sc_core::sc_max_time();
sc_core::sc_time timeToSchedule = sc_core::sc_max_time();
CheckerIF *checker;
Command nextCommand = Command::NOP;

1
DRAMSys/library/src/controller/respqueue/RespQueueFifo.cpp
View File

@@ -34,6 +34,7 @@
#include "RespQueueFifo.h"
using namespace sc_core;
using namespace tlm;
void RespQueueFifo::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd)

13
DRAMSys/library/src/controller/respqueue/RespQueueFifo.h
View File

@@ -35,21 +35,22 @@
#ifndef RESPQUEUEFIFO_H
#define RESPQUEUEFIFO_H
#include <systemc.h>
#include <tlm.h>
#include "RespQueueIF.h"
#include <utility>
#include <queue>
#include <systemc>
#include <tlm>
#include "RespQueueIF.h"
class RespQueueFifo final : public RespQueueIF
{
public:
void insertPayload(tlm::tlm_generic_payload *, sc_time) override;
void insertPayload(tlm::tlm_generic_payload *, sc_core::sc_time) override;
tlm::tlm_generic_payload *nextPayload() override;
sc_time getTriggerTime() const override;
sc_core::sc_time getTriggerTime() const override;
private:
std::queue<std::pair<tlm::tlm_generic_payload *, sc_time>> buffer;
std::queue<std::pair<tlm::tlm_generic_payload *, sc_core::sc_time>> buffer;
};
#endif // RESPQUEUEFIFO_H

8
DRAMSys/library/src/controller/respqueue/RespQueueIF.h
View File

@@ -35,15 +35,15 @@
#ifndef RESPQUEUEIF_H
#define RESPQUEUEIF_H
#include <systemc.h>
#include <tlm.h>
#include <systemc>
#include <tlm>
class RespQueueIF
{
public:
virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) = 0;
virtual void insertPayload(tlm::tlm_generic_payload *, sc_core::sc_time) = 0;
virtual tlm::tlm_generic_payload *nextPayload() = 0;
virtual sc_time getTriggerTime() const = 0;
virtual sc_core::sc_time getTriggerTime() const = 0;
virtual ~RespQueueIF() = default;
};

1
DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp
View File

@@ -35,6 +35,7 @@
#include "RespQueueReorder.h"
#include "../../common/dramExtensions.h"
using namespace sc_core;
using namespace tlm;
void RespQueueReorder::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd)

13
DRAMSys/library/src/controller/respqueue/RespQueueReorder.h
View File

@@ -35,21 +35,22 @@
#ifndef RESPQUEUEREORDER_H
#define RESPQUEUEREORDER_H
#include <systemc.h>
#include <tlm.h>
#include "RespQueueIF.h"
#include <map>
#include <systemc>
#include <tlm>
#include "RespQueueIF.h"
class RespQueueReorder final : public RespQueueIF
{
public:
void insertPayload(tlm::tlm_generic_payload *, sc_time) override;
void insertPayload(tlm::tlm_generic_payload *, sc_core::sc_time) override;
tlm::tlm_generic_payload *nextPayload() override;
sc_time getTriggerTime() const override;
sc_core::sc_time getTriggerTime() const override;
private:
uint64_t nextPayloadID = 1;
std::map<uint64_t, std::pair<tlm::tlm_generic_payload *, sc_time>> buffer;
std::map<uint64_t, std::pair<tlm::tlm_generic_payload *, sc_core::sc_time>> buffer;
};
#endif // RESPQUEUEREORDER_H

6
DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.cpp
View File

@@ -35,6 +35,8 @@
#include "BufferCounterBankwise.h"
#include "../../common/dramExtensions.h"
using namespace tlm;
BufferCounterBankwise::BufferCounterBankwise(unsigned requestBufferSize, unsigned numberOfBanks)
: requestBufferSize(requestBufferSize)
{
@@ -46,13 +48,13 @@ bool BufferCounterBankwise::hasBufferSpace() const
return (numRequestsOnBank[lastBankID] < requestBufferSize);
}
void BufferCounterBankwise::storeRequest(tlm::tlm_generic_payload *payload)
void BufferCounterBankwise::storeRequest(tlm_generic_payload *payload)
{
lastBankID = DramExtension::getBank(payload).ID();
numRequestsOnBank[lastBankID]++;
}
void BufferCounterBankwise::removeRequest(tlm::tlm_generic_payload *payload)
void BufferCounterBankwise::removeRequest(tlm_generic_payload *payload)
{
numRequestsOnBank[DramExtension::getBank(payload).ID()]--;
}

1
DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.h
View File

@@ -37,6 +37,7 @@
#include <vector>
#include <tlm>
#include "BufferCounterIF.h"
class BufferCounterBankwise final : public BufferCounterIF

4
DRAMSys/library/src/controller/scheduler/BufferCounterIF.h
View File

@@ -35,7 +35,9 @@
#ifndef BUFFERCOUNTERIF_H
#define BUFFERCOUNTERIF_H
#include <tlm.h>
#include <vector>
#include <tlm>
class BufferCounterIF
{

6
DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.cpp
View File

@@ -34,6 +34,8 @@
#include "BufferCounterReadWrite.h"
using namespace tlm;
BufferCounterReadWrite::BufferCounterReadWrite(unsigned requestBufferSize)
: requestBufferSize(requestBufferSize)
{
@@ -45,7 +47,7 @@ bool BufferCounterReadWrite::hasBufferSpace() const
return (numReadWriteRequests[0] < requestBufferSize && numReadWriteRequests[1] < requestBufferSize);
}
void BufferCounterReadWrite::storeRequest(tlm::tlm_generic_payload *payload)
void BufferCounterReadWrite::storeRequest(tlm_generic_payload *payload)
{
if (payload->is_read())
numReadWriteRequests[0]++;
@@ -53,7 +55,7 @@ void BufferCounterReadWrite::storeRequest(tlm::tlm_generic_payload *payload)
numReadWriteRequests[1]++;
}
void BufferCounterReadWrite::removeRequest(tlm::tlm_generic_payload *payload)
void BufferCounterReadWrite::removeRequest(tlm_generic_payload *payload)
{
if (payload->is_read())
numReadWriteRequests[0]--;

3
DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.h
View File

@@ -35,6 +35,9 @@
#ifndef BUFFERCOUNTERREADWRITE_H
#define BUFFERCOUNTERREADWRITE_H
#include <vector>
#include <tlm>
#include "BufferCounterIF.h"
class BufferCounterReadWrite final : public BufferCounterIF

6
DRAMSys/library/src/controller/scheduler/BufferCounterShared.cpp
View File

@@ -34,6 +34,8 @@
#include "BufferCounterShared.h"
using namespace tlm;
BufferCounterShared::BufferCounterShared(unsigned requestBufferSize)
: requestBufferSize(requestBufferSize)
{
@@ -45,12 +47,12 @@ bool BufferCounterShared::hasBufferSpace() const
return (numRequests[0] < requestBufferSize);
}
void BufferCounterShared::storeRequest(tlm::tlm_generic_payload *)
void BufferCounterShared::storeRequest(tlm_generic_payload *)
{
numRequests[0]++;
}
void BufferCounterShared::removeRequest(tlm::tlm_generic_payload *)
void BufferCounterShared::removeRequest(tlm_generic_payload *)
{
numRequests[0]--;
}

3
DRAMSys/library/src/controller/scheduler/BufferCounterShared.h
View File

@@ -35,6 +35,9 @@
#ifndef BUFFERCOUNTERSHARED_H
#define BUFFERCOUNTERSHARED_H
#include <vector>
#include <tlm>
#include "BufferCounterIF.h"
class BufferCounterShared final : public BufferCounterIF

2
DRAMSys/library/src/controller/scheduler/SchedulerFifo.h
View File

@@ -35,10 +35,10 @@
#ifndef SCHEDULERFIFO_H
#define SCHEDULERFIFO_H
#include <tlm.h>
#include <vector>
#include <deque>
#include <tlm>
#include "SchedulerIF.h"
#include "../../common/dramExtensions.h"
#include "../BankMachine.h"

2
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h
View File

@@ -35,10 +35,10 @@
#ifndef SCHEDULERFRFCFS_H
#define SCHEDULERFRFCFS_H
#include <tlm.h>
#include <vector>
#include <list>
#include <tlm>
#include "SchedulerIF.h"
#include "../../common/dramExtensions.h"
#include "../BankMachine.h"

2
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h
View File

@@ -35,10 +35,10 @@
#ifndef SCHEDULERFRFCFSGRP_H
#define SCHEDULERFRFCFSGRP_H
#include <tlm.h>
#include <vector>
#include <list>
#include <tlm>
#include "SchedulerIF.h"
#include "../../common/dramExtensions.h"
#include "../BankMachine.h"

4
DRAMSys/library/src/controller/scheduler/SchedulerIF.h
View File

@@ -35,10 +35,10 @@
#ifndef SCHEDULERIF_H
#define SCHEDULERIF_H
#include <tlm.h>
#include <vector>
#include <tlm>
#include "../../common/dramExtensions.h"
#include "../../common/DebugManager.h"
class BankMachine;

Some files were not shown because too many files have changed in this diff Show More