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Resolve merge conflicts.

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This commit is contained in:
Lukas Steiner
2020-07-06 17:57:04 +02:00
parent 0e0b80d646
commit bacf0017ba
258 changed files with 4507 additions and 9575 deletions
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3
.gitmodules vendored
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@@ -1,6 +1,3 @@
[submodule "DRAMSys/library/src/common/third_party/tinyxml2"]
path = DRAMSys/library/src/common/third_party/tinyxml2
url = https://github.com/leethomason/tinyxml2.git
[submodule "DRAMSys/library/src/common/third_party/DRAMPower"]
path = DRAMSys/library/src/common/third_party/DRAMPower
url = https://github.com/tukl-msd/DRAMPower.git

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DRAMSys/docs/Timings.ods
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4
DRAMSys/gem5/configs/configs.pri
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@@ -1,4 +0,0 @@
DISTFILES += dualElasticTraceReplay.ini
DISTFILES += nvdimmp.ini
DISTFILES += singleElasticTraceReplay.ini

167
DRAMSys/gem5/gem5.pro
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@@ -1,167 +0,0 @@
TARGET = DRAMSys_gem5
TEMPLATE = app
CONFIG += console
CONFIG -= app_bundle
CONFIG -= qt
# gem5 parameters:
gem5_arch = 'ARM'
gem5_variant = 'opt'
gem5_root = $$(GEM5)
systemc_home = $$(SYSTEMC_HOME)
isEmpty(systemc_home) {
systemc_home = /opt/systemc
}
message(SystemC home is $${systemc_home})
systemc_target_arch = $$(SYSTEMC_TARGET_ARCH)
isEmpty(systemc_target_arch) {
systemc_target_arch = linux64
}
message(SystemC target architecture is $${systemc_target_arch})
unix:!macx {
message(Building on a GNU/Linux)
QMAKE_RPATHDIR += $${systemc_home}/lib-$${systemc_target_arch}
QMAKE_RPATHDIR += $${gem5_root}/build/$${gem5_arch}
message(Linker options QMAKE_RPATHDIR is $${QMAKE_RPATHDIR})
}
DEFINES += TIXML_USE_STL
DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES
DEFINES += DRAMSYS_GEM5
dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK)
isEmpty(dramsys_disable_coverage_check) {
coverage_check = true
message(Coverage check ENABLED)
} else {
coverage_check = false
message(Coverage check DISABLED)
}
unix:!macx {
QMAKE_CXXFLAGS += -std=c++11 -O0 -g
$$eval(coverage_check) {
QMAKE_CXXFLAGS += -fprofile-arcs -ftest-coverage -fPIC -O0
QMAKE_LFLAGS += -lgcov --coverage
}
}
macx: {
CONFIG += c++11
QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ -O0 -g
$$eval(coverage_check) {
QMAKE_CXXFLAGS += --coverage
QMAKE_LFLAGS += --coverage
}
}
INCLUDEPATH += ../library/src/simulation/
INCLUDEPATH += $${systemc_home}/include
INCLUDEPATH += ../library/src/common/third_party/DRAMPower/src
INCLUDEPATH += ../library/src/common/third_party/DRAMPower/src/libdrampower
INCLUDEPATH += $${gem5_root}/build/$${gem5_arch}/
INCLUDEPATH += $${gem5_root}/util/tlm/examples/slave_port
INCLUDEPATH += $${gem5_root}/util/tlm/examples/common
INCLUDEPATH += $${gem5_root}/util/tlm/src/
INCLUDEPATH += $${gem5_root}/util/systemc
LIBS += -L$${systemc_home}/lib-$${systemc_target_arch} -lsystemc
LIBS += ../library/libDRAMSys.a
LIBS += ../../DRAMSys/library/src/common/third_party/DRAMPower/src/libdrampower.a
LIBS += -lsqlite3
LIBS += -L$${gem5_root}/build/$${gem5_arch} -lgem5_$${gem5_variant}
SOURCES += $${gem5_root}/util/systemc/sc_gem5_control.cc
SOURCES += $${gem5_root}/util/systemc/sc_logger.cc
SOURCES += $${gem5_root}/util/systemc/sc_module.cc
SOURCES += $${gem5_root}/util/systemc/stats.cc
SOURCES += $${gem5_root}/util/tlm/examples/common/cli_parser.cc
SOURCES += $${gem5_root}/util/tlm/examples/common/report_handler.cc
SOURCES += $${gem5_root}/util/tlm/src/master_transactor.cc
SOURCES += $${gem5_root}/util/tlm/src/sc_master_port.cc
SOURCES += $${gem5_root}/util/tlm/src/sc_slave_port.cc
SOURCES += $${gem5_root}/util/tlm/src/slave_transactor.cc
SOURCES += $${gem5_root}/util/tlm/src/sc_ext.cc
SOURCES += $${gem5_root}/util/tlm/src/sc_mm.cc
SOURCES += $${gem5_root}/util/tlm/src/sim_control.cc
SOURCES += main.cpp
DISTFILES += ../DRAMSys.astylerc
DISTFILES += etrace_single/config.ini
DISTFILES += etrace_single_L2/HPCG-47MB/config.ini
DISTFILES += etrace_single_L2/Pathfinder/config.ini
DISTFILES += etrace_single_L2/hpcc-linpack/config.ini
DISTFILES += etrace_single_L2/hpcc-fft/config.ini
DISTFILES += etrace_single_L2/config.ini
DISTFILES += etrace_single_L2/hpcc-dgemm/config.ini
DISTFILES += etrace_single_L2/hpcc-gups/config.ini
DISTFILES += configs/singleElasticTraceReplayWithL2.ini
DISTFILES += configs/nvdimmp.ini
DISTFILES += configs/hello.ini
DISTFILES += configs/dualElasticTraceReplay.ini
DISTFILES += configs/singleElasticTraceReplay.ini
DISTFILES += configs/boot_linux.ini
DISTFILES += gem5_fs/stream/config.ini
DISTFILES += gem5_fs/stream/stream_1_cores.rcS
DISTFILES += gem5_fs/parsec/simmedium/fluidanimate/fluidanimate_simmedium_2.rcS
DISTFILES += gem5_fs/parsec/simmedium/fluidanimate/config.ini
DISTFILES += gem5_fs/parsec/simmedium/ferret/config.ini
DISTFILES += gem5_fs/parsec/simmedium/ferret/ferret_simmedium_2.rcS
DISTFILES += gem5_fs/parsec/simmedium/blackscholes/blackscholes_simmedium_2.rcS
DISTFILES += gem5_fs/parsec/simmedium/blackscholes/config.ini
DISTFILES += gem5_fs/parsec/simlarge/streamcluster/config.ini
DISTFILES += gem5_fs/parsec/simlarge/streamcluster/streamcluster_simlarge_2.rcS
DISTFILES += gem5_fs/parsec/simsmall/fluidanimate/fluidanimate_simsmall_2.rcS
DISTFILES += gem5_fs/parsec/simsmall/fluidanimate/config.ini
DISTFILES += gem5_fs/parsec/simsmall/bodytrack/bodytrack_simsmall_2.rcS
DISTFILES += gem5_fs/parsec/simsmall/bodytrack/config.ini
DISTFILES += gem5_fs/parsec/simsmall/ferret/config.ini
DISTFILES += gem5_fs/parsec/simsmall/ferret/ferret_simsmall_2.rcS
DISTFILES += gem5_fs/parsec/simsmall/blackscholes/config.ini
DISTFILES += gem5_fs/parsec/simsmall/blackscholes/blackscholes_simsmall_2.rcS
DISTFILES += gem5_fs/parsec/simdev/fluidanimate/config.ini
DISTFILES += gem5_fs/parsec/simdev/fluidanimate/fluidanimate_simdev_2.rcS
DISTFILES += gem5_fs/parsec/simdev/blackscholes/blackscholes_simdev_2.rcS
DISTFILES += gem5_fs/parsec/simdev/blackscholes/config.ini
DISTFILES += examples/tlm_elastic_slave.py
DISTFILES += examples/tlm_elastic_slave_mc_direct.py
DISTFILES += examples/tlm_elastic_slave_with_l2.py
DISTFILES += gem5_se/almabench/config.ini
DISTFILES += gem5_se/fldry/config.ini
DISTFILES += gem5_se/Queens/config.ini
DISTFILES += gem5_se/chomp/config.ini
DISTFILES += gem5_se/l1_cache/Queens/config.ini
DISTFILES += gem5_se/l1_cache/chomp/config.ini
DISTFILES += gem5_se/l1_cache/Puzzle/config.ini
DISTFILES += gem5_se/l1_cache/RealMM/config.ini
DISTFILES += gem5_se/l1_cache/Perm/config.ini
DISTFILES += gem5_se/l1_cache/Treesort/config.ini
DISTFILES += gem5_se/l1_cache/Bubblesort/config.ini
DISTFILES += gem5_se/l1_cache/misr/config.ini
DISTFILES += gem5_se/l1_cache/exptree/config.ini
DISTFILES += gem5_se/l1_cache/Quicksort/config.ini
DISTFILES += gem5_se/l1_cache/IntMM/config.ini
DISTFILES += gem5_se/l1_cache/Oscar/config.ini
DISTFILES += gem5_se/l1_cache/FloatMM/config.ini
DISTFILES += gem5_se/l1_cache/Towers/config.ini
DISTFILES += gem5_se/run.sh
DISTFILES += gem5_se/Puzzle/config.ini
DISTFILES += gem5_se/RealMM/config.ini
DISTFILES += gem5_se/Perm/config.ini
DISTFILES += gem5_se/Treesort/config.ini
DISTFILES += gem5_se/Bubblesort/config.ini
DISTFILES += gem5_se/misr/config.ini
DISTFILES += gem5_se/lpbench/config.ini
DISTFILES += gem5_se/8_cores/config.ini
DISTFILES += gem5_se/exptree/config.ini
DISTFILES += gem5_se/Quicksort/config.ini
DISTFILES += gem5_se/IntMM/config.ini
DISTFILES += gem5_se/Oscar/config.ini
DISTFILES += gem5_se/FloatMM/config.ini
DISTFILES += gem5_se/Towers/config.ini

71
DRAMSys/gem5/main.cpp
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@@ -41,24 +41,29 @@
#include <string>
#include <cstdlib>
#include "DRAMSys.h"
#include "TraceSetup.h"
#include "report_handler.hh"
#include "sc_target.hh"
#include "sim_control.hh"
#include "slave_transactor.hh"
#include "stats.hh"
using namespace std;
#include "DRAMSys.h"
class Gem5SimControlDRAMsys: public Gem5SystemC::Gem5SimControl
#ifdef RECORDING
#include "DRAMSysRecordable.h"
#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
using json = nlohmann::json;
#endif
using namespace tlm;
class Gem5SimControlDRAMsys : public Gem5SystemC::Gem5SimControl
{
public:
Gem5SimControlDRAMsys(string configFile) :
Gem5SimControlDRAMsys(std::string configFile) :
Gem5SystemC::Gem5SimControl("gem5", configFile, 0, "MemoryAccess")
{
}
{}
void afterSimulate()
{
@@ -67,7 +72,8 @@ public:
};
struct AddressOffset: sc_module {
class AddressOffset : sc_module
{
private:
unsigned long long int offset;
@@ -85,7 +91,7 @@ public:
}
//Forward Interface
tlm::tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase,
tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase,
sc_time &delay)
{
//std::cout << "NB "<< this->name() <<": " << trans.get_address() << " -" << offset;
@@ -94,7 +100,7 @@ public:
return i_socket->nb_transport_fw(trans, phase, delay);
}
unsigned int transport_dbg(tlm::tlm_generic_payload &trans)
unsigned int transport_dbg(tlm_generic_payload &trans)
{
// adjust address offset:
//std::cout << "Debug "<< this->name() <<": " << trans.get_address() << " -" << offset;
@@ -103,7 +109,7 @@ public:
return i_socket->transport_dbg(trans);
}
void b_transport(tlm::tlm_generic_payload &trans, sc_time &delay)
void b_transport(tlm_generic_payload &trans, sc_time &delay)
{
// adjust address offset:
//std::cout << "B "<< this->name() <<": " << trans.get_address() << " -" << offset;
@@ -113,7 +119,7 @@ public:
}
//Backward Interface
tlm::tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase,
tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase,
sc_time &delay)
{
//trans.set_address(trans.get_address()+offset);
@@ -122,7 +128,7 @@ public:
};
string pathOfFile(string file)
std::string pathOfFile(std::string file)
{
return file.substr(0, file.find_last_of('/'));
}
@@ -131,9 +137,9 @@ int sc_main(int argc, char **argv)
{
SC_REPORT_INFO("sc_main", "Simulation Setup");
string SimulationXML;
string gem5ConfigFile;
string resources;
std::string simulationJson;
std::string gem5ConfigFile;
std::string resources;
unsigned int numTransactors;
Gem5SystemC::Gem5SlaveTransactor *t;
std::vector<Gem5SystemC::Gem5SlaveTransactor *> transactors;
@@ -141,18 +147,28 @@ int sc_main(int argc, char **argv)
if (argc == 4) {
// Get path of resources:
resources = pathOfFile(argv[0])
+ string("/../../DRAMSys/library/resources/");
+ std::string("/../../DRAMSys/library/resources/");
SimulationXML = argv[1];
simulationJson = argv[1];
gem5ConfigFile = argv[2];
numTransactors = atoi(argv[3]);
numTransactors = std::stoul(argv[3]);
} else {
SC_REPORT_FATAL("sc_main", "Please provide configuration files and number of ports");
}
// Instantiate DRAMSys:
DRAMSys dramSys("DRAMSys", SimulationXML, resources);
DRAMSys *dramSys;
#ifdef RECORDING
json simulationdoc = parseJSON(simulationJson);
json simulatordoc = parseJSON(resources + "configs/simulator/"
+ std::string(simulationdoc["simulation"]["simconfig"]));
if (simulatordoc["simconfig"]["DatabaseRecording"])
dramSys = new DRAMSysRecordable("DRAMSys", simulationJson, resources);
else
#endif
dramSys = new DRAMSys("DRAMSys", simulationJson, resources);
// Instantiate gem5:
Gem5SimControlDRAMsys sim_control(gem5ConfigFile);
@@ -163,7 +179,7 @@ int sc_main(int argc, char **argv)
// Names generated here must match port names used by the gem5 config file, e.g., config.ini
if (numTransactors == 1) {
t = new Gem5SystemC::Gem5SlaveTransactor("transactor", "transactor");
t->socket.bind(dramSys.tSocket);
t->socket.bind(dramSys->tSocket);
t->sim_control.bind(sim_control);
transactors.push_back(t);
} else {
@@ -173,7 +189,7 @@ int sc_main(int argc, char **argv)
std::string name = "transactor" + std::to_string(index);
std::string portName = "transactor" + std::to_string(index);
t = new Gem5SystemC::Gem5SlaveTransactor(name.c_str(), portName.c_str());
t->socket.bind(dramSys.tSocket);
t->socket.bind(dramSys->tSocket);
t->sim_control.bind(sim_control);
transactors.push_back(t);
}
@@ -189,9 +205,9 @@ int sc_main(int argc, char **argv)
AddressOffset dramOffset("dramOffset", (2147483648 - 67108863)); //+67108863);
dramInterface.socket.bind(dramOffset.t_socket);
dramOffset.i_socket.bind(dramSys.tSocket); // ID0
dramOffset.i_socket.bind(dramSys->tSocket); // ID0
nvmInterface.socket.bind(nvmOffset.t_socket);
nvmOffset.i_socket.bind(dramSys.tSocket);
nvmOffset.i_socket.bind(dramSys->tSocket);
dramInterface.sim_control.bind(sim_control);
nvmInterface.sim_control.bind(sim_control);
@@ -207,9 +223,10 @@ int sc_main(int argc, char **argv)
sc_core::sc_stop();
}
for (auto t : transactors) {
for (auto t : transactors)
delete t;
}
delete dramSys;
SC_REPORT_INFO("sc_main", "End of Simulation");

6
DRAMSys/library/resources/configs/amconfigs/am_ddr3.xml
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@@ -1,6 +0,0 @@
<addressmapping>
<bank from="27" to="29" />
<row from="13" to="26" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

21
DRAMSys/library/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml
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@@ -1,21 +0,0 @@
<!--
DDR3-SDRAM 1Gbit x8 (single device, e.g. Micron MT41J128M8) with Page Size: 1KB
Addressing:
Row addressing: 16K (A[13:0]) -> 14 bits
Bank addressing: 8 (BA[2:0]) -> 3 bits
Column addressing: 1K (A[9:0] -> 10 bits
2 2 2 | 2 2 2 2 1 1 1 1 1 1 1 1 1 1 |
6 5 4 | 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | 9 8 7 6 5 4 3 2 1 0 |
B B B | R R R R R R R R R R R R R R | C C C C C C C C C C |
-->
<addressmapping>
<bank from="24" to="26" />
<row from="10" to="23" />
<column from="0" to="9" />
</addressmapping>

43
DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
28,
29,
30
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

34
DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml
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@@ -1,34 +0,0 @@
<!--
DDR3L Unbuffered SODIMM Information:
Part Number: M471B5674QH0-YH9/K0
Density: 2GB
Organization: 256Mx64
Component Composition: 256Mx16(K4B4G1646Q-HY##)*4
Number of Rank: 1
Device mounted: K4B4G1646Q-HYK0
Original fck is 800 MHz (DDR3-1600). Adapted to fck 533 MHz (DDR-1066).
Deepak provided most of the timing and current values. For the ones not provided datasheet values were used.
2GB x64 DIMM with: 4 * 4Gb x16 devices (K4B4G1646Q-HYK0) with Page Size: 2KB
DIMM Characteristics:
Byte Offset (Y): 8 [0:2] (8-byte-wide memory module, i.e., 64-bit-wide data bus) -> 3 bit
Cols (C): 1K [3:12] (A0 - A9) -> 10 bit
Rows (R): 32K [13:27] (A0 - A14) -> 15 bit
Bank (B): 8 [28:30] (BA0 - BA2) -> 3 bit
3 2 2 | 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
0 9 8 | 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
B B B | R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<bank from="28" to="30" />
<row from="13" to="27" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

43
DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

34
DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml
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@@ -1,34 +0,0 @@
<!--
DDR3L Unbuffered SODIMM Information:
Part Number: M471B5674QH0-YH9/K0
Density: 2GB
Organization: 256Mx64
Component Composition: 256Mx16(K4B4G1646Q-HY##)*4
Number of Rank: 1
Device mounted: K4B4G1646Q-HYK0
Original fck is 800 MHz (DDR3-1600). Adapted to fck 533 MHz (DDR-1066).
Deepak provided most of the timing and current values. For the ones not provided datasheet values were used.
2GB x64 DIMM with: 4 * 4Gb x16 devices (K4B4G1646Q-HYK0) with Page Size: 2KB
DIMM Characteristics:
Byte Offset (Y): 8 [0:2] (8-byte-wide memory module, i.e., 64-bit-wide data bus) -> 3 bit
Cols (C): 1K [3:12] (A0 - A9) -> 10 bit
Bank (B): 8 [13:15] (BA0 - BA2) -> 3 bit
Rows (R): 32K [16:30] (A0 - A14) -> 15 bit
3 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1 | 1 1 1
0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 | 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
R R R R R R R R R R R R R R R | B B B | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<row from="16" to="30" />
<bank from="13" to="15" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

42
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json Normal file
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@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

24
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml
View File

@@ -1,24 +0,0 @@
<!--
DDR3 Example:
1GB x64 DIMM with: 8 * 1 Gb x8 Devices (e.g. Micron MT41J128M8) with Page Size: 1KB
Device Characteristics:
Rows: 16 K [13:0] -> 14 bit
Bank: 8 [2:0] -> 3 bit
Cols: 1 K [9:0] -> 10 bit
Due to the DIMM we have a Byte Offset Y
2 2 2 | 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
9 8 7 | 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<bank from="27" to="29" />
<row from="13" to="26" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

42
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

24
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml
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@@ -1,24 +0,0 @@
<!--
DDR3 Example:
1GB x64 DIMM with: 8 * 1 Gb x8 Devices (e.g. Micron MT41J128M8) with Page Size: 1KB
Device Characteristics:
Rows: 16 K [13:0] -> 14 bit
Bank: 8 [2:0] -> 3 bit
Cols: 1 K [9:0] -> 10 bit
Due to the DIMM we have a Byte Offset Y
2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1 | 1 1 1
9 8 7 6 5 4 3 2 1 0 9 8 7 6 | 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
R R R R R R R R R R R R R R | B B B | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<row from="16" to="29" />
<bank from="13" to="15" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

43
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
28,
29,
30
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

24
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.xml
View File

@@ -1,24 +0,0 @@
<!--
DDR3 Example:
2GB x64 DIMM with: 8 * 2 Gb x8 Devices (e.g. Micron MT41J256M8) with Page Size: 1KB
Device Characteristics:
Rows: 32 K [14:0] -> 15 bit
Bank: 8 [2:0] -> 3 bit
Cols: 1 K [9:0] -> 10 bit
Due to the DIMM we have a Byte Offset Y
3 2 2 | 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
0 9 8 | 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
B B B | R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<bank from="28" to="30" />
<row from="13" to="27" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

43
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

24
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.xml
View File

@@ -1,24 +0,0 @@
<!--
DDR3 Example:
2GB x64 DIMM with: 8 * 2 Gb x8 Devices (e.g. Micron MT41J256M8) with Page Size: 1KB
Device Characteristics:
Rows: 32 K [14:0] -> 15 bit
Bank: 8 [2:0] -> 3 bit
Cols: 1 K [9:0] -> 10 bit
Due to the DIMM we have a Byte Offset Y
3 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1 | 1 1 1
0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 | 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
R R R R R R R R R R R R R R R | B B B | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<row from="16" to="30" />
<bank from="13" to="15" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

41
DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.json Normal file
View File

@@ -0,0 +1,41 @@
{
"CONGEN": {
"BANK_BIT": [
26,
27,
28
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<bank from="26" to="28" />
<row from="13" to="25" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

41
DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.json Normal file
View File

@@ -0,0 +1,41 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<row from="16" to="28" />
<bank from="13" to="15" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

16
DRAMSys/library/resources/configs/amconfigs/am_ddr4.xml
View File

@@ -1,16 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!-- highest bank parallelism - high hits -->
<dramconfig>
<addressmap length="32">
<row from="19" to="31" />
<column from="9" to="18" />
<bank from="5" to="8" />
</addressmap>
</dramconfig>

46
DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json Normal file
View File

@@ -0,0 +1,46 @@
{
"CONGEN": {
"BANKGROUP_BIT":[
28,
29
],
"BANK_BIT": [
30,
31
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<bankgroup from="30" to="31" />
<bank from="28" to="29" />
<row from="13" to="27" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

46
DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json Normal file
View File

@@ -0,0 +1,46 @@
{
"CONGEN": {
"RANK_BIT":[
29
],
"BANKGROUP_BIT":[
27,
28
],
"BANK_BIT": [
25,
26
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9
],
"ROW_BIT": [
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

9
DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.xml
View File

@@ -1,9 +0,0 @@
<addressmapping>
<!--channel from="30" to="32" /-->
<rank from="29" to="29" /> <!-- 2 pseudo channels -->
<bankgroup from="27" to="28" />
<bank from="25" to="26" />
<row from="10" to="24" />
<column from="3" to="9" />
<bytes from="0" to="2" />
</addressmapping>

9
DRAMSys/library/resources/configs/amconfigs/am_highHits.xml
View File

@@ -1,9 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!-- should have highest hit rate, since a (row, bank) bank pair changes infrequently -->
<dramconfig>
<addressmap length="32">
<row from="19" to="31" />
<bank from="15" to="18" />
<column from="5" to="14" />
</addressmap>
</dramconfig>

10
DRAMSys/library/resources/configs/amconfigs/am_highPara.xml
View File

@@ -1,10 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!-- should have high bank parallelism with good row hit rate, since bank bits have the
highest entropy and row bits the lowest -->
<dramconfig>
<addressmap length="32">
<row from="19" to="31" />
<column from="9" to="18" />
<bank from="5" to="8" />
</addressmap>
</dramconfig>

10
DRAMSys/library/resources/configs/amconfigs/am_lowHits.xml
View File

@@ -1,10 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!-- should have high bank parallelism with a low hit rate -->
<dramconfig>
<addressmap length="32">
<column from="24" to="31" />
<row from="9" to="23" />
<bank from="5" to="8" />
</addressmap>
</dramconfig>

12
DRAMSys/library/resources/configs/amconfigs/am_lowPara.xml
View File

@@ -1,12 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!-- should have low bank parallelism and a high hit rate -->
<dramconfig>
<addressmap length="32">
<bank from="30" to="31" />
<row from="15" to="29" />
<column from="5" to="14" />
</addressmap>
</dramconfig>

42
DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

6
DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.xml
View File

@@ -1,6 +0,0 @@
<addressmapping>
<bank from="27" to="29" />
<row from="11" to="26" />
<column from="1" to="10" />
<bytes from="0" to="0" />
</addressmapping>

6
DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_rbc.xml
View File

@@ -1,6 +0,0 @@
<addressmapping>
<row from="14" to="29" />
<bank from="11" to="13" />
<column from="1" to="10" />
<bytes from="0" to="0" />
</addressmapping>

46
DRAMSys/library/resources/configs/amconfigs/am_ranktest.json Normal file
View File

@@ -0,0 +1,46 @@
{
"CONGEN": {
"RANK_BIT":[
30,
31
],
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

25
DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml
View File

@@ -1,25 +0,0 @@
<!--
DDR3 Example:
1GB x64 DIMM with: 8 * 1 Gb x8 Devices (e.g. Micron MT41J128M8) with Page Size: 1KB
Device Characteristics:
Rows: 16 K [13:0] -> 14 bit
Bank: 8 [2:0] -> 3 bit
Cols: 1 K [9:0] -> 10 bit
Due to the DIMM we have a Byte Offset Y
2 2 2 | 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
9 8 7 | 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<rank from="30" to="31" />
<bank from="27" to="29" />
<row from="13" to="26" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

22
DRAMSys/library/resources/configs/amconfigs/am_wideio.xml
View File

@@ -1,22 +0,0 @@
<!-- Row Bank Column -->
<addressmapping>
<channel from="27" to="28" />
<row from="14" to="26" />
<bank from="11" to="13" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>
<!-- Bank Row Column -->
<!--
<addressmapping>
<channel from="27" to="28" />
<bank from="24" to="26" />
<row from="11" to="23" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>
-->

44
DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json Normal file
View File

@@ -0,0 +1,44 @@
{
"CONGEN": {
"BANK_BIT": [
25,
26,
27
],
"BYTE_BIT": [
0,
1,
2
],
"CHANNEL_BIT": [
28,
29
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"ROW_BIT": [
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

11
DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml
View File

@@ -1,11 +0,0 @@
<!-- Bank Row Column -->
<addressmapping>
<channel from="28" to="29" />
<bank from="25" to="27" />
<row from="12" to="24" />
<column from="3" to="11" />
<bytes from="0" to="2" />
</addressmapping>
<!-- Bank Row Column -->

44
DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json Normal file
View File

@@ -0,0 +1,44 @@
{
"CONGEN": {
"BANK_BIT": [
12,
13,
14
],
"BYTE_BIT": [
0,
1,
2
],
"CHANNEL_BIT": [
28,
29
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

11
DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml
View File

@@ -1,11 +0,0 @@
<!-- Row Bank Column -->
<addressmapping>
<channel from="28" to="29" />
<row from="15" to="27" />
<bank from="12" to="14" />
<column from="3" to="11" />
<bytes from="0" to="2" />
</addressmapping>
<!-- Bank Row Column -->

27
DRAMSys/library/resources/configs/amconfigs/am_wideioFourBanks.xml
View File

@@ -1,27 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!--
<dramconfig>
<addressmap length="29">
<channel from="27" to="28" />
<bank from="24" to="26" />
<row from="11" to="23" />
<colum from="4" to="10" />
<bytes from="0" to="3" />
</addressmap>
</dramconfig>
-->
<dramconfig>
<addressmap length="29">
<channel from="27" to="28" />
<row from="13" to="26" />
<bank from="11" to="12" />
<column from="4" to="10" />
<bytes from="0" to="3" />
<!-- <channel from="27" to="28" />
<row from="14" to="26" />
<bytes from="10" to="13" />
<colum from="3" to="9" />
<bank from="0" to="2" /> -->
</addressmap>
</dramconfig>

43
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
25,
26
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
27,
28
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="27" to="28" />
<bank from="25" to="26" />
<row from="11" to="24" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

43
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
27,
28
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="27" to="28" />
<row from="13" to="26" />
<bank from="11" to="12" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

41
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.json Normal file
View File

@@ -0,0 +1,41 @@
{
"CONGEN": {
"BANK_BIT": [
23,
24
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
25,
26
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="25" to="26" />
<bank from="23" to="24" />
<row from="11" to="22" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

41
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json Normal file
View File

@@ -0,0 +1,41 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
25,
26
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="25" to="26" />
<row from="13" to="24" />
<bank from="11" to="12" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

44
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.json Normal file
View File

@@ -0,0 +1,44 @@
{
"CONGEN": {
"BANK_BIT": [
26,
27
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
28,
29
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="28" to="29" />
<bank from="26" to="27" />
<row from="11" to="25" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

44
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json Normal file
View File

@@ -0,0 +1,44 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
28,
29
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="28" to="29" />
<row from="13" to="27" />
<bank from="11" to="12" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

45
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.json Normal file
View File

@@ -0,0 +1,45 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
29,
30
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10,
11
],
"ROW_BIT": [
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="29" to="30" />
<bank from="27" to="28" />
<row from="12" to="26" />
<column from="4" to="11" />
<bytes from="0" to="3" />
</addressmapping>

45
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json Normal file
View File

@@ -0,0 +1,45 @@
{
"CONGEN": {
"BANK_BIT": [
12,
13
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
29,
30
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10,
11
],
"ROW_BIT": [
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="29" to="30" />
<row from="14" to="28" />
<bank from="12" to="13" />
<column from="4" to="11" />
<bytes from="0" to="3" />
</addressmapping>

42
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
24,
25
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
26,
27
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="26" to="27" />
<bank from="24" to="25" />
<row from="11" to="23" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

42
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
26,
27
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="26" to="27" />
<row from="13" to="25" />
<bank from="11" to="12" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

36
DRAMSys/library/resources/configs/amconfigs/congen_extended.xml
View File

@@ -1,36 +0,0 @@
<?xml version="1.0" ?>
<CONGEN>
<SOLUTION ID="0">
<XOR FIRST="13" SECOND="16"/>
<BYTE_BIT>0</BYTE_BIT>
<BYTE_BIT>1</BYTE_BIT>
<BYTE_BIT>2</BYTE_BIT>
<COLUMN_BIT>3</COLUMN_BIT>
<COLUMN_BIT>4</COLUMN_BIT>
<COLUMN_BIT>5</COLUMN_BIT>
<COLUMN_BIT>6</COLUMN_BIT>
<COLUMN_BIT>7</COLUMN_BIT>
<COLUMN_BIT>8</COLUMN_BIT>
<COLUMN_BIT>9</COLUMN_BIT>
<COLUMN_BIT>10</COLUMN_BIT>
<COLUMN_BIT>11</COLUMN_BIT>
<COLUMN_BIT>12</COLUMN_BIT>
<BANK_BIT>13</BANK_BIT>
<BANK_BIT>14</BANK_BIT>
<BANK_BIT>15</BANK_BIT>
<ROW_BIT>16</ROW_BIT>
<ROW_BIT>17</ROW_BIT>
<ROW_BIT>18</ROW_BIT>
<ROW_BIT>19</ROW_BIT>
<ROW_BIT>20</ROW_BIT>
<ROW_BIT>21</ROW_BIT>
<ROW_BIT>22</ROW_BIT>
<ROW_BIT>23</ROW_BIT>
<ROW_BIT>24</ROW_BIT>
<ROW_BIT>25</ROW_BIT>
<ROW_BIT>26</ROW_BIT>
<ROW_BIT>27</ROW_BIT>
<ROW_BIT>28</ROW_BIT>
<ROW_BIT>29</ROW_BIT>
</SOLUTION>
</CONGEN>

19
DRAMSys/library/resources/configs/amconfigs/orgr_ddr4_4x16Gbx16_dimm_p2KB_brc.xml
View File

@@ -1,19 +0,0 @@
<!--
DIMM Characteristics:
Bank (B): 8 [30:32] (BA0 - BA2) -> 3 bit
Rows (R): 128K [13:29] (A0 - A16) -> 17 bit
Cols (C): 1K [3:12] (A0 - A9) -> 10 bit
Byte Offset (Y): 8 [0:2] (8-byte-wide memory module, i.e., 64-bit-wide data bus) -> 3 bit
3 3 3 | 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
2 1 0 | 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
B B B | R R R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<bank from="30" to="32" />
<row from="13" to="29" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

7
DRAMSys/library/resources/configs/amconfigs/rgram-rbc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<row from="16" to="32" />
<bank from="13" to="15" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

7
DRAMSys/library/resources/configs/amconfigs/rgram.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<bank from="30" to="32" />
<row from="13" to="29" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

20
DRAMSys/library/resources/configs/mcconfigs/fifo.xml
View File

@@ -1,20 +0,0 @@
<mcconfig>
<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
<PagePolicy value="Open" />
<!-- Fifo, FrFcfs, FrFcfsGrp -->
<Scheduler value="Fifo" />
<RequestBufferSize value="8" />
<!-- Oldest, Strict -->
<CmdMux value="Strict" />
<!-- Fifo, Reorder -->
<RespQueue value="Fifo" />
<!-- NoRefresh, Rankwise, Bankwise -->
<RefreshPolicy value="Rankwise" />
<!-- 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<RefreshMode value="1" />
<RefreshMaxPostponed value="8"/>
<RefreshMaxPulledin value="8"/>
<!-- NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownPolicy value="NoPowerDown" />
<PowerDownTimeout value="100" />
</mcconfig>

20
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml
View File

@@ -1,20 +0,0 @@
<mcconfig>
<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
<PagePolicy value="Open" />
<!-- Fifo, FrFcfs, FrFcfsGrp -->
<Scheduler value="FrFcfs" />
<RequestBufferSize value="8" />
<!-- Oldest, Strict -->
<CmdMux value="Oldest" />
<!-- Fifo, Reorder -->
<RespQueue value="Fifo" />
<!-- NoRefresh, Rankwise, Bankwise -->
<RefreshPolicy value="Rankwise" />
<!-- 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<RefreshMode value="1" />
<RefreshMaxPostponed value="8"/>
<RefreshMaxPulledin value="8"/>
<!-- NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownPolicy value="NoPowerDown" />
<PowerDownTimeout value="100" />
</mcconfig>

20
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml
View File

@@ -1,20 +0,0 @@
<mcconfig>
<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
<PagePolicy value="Open" />
<!-- Fifo, FrFcfs, FrFcfsGrp -->
<Scheduler value="FrFcfsGrp" />
<RequestBufferSize value="8" />
<!-- Oldest, Strict -->
<CmdMux value="Oldest" />
<!-- Fifo, Reorder -->
<RespQueue value="Fifo" />
<!-- NoRefresh, Rankwise, Bankwise -->
<RefreshPolicy value="Rankwise" />
<!-- 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<RefreshMode value="1" />
<RefreshMaxPostponed value="8"/>
<RefreshMaxPulledin value="8"/>
<!-- NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownPolicy value="NoPowerDown" />
<PowerDownTimeout value="100" />
</mcconfig>

61
DRAMSys/library/resources/configs/memspecs/DDR4.xml
View File

@@ -1,61 +0,0 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="MICRON_4Gb_DDR4-2400_8bit_A" />
<parameter id="memoryType" type="string" value="DDR4" />
<memarchitecturespec>
<parameter id="width" type="uint" value="8" />
<parameter id="nbrOfBankGroups" type="uint" value="4" />
<parameter id="nbrOfBanks" type="uint" value="16" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="32768" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="8" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="1200" />
<parameter id="REFI" type="uint" value="4680" />
<parameter id="RFC" type="uint" value="313" />
<parameter id="RL" type="uint" value="16" />
<parameter id="WL" type="uint" value="16" />
<parameter id="CL" type="uint" value="16" />
<parameter id="AL" type="uint" value="0" />
<parameter id="RP" type="uint" value="16" />
<parameter id="RAS" type="uint" value="39" />
<parameter id="RCD" type="uint" value="16" />
<parameter id="RC" type="uint" value="55" />
<parameter id="FAW" type="uint" value="26" />
<parameter id="RTP" type="uint" value="12" />
<parameter id="WR" type="uint" value="18" />
<parameter id="RRD_S" type="uint" value="4" />
<parameter id="RRD_L" type="uint" value="6" />
<parameter id="CCD_S" type="uint" value="4" />
<parameter id="CCD_L" type="uint" value="6" />
<parameter id="WTR_S" type="uint" value="3" />
<parameter id="WTR_L" type="uint" value="9" />
<parameter id="DQSCK" type="uint" value="2" />
<parameter id="XP" type="uint" value="8" />
<parameter id="XPDLL" type="uint" value="325" />
<parameter id="XS" type="uint" value="324" />
<parameter id="XSDLL" type="uint" value="512" />
<parameter id="CKE" type="uint" value="6" />
<parameter id="CKESR" type="uint" value="7" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="60.75" />
<parameter id="idd02" type="double" value="4.05" />
<parameter id="idd2p0" type="double" value="17.0" />
<parameter id="idd2p1" type="double" value="17.0" />
<parameter id="idd2n" type="double" value="38.25" />
<parameter id="idd3p0" type="double" value="22.5" />
<parameter id="idd3p1" type="double" value="22.5" />
<parameter id="idd3n" type="double" value="44.0" />
<parameter id="idd4r" type="double" value="184.5" />
<parameter id="idd4w" type="double" value="168.75" />
<parameter id="idd5" type="double" value="118.0" />
<parameter id="idd6" type="double" value="20.25" />
<parameter id="idd62" type="double" value="2.6" />
<parameter id="vdd" type="double" value="1.2" />
<parameter id="vdd2" type="double" value="2.5" />
</mempowerspec>
</memspec>

49
DRAMSys/library/resources/configs/memspecs/HBM2.xml
View File

@@ -1,49 +0,0 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<!--8GiB, 8 channels, 1GiB per channel-->
<memspec>
<parameter id="memoryId" type="string" value="https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder" />
<parameter id="memoryType" type="string" value="HBM2" />
<memarchitecturespec>
<parameter id="width" type="uint" value="64" />
<parameter id="nbrOfBanks" type="uint" value="16" />
<parameter id="nbrOfBankGroups" type="uint" value="4" />
<parameter id="nbrOfRanks" type="uint" value="2" />
<parameter id="nbrOfColumns" type="uint" value="128" />
<parameter id="nbrOfRows" type="uint" value="32768" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="1000" />
<parameter id="DQSCK" type="uint" value="1" />
<parameter id="RC" type="uint" value="42" />
<parameter id="RAS" type="uint" value="28" />
<parameter id="RCDRD" type="uint" value="12" />
<parameter id="RCDWR" type="uint" value="6" />
<parameter id="RRDL" type="uint" value="6" />
<parameter id="RRDS" type="uint" value="4" />
<parameter id="FAW" type="uint" value="16" />
<parameter id="RTP" type="uint" value="5" />
<parameter id="RP" type="uint" value="14" />
<parameter id="RL" type="uint" value="17" />
<parameter id="WL" type="uint" value="7" />
<parameter id="PL" type="uint" value="0" />
<parameter id="WR" type="uint" value="14" />
<parameter id="CCDL" type="uint" value="3" />
<parameter id="CCDS" type="uint" value="2" />
<parameter id="WTRL" type="uint" value="9" />
<parameter id="WTRS" type="uint" value="4" />
<parameter id="RTW" type="uint" value="18" />
<parameter id="XP" type="uint" value="8" />
<parameter id="CKE" type="uint" value="8" />
<parameter id="XS" type="uint" value="216" />
<parameter id="RFC" type="uint" value="220" />
<parameter id="RFCSB" type="uint" value="96" />
<parameter id="RREFD" type="uint" value="8" />
<parameter id="REFI" type="uint" value="3900" />
<parameter id="REFISB" type="uint" value="244" />
</memtimingspec>
<mempowerspec>
<!-- to be completed -->
</mempowerspec>
</memspec>

64
DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml
View File

@@ -1,64 +0,0 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<!--BL 2/4, REFM 1/0.5/0.25-->
<memspec>
<parameter id="memoryId" type="string" value="JEDEC_256Mb_WIDEIO_SDR-200_128bit" />
<parameter id="memoryType" type="string" value="WIDEIO_SDR" />
<memarchitecturespec>
<parameter id="width" type="uint" value="128" />
<parameter id="nbrOfBanks" type="uint" value="4" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="128" />
<parameter id="nbrOfRows" type="uint" value="4096" />
<parameter id="dataRate" type="uint" value="1" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="200" />
<parameter id="RC" type="uint" value="12" />
<parameter id="RCD" type="uint" value="4" />
<parameter id="RL" type="uint" value="3" />
<parameter id="RP" type="uint" value="4" />
<parameter id="RFC" type="uint" value="18" />
<parameter id="RAS" type="uint" value="9" />
<parameter id="WL" type="uint" value="1" />
<parameter id="DQSCK" type="uint" value="1" />
<parameter id="AC" type="uint" value="1" />
<parameter id="WR" type="uint" value="3" />
<parameter id="XP" type="uint" value="2" />
<parameter id="XS" type="uint" value="20" />
<parameter id="REFI" type="uint" value="3120" />
<parameter id="TAW" type="uint" value="10" />
<parameter id="RRD" type="uint" value="2" />
<parameter id="CCD_R" type="uint" value="2" />
<parameter id="CCD_W" type="uint" value="1" />
<parameter id="WTR" type="uint" value="3" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="CKESR" type="uint" value="3" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="5.88" />
<parameter id="idd02" type="double" value="21.18" />
<parameter id="idd2p0" type="double" value="0.05" />
<parameter id="idd2p02" type="double" value="0.17" />
<parameter id="idd2p1" type="double" value="0.05" />
<parameter id="idd2p12" type="double" value="0.17" />
<parameter id="idd2n" type="double" value="0.13" />
<parameter id="idd2n2" type="double" value="4.04" />
<parameter id="idd3p0" type="double" value="0.25" />
<parameter id="idd3p02" type="double" value="1.49" />
<parameter id="idd3p1" type="double" value="0.25" />
<parameter id="idd3p12" type="double" value="1.49" />
<parameter id="idd3n" type="double" value="0.52" />
<parameter id="idd3n2" type="double" value="6.55" />
<parameter id="idd4r" type="double" value="1.41" />
<parameter id="idd4r2" type="double" value="85.73" />
<parameter id="idd4w" type="double" value="1.42" />
<parameter id="idd4w2" type="double" value="60.79" />
<parameter id="idd5" type="double" value="14.43" />
<parameter id="idd52" type="double" value="48.17" />
<parameter id="idd6" type="double" value="0.07" />
<parameter id="idd62" type="double" value="0.27" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.2" />
</mempowerspec>
</memspec>

64
DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml
View File

@@ -1,64 +0,0 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<!--BL 2/4, REFM 1/0.5/0.25-->
<memspec>
<parameter id="memoryId" type="string" value="JEDEC_256Mb_WIDEIO_SDR-266_128bit" />
<parameter id="memoryType" type="string" value="WIDEIO_SDR" />
<memarchitecturespec>
<parameter id="width" type="uint" value="128" />
<parameter id="nbrOfBanks" type="uint" value="4" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="128" />
<parameter id="nbrOfRows" type="uint" value="4096" />
<parameter id="dataRate" type="uint" value="1" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="266" />
<parameter id="RC" type="uint" value="16" />
<parameter id="RCD" type="uint" value="5" />
<parameter id="RL" type="uint" value="3" />
<parameter id="RP" type="uint" value="5" />
<parameter id="RFC" type="uint" value="24" />
<parameter id="RAS" type="uint" value="12" />
<parameter id="WL" type="uint" value="1" />
<parameter id="DQSCK" type="uint" value="1" />
<parameter id="AC" type="uint" value="1" />
<parameter id="WR" type="uint" value="4" />
<parameter id="XP" type="uint" value="3" />
<parameter id="XS" type="uint" value="27" />
<parameter id="REFI" type="uint" value="4160" />
<parameter id="TAW" type="uint" value="14" />
<parameter id="RRD" type="uint" value="3" />
<parameter id="CCD_R" type="uint" value="2" />
<parameter id="CCD_W" type="uint" value="1" />
<parameter id="WTR" type="uint" value="4" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="CKESR" type="uint" value="4" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="6.06" />
<parameter id="idd02" type="double" value="21.82" />
<parameter id="idd2p0" type="double" value="0.05" />
<parameter id="idd2p02" type="double" value="0.17" />
<parameter id="idd2p1" type="double" value="0.05" />
<parameter id="idd2p12" type="double" value="0.17" />
<parameter id="idd2n" type="double" value="0.16" />
<parameter id="idd2n2" type="double" value="4.76" />
<parameter id="idd3p0" type="double" value="0.25" />
<parameter id="idd3p02" type="double" value="1.49" />
<parameter id="idd3p1" type="double" value="0.25" />
<parameter id="idd3p12" type="double" value="1.49" />
<parameter id="idd3n" type="double" value="0.58" />
<parameter id="idd3n2" type="double" value="7.24" />
<parameter id="idd4r" type="double" value="1.82" />
<parameter id="idd4r2" type="double" value="111.22" />
<parameter id="idd4w" type="double" value="1.82" />
<parameter id="idd4w2" type="double" value="78.0" />
<parameter id="idd5" type="double" value="14.48" />
<parameter id="idd52" type="double" value="48.34" />
<parameter id="idd6" type="double" value="0.07" />
<parameter id="idd62" type="double" value="0.27" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.2" />
</mempowerspec>
</memspec>

1
DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-200_128bit.xml
View File

@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/JEDEC_256Mb_WIDEIO_SDR-200_128bit.xml

1
DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-266_128bit.xml
View File

@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/JEDEC_256Mb_WIDEIO_SDR-266_128bit.xml

64
DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.xml
View File

@@ -1,64 +0,0 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="MICRON_4Gb_DDR4-1866_8bit_A" />
<parameter id="memoryType" type="string" value="DDR4" />
<memarchitecturespec>
<parameter id="width" type="uint" value="8" />
<parameter id="nbrOfBankGroups" type="uint" value="4" />
<parameter id="nbrOfBanks" type="uint" value="16" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="32768" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="8" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="933" />
<parameter id="REFI" type="uint" value="7280" />
<parameter id="RFC" type="uint" value="243" />
<parameter id="RFC2" type="uint" value="150" />
<parameter id="RFC4" type="uint" value="103" />
<parameter id="RL" type="uint" value="13" />
<parameter id="WL" type="uint" value="12" />
<parameter id="CL" type="uint" value="13" />
<parameter id="AL" type="uint" value="0" />
<parameter id="RP" type="uint" value="13" />
<parameter id="RAS" type="uint" value="32" />
<parameter id="RCD" type="uint" value="13" />
<parameter id="RC" type="uint" value="45" />
<parameter id="FAW" type="uint" value="22" />
<parameter id="RTP" type="uint" value="8" />
<parameter id="WR" type="uint" value="14" />
<parameter id="RRD_S" type="uint" value="4" />
<parameter id="RRD_L" type="uint" value="5" />
<parameter id="CCD_S" type="uint" value="4" />
<parameter id="CCD_L" type="uint" value="5" />
<parameter id="WTR_S" type="uint" value="3" />
<parameter id="WTR_L" type="uint" value="7" />
<parameter id="DQSCK" type="uint" value="2" />
<parameter id="XP" type="uint" value="8" />
<parameter id="XPDLL" type="uint" value="255" />
<parameter id="XS" type="uint" value="252" />
<parameter id="XSDLL" type="uint" value="512" />
<parameter id="CKE" type="uint" value="6" />
<parameter id="CKESR" type="uint" value="7" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="56.25" />
<parameter id="idd02" type="double" value="4.05" />
<parameter id="idd2p0" type="double" value="17.0" />
<parameter id="idd2p1" type="double" value="17.0" />
<parameter id="idd2n" type="double" value="33.75" />
<parameter id="idd3p0" type="double" value="22.5" />
<parameter id="idd3p1" type="double" value="22.5" />
<parameter id="idd3n" type="double" value="39.5" />
<parameter id="idd4r" type="double" value="157.5" />
<parameter id="idd4w" type="double" value="135.0" />
<parameter id="idd5" type="double" value="118.0" />
<parameter id="idd6" type="double" value="20.25" />
<parameter id="idd62" type="double" value="2.6" />
<parameter id="vdd" type="double" value="1.2" />
<parameter id="vdd2" type="double" value="2.5" />
</mempowerspec>
</memspec>

64
DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.xml
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@@ -1,64 +0,0 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="MICRON_4Gb_DDR4-2400_8bit_A" />
<parameter id="memoryType" type="string" value="DDR4" />
<memarchitecturespec>
<parameter id="width" type="uint" value="8" />
<parameter id="nbrOfBankGroups" type="uint" value="4" />
<parameter id="nbrOfBanks" type="uint" value="16" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="32768" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="8" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="1200" />
<parameter id="REFI" type="uint" value="9360" />
<parameter id="RFC" type="uint" value="312" />
<parameter id="RFC2" type="uint" value="192" />
<parameter id="RFC4" type="uint" value="132" />
<parameter id="RL" type="uint" value="16" />
<parameter id="WL" type="uint" value="16" />
<parameter id="CL" type="uint" value="16" />
<parameter id="AL" type="uint" value="0" />
<parameter id="RP" type="uint" value="16" />
<parameter id="RAS" type="uint" value="39" />
<parameter id="RCD" type="uint" value="16" />
<parameter id="RC" type="uint" value="55" />
<parameter id="FAW" type="uint" value="26" />
<parameter id="RTP" type="uint" value="12" />
<parameter id="WR" type="uint" value="18" />
<parameter id="RRD_S" type="uint" value="4" />
<parameter id="RRD_L" type="uint" value="6" />
<parameter id="CCD_S" type="uint" value="4" />
<parameter id="CCD_L" type="uint" value="6" />
<parameter id="WTR_S" type="uint" value="3" />
<parameter id="WTR_L" type="uint" value="9" />
<parameter id="DQSCK" type="uint" value="2" />
<parameter id="XP" type="uint" value="8" />
<parameter id="XPDLL" type="uint" value="325" />
<parameter id="XS" type="uint" value="324" />
<parameter id="XSDLL" type="uint" value="512" />
<parameter id="CKE" type="uint" value="6" />
<parameter id="CKESR" type="uint" value="7" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="60.75" />
<parameter id="idd02" type="double" value="4.05" />
<parameter id="idd2p0" type="double" value="17.0" />
<parameter id="idd2p1" type="double" value="17.0" />
<parameter id="idd2n" type="double" value="38.25" />
<parameter id="idd3p0" type="double" value="22.5" />
<parameter id="idd3p1" type="double" value="22.5" />
<parameter id="idd3n" type="double" value="44.0" />
<parameter id="idd4r" type="double" value="184.5" />
<parameter id="idd4w" type="double" value="168.75" />
<parameter id="idd5" type="double" value="118.0" />
<parameter id="idd6" type="double" value="20.25" />
<parameter id="idd62" type="double" value="2.6" />
<parameter id="vdd" type="double" value="1.2" />
<parameter id="vdd2" type="double" value="2.5" />
</mempowerspec>
</memspec>

43
DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml
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@@ -1,43 +0,0 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<!--BL 4/8, DBI disabled/enabled, REFM 0.25/0.5/1/2/4-->
<memspec>
<parameter id="memoryId" type="string" value="JEDEC_4x64_2Gb_WIDEIO2-400_64bit" />
<parameter id="memoryType" type="string" value="WIDEIO2" />
<memarchitecturespec>
<parameter id="width" type="uint" value="64" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="512" />
<parameter id="nbrOfRows" type="uint" value="8192" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="400" />
<parameter id="RCD" type="uint" value="8" />
<parameter id="RPPB" type="uint" value="8" />
<parameter id="RPAB" type="uint" value="9" />
<parameter id="RAS" type="uint" value="17" />
<parameter id="RCPB" type="uint" value="24" />
<parameter id="RCAB" type="uint" value="26" />
<parameter id="WTR" type="uint" value="4" />
<parameter id="RRD" type="uint" value="4" />
<parameter id="FAW" type="uint" value="24" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="REFM" type="uint" value="1" />
<parameter id="REFI" type="uint" value="1560" />
<parameter id="RFCAB" type="uint" value="72" />
<parameter id="RFCPB" type="uint" value="36" />
<parameter id="CKESR" type="uint" value="6" />
<parameter id="XS" type="uint" value="76" />
<parameter id="XP" type="uint" value="3" />
<parameter id="RL" type="uint" value="7" />
<parameter id="WL" type="uint" value="5" />
<parameter id="WR" type="uint" value="8" />
<parameter id="RTP" type="uint" value="3" />
<parameter id="CCD" type="uint" value="2" />
</memtimingspec>
<mempowerspec>
<!-- to be completed -->
</mempowerspec>
</memspec>

43
DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml
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@@ -1,43 +0,0 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<!--BL 4/8, DBI disabled/enabled, REFM 0.25/0.5/1/2/4-->
<memspec>
<parameter id="memoryId" type="string" value="JEDEC_4x64_2Gb_WIDEIO2-533_64bit" />
<parameter id="memoryType" type="string" value="WIDEIO2" />
<memarchitecturespec>
<parameter id="width" type="uint" value="64" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="512" />
<parameter id="nbrOfRows" type="uint" value="8192" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="533" />
<parameter id="RCD" type="uint" value="10" />
<parameter id="RPPB" type="uint" value="10" />
<parameter id="RPAB" type="uint" value="12" />
<parameter id="RAS" type="uint" value="23" />
<parameter id="RCPB" type="uint" value="32" />
<parameter id="RCAB" type="uint" value="34" />
<parameter id="WTR" type="uint" value="6" />
<parameter id="RRD" type="uint" value="6" />
<parameter id="FAW" type="uint" value="32" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="REFM" type="uint" value="1" />
<parameter id="REFI" type="uint" value="2078" />
<parameter id="RFCAB" type="uint" value="96" />
<parameter id="RFCPB" type="uint" value="48" />
<parameter id="CKESR" type="uint" value="8" />
<parameter id="XS" type="uint" value="102" />
<parameter id="XP" type="uint" value="4" />
<parameter id="RL" type="uint" value="9" />
<parameter id="WL" type="uint" value="7" />
<parameter id="WR" type="uint" value="11" />
<parameter id="RTP" type="uint" value="4" />
<parameter id="CCD" type="uint" value="2" />
</memtimingspec>
<mempowerspec>
<!-- to be completed -->
</mempowerspec>
</memspec>

50
DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml
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@@ -1,50 +0,0 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<!--Single channel device with 8Gb, Set A WL-->
<memspec>
<parameter id="memoryId" type="string" value="JEDEC_8Gb_LPDDR4-3200_16bit" />
<parameter id="memoryType" type="string" value="LPDDR4" />
<memarchitecturespec>
<parameter id="width" type="uint" value="16" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfRows" type="uint" value="65536" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="16" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="1600" />
<parameter id="REFI" type="uint" value="6246" />
<parameter id="REFIPB" type="uint" value="780" />
<parameter id="RFCAB" type="uint" value="448" />
<parameter id="RFCPB" type="uint" value="224" />
<parameter id="RPAB" type="uint" value="34" />
<parameter id="RPPB" type="uint" value="29" />
<parameter id="PPD" type="uint" value="4" />
<parameter id="RAS" type="uint" value="68" />
<parameter id="RCD" type="uint" value="29" />
<parameter id="FAW" type="uint" value="64" />
<parameter id="RRD" type="uint" value="16" />
<parameter id="CCD" type="uint" value="8" />
<parameter id="RL" type="uint" value="28" />
<parameter id="RPST" type="uint" value="0" />
<parameter id="DQSCK" type="uint" value="6" />
<parameter id="RTP" type="uint" value="12" />
<parameter id="WL" type="uint" value="14" />
<parameter id="DQSS" type="uint" value="1" />
<parameter id="DQS2DQ" type="uint" value="2" />
<!--parameter id="nWR" type="uint" value="30" /-->
<parameter id="WR" type="uint" value="29" />
<parameter id="WPRE" type="uint" value="2" />
<parameter id="WTR" type="uint" value="16" />
<parameter id="XP" type="uint" value="12" />
<parameter id="SR" type="uint" value="24" />
<parameter id="XSR" type="uint" value="460" />
<parameter id="ESCKE" type="uint" value="3" />
<parameter id="CKE" type="uint" value="12" />
<parameter id="CMDCKE" type="uint" value="3" />
</memtimingspec>
<mempowerspec>
<!-- to be completed -->
</mempowerspec>
</memspec>

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.xml

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR2-800_16bit_H.xml

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.xml

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.xml

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.xml

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.xml

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.xml

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.xml

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.xml

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.xml

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.xml

55
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.xml
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@@ -1,55 +0,0 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="MICRON_1Gb_DDR3-1600_8bit_G" />
<parameter id="memoryType" type="string" value="DDR3" />
<memarchitecturespec>
<parameter id="width" type="uint" value="8" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="16384" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="8" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="800" />
<parameter id="RC" type="uint" value="38" />
<parameter id="RCD" type="uint" value="10" />
<parameter id="RL" type="uint" value="10" />
<parameter id="RP" type="uint" value="10" />
<parameter id="RFC" type="uint" value="88" />
<parameter id="RAS" type="uint" value="28" />
<parameter id="WL" type="uint" value="8" />
<parameter id="AL" type="uint" value="0" />
<parameter id="DQSCK" type="uint" value="0" />
<parameter id="RTP" type="uint" value="6" />
<parameter id="WR" type="uint" value="12" />
<parameter id="XP" type="uint" value="6" />
<parameter id="XPDLL" type="uint" value="20" />
<parameter id="XS" type="uint" value="96" />
<parameter id="XSDLL" type="uint" value="512" />
<parameter id="REFI" type="uint" value="300000000" />
<parameter id="CL" type="uint" value="10" />
<parameter id="FAW" type="uint" value="24" />
<parameter id="RRD" type="uint" value="5" />
<parameter id="CCD" type="uint" value="4" />
<parameter id="WTR" type="uint" value="6" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="CKESR" type="uint" value="4" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="70.0" />
<parameter id="idd2p0" type="double" value="12.0" />
<parameter id="idd2p1" type="double" value="30.0" />
<parameter id="idd2n" type="double" value="45.0" />
<parameter id="idd3p0" type="double" value="35.0" />
<parameter id="idd3p1" type="double" value="35.0" />
<parameter id="idd3n" type="double" value="45.0" />
<parameter id="idd4w" type="double" value="145.0" />
<parameter id="idd4r" type="double" value="140.0" />
<parameter id="idd5" type="double" value="170.0" />
<parameter id="idd6" type="double" value="8.0" />
<parameter id="vdd" type="double" value="1.5" />
</mempowerspec>
</memspec>

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.xml

55
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml
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@@ -1,55 +0,0 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="MICRON_1Gb_DDR3-800_8bit_G" />
<parameter id="memoryType" type="string" value="DDR3" />
<memarchitecturespec>
<parameter id="width" type="uint" value="8" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="16384" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="8" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="400" />
<parameter id="RC" type="uint" value="20" /> <!-- 50 ns -->
<parameter id="RCD" type="uint" value="5" /> <!-- 12.5 ns -->
<parameter id="RL" type="uint" value="5" /> <!-- 12.5 ns -->
<parameter id="RP" type="uint" value="5" /> <!-- 12.5 ns -->
<parameter id="RFC" type="uint" value="44" /> <!-- 110 ns for 1Gb -->
<parameter id="RAS" type="uint" value="15" /> <!-- 37.5 ns -->
<parameter id="WL" type="uint" value="5" /> <!-- jedec 5 clk cycles -->
<parameter id="AL" type="uint" value="0" />
<parameter id="DQSCK" type="uint" value="0" /> <!-- 0.4 ns -->
<parameter id="RTP" type="uint" value="4" /> <!-- 4 clk cycles -->
<parameter id="WR" type="uint" value="6" /> <!-- 15 ns -->
<parameter id="XP" type="uint" value="3" /> <!-- 3 clk cycles -->
<parameter id="XPDLL" type="uint" value="10" /> <!-- 10 clk cycles -->
<parameter id="XS" type="uint" value="48" /> <!-- 110ns + 10ns -->
<parameter id="XSDLL" type="uint" value="512" /> <!-- 512 clk cycles ns -->
<parameter id="REFI" type="uint" value="3120" /> <!-- 78 000 ns -->
<parameter id="CL" type="uint" value="5" /> <!-- jedec 5 clk cycles -->
<parameter id="FAW" type="uint" value="16" /> <!-- 40 ns -->
<parameter id="RRD" type="uint" value="4" /> <!-- 4 clk cycles -->
<parameter id="CCD" type="uint" value="4" /> <!-- 4 clk cycles -->
<parameter id="WTR" type="uint" value="4" /> <!-- 4 clk cycles -->
<parameter id="CKE" type="uint" value="3" /> <!-- 3 clk cycles -->
<parameter id="CKESR" type="uint" value="4" /> <!-- 4 clk cycles -->
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="60.0" />
<parameter id="idd2p0" type="double" value="12.0" />
<parameter id="idd2p1" type="double" value="25.0" />
<parameter id="idd2n" type="double" value="35.0" />
<parameter id="idd3p0" type="double" value="30.0" />
<parameter id="idd3p1" type="double" value="30.0" />
<parameter id="idd3n" type="double" value="40.0" />
<parameter id="idd4w" type="double" value="110.0" />
<parameter id="idd4r" type="double" value="105.0" />
<parameter id="idd5" type="double" value="160.0" />
<parameter id="idd6" type="double" value="8.0" />
<parameter id="vdd" type="double" value="1.5" />
</mempowerspec>
</memspec>

1
DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.xml

1
DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.xml

1
DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.xml
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@@ -1 +0,0 @@
../../../src/common/third_party/DRAMPower/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.xml

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