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47bdddc5f163bb5fedb64869091d53fd35e3e6e0
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89 Commits

Author SHA1 Message Date
Derek Christ
47bdddc5f1 Different tCCDMW timing when previous WR had BL32 in LPDDR4 2023-08-22 09:41:36 +02:00
Derek Christ
4548d20b6e Rename requiresMaskedWrite to requiresReadModifyWrite 2023-08-21 10:55:41 +02:00
Derek Christ
b30df49d67 Use tCCDMW for masked write in LPDDR4 2023-08-21 09:26:05 +02:00
Derek Christ
3f0372f1f7 Add Partial Write support for blocking accesses 2023-08-16 09:45:32 +02:00
Derek Christ
570fb985df Fix MWR and MWRA command lengths for LPDDR4 2023-08-16 09:38:57 +02:00
Derek Christ
c5f1320399 Implement Partial Write for DDR5 2023-08-16 09:38:57 +02:00
Derek Christ
40dbc518b6 Add hack in TimingCheckers to convert MWR to WR in insertion stage 2023-08-16 09:38:54 +02:00
Derek Christ
f7066a22b0 First implementation of Partial Writes 2023-08-16 09:38:54 +02:00
Lukas Steiner
a8d15e35a5 Merge branch 'work/regression_tests' into 'develop' 
Add a regression test for every standard

See merge request ems/astdm/modeling.dram/dram.sys.5!34
 2023-08-15 12:00:48 +00:00
Lukas Steiner
5598d53ebd Merge branch 'cmake_debug' into 'develop' 
Disable CMake diagnostics print

See merge request ems/astdm/modeling.dram/dram.sys.5!40
 2023-08-15 09:28:28 +00:00
Derek Christ
81eaccf3d6 Add lastCommandOn{C,R}asBus != scMaxTime check for HBM2 and HBM3 2023-08-15 10:58:10 +02:00
Derek Christ
e3bd773cac Implement isFullCycle, alignAtNext functions in utils and add tests 2023-08-15 10:58:10 +02:00
Lukas Steiner
56c9f5f5f0 Merge branch 'initialize_generalinfotable' into 'develop' 
Write GeneralInfo table at the beginning

See merge request ems/astdm/modeling.dram/dram.sys.5!39
 2023-08-14 13:33:40 +00:00
Lukas Steiner
962cc5cf30 Merge branch 'bugfix_includes' into 'develop' 
Fix includes that cause build errors on some platforms

See merge request ems/astdm/modeling.dram/dram.sys.5!38
 2023-08-14 11:36:57 +00:00
Lukas Steiner
766e12fff1 Merge branch 'bugfix/initiator' into 'develop' 
Fix a timing issue in the traffic initiator

See merge request ems/astdm/modeling.dram/dram.sys.5!37
 2023-08-14 09:14:50 +00:00
Lukas Steiner
b5fb23b55d Merge branch 'debug_file' into 'develop' 
Don't create log file when debug is not enabled

See merge request ems/astdm/modeling.dram/dram.sys.5!36
 2023-08-10 12:27:54 +00:00
Lukas Steiner
cb9689a08d Merge branch 'work/simulator_library' into 'develop' 
Introduce Simulator class

See merge request ems/astdm/modeling.dram/dram.sys.5!35
 2023-08-10 12:19:33 +00:00
Derek Christ
a6e1f83570 Remove unnecessary includes from Cache 2023-08-09 16:00:43 +02:00
Derek Christ
ccc1bc73c4 Disable CMake diagnostics print 2023-08-09 14:57:29 +02:00
Derek Christ
d392d0ab98 Write GeneralInfo table at the beginning 
and do not include information in it that is only known at the end of
the simulation. These can trivially be calculated by the trace itself
and would be redundant information regardless.

The TraceAnalyzer gets the number of transactions and the length of
the trace by additional SQL queries.

This enables us to inspect traces of simulations that were aborted
without finishing cleanlywithout finishing cleanly.
 2023-08-09 11:55:10 +02:00
Derek Christ
a064f46413 Fix includes that cause build errors on some platforms 2023-08-03 15:04:39 +02:00
Derek Christ
24654be952 Fix a timing issue in the traffic initiator 
When the generator clock did not match the memory clock,
the generator always created a constant delay to the
next transaction.

This is not correct as due to rounding, the delay should be
one cycle more or less depending on the current simulation time.
 2023-07-27 11:02:45 +02:00
Derek Christ
085bfbd8de Don't create log file when debug is not enabled 2023-07-21 09:39:52 +02:00
Derek Christ
14ecc64ed0 Introduce Simulator class 2023-07-14 14:31:03 +02:00
Lukas Steiner
12dcbfd917 Use scoped enums for DRAM types. 2023-06-30 15:49:41 +02:00
Lukas Steiner
4e0891affb Inherit privately from std::vector. 2023-06-26 16:32:39 +02:00
Lukas Steiner
413921f420 Minor formatting. 2023-06-22 10:19:34 +02:00
Lukas Steiner
c833471480 Use type safe index vectors in remaining controller. 2023-06-21 14:51:15 +02:00
Lukas Steiner
ba3f367676 Use type safe index vectors in timing checkers (2/2). 2023-06-21 12:59:26 +02:00
Lukas Steiner
d045af9d16 Use type safe index vectors in timing checkers (1). 2023-06-20 13:54:36 +02:00
Lukas Steiner
f3f9f9e8cd Merge branch 'bug/stl_exceptions' into 'develop' 
Add checks for empty trace and catch conversion exceptions.

See merge request ems/astdm/modeling.dram/dram.sys.5!30
 2023-06-15 14:45:09 +00:00
Lukas Steiner
6e582907c0 Add checks for empty trace and catch conversion exceptions. 2023-06-15 11:32:51 +02:00
Derek Christ
20f4f111ac Align next request to initiator clock period 2023-06-15 10:59:29 +02:00
Lukas Steiner
ec731888a3 Remove check to issue first transaction at zero time. 2023-06-12 10:29:25 +02:00
Lukas Steiner
71172f9545 Remove old files, move pct to extensions. 2023-05-26 15:39:06 +02:00
Lukas Steiner
20f6aae787 Replace tabs with whitespaces. 2023-05-25 16:09:55 +02:00
Lukas Steiner
b3955d6d02 Update TUK to RPTU. 2023-05-25 15:15:52 +02:00
Lukas Steiner
4212e55f6c Set cmake defaults, replace TUK with RPTU. 2023-05-23 16:47:03 +02:00
Lukas Steiner
93aecc3555 Merge branch 'gem5_instructions' into 'develop' 
Add instructions for the new gem5 integration

See merge request ems/astdm/modeling.dram/dram.sys.5!23
 2023-05-23 13:12:07 +00:00
Lukas Steiner
e389474139 Remove deprecated gem5 files. 2023-05-23 14:53:06 +02:00
Derek Christ
b2fd6f2a84 Add instructions for the new gem5 integration 2023-05-22 12:17:59 +02:00
Derek Christ
69cd04c448 Namespace the complete DRAMSys library 2023-05-17 11:42:00 +02:00
Lukas Steiner
58d486fb82 Merge branch 'work/hbm_rfm_fixes' into 'develop' 
HBM and RFM fixes

See merge request ems/astdm/modeling.dram/dram.sys.5!17
 2023-04-26 08:36:08 +00:00
Derek Christ
fa88b34052 Refactor deserilization of RefreshPolicyType and remove McConfig.cpp 2023-04-24 09:34:50 +02:00
Derek Christ
44a4d71635 Fix HBM pseudochannels not respeced in AddressDecoder 2023-04-21 11:12:21 +02:00
Derek Christ
85f944fe58 Rename RAACDR to RAADEC 2023-04-21 11:10:09 +02:00
Lukas Steiner
7c0198cf21 Change default simulation file back to DDR4. 2023-04-20 10:38:33 +02:00
Derek Christ
0814aa0cf1 Fix DatabaseRecording and SimulationProgressBar fields in SimConfig 2023-04-14 14:04:31 +02:00
Lukas Steiner
9a1443835d Merge branch 'develop' into wip/unit_test_preps 
# Conflicts:
#	extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
 2023-04-14 11:35:32 +02:00
Lukas Steiner
f844449d50 Remove empty cpp files. 2023-04-14 11:21:36 +02:00