Sandipan Das 9931e7ce0d arch-power: Add character compare instructions ...

This adds the following instructions.
  * Compare Ranged Byte (cmprb)
  * Compare Equal Byte (cmpeqb)

Change-Id: I12a9135bf302acd741abe27cb557e8e8bba82edc
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40915
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-06-29 14:00:38 +00:00

..

insts

arch-power: Fix disassembly for compare instructions

2021-06-29 14:00:38 +00:00

isa

arch-power: Add character compare instructions

2021-06-29 14:00:38 +00:00

linux

base: Rename Loader namespace as loader

2021-05-29 11:13:49 +00:00

regs

arch-power: Fix arithmetic instructions

2021-06-29 02:23:32 +00:00

decoder.cc

arch: Templatize the BasicDecodeCache.

2021-02-03 03:54:34 +00:00

decoder.hh

arch,cpu: Make the decoder width a property of the decoder.

2021-05-26 00:31:54 +00:00

faults.hh

power: Delete the authors lists from the power ISA.

2020-02-18 03:36:00 +00:00

interrupts.hh

misc: Remove unused params() definitions

2021-02-19 23:27:34 +00:00

isa.cc

cpu,arch: Move the zero register index into RegClassInfo.

2021-04-29 12:48:47 +00:00

isa.hh

arch-power: Pull non-public information out of registers.hh.

2021-04-10 01:11:21 +00:00

locked_mem.hh

arch: Rename LockedMem namespace as locked_mem

2021-05-26 23:08:21 +00:00

mmu.hh

misc: Standardize the way create() constructs SimObjects.

2020-10-14 12:06:44 +00:00

page_size.hh

arch,dev,gpu-compute,sim: Rename isa_traits.hh page_size.hh.

2021-03-30 10:17:48 +00:00

pagetable.cc

power: Delete the authors lists from the power ISA.

2020-02-18 03:36:00 +00:00

pagetable.hh

arch,dev,gpu-compute,sim: Rename isa_traits.hh page_size.hh.

2021-03-30 10:17:48 +00:00

pcstate.hh

arch,base,cpu: Split arch/pcstate.hh out of arch/types.hh.

2021-05-28 23:41:03 +00:00

PowerInterrupts.py

power: Delete the authors lists from the power ISA.

2020-02-18 03:36:00 +00:00

PowerISA.py

power: Delete the authors lists from the power ISA.

2020-02-18 03:36:00 +00:00

PowerMMU.py

arch: Add generic BaseMMU

2020-10-07 10:48:14 +00:00

PowerSeWorkload.py

power: Implement an SE workload for Linux.

2020-10-26 20:32:03 +00:00

PowerTLB.py

power: Delete the authors lists from the power ISA.

2020-02-18 03:36:00 +00:00

process.cc

base: Rename Loader namespace as loader

2021-05-29 11:13:49 +00:00

process.hh

base: Rename Loader namespace as loader

2021-05-29 11:13:49 +00:00

remote_gdb.cc

arch,base,sim: Construct the GDB stub with no threads.

2021-05-28 07:56:19 +00:00

remote_gdb.hh

arch,base,sim: Construct the GDB stub with no threads.

2021-05-28 07:56:19 +00:00

SConscript

arch,cpu: Move TheISA::copyRegs to TheISA::ISA::copyRegsFrom.

2021-03-22 21:01:33 +00:00

SConsopts

power: Delete the authors lists from the power ISA.

2020-02-18 03:36:00 +00:00

se_workload.cc

power: Implement an SE workload for Linux.

2020-10-26 20:32:03 +00:00

se_workload.hh

base: Rename Loader namespace as loader

2021-05-29 11:13:49 +00:00

stacktrace.hh

arch,cpu: Consolidate most of the StackTrace classes into a base class.

2020-07-11 00:24:38 +00:00

tlb.cc

arch,cpu,kern,sim: Eliminate the utility.hh switching header.

2021-03-22 21:01:58 +00:00

tlb.hh

arch,dev,gpu-compute,sim: Rename isa_traits.hh page_size.hh.

2021-03-30 10:17:48 +00:00

types.hh

arch-power: Add fields for D and X form instructions

2021-06-29 14:00:38 +00:00

vecregs.hh

arch: Delete a few unused vector register types/constants.

2021-05-08 19:37:26 +00:00