213c9186de
In this context, the decoder width is the number of bytes that are fed into the decoder at once. This is frequently the same as the size of an instruction, but in instructions with occasionally variable instruction sizes (ARM, RISCV), or extremely variable instruction sizes (x86) there may be no relation. Rather than determining the amount of data to feed to the decoder based on a MachInst type defined by each ISA, this new interface adds some new properties to the base InstDecoder class each arch specific decoder inherits from. These are the size of the incoming buffer, a pointer to wherever that data should end up, and a mask for masking a PC value so it aligns with the instruction size. These values are filled in by a templated InstDecoder constructor which is templated based on what would have historically been the MachInst type. Because the "moreBytes" method would historically accept a parameter of type MachInst, this parameter has also been eliminated. Now, the decoder's parent object should use the pointer and size values to fill in the buffer moreBytes reads. Then when moreBytes is called, it just uses the buffer without having to show what its type is externally. Change-Id: I0642cdb6a61e152441ca4ce47d748639175cda90 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40175 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
119 lines
3.4 KiB
C++
119 lines
3.4 KiB
C++
/*
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* Copyright (c) 2012 Google
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_POWER_DECODER_HH__
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#define __ARCH_POWER_DECODER_HH__
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#include "arch/generic/decode_cache.hh"
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#include "arch/generic/decoder.hh"
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#include "arch/power/types.hh"
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#include "cpu/static_inst.hh"
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#include "debug/Decode.hh"
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namespace PowerISA
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{
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class ISA;
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class Decoder : public InstDecoder
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{
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protected:
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// The extended machine instruction being generated
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ExtMachInst emi;
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bool instDone;
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public:
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Decoder(ISA* isa=nullptr) : InstDecoder(&emi), instDone(false) {}
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void
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process()
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{
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}
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void
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reset()
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{
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instDone = false;
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}
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// Use this to give data to the predecoder. This should be used
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// when there is control flow.
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void
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moreBytes(const PCState &pc, Addr fetchPC)
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{
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emi = betoh(emi);
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instDone = true;
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}
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bool
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needMoreBytes()
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{
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return true;
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}
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bool
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instReady()
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{
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return instDone;
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}
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void takeOverFrom(Decoder *old) {}
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protected:
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/// A cache of decoded instruction objects.
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static GenericISA::BasicDecodeCache<Decoder, ExtMachInst> defaultCache;
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friend class GenericISA::BasicDecodeCache<Decoder, ExtMachInst>;
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StaticInstPtr decodeInst(ExtMachInst mach_inst);
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/// Decode a machine instruction.
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/// @param mach_inst The binary instruction to decode.
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/// @retval A pointer to the corresponding StaticInst object.
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StaticInstPtr
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decode(ExtMachInst mach_inst, Addr addr)
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{
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StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
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DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
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si->getName(), mach_inst);
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return si;
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}
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public:
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StaticInstPtr
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decode(PowerISA::PCState &nextPC)
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{
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if (!instDone)
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return NULL;
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instDone = false;
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return decode(emi, nextPC.instAddr());
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}
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};
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} // namespace PowerISA
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#endif // __ARCH_POWER_DECODER_HH__
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