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79a3091605e2188e5f50c522ce48ab6847cee344
gem5/src/arch/arm
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Giacomo Travaglini 79a3091605 arch-arm: Default ArmSystem to AArch64 
Change-Id: I4dad29086c0b3e50bd2011363cb23625811b4b27
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35775
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-10-08 08:53:11 +00:00
..
fastmodel
fastmodel: Add IrisMMU model
2020-10-07 10:48:14 +00:00
freebsd
base, sim: Make ByteOrder into a ScopedEnum accessible to Python
2020-09-08 16:24:00 +00:00
insts
misc: Merge branch 'release-staging-v20.1.0.0' into develop
2020-09-30 20:39:06 -07:00
isa
arch-arm: Using new "raw" memhelpers
2020-09-30 08:50:39 +00:00
kvm
arch-arm: Fix ArmISA namespace requirement for Arm KVM
2020-09-13 11:43:44 +00:00
linux
arm: Remove "using namespace ArmISA" from arch/arm/isa_traits.hh.
2020-09-08 23:57:56 +00:00
tracers
arm,base,gpu: Use std::make_unique instead of m5::make_unique.
2020-09-28 05:41:08 +00:00
aapcs32.hh
base, sim: Make ByteOrder into a ScopedEnum accessible to Python
2020-09-08 16:24:00 +00:00
aapcs64.hh
misc: Replace scalar TypedBufferArg with VPtr.
2020-08-19 12:04:18 +00:00
aapcs64.test.cc
arm: Add a unit test for some aspects of the aapcs64 ABI.
2020-04-29 11:30:58 +00:00
ArmFsWorkload.py
arch,sim,kern,dev,cpu: Create a Workload SimObject.
2020-04-22 00:22:28 +00:00
ArmInterrupts.py
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
ArmISA.py
arch-arm: Add recursion for DTB entry generation inside ArmISA
2020-10-06 13:56:08 +00:00
ArmMMU.py
arch: Add generic BaseMMU
2020-10-07 10:48:14 +00:00
ArmNativeTrace.py
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
ArmPMU.py
arch-arm: Correct the Ids and names of the PMU events
2020-03-11 10:54:24 +00:00
ArmSemihosting.py
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
ArmSystem.py
arch-arm: Default ArmSystem to AArch64
2020-10-08 08:53:11 +00:00
ArmTLB.py
arch: update port terminology
2020-08-26 16:48:13 +00:00
ccregs.hh
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
decoder.cc
arch-arm: Implementation of SelfHosted Debug Software step
2020-07-02 11:53:15 +00:00
decoder.hh
arch: Create a base class for decoders.
2020-08-20 01:07:13 +00:00
faults.cc
misc: Update attribute syntax, and reorganize compiler.hh.
2020-09-28 21:52:59 +00:00
faults.hh
arch-arm: Fix Fault subsystem adding EL2Enable func
2020-07-21 14:37:54 +00:00
fs_workload.cc
arch,cpu,dev,sim,mem: Collect System thread elements into a subclass.
2020-06-09 23:37:29 +00:00
fs_workload.hh
base,arch,sim,cpu: Move object file loader components into a namespace.
2020-04-22 06:08:54 +00:00
htm.cc
arch-arm: Transactional Memory Extension (TME)
2020-09-08 23:37:40 +00:00
htm.hh
arch-arm: Transactional Memory Extension (TME)
2020-09-08 23:37:40 +00:00
interrupts.cc
arch-arm: Implementing SecureEL2 feature for Armv8
2020-07-31 13:13:57 +00:00
interrupts.hh
arm: Clear out isa_traits.hh.
2020-08-25 19:47:10 +00:00
intregs.hh
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
isa_device.cc
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
isa_device.hh
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
isa_traits.hh
arm: Remove "using namespace ArmISA" from arch/arm/isa_traits.hh.
2020-09-08 23:57:56 +00:00
isa.cc
misc: Merge branch 'release-staging-v20.1.0.0' into develop
2020-09-30 20:39:06 -07:00
isa.hh
arch-arm: Transactional Memory Extension (TME)
2020-09-08 23:37:40 +00:00
locked_mem.hh
sim-se: don't wake up SE futex syscalls on ARM events
2020-08-10 08:52:03 +00:00
miscregs_types.hh
arch-arm: Rewrite addressTranslation to use BitUnions
2020-08-26 13:56:54 +00:00
miscregs.cc
arch-arm: Implementing SecureEL2 feature for Armv8
2020-07-31 13:13:57 +00:00
miscregs.hh
arch-arm: Implementing SecureEL2 feature for Armv8
2020-07-31 13:13:57 +00:00
mmu.cc
arch: Add generic BaseMMU
2020-10-07 10:48:14 +00:00
mmu.hh
arch: Add generic BaseMMU
2020-10-07 10:48:14 +00:00
nativetrace.cc
arm: Remove "using namespace ArmISA" from arch/arm/isa_traits.hh.
2020-09-08 23:57:56 +00:00
nativetrace.hh
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
pagetable.hh
arm: Clear out isa_traits.hh.
2020-08-25 19:47:10 +00:00
pauth_helpers.cc
arch-arm: Initialized some variables
2020-07-10 18:10:20 +00:00
pauth_helpers.hh
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
pmu.cc
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
pmu.hh
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
process.cc
base, sim: Make ByteOrder into a ScopedEnum accessible to Python
2020-09-08 16:24:00 +00:00
process.hh
base,arch,sim,cpu: Move object file loader components into a namespace.
2020-04-22 06:08:54 +00:00
pseudo_inst.hh
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
qarma.cc
arch-arm: Add missing include in QARMA implementation
2020-04-02 13:31:59 +00:00
qarma.hh
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
registers.hh
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
remote_gdb.cc
arch: Eliminate vtophys and its switching header file.
2020-03-19 01:38:01 +00:00
remote_gdb.hh
misc: Update attribute syntax, and reorganize compiler.hh.
2020-09-28 21:52:59 +00:00
SConscript
arch: Add generic BaseMMU
2020-10-07 10:48:14 +00:00
SConsopts
arm: Delete authors lists from the arm files.
2020-02-18 03:35:23 +00:00
self_debug.cc
arch-arm: Rename SelfDebug member variables
2020-08-18 13:04:58 +00:00
self_debug.hh
arch-arm: Rename SelfDebug member variables
2020-08-18 13:04:58 +00:00
semihosting.cc
arch-arm: Replace call to tmpnam() by a deterministic one
2020-10-06 20:07:26 +00:00
semihosting.hh
arch-arm: Replace call to tmpnam() by a deterministic one
2020-10-06 20:07:26 +00:00
stacktrace.hh
arch,cpu: Consolidate most of the StackTrace classes into a base class.
2020-07-11 00:24:38 +00:00
stage2_lookup.cc
arch-arm: Implementing SecureEL2 feature for Armv8
2020-07-31 13:13:57 +00:00
stage2_lookup.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
stage2_mmu.cc
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
stage2_mmu.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
system.cc
arm: Remove "using namespace ArmISA" from arch/arm/isa_traits.hh.
2020-09-08 23:57:56 +00:00
system.hh
arm: Remove "using namespace ArmISA" from arch/arm/isa_traits.hh.
2020-09-08 23:57:56 +00:00
table_walker.cc
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
table_walker.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
tlb.cc
misc: Update attribute syntax, and reorganize compiler.hh.
2020-09-28 21:52:59 +00:00
tlb.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
tlbi_op.cc
arch-arm: Implement ARM8.1-VHE feature
2020-07-27 17:23:55 +00:00
tlbi_op.hh
arch,cpu,dev,sim,mem: Collect System thread elements into a subclass.
2020-06-09 23:37:29 +00:00
types.hh
arch-arm: Implementation of Vector Catch debug exception
2020-07-06 09:10:33 +00:00
utility.cc
arch,base,cpu,dev: Get rid of the M5_DUMMY_RETURN macro.
2020-09-28 05:41:26 +00:00
utility.hh
base, sim: Make ByteOrder into a ScopedEnum accessible to Python
2020-09-08 16:24:00 +00:00