arm: Clear out isa_traits.hh.

Remove unused constants, move the interrupt related constants to
arch/arm/interrupts.hh, move a paging related constant to
arch/arm/pagetable.hh, and get rid of unnecessary includes.

Change-Id: Ide219f7a8515e010c1dd029db2ef22d8f614d8a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33198
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/faults.cc

@@ -42,6 +42,7 @@
 #include "arch/arm/faults.hh"
 
 #include "arch/arm/insts/static_inst.hh"
+#include "arch/arm/interrupts.hh"
 #include "arch/arm/isa.hh"
 #include "arch/arm/self_debug.hh"
 #include "arch/arm/system.hh"
@@ -56,6 +57,8 @@
 namespace ArmISA
 {
 
+const uint32_t HighVecs = 0xFFFF0000;
+
 uint8_t ArmFault::shortDescFaultSources[] = {
     0x01,  // AlignmentFault
     0x04,  // InstructionCacheMaintenance

src/arch/arm/interrupts.hh

@@ -54,6 +54,18 @@
 namespace ArmISA
 {
 
+enum InterruptTypes
+{
+    INT_RST,
+    INT_ABT,
+    INT_IRQ,
+    INT_FIQ,
+    INT_SEV, // Special interrupt for recieving SEV's
+    INT_VIRT_IRQ,
+    INT_VIRT_FIQ,
+    NumInterruptTypes
+};
+
 class Interrupts : public BaseInterrupts
 {
   private:

src/arch/arm/isa_traits.hh

@@ -42,67 +42,14 @@
 #ifndef __ARCH_ARM_ISA_TRAITS_HH__
 #define __ARCH_ARM_ISA_TRAITS_HH__
 
-#include "arch/arm/types.hh"
 #include "base/types.hh"
-#include "cpu/static_inst_fwd.hh"
 
 namespace ArmISA
 {
     const ByteOrder GuestByteOrder = LittleEndianByteOrder;
 
-    StaticInstPtr decodeInst(ExtMachInst);
-
     const Addr PageShift = 12;
     const Addr PageBytes = ULL(1) << PageShift;
-    const Addr Page_Mask = ~(PageBytes - 1);
-    const Addr PageOffset = PageBytes - 1;
-
-
-    ////////////////////////////////////////////////////////////////////////
-    //
-    //  Translation stuff
-    //
-
-    const Addr PteShift = 3;
-    const Addr NPtePageShift = PageShift - PteShift;
-    const Addr NPtePage = ULL(1) << NPtePageShift;
-    const Addr PteMask = NPtePage - 1;
-
-    //// All 'Mapped' segments go through the TLB
-    //// All other segments are translated by dropping the MSB, to give
-    //// the corresponding physical address
-    // User Segment - Mapped
-    const Addr USegBase = ULL(0x0);
-    const Addr USegEnd = ULL(0x7FFFFFFF);
-
-    const unsigned VABits = 32;
-    const unsigned PABits = 32; // Is this correct?
-    const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
-    const Addr VAddrUnImplMask = ~VAddrImplMask;
-    inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
-    inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; }
-    inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; }
-
-    const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
-
-    // Max. physical address range in bits supported by the architecture
-    const unsigned MaxPhysAddrRange = 48;
-
-    const int MachineBytes = 4;
-
-    const uint32_t HighVecs = 0xFFFF0000;
-
-    enum InterruptTypes
-    {
-        INT_RST,
-        INT_ABT,
-        INT_IRQ,
-        INT_FIQ,
-        INT_SEV, // Special interrupt for recieving SEV's
-        INT_VIRT_IRQ,
-        INT_VIRT_FIQ,
-        NumInterruptTypes
-    };
 } // namespace ArmISA
 
 using namespace ArmISA;

src/arch/arm/pagetable.hh

@@ -47,7 +47,11 @@
 #include "arch/arm/utility.hh"
 #include "sim/serialize.hh"
 
-namespace ArmISA {
+namespace ArmISA
+{
+
+// Max. physical address range in bits supported by the architecture
+const unsigned MaxPhysAddrRange = 48;
 
 // ITB/DTB page table entry
 struct PTE

src/arch/arm/utility.cc

@@ -40,6 +40,7 @@
 #include <memory>
 
 #include "arch/arm/faults.hh"
+#include "arch/arm/interrupts.hh"
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/system.hh"
 #include "arch/arm/tlb.hh"
@@ -74,8 +75,7 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
         }
     } else {
         if (size == (uint16_t)(-1))
-            // todo: should this not be sizeof(uint32_t) rather?
-            size = ArmISA::MachineBytes;
+            size = sizeof(uint32_t);
 
         if (number < NumArgumentRegs) {
             // If the argument is 64 bits, it must be in an even regiser

src/dev/arm/gic_v2.hh

@@ -48,6 +48,7 @@
 
 #include <vector>
 
+#include "arch/arm/interrupts.hh"
 #include "base/addr_range.hh"
 #include "base/bitunion.hh"
 #include "cpu/intr_control.hh"

src/dev/arm/gic_v3.hh

@@ -41,6 +41,7 @@
 #ifndef __DEV_ARM_GICV3_H__
 #define __DEV_ARM_GICV3_H__
 
+#include "arch/arm/interrupts.hh"
 #include "dev/arm/base_gic.hh"
 #include "params/Gicv3.hh"
 

src/dev/arm/vgic.cc

@@ -37,6 +37,7 @@
 
 #include "dev/arm/vgic.hh"
 
+#include "arch/arm/interrupts.hh"
 #include "base/trace.hh"
 #include "debug/Checkpoint.hh"
 #include "debug/VGIC.hh"