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arm,base,gpu: Use std::make_unique instead of m5::make_unique.

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Now that we're using c++14, we can just assume that std::make_unique
exists. We no longer have to conditionally inject our own version.

Change-Id: I5d851afb02dd05c7af93864ffec3b3184f3d4ec8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35215
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-09-26 16:00:35 -07:00
parent ff6a3a6171
commit 50a0b85367
5 changed files with 29 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/arch/arm/tracers/tarmac_record.cc
View File

@@ -37,6 +37,8 @@
#include "arch/arm/tracers/tarmac_record.hh"
#include <memory>
#include "arch/arm/insts/static_inst.hh"
#include "tarmac_tracer.hh"
@@ -291,7 +293,7 @@ TarmacTracerRecord::addInstEntry(std::vector<InstPtr>& queue,
// Generate an instruction entry in the record and
// add it to the Instruction Queue
queue.push_back(
m5::make_unique<TraceInstEntry>(tarmCtx, predicate)
std::make_unique<TraceInstEntry>(tarmCtx, predicate)
);
}
@@ -304,9 +306,9 @@ TarmacTracerRecord::addMemEntry(std::vector<MemPtr>& queue,
// Memory Queue
if (getMemValid()) {
queue.push_back(
m5::make_unique<TraceMemEntry>(tarmCtx,
static_cast<uint8_t>(getSize()),
getAddr(), getIntData())
std::make_unique<TraceMemEntry>(tarmCtx,
static_cast<uint8_t>(getSize()),
getAddr(), getIntData())
);
}
}
@@ -326,9 +328,7 @@ TarmacTracerRecord::addRegEntry(std::vector<RegPtr>& queue,
// Copying the entry and adding it to the "list"
// of entries to be dumped to trace.
queue.push_back(
m5::make_unique<TraceRegEntry>(single_reg)
);
queue.push_back(std::make_unique<TraceRegEntry>(single_reg));
}
// Gem5 is treating CPSR flags as separate registers (CC registers),

4
src/arch/arm/tracers/tarmac_record.hh
View File

@@ -43,6 +43,8 @@
#ifndef __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__
#define __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__
#include <memory>
#include "arch/arm/tracers/tarmac_base.hh"
#include "base/printable.hh"
#include "config/the_isa.hh"
@@ -246,7 +248,7 @@ class TarmacTracerRecord : public TarmacBaseRecord
if (cpsr_it == queue.end()) {
RegId reg(MiscRegClass, ArmISA::MISCREG_CPSR);
queue.push_back(
m5::make_unique<RegEntry>(
std::make_unique<RegEntry>(
genRegister<RegEntry>(tarmCtx, reg))
);
}

14
src/arch/arm/tracers/tarmac_record_v8.cc
View File

@@ -37,6 +37,8 @@
#include "arch/arm/tracers/tarmac_record_v8.hh"
#include <memory>
#include "arch/arm/insts/static_inst.hh"
#include "arch/arm/tlb.hh"
#include "arch/arm/tracers/tarmac_tracer.hh"
@@ -185,7 +187,7 @@ TarmacTracerRecordV8::addInstEntry(std::vector<InstPtr>& queue,
// Generate an instruction entry in the record and
// add it to the Instruction Queue
queue.push_back(
m5::make_unique<TraceInstEntryV8>(tarmCtx, predicate)
std::make_unique<TraceInstEntryV8>(tarmCtx, predicate)
);
}
@@ -198,9 +200,9 @@ TarmacTracerRecordV8::addMemEntry(std::vector<MemPtr>& queue,
// Memory Queue
if (getMemValid()) {
queue.push_back(
m5::make_unique<TraceMemEntryV8>(tarmCtx,
static_cast<uint8_t>(getSize()),
getAddr(), getIntData())
std::make_unique<TraceMemEntryV8>(tarmCtx,
static_cast<uint8_t>(getSize()),
getAddr(), getIntData())
);
}
}
@@ -220,9 +222,7 @@ TarmacTracerRecordV8::addRegEntry(std::vector<RegPtr>& queue,
// Copying the entry and adding it to the "list"
// of entries to be dumped to trace.
queue.push_back(
m5::make_unique<TraceRegEntryV8>(single_reg)
);
queue.push_back(std::make_unique<TraceRegEntryV8>(single_reg));
}
// Gem5 is treating CPSR flags as separate registers (CC registers),

24
src/base/compiler.hh
View File

@@ -88,28 +88,4 @@
#define M5_NODISCARD
#endif
// std::make_unique redefined for C++11 compilers
namespace m5
{
#if __cplusplus >= 201402L // C++14
using std::make_unique;
#else // C++11
/** Defining custom version of make_unique: m5::make_unique<>() */
template<typename T, typename... Args>
std::unique_ptr<T>
make_unique( Args&&... constructor_args )
{
return std::unique_ptr<T>(
new T( std::forward<Args>(constructor_args)... )
);
}
#endif // __cplusplus >= 201402L
} //namespace m5
#endif // __BASE_COMPILER_HH__

23
src/gpu-compute/gpu_dyn_inst.hh
View File

@@ -35,6 +35,7 @@
#define __GPU_DYN_INST_HH__
#include <cstdint>
#include <memory>
#include <string>
#include "base/amo.hh"
@@ -255,27 +256,27 @@ class GPUDynInst : public GPUExecContext
makeAtomicOpFunctor(c0 *reg0, c0 *reg1)
{
if (isAtomicAnd()) {
return m5::make_unique<AtomicOpAnd<c0>>(*reg0);
return std::make_unique<AtomicOpAnd<c0>>(*reg0);
} else if (isAtomicOr()) {
return m5::make_unique<AtomicOpOr<c0>>(*reg0);
return std::make_unique<AtomicOpOr<c0>>(*reg0);
} else if (isAtomicXor()) {
return m5::make_unique<AtomicOpXor<c0>>(*reg0);
return std::make_unique<AtomicOpXor<c0>>(*reg0);
} else if (isAtomicCAS()) {
return m5::make_unique<AtomicOpCAS<c0>>(*reg0, *reg1, cu);
return std::make_unique<AtomicOpCAS<c0>>(*reg0, *reg1, cu);
} else if (isAtomicExch()) {
return m5::make_unique<AtomicOpExch<c0>>(*reg0);
return std::make_unique<AtomicOpExch<c0>>(*reg0);
} else if (isAtomicAdd()) {
return m5::make_unique<AtomicOpAdd<c0>>(*reg0);
return std::make_unique<AtomicOpAdd<c0>>(*reg0);
} else if (isAtomicSub()) {
return m5::make_unique<AtomicOpSub<c0>>(*reg0);
return std::make_unique<AtomicOpSub<c0>>(*reg0);
} else if (isAtomicInc()) {
return m5::make_unique<AtomicOpInc<c0>>();
return std::make_unique<AtomicOpInc<c0>>();
} else if (isAtomicDec()) {
return m5::make_unique<AtomicOpDec<c0>>();
return std::make_unique<AtomicOpDec<c0>>();
} else if (isAtomicMax()) {
return m5::make_unique<AtomicOpMax<c0>>(*reg0);
return std::make_unique<AtomicOpMax<c0>>(*reg0);
} else if (isAtomicMin()) {
return m5::make_unique<AtomicOpMin<c0>>(*reg0);
return std::make_unique<AtomicOpMin<c0>>(*reg0);
} else {
fatal("Unrecognized atomic operation");
}