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arch-arm: Correct the Ids and names of the PMU events

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0x0C is the PC_WRITE_RETIRED event and 0x21 is the RetiredBranches.

Change-Id: I5f1173ff06f67b6a46e8a914c8acb9639edf67ec
Signed-off-by: Andriani Mappoura <andriani.mappoura@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26485
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Andriani Mappoura
2020-03-09 17:17:22 +00:00
committed by Giacomo Travaglini
parent 077bc85196
commit ba78eaf876
1 changed files with 3 additions and 3 deletions
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6
src/arch/arm/ArmPMU.py
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@@ -1,5 +1,5 @@
# -*- mode:python -*-
# Copyright (c) 2009-2014, 2017 ARM Limited
# Copyright (c) 2009-2014, 2017, 2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -128,7 +128,7 @@ class ArmPMU(SimObject):
# 0x09: EXC_TAKEN
# 0x0A: EXC_RETURN
# 0x0B: CID_WRITE_RETIRED
self.addEvent(ProbeEvent(self,0x0C, cpu, "RetiredBranches"))
# 0x0C: PC_WRITE_RETIRED
# 0x0D: BR_IMMED_RETIRED
# 0x0E: BR_RETURN_RETIRED
# 0x0F: UNALIGEND_LDST_RETIRED
@@ -151,7 +151,7 @@ class ArmPMU(SimObject):
# 0x1E: CHAIN
# 0x1F: L1D_CACHE_ALLOCATE
# 0x20: L2D_CACHE_ALLOCATE
# 0x21: BR_RETIRED
self.addEvent(ProbeEvent(self,0x21, cpu, "RetiredBranches"))
# 0x22: BR_MIS_PRED_RETIRED
# 0x23: STALL_FRONTEND
# 0x24: STALL_BACKEND