derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
712096b8661e63d3e4c313226791541f46f6e6e7
gem5/src/cpu
History
Gabe Black 6903547957 cpu-o3: Fix minor style issue in rename_map.hh. 
Change-Id: I670e504320b41e38666dab6eb7a83e4a39bc3b00
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49146
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-12 22:01:30 +00:00
..
checker
cpu: Simplify or eliminate set${type}Result methods for o3 and checker.
2021-08-11 20:24:54 +00:00
kvm
misc: Replace GEM5_FALLTHROUGH with [[fallthrough]].
2021-07-24 21:57:04 +00:00
minor
cpu: Use RegVal for VecElems instead of TheISA::VecElem.
2021-08-11 04:48:02 +00:00
o3
cpu-o3: Fix minor style issue in rename_map.hh.
2021-08-12 22:01:30 +00:00
pred
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
simple
cpu: Use RegVal for VecElems instead of TheISA::VecElem.
2021-08-11 04:48:02 +00:00
testers
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
trace
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
activity.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
activity.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
base.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
base.hh
misc: Replace THE_ISA macro with IS_NULL_ISA.
2021-08-04 21:04:22 +00:00
BaseCPU.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
CheckerCPU.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
CPUTracers.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
decode_cache.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dummy_checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
DummyChecker.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
exec_context.hh
cpu: Use RegVal for VecElems instead of TheISA::VecElem.
2021-08-11 04:48:02 +00:00
exetrace.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
exetrace.hh
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
func_unit.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
func_unit.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
FuncUnit.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inst_pb_trace.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
inst_pb_trace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inst_res.hh
cpu: Use std::variant to simplify InstResult.
2021-08-11 20:24:54 +00:00
inst_seq.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
InstPBTrace.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inteltrace.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inteltrace.hh
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
nativetrace.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
nativetrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
nop_static_inst.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
nop_static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
null_static_inst.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
null_static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
op_class.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pc_event.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
pc_event.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
profile.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
profile.hh
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
reg_class.cc
cpu: Add a mechanism which lets a reg class name its members.
2021-08-04 06:07:22 +00:00
reg_class.hh
cpu: Rename RegClassInfo to RegClass.
2021-08-09 20:04:51 +00:00
SConscript
arch,cpu,sim: Move the null and nop StaticInstPtrs to their own files.
2021-04-17 22:39:37 +00:00
SConsopts
scons: Turn the ISA and GPU ISA lists into construction variables.
2021-08-07 03:12:56 +00:00
simple_thread.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
simple_thread.hh
cpu: Use RegVal for VecElems instead of TheISA::VecElem.
2021-08-11 04:48:02 +00:00
smt.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst_fwd.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
StaticInstFlags.py
arch,cpu: Get rid of the IsMemRef StaticInst flag.
2020-09-16 12:13:08 +00:00
thread_context.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
thread_context.hh
cpu: Use RegVal for VecElems instead of TheISA::VecElem.
2021-08-11 04:48:02 +00:00
thread_state.cc
fastmodel,cpu: Eliminate the unused getVirtProxy.
2021-07-23 08:59:36 +00:00
thread_state.hh
cpu,fastmodel: Eliminate the now unnecessary initMemProxies method.
2021-07-23 08:59:54 +00:00
timebuf.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
timing_expr.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
timing_expr.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
TimingExpr.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
translation.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
utils.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00