Gabe Black 3f64b374c4 x86: Use operand size 4 when it would be 2 for cmpxchg8b. ...

This means the instruction is treated as cmpxchg8b when the effective
operand size is 16 bits.

Change-Id: I4d9bb295f96097e1746a9bbccb2c579d14738fab
Reviewed-on: https://gem5-review.googlesource.com/6603
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

2017-12-14 00:25:21 +00:00

..

bios

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

insts

cpu: Simplify the rename interface and use RegId

2017-07-05 14:43:49 +00:00

isa

x86: Use operand size 4 when it would be 2 for cmpxchg8b.

2017-12-14 00:25:21 +00:00

linux

syscall-emul: Ignore unimplemented system calls

2017-03-09 22:42:45 +00:00

regs

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

cpuid.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

cpuid.hh

scons: Add warning for missing declarations

2013-02-19 05:56:07 -05:00

decoder_tables.cc

x86: Rework how VEX prefixes are decoded.

2017-05-26 20:01:03 +00:00

decoder.cc

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

decoder.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

emulenv.cc

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

emulenv.hh

gcc: Clean-up of non-C++0x compliant code, first steps

2012-03-19 06:36:09 -04:00

faults.cc

x86,misc: add additional info on faulting X86 instruction, fetched PC

2017-12-08 04:05:58 +00:00

faults.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

interrupts.cc

mips, x86: Refactor some Event subclasses into lambdas

2017-07-12 20:07:05 +00:00

interrupts.hh

mips, x86: Refactor some Event subclasses into lambdas

2017-07-12 20:07:05 +00:00

intmessage.hh

MEM: Remove the Broadcast destination from the packet

2012-04-14 05:45:55 -04:00

isa_traits.hh

style: [patch 3/22] reduce include dependencies in some headers

2016-11-09 14:27:40 -06:00

isa.cc

x86: Split apart x87's FSW and TOP, and add a missing break.

2017-12-06 08:02:25 +00:00

isa.hh

cpu: Added interface for vector reg file

2017-07-05 14:43:49 +00:00

kernel_stats.hh

stats: Get rid of some kernel stats related cruft.

2017-09-11 04:58:38 +00:00

ldstflags.hh

arch,x86,mem: Dynamically determine the ISA for Ruby store check

2014-10-16 05:49:44 -04:00

locked_mem.hh

mem: Signal the local monitor when clearing the global monitor

2017-10-13 08:41:08 +00:00

memhelpers.hh

x86: Rework how "split" loads/stores are handled.

2017-12-13 23:50:53 +00:00

microcode_rom.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

mmapped_ipr.hh

arch: Add support for m5ops using mmapped IPRs

2013-09-30 12:20:43 +02:00

nativetrace.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

nativetrace.hh

Make commenting on close namespace brackets consistent.

2011-01-03 14:35:43 -08:00

pagetable_walker.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

pagetable_walker.hh

sim, x86: Replace EventWrapper use with EventFunctionWrapper

2017-06-20 18:03:21 +00:00

pagetable.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

pagetable.hh

style: [patch 3/22] reduce include dependencies in some headers

2016-11-09 14:27:40 -06:00

process.cc

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

process.hh

sim, x86: Make clone a virtual function

2017-07-17 15:16:32 +00:00

pseudo_inst.cc

syscall_emul: [patch 13/22] add system call retry capability

2015-07-20 09:15:21 -05:00

pseudo_inst.hh

kvm, x86: Adding support for SE mode execution

2014-11-23 18:01:08 -08:00

registers.hh

cpu: Added interface for vector reg file

2017-07-05 14:43:49 +00:00

remote_gdb.cc

base: Refactor the GDB code.

2017-05-18 16:48:09 +00:00

remote_gdb.hh

x86: Fixed remote debugging of simulated code

2017-06-15 21:00:34 +00:00

SConscript

scons: Stop generating inc.d in the isa parser.

2017-10-17 18:57:50 +00:00

SConsopts

copyright: This file need not have had the more restrictive copyright.

2009-02-09 20:10:15 -08:00

stacktrace.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

stacktrace.hh

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

system.cc

style: [patch 3/22] reduce include dependencies in some headers

2016-11-09 14:27:40 -06:00

system.hh

style: [patch 3/22] reduce include dependencies in some headers

2016-11-09 14:27:40 -06:00

tlb.cc

x86: Add stats to X86 TLB

2017-07-17 15:16:16 +00:00

tlb.hh

arch-x86: Add missing override in the X86 TLB

2017-08-30 16:26:19 +00:00

types.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

types.hh

x86: Rework how VEX prefixes are decoded.

2017-05-26 20:01:03 +00:00

utility.cc

style: [patch 3/22] reduce include dependencies in some headers

2016-11-09 14:27:40 -06:00

utility.hh

style: [patch 3/22] reduce include dependencies in some headers

2016-11-09 14:27:40 -06:00

vtophys.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

vtophys.hh

gcc: Clean-up of non-C++0x compliant code, first steps

2012-03-19 06:36:09 -04:00

x86_traits.hh

arch/x86: add support for explicit CC register file

2013-10-15 14:22:44 -04:00

X86ISA.py

arch: Make the ISA class inherit from SimObject

2013-01-07 13:05:35 -05:00

X86LocalApic.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

X86NativeTrace.py

cpu: Put all CPU instruction tracers in a single file

2015-01-25 07:22:17 -05:00

X86System.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

X86TLB.py

x86: add tlb checkpointing

2013-08-07 14:51:17 -05:00