derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

x86: Rework how VEX prefixes are decoded.

Browse Source 
Remove redundant information from the ExtMachInst, hash the vex
information to ensure the decode cache works properly, print the vex info
when printing an ExtMachInst, consider the vex info when comparing two
ExtMachInsts, fold the info from the vex prefixes into existing settings,
remove redundant decode code, handle vex prefixes one byte at a time and
don't bother building up the entire prefix, and let instructions that care
about vex use it in their implementation, instead of developing an entire
parallel decode tree.

This also eliminates the error prone vex immediate decode table which was
incomplete and would result in an out of bounds access for incorrectly
encoded instructions or when the CPU was mispeculating, as it was (as far
as I can tell) redundant with the tables that already existed for two and
three byte opcodes. There were differences, but I think those may have
been mistakes based on the documentation I found.

Also, in 32 bit mode, the VEX prefixes might actually be LDS or LES
instructions which are still legal in that mode. A valid VEX prefix would
look like an LDS/LES with an otherwise invalid modrm encoding, so use that
as a signal to abort processing the VEX and turn the instruction into an
LES/LDS as appropriate.

Change-Id: Icb367eaaa35590692df1c98862f315da4c139f5c
Reviewed-on: https://gem5-review.googlesource.com/3501
Reviewed-by: Joe Gross <joe.gross@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
This commit is contained in:
Gabe Black
2017-05-24 03:09:56 -07:00
parent 91228e9b22
commit 7159ea6698
7 changed files with 181 additions and 1658 deletions
Download Patch File Download Diff File Expand all files Collapse all files

219
src/arch/x86/decoder.cc
View File

@@ -96,19 +96,18 @@ Decoder::process()
case PrefixState:
state = doPrefixState(nextByte);
break;
case TwoByteVexState:
state = doTwoByteVexState(nextByte);
case Vex2Of2State:
state = doVex2Of2State(nextByte);
break;
case ThreeByteVexFirstState:
state = doThreeByteVexFirstState(nextByte);
case Vex2Of3State:
state = doVex2Of3State(nextByte);
break;
case ThreeByteVexSecondState:
state = doThreeByteVexSecondState(nextByte);
case Vex3Of3State:
state = doVex3Of3State(nextByte);
break;
case VexOpcodeState:
state = doVexOpcodeState(nextByte);
break;
case OneByteOpcodeState:
state = doOneByteOpcodeState(nextByte);
break;
@@ -222,19 +221,16 @@ Decoder::doPrefixState(uint8_t nextByte)
DPRINTF(Decoder, "Found Rex prefix %#x.\n", nextByte);
emi.rex = nextByte;
break;
case Vex2Prefix:
DPRINTF(Decoder, "Found VEX two-byte prefix %#x.\n", nextByte);
emi.vex.zero = nextByte;
nextState = TwoByteVexState;
emi.vex.present = 1;
nextState = Vex2Of2State;
break;
case Vex3Prefix:
DPRINTF(Decoder, "Found VEX three-byte prefix %#x.\n", nextByte);
emi.vex.zero = nextByte;
nextState = ThreeByteVexFirstState;
emi.vex.present = 1;
nextState = Vex2Of3State;
break;
case 0:
nextState = OneByteOpcodeState;
break;
@@ -246,42 +242,132 @@ Decoder::doPrefixState(uint8_t nextByte)
}
Decoder::State
Decoder::doTwoByteVexState(uint8_t nextByte)
Decoder::doVex2Of2State(uint8_t nextByte)
{
assert(emi.vex.zero == 0xc5);
consumeByte();
TwoByteVex tbe = 0;
tbe.first = nextByte;
Vex2Of2 vex = nextByte;
emi.vex.first.r = tbe.first.r;
emi.vex.first.x = 1;
emi.vex.first.b = 1;
emi.vex.first.map_select = 1;
emi.rex.r = !vex.r;
emi.vex.second.w = 0;
emi.vex.second.vvvv = tbe.first.vvvv;
emi.vex.second.l = tbe.first.l;
emi.vex.second.pp = tbe.first.pp;
emi.vex.l = vex.l;
emi.vex.v = ~vex.v;
emi.opcode.type = Vex;
return OneByteOpcodeState;
switch (vex.p) {
case 0:
break;
case 1:
emi.legacy.op = 1;
break;
case 2:
emi.legacy.rep = 1;
break;
case 3:
emi.legacy.repne = 1;
break;
}
emi.opcode.type = TwoByteOpcode;
return VexOpcodeState;
}
Decoder::State
Decoder::doThreeByteVexFirstState(uint8_t nextByte)
Decoder::doVex2Of3State(uint8_t nextByte)
{
if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
// This was actually an LDS instruction. Reroute to that path.
emi.vex.present = 0;
emi.opcode.type = OneByteOpcode;
emi.opcode.op = 0xC4;
return processOpcode(ImmediateTypeOneByte, UsesModRMOneByte,
nextByte >= 0xA0 && nextByte <= 0xA3);
}
consumeByte();
emi.vex.first = nextByte;
return ThreeByteVexSecondState;
Vex2Of3 vex = nextByte;
emi.rex.r = !vex.r;
emi.rex.x = !vex.x;
emi.rex.b = !vex.b;
switch (vex.m) {
case 1:
emi.opcode.type = TwoByteOpcode;
break;
case 2:
emi.opcode.type = ThreeByte0F38Opcode;
break;
case 3:
emi.opcode.type = ThreeByte0F3AOpcode;
break;
default:
// These encodings are reserved. Pretend this was an undefined
// instruction so the main decoder will behave correctly, and stop
// trying to interpret bytes.
emi.opcode.type = TwoByteOpcode;
emi.opcode.op = 0x0B;
instDone = true;
return ResetState;
}
return Vex3Of3State;
}
Decoder::State
Decoder::doThreeByteVexSecondState(uint8_t nextByte)
Decoder::doVex3Of3State(uint8_t nextByte)
{
if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
// This was actually an LES instruction. Reroute to that path.
emi.vex.present = 0;
emi.opcode.type = OneByteOpcode;
emi.opcode.op = 0xC5;
return processOpcode(ImmediateTypeOneByte, UsesModRMOneByte,
nextByte >= 0xA0 && nextByte <= 0xA3);
}
consumeByte();
emi.vex.second = nextByte;
emi.opcode.type = Vex;
return OneByteOpcodeState;
Vex3Of3 vex = nextByte;
emi.rex.w = vex.w;
emi.vex.l = vex.l;
emi.vex.v = ~vex.v;
switch (vex.p) {
case 0:
break;
case 1:
emi.legacy.op = 1;
break;
case 2:
emi.legacy.rep = 1;
break;
case 3:
emi.legacy.repne = 1;
break;
}
return VexOpcodeState;
}
Decoder::State
Decoder::doVexOpcodeState(uint8_t nextByte)
{
DPRINTF(Decoder, "Found VEX opcode %#x.\n", nextByte);
emi.opcode.op = nextByte;
switch (emi.opcode.type) {
case TwoByteOpcode:
return processOpcode(ImmediateTypeTwoByte, UsesModRMTwoByte);
case ThreeByte0F38Opcode:
return processOpcode(ImmediateTypeThreeByte0F38,
UsesModRMThreeByte0F38);
case ThreeByte0F3AOpcode:
return processOpcode(ImmediateTypeThreeByte0F3A,
UsesModRMThreeByte0F3A);
default:
panic("Unrecognized opcode type %d.\n", emi.opcode.type);
}
}
// Load the first opcode byte. Determine if there are more opcode bytes, and
@@ -292,14 +378,9 @@ Decoder::doOneByteOpcodeState(uint8_t nextByte)
State nextState = ErrorState;
consumeByte();
if (emi.vex.zero != 0) {
DPRINTF(Decoder, "Found VEX opcode %#x.\n", nextByte);
emi.opcode.op = nextByte;
const uint8_t opcode_map = emi.vex.first.map_select;
nextState = processExtendedOpcode(ImmediateTypeVex[opcode_map]);
} else if (nextByte == 0x0f) {
nextState = TwoByteOpcodeState;
if (nextByte == 0x0f) {
DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
nextState = TwoByteOpcodeState;
} else {
DPRINTF(Decoder, "Found one byte opcode %#x.\n", nextByte);
emi.opcode.type = OneByteOpcode;
@@ -421,54 +502,6 @@ Decoder::processOpcode(ByteTable &immTable, ByteTable &modrmTable,
return nextState;
}
Decoder::State
Decoder::processExtendedOpcode(ByteTable &immTable)
{
//Figure out the effective operand size. This can be overriden to
//a fixed value at the decoder level.
int logOpSize;
if (emi.vex.second.w)
logOpSize = 3; // 64 bit operand size
else if (emi.vex.second.pp == 1)
logOpSize = altOp;
else
logOpSize = defOp;
//Set the actual op size
emi.opSize = 1 << logOpSize;
//Figure out the effective address size. This can be overriden to
//a fixed value at the decoder level.
int logAddrSize;
if (emi.legacy.addr)
logAddrSize = altAddr;
else
logAddrSize = defAddr;
//Set the actual address size
emi.addrSize = 1 << logAddrSize;
//Figure out the effective stack width. This can be overriden to
//a fixed value at the decoder level.
emi.stackSize = 1 << stack;
//Figure out how big of an immediate we'll retreive based
//on the opcode.
const uint8_t opcode = emi.opcode.op;
if (emi.vex.zero == 0xc5 || emi.vex.zero == 0xc4) {
int immType = immTable[opcode];
// Assume 64-bit mode;
immediateSize = SizeTypeToSize[2][immType];
}
if (opcode == 0x77) {
instDone = true;
return ResetState;
}
return ModRMState;
}
//Get the ModRM byte and determine what displacement, if any, there is.
//Also determine whether or not to get the SIB byte, displacement, or
//immediate next.

14
src/arch/x86/decoder.hh
View File

@@ -178,9 +178,10 @@ class Decoder
ResetState,
FromCacheState,
PrefixState,
TwoByteVexState,
ThreeByteVexFirstState,
ThreeByteVexSecondState,
Vex2Of2State,
Vex2Of3State,
Vex3Of3State,
VexOpcodeState,
OneByteOpcodeState,
TwoByteOpcodeState,
ThreeByte0F38OpcodeState,
@@ -199,9 +200,10 @@ class Decoder
State doResetState();
State doFromCacheState();
State doPrefixState(uint8_t);
State doTwoByteVexState(uint8_t);
State doThreeByteVexFirstState(uint8_t);
State doThreeByteVexSecondState(uint8_t);
State doVex2Of2State(uint8_t);
State doVex2Of3State(uint8_t);
State doVex3Of3State(uint8_t);
State doVexOpcodeState(uint8_t);
State doOneByteOpcodeState(uint8_t);
State doTwoByteOpcodeState(uint8_t);
State doThreeByte0F38OpcodeState(uint8_t);

70
src/arch/x86/decoder_tables.cc
View File

@@ -284,74 +284,4 @@ namespace X86ISA
/* E */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* F */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
};
const Decoder::ByteTable Decoder::ImmediateTypeVex[10] =
{
// Table for opcode map 1
{
//LSB
// MSB 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F
/* 0 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 1 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 2 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 3 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 4 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 5 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 6 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 7 */ BY, BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 8 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 9 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* A */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* B */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* C */ 0 , 0 , BY, 0 , BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* D */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* E */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* F */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
},
// Table for opcode map 2
{
//LSB
// MSB 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F
/* 0 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 1 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 2 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 3 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 4 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 5 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 6 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 7 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 8 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 9 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* A */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* B */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* C */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* D */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* E */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* F */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
},
// Table for opcode map 3
{
//LSB
// MSB 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F
/* 0 */ 0 , 0 , 0 , 0 , BY, BY, BY, 0 , BY, BY, BY, BY, BY, BY, BY, BY,
/* 1 */ 0 , 0 , 0 , 0 , BY, BY, BY, BY, BY, BY, 0 , 0 , 0 , BY, 0 , 0 ,
/* 2 */ BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 3 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 4 */ BY, BY, BY, 0 , BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 5 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 6 */ BY, BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 7 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 8 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 9 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* A */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* B */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* C */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* D */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY,
/* E */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* F */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
},
{}, {}, {}, {}, {}, {}, {}
};
}

10
src/arch/x86/isa/bitfields.isa
View File

@@ -88,11 +88,5 @@ def bitfield MODE mode;
def bitfield MODE_MODE mode.mode;
def bitfield MODE_SUBMODE mode.submode;
def bitfield VEX_R vex.first.r;
def bitfield VEX_X vex.first.x;
def bitfield VEX_B vex.first.b;
def bitfield VEX_MAP vex.first.map_select;
def bitfield VEX_W vex.second.w;
def bitfield VEX_VVVV vex.second.vvvv;
def bitfield VEX_L vex.second.l;
def bitfield VEX_PP vex.second.pp;
def bitfield VEX_V vex.v;
def bitfield VEX_L vex.l;

1
src/arch/x86/isa/decoder/decoder.isa
View File

@@ -49,7 +49,6 @@ decode LEGACY_LOCK default Unknown::unknown()
##include "two_byte_opcodes.isa"
##include "three_byte_0f38_opcodes.isa"
##include "three_byte_0f3a_opcodes.isa"
##include "vex_opcodes.isa"
}
//Lock prefix
##include "locked_opcodes.isa"

1431
src/arch/x86/isa/decoder/vex_opcodes.isa
View File

File diff suppressed because it is too large Load Diff

94
src/arch/x86/types.hh
View File

@@ -106,47 +106,45 @@ namespace X86ISA
Bitfield<0> b;
EndBitUnion(Rex)
BitUnion(uint32_t, ThreeByteVex)
Bitfield<7,0> zero;
SubBitUnion(first, 15, 8)
// Inverted one-bit extension of ModRM reg field
Bitfield<15> r;
// Inverted one-bit extension of SIB index field
Bitfield<14> x;
// Inverted one-bit extension, r/m field or SIB base field
Bitfield<13> b;
// Opcode map select
Bitfield<12, 8> map_select;
EndSubBitUnion(first)
SubBitUnion(second, 23, 16)
// Default operand size override for a general purpose register to
// 64-bit size in 64-bit mode; operand configuration specifier for
// certain YMM/XMM-based operations.
Bitfield<23> w;
// Source or destination register selector, in ones' complement
// format
Bitfield<22, 19> vvvv;
// Vector length specifier
Bitfield<18> l;
// Implied 66, F2, or F3 opcode extension
Bitfield<17, 16> pp;
EndSubBitUnion(second)
EndBitUnion(ThreeByteVex)
BitUnion8(Vex2Of3)
// Inverted bits from the REX prefix.
Bitfield<7> r;
Bitfield<6> x;
Bitfield<5> b;
// Selector for what would be two or three byte opcode types.
Bitfield<4, 0> m;
EndBitUnion(Vex2Of3)
BitUnion16(TwoByteVex)
Bitfield<7,0> zero;
SubBitUnion(first, 15, 8)
// Inverted one-bit extension of ModRM reg field
Bitfield<15> r;
// Source or destination register selector, in ones' complement
// format
Bitfield<14, 11> vvvv;
// Vector length specifier
Bitfield<10> l;
// Implied 66, F2, or F3 opcode extension
Bitfield<9, 8> pp;
EndSubBitUnion(first)
EndBitUnion(TwoByteVex)
BitUnion8(Vex3Of3)
// Bit from the REX prefix.
Bitfield<7> w;
// Inverted extra register index.
Bitfield<6, 3> v;
// Vector length specifier.
Bitfield<2> l;
// Implied 66, F2, or F3 opcode prefix.
Bitfield<1, 0> p;
EndBitUnion(Vex3Of3)
BitUnion8(Vex2Of2)
// Inverted bit from the REX prefix.
Bitfield<7> r;
// Inverted extra register index.
Bitfield<6, 3> v;
// Vector length specifier
Bitfield<2> l;
// Implied 66, F2, or F3 opcode prefix.
Bitfield<1, 0> p;
EndBitUnion(Vex2Of2)
BitUnion8(VexInfo)
// Extra register index.
Bitfield<6, 3> v;
// Vector length specifier.
Bitfield<2> l;
// Whether the VEX prefix was used.
Bitfield<0> present;
EndBitUnion(VexInfo)
enum OpcodeType {
BadOpcode,
@@ -154,7 +152,6 @@ namespace X86ISA
TwoByteOpcode,
ThreeByte0F38Opcode,
ThreeByte0F3AOpcode,
Vex,
};
static inline const char *
@@ -171,8 +168,6 @@ namespace X86ISA
return "three byte 0f38";
case ThreeByte0F3AOpcode:
return "three byte 0f3a";
case Vex:
return "vex";
default:
return "unrecognized!";
}
@@ -207,9 +202,7 @@ namespace X86ISA
//Prefixes
LegacyPrefixVector legacy;
Rex rex;
// We use the following field for encoding both two byte and three byte
// escape sequences
ThreeByteVex vex;
VexInfo vex;
//This holds all of the bytes of the opcode
struct
@@ -248,7 +241,7 @@ namespace X86ISA
"immediate = %#x,\n\tdisplacement = %#x\n\t"
"dispSize = %d}\n",
(uint8_t)emi.legacy, (uint8_t)emi.rex,
(uint32_t)emi.vex,
(uint8_t)emi.vex,
opcodeTypeToStr(emi.opcode.type), (uint8_t)emi.opcode.op,
(uint8_t)emi.modRM, (uint8_t)emi.sib,
emi.immediate, emi.displacement, emi.dispSize);
@@ -262,6 +255,8 @@ namespace X86ISA
return false;
if (emi1.rex != emi2.rex)
return false;
if (emi1.vex != emi2.vex)
return false;
if (emi1.opcode.type != emi2.opcode.type)
return false;
if (emi1.opcode.op != emi2.opcode.op)
@@ -357,8 +352,9 @@ namespace std {
template<>
struct hash<X86ISA::ExtMachInst> {
size_t operator()(const X86ISA::ExtMachInst &emi) const {
return (((uint64_t)emi.legacy << 40) |
((uint64_t)emi.rex << 32) |
return (((uint64_t)emi.legacy << 48) |
((uint64_t)emi.rex << 40) |
((uint64_t)emi.vex << 32) |
((uint64_t)emi.modRM << 24) |
((uint64_t)emi.sib << 16) |
((uint64_t)emi.opcode.type << 8) |