mips, x86: Refactor some Event subclasses into lambdas

Change-Id: I09570e569efe55f5502bc201e03456738999e714
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3920
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Sean Wilson
2017-06-16 16:48:36 -05:00
parent 373054232e
commit 1b7bf4ed75
4 changed files with 16 additions and 75 deletions

View File

@@ -523,7 +523,9 @@ ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay)
cp0Updated = true;
//schedule UPDATE
CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
auto cp0_event = new EventFunctionWrapper(
[this, cpu]{ processCP0Event(cpu, UpdateCP0); },
"Coprocessor-0 event", true, Event::CPU_Tick_Pri);
cpu->schedule(cp0_event, cpu->clockEdge(delay));
}
}
@@ -557,40 +559,17 @@ ISA::updateCPU(BaseCPU *cpu)
cp0Updated = false;
}
ISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type)
: Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type)
{ }
void
ISA::CP0Event::process()
ISA::processCP0Event(BaseCPU *cpu, CP0EventType cp0EventType)
{
switch (cp0EventType)
{
case UpdateCP0:
cp0->updateCPU(cpu);
updateCPU(cpu);
break;
}
}
const char *
ISA::CP0Event::description() const
{
return "Coprocessor-0 event";
}
void
ISA::CP0Event::scheduleEvent(Cycles delay)
{
cpu->reschedule(this, cpu->clockEdge(delay), true);
}
void
ISA::CP0Event::unscheduleEvent()
{
if (scheduled())
squash();
}
}
MipsISA::ISA *

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@@ -118,31 +118,8 @@ namespace MipsISA
UpdateCP0
};
// Declare A CP0Event Class for scheduling
class CP0Event : public Event
{
protected:
ISA::CP0 *cp0;
BaseCPU *cpu;
CP0EventType cp0EventType;
Fault fault;
public:
/** Constructs a CP0 event. */
CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type);
/** Process this event. */
virtual void process();
/** Returns the description of this event. */
const char *description() const;
/** Schedule This Event */
void scheduleEvent(Cycles delay);
/** Unschedule This Event */
void unscheduleEvent();
};
/** Process a CP0 event */
void processCP0Event(BaseCPU *cpu, CP0EventType);
// Schedule a CP0 Update Event
void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
@@ -151,9 +128,6 @@ namespace MipsISA
// and if necessary alert the CPU
void updateCPU(BaseCPU *cpu);
// Keep a List of CPU Events that need to be deallocated
std::queue<CP0Event*> cp0EventRemoveList;
static std::string miscRegNames[NumMiscRegs];
public:

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@@ -588,7 +588,7 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
X86ISA::Interrupts::Interrupts(Params * p)
: BasicPioDevice(p, PageBytes), IntDevice(this, p->int_latency),
apicTimerEvent(this),
apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
pendingSmi(false), smiVector(0),
pendingNmi(false), nmiVector(0),
pendingExtInt(false), extIntVector(0),
@@ -767,3 +767,9 @@ X86LocalApicParams::create()
{
return new X86ISA::Interrupts(this);
}
void
X86ISA::Interrupts::processApicTimerEvent() {
if (triggerTimerInterrupt())
setReg(APIC_INITIAL_COUNT, readReg(APIC_INITIAL_COUNT));
}

View File

@@ -92,26 +92,8 @@ class Interrupts : public BasicPioDevice, IntDevice
/*
* Timing related stuff.
*/
class ApicTimerEvent : public Event
{
private:
Interrupts *localApic;
public:
ApicTimerEvent(Interrupts *_localApic) :
Event(), localApic(_localApic)
{}
void process()
{
assert(localApic);
if (localApic->triggerTimerInterrupt()) {
localApic->setReg(APIC_INITIAL_COUNT,
localApic->readReg(APIC_INITIAL_COUNT));
}
}
};
ApicTimerEvent apicTimerEvent;
EventFunctionWrapper apicTimerEvent;
void processApicTimerEvent();
/*
* A set of variables to keep track of interrupts that don't go through