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x86,misc: add additional info on faulting X86 instruction, fetched PC

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Print faulting instruction for unmapped address panic in faults.cc
and print extra info about corresponding fetched PC in base.cc.

Change-Id: Id9e15d3e88df2ad6b809fb3cf9f6ae97e9e97e0f
Reviewed-on: https://gem5-review.googlesource.com/6461
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Matt Sinclair
2017-12-06 20:29:11 -05:00
parent 66a55ce3ff
commit bd7eadb467
2 changed files with 14 additions and 5 deletions
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11
src/arch/x86/faults.cc
View File

@@ -44,6 +44,7 @@
#include "arch/x86/generated/decoder.hh"
#include "arch/x86/isa_traits.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Faults.hh"
@@ -161,7 +162,15 @@ namespace X86ISA
modeStr = "write";
else
modeStr = "read";
panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
// print information about what we are panic'ing on
if (!inst) {
panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
} else {
panic("Tried to %s unmapped address %#x.\nPC: %#x, Instr: %s",
modeStr, addr, tc->pcState().pc(),
inst->disassemble(tc->pcState().pc(), debugSymbolTable));
}
}
}

8
src/cpu/simple/base.cc
View File

@@ -475,13 +475,13 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
SimpleThread* thread = t_info.thread;
Addr instAddr = thread->instAddr();
Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
// set up memory request for instruction fetch
DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr, fetchPC);
Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
instAddr);
req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH,
instMasterId(), instAddr);
}