Gabe Black 3f64b374c4 x86: Use operand size 4 when it would be 2 for cmpxchg8b. ...

This means the instruction is treated as cmpxchg8b when the effective
operand size is 16 bits.

Change-Id: I4d9bb295f96097e1746a9bbccb2c579d14738fab
Reviewed-on: https://gem5-review.googlesource.com/6603
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

2017-12-14 00:25:21 +00:00

..

alpha

cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.

2017-12-13 23:51:05 +00:00

arm

arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.

2017-12-13 23:51:59 +00:00

generic

arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.

2017-12-13 23:51:59 +00:00

hsail

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

mips

cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.

2017-12-13 23:51:05 +00:00

null

scons: Stop generating inc.d in the isa parser.

2017-10-17 18:57:50 +00:00

power

cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.

2017-12-13 23:51:05 +00:00

riscv

cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.

2017-12-13 23:51:05 +00:00

sparc

arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.

2017-12-13 23:51:59 +00:00

x86

x86: Use operand size 4 when it would be 2 for cmpxchg8b.

2017-12-14 00:25:21 +00:00

isa_parser.py

alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.

2017-11-02 09:43:35 +00:00

micro_asm_test.py

Add a second section to make sure the ROM is extended properly.

2007-05-31 22:21:21 +00:00

micro_asm.py

scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access

2009-09-22 15:24:16 -07:00

SConscript

scons: Move Transform and termcap functionality into their own files.

2017-11-10 13:17:29 +00:00