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cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.

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Neither of these were used, particularly memAccInst.

Change-Id: I4ac9e44cf624e5de42519d586d7b699f08a2cdfc
Reviewed-on: https://gem5-review.googlesource.com/6601
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Gabe Black
2017-12-12 23:12:30 -08:00
parent 36d5e89255
commit 93a168c25e
11 changed files with 5 additions and 187 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
src/arch/alpha/isa/mem.isa
View File

@@ -130,7 +130,6 @@ def template LoadStoreDeclare {{
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault eaComp(ExecContext *, Trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
@@ -144,27 +143,6 @@ def template LoadStoreConstructor {{
}
}};
def template EACompExecute {{
Fault %(class_name)s::eaComp(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
if (fault == NoFault) {
%(op_wb)s;
xc->setEA(EA);
}
return fault;
}
}};
def template LoadExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
@@ -467,7 +445,6 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
LoadStoreConstructor.subst(iop),
decode_template.subst(iop),
fullExecTemplate.subst(iop)
+ EACompExecute.subst(iop)
+ initiateAccTemplate.subst(iop)
+ completeAccTemplate.subst(iop))
}};

29
src/arch/mips/isa/formats/mem.isa
View File

@@ -143,7 +143,6 @@ def template LoadStoreDeclare {{
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault eaComp(ExecContext *, Trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
Fault completeAcc(Packet *, ExecContext *, Trace::InstRecord *) const;
};
@@ -158,34 +157,6 @@ def template LoadStoreConstructor {{
}
}};
def template EACompExecute {{
Fault
%(class_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
if (this->isFloating()) {
%(fp_enable_check)s;
if(fault != NoFault)
return fault;
}
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
// NOTE: Trace Data is written using execute or completeAcc templates
if (fault == NoFault) {
xc->setEA(EA);
}
return fault;
}
}};
def template LoadExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const

1
src/arch/mips/isa/formats/util.isa
View File

@@ -71,7 +71,6 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
LoadStoreConstructor.subst(iop),
decode_template.subst(iop),
fullExecTemplate.subst(iop)
+ EACompExecute.subst(iop)
+ initiateAccTemplate.subst(iop)
+ completeAccTemplate.subst(iop))
}};

19
src/arch/power/insts/mem.hh
View File

@@ -45,19 +45,11 @@ class MemOp : public PowerStaticInst
/// Memory request flags. See mem_req_base.hh.
unsigned memAccessFlags;
/// Pointer to EAComp object.
const StaticInstPtr eaCompPtr;
/// Pointer to MemAcc object.
const StaticInstPtr memAccPtr;
/// Constructor
MemOp(const char *mnem, MachInst _machInst, OpClass __opClass,
StaticInstPtr _eaCompPtr = nullStaticInstPtr,
StaticInstPtr _memAccPtr = nullStaticInstPtr)
MemOp(const char *mnem, MachInst _machInst, OpClass __opClass)
: PowerStaticInst(mnem, _machInst, __opClass),
memAccessFlags(0),
eaCompPtr(_eaCompPtr),
memAccPtr(_memAccPtr)
memAccessFlags(0)
{
}
@@ -75,11 +67,8 @@ class MemDispOp : public MemOp
int16_t disp;
/// Constructor
MemDispOp(const char *mnem, MachInst _machInst, OpClass __opClass,
StaticInstPtr _eaCompPtr = nullStaticInstPtr,
StaticInstPtr _memAccPtr = nullStaticInstPtr)
: MemOp(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
disp(machInst.d)
MemDispOp(const char *mnem, MachInst _machInst, OpClass __opClass)
: MemOp(mnem, _machInst, __opClass), disp(machInst.d)
{
}

27
src/arch/riscv/isa/formats/amo.isa
View File

@@ -52,7 +52,6 @@ def template AtomicMemOpDeclare {{
%(class_name)sLoad(ExtMachInst machInst, %(class_name)s *_p);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault eaComp(ExecContext *, Trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const;
@@ -65,7 +64,6 @@ def template AtomicMemOpDeclare {{
%(class_name)sStore(ExtMachInst machInst, %(class_name)s *_p);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault eaComp(ExecContext *, Trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const;
@@ -212,27 +210,6 @@ def template AtomicMemOpStoreExecute {{
}
}};
def template AtomicMemOpEACompExecute {{
Fault
%(class_name)s::%(class_name)s%(op_name)s::eaComp(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
if (fault == NoFault) {
%(op_wb)s;
xc->setEA(EA);
}
return fault;
}
}};
def template AtomicMemOpLoadInitiateAcc {{
Fault %(class_name)s::%(class_name)sLoad::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
@@ -349,7 +326,6 @@ def format LoadReserved(memacc_code, postacc_code={{ }}, ea_code={{EA = Rs1;}},
decoder_output = LRSCConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = LoadExecute.subst(iop) \
+ EACompExecute.subst(iop) \
+ LoadInitiateAcc.subst(iop) \
+ LoadCompleteAcc.subst(iop)
}};
@@ -368,7 +344,6 @@ def format StoreCond(memacc_code, postacc_code={{ }}, ea_code={{EA = Rs1;}},
decoder_output = LRSCConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = StoreCondExecute.subst(iop) \
+ EACompExecute.subst(iop) \
+ StoreInitiateAcc.subst(iop) \
+ StoreCondCompleteAcc.subst(iop)
}};
@@ -387,7 +362,6 @@ def format AtomicMemOp(load_code, store_code, ea_code, load_flags=[],
load_inst_flags)
decoder_output += AtomicMemOpLoadConstructor.subst(load_iop)
exec_output += AtomicMemOpLoadExecute.subst(load_iop) \
+ AtomicMemOpEACompExecute.subst(load_iop) \
+ AtomicMemOpLoadInitiateAcc.subst(load_iop) \
+ AtomicMemOpLoadCompleteAcc.subst(load_iop)
@@ -397,7 +371,6 @@ def format AtomicMemOp(load_code, store_code, ea_code, load_flags=[],
store_inst_flags)
decoder_output += AtomicMemOpStoreConstructor.subst(store_iop)
exec_output += AtomicMemOpStoreExecute.subst(store_iop) \
+ AtomicMemOpEACompExecute.subst(store_iop) \
+ AtomicMemOpStoreInitiateAcc.subst(store_iop) \
+ AtomicMemOpStoreCompleteAcc.subst(store_iop)
}};

22
src/arch/riscv/isa/formats/mem.isa
View File

@@ -44,7 +44,6 @@ def template LoadStoreDeclare {{
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault eaComp(ExecContext *, Trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
@@ -60,26 +59,6 @@ def template LoadStoreConstructor {{
}
}};
def template EACompExecute {{
Fault
%(class_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
if (fault == NoFault) {
%(op_wb)s;
xc->setEA(EA);
}
return fault;
}
}};
let {{
def LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
inst_flags, base_class, postacc_code='', decode_template=BasicDecode,
@@ -109,7 +88,6 @@ def LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
LoadStoreConstructor.subst(iop),
decode_template.subst(iop),
fullExecTemplate.subst(iop) +
EACompExecute.subst(iop) +
initiateAccTemplate.subst(iop) +
completeAccTemplate.subst(iop))
}};

3
src/arch/sparc/isa/formats/mem/basicmem.isa
View File

@@ -46,7 +46,6 @@ def template MemDeclare {{
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault eaComp(ExecContext *, Trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const;
@@ -71,8 +70,6 @@ let {{
exec_output = doDualSplitExecute(code, postacc_code, addrCalcReg,
addrCalcImm, execute, faultCode, name, name + "Imm",
Name, Name + "Imm", asi, opt_flags)
exec_output += EACompExecute.subst(iop);
exec_output += EACompExecute.subst(iop_imm);
return (header_output, decoder_output, exec_output, decode_block)
}};

2
src/arch/sparc/isa/formats/mem/swap.isa
View File

@@ -164,7 +164,7 @@ let {{
"EA_trunc" : TruncateEA}
exec_output = doSplitExecute(execute, name, Name, mem_flags,
["IsStoreConditional"], microParams);
return (header_output, decoder_output, exec_output + EACompExecute.subst(iop), decode_block)
return (header_output, decoder_output, exec_output, decode_block)
}};

22
src/arch/sparc/isa/formats/mem/util.isa
View File

@@ -163,28 +163,6 @@ def template StoreCompleteAcc {{
}
}};
def template EACompExecute {{
Fault
%(class_name)s::eaComp(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
%(fault_check)s;
// NOTE: Trace Data is written using execute or completeAcc templates
if (fault == NoFault) {
%(EA_trunc)s
xc->setEA(EA);
}
return fault;
}
}};
// Here are some code snippets which check for various fault conditions
let {{
LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc]

19
src/cpu/o3/dyn_inst.hh
View File

@@ -429,25 +429,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
panic("MIPS MT not defined for O3 CPU.\n");
}
#endif
public:
/** Calculates EA part of a memory instruction. Currently unused,
* though it may be useful in the future if we want to split
* memory operations into EA calculation and memory access parts.
*/
Fault calcEA()
{
return this->staticInst->eaCompInst()->execute(this, this->traceData);
}
/** Does the memory access part of a memory instruction. Currently unused,
* though it may be useful in the future if we want to split
* memory operations into EA calculation and memory access parts.
*/
Fault memAccess()
{
return this->staticInst->memAccInst()->execute(this, this->traceData);
}
};
#endif // __CPU_O3_ALPHA_DYN_INST_HH__

25
src/cpu/static_inst.hh
View File

@@ -203,28 +203,8 @@ class StaticInst : public RefCounted, public StaticInstFlags
const RegId& srcRegIdx(int i) const { return _srcRegIdx[i]; }
/// Pointer to a statically allocated "null" instruction object.
/// Used to give eaCompInst() and memAccInst() something to return
/// when called on non-memory instructions.
static StaticInstPtr nullStaticInstPtr;
/**
* Memory references only: returns "fake" instruction representing
* the effective address part of the memory operation. Used to
* obtain the dependence info (numSrcRegs and srcRegIdx[]) for
* just the EA computation.
*/
virtual const
StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
/**
* Memory references only: returns "fake" instruction representing
* the memory access part of the memory operation. Used to
* obtain the dependence info (numSrcRegs and srcRegIdx[]) for
* just the memory access (not the EA computation).
*/
virtual const
StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
/// The binary machine instruction.
const ExtMachInst machInst;
@@ -272,11 +252,6 @@ class StaticInst : public RefCounted, public StaticInstFlags
virtual Fault execute(ExecContext *xc,
Trace::InstRecord *traceData) const = 0;
virtual Fault eaComp(ExecContext *xc,
Trace::InstRecord *traceData) const
{
panic("eaComp not defined!");
}
virtual Fault initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const