Gabe Black 93a168c25e cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst. ...

Neither of these were used, particularly memAccInst.

Change-Id: I4ac9e44cf624e5de42519d586d7b699f08a2cdfc
Reviewed-on: https://gem5-review.googlesource.com/6601
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

2017-12-13 23:51:05 +00:00

..

freebsd

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

isa

cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.

2017-12-13 23:51:05 +00:00

linux

syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations

2017-02-27 14:10:15 -05:00

AlphaInterrupts.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

AlphaISA.py

arch, cpu: Add support for flattening misc register indexes.

2014-01-24 15:29:30 -06:00

AlphaSystem.py

alpha: Remove ALPHA tru64 support and associated tests

2016-11-17 04:54:14 -05:00

AlphaTLB.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

aout_machdep.h

style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs

2008-09-10 14:26:15 -04:00

decoder.cc

ISA,CPU: Generalize and split out the components of the decode cache.

2012-05-26 13:45:12 -07:00

decoder.hh

isa: Add parameter to pick different decoder inside ISA

2015-10-09 14:50:54 -05:00

ecoff_machdep.h

…

ev5.cc

sim: don't ignore SIG_TRAP

2016-01-17 18:27:46 -08:00

ev5.hh

Alpha: Pull the MiscRegFile fully into the ISA object.

2009-07-08 23:02:22 -07:00

faults.cc

arch: ISA parser additions of vector registers

2017-07-05 14:43:49 +00:00

faults.hh

arch: ISA parser additions of vector registers

2017-07-05 14:43:49 +00:00

idle_event.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

idle_event.hh

…

interrupts.cc

Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.

2008-10-12 09:09:56 -07:00

interrupts.hh

isa: Modify get/check interrupt routines

2016-07-21 17:19:15 +01:00

ipr.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

ipr.hh

style: Make a style pass over the whole arch/alpha directory.

2008-09-27 21:03:48 -07:00

isa_traits.hh

arch: Cleanup unused ISA traits constants

2014-09-03 07:42:21 -04:00

isa.cc

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

isa.hh

cpu: Added interface for vector reg file

2017-07-05 14:43:49 +00:00

kernel_stats.cc

stats: Move the swpipl function into the Alpha kernel stats.

2017-09-11 04:59:01 +00:00

kernel_stats.hh

stats: Move the swpipl function into the Alpha kernel stats.

2017-09-11 04:59:01 +00:00

locked_mem.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

microcode_rom.hh

CPU: Create a microcode ROM object in the CPU which is defined by the ISA.

2008-10-12 15:59:21 -07:00

mmapped_ipr.hh

arch: Add support for m5ops using mmapped IPRs

2013-09-30 12:20:43 +02:00

mt.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

osfpal.cc

style: Make a style pass over the whole arch/alpha directory.

2008-09-27 21:03:48 -07:00

osfpal.hh

style: Make a style pass over the whole arch/alpha directory.

2008-09-27 21:03:48 -07:00

pagetable.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

pagetable.hh

misc: Remove redundant compiler-specific defines

2015-10-12 04:07:59 -04:00

process.cc

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

process.hh

alpha: Move some initialization logic from loadState into unserialize.

2017-09-21 17:43:50 +00:00

pseudo_inst.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

registers.hh

cpu: Added interface for vector reg file

2017-07-05 14:43:49 +00:00

regredir.cc

SE/FS: Get rid of uses of FULL_SYSTEM in Alpha.

2011-11-01 04:01:14 -07:00

regredir.hh

Registers: Add a registers.hh file as an ISA switched header.

2009-07-08 23:02:21 -07:00

remote_gdb.cc

base: Refactor the GDB code.

2017-05-18 16:48:09 +00:00

remote_gdb.hh

arch-alpha: Add missing overrides

2017-08-30 16:26:19 +00:00

SConscript

scons: Stop generating inc.d in the isa parser.

2017-10-17 18:57:50 +00:00

SConsopts

alpha: get rid of all turbolaser remnants

2009-04-08 22:22:49 -07:00

stacktrace.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

stacktrace.hh

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

system.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

system.hh

misc: Add explicit overrides and fix other clang >= 3.5 issues

2015-10-12 04:08:01 -04:00

tlb.cc

stats: Fixing regStats function for some SimObjects

2016-06-06 17:16:43 +01:00

tlb.hh

misc: Add explicit overrides and fix other clang >= 3.5 issues

2015-10-12 04:08:01 -04:00

types.hh

arch: get rid of unused LargestRead typedef

2016-01-17 18:27:46 -08:00

utility.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

utility.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

vtophys.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

vtophys.hh

MEM: Make port proxies use references rather than pointers

2012-02-24 11:45:30 -05:00