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  • 2f7421b12b EXTRAS now points to src instead of needing 'src' subdir. Steve Reinhardt 2008-02-11 08:04:01 -08:00
  • 476a2ee950 Wait to set BUILD_DIR until *after* env is copied. Steve Reinhardt 2008-02-11 07:47:44 -08:00
  • 4c7eb21119 Bus: Only update port cache when there is an item to update it with. Nicolas Zea 2008-02-10 19:41:03 -05:00
  • d167e2bb97 IGbE: Fix a couple of bugs. Ali Saidi 2008-02-10 19:32:12 -05:00
  • 9d7a69c582 Fix #include lines for renamed cache files. Steve Reinhardt 2008-02-10 14:45:25 -08:00
  • d56e77c180 Rename cache files for brevity and consistency with rest of tree. Steve Reinhardt 2008-02-10 14:15:42 -08:00
  • 6cc1573923 Make the Event::description() a const function Stephen Hines 2008-02-06 16:32:40 -05:00
  • 0ccf9a2c37 Add base ARM code to M5 Stephen Hines 2008-02-05 23:44:13 -05:00
  • b96631e1a0 Cleaned up os.path imports a bit. Steve Reinhardt 2008-02-05 17:43:45 -08:00
  • d725ff450d Make EXTRAS work for SConsopts too. Requires pushing source files down into 'src' subdir relative to directory listed in EXTRAS. Steve Reinhardt 2008-02-05 17:40:08 -08:00
  • ca313e2303 X86: Put an SMBios/DMI table in memory. This is basically just the header right now, but there's an untested mechanism in place to fill out the table and make sure everything is updated correctly. Gabe Black 2008-01-23 15:28:54 -05:00
  • 423bbe6499 X86: Optomize the bit scanning instruction microassembly a little. More can be done. Gabe Black 2008-01-23 08:18:27 -05:00
  • 60c2d98fc0 X86: Implement and attach the BSR and BSF instructions. Gabe Black 2008-01-22 00:10:33 -05:00
  • f809637011 X86: Fill out group17 in the decoder. Gabe Black 2008-01-21 16:27:40 -05:00
  • 657b52fea1 X86: Use the existing boot_osflags instead of duplicating it. Gabe Black 2008-01-21 04:32:34 -05:00
  • 48295aa514 Update long o3 regressions for o3 change in previous changeset Ali Saidi 2008-01-16 11:11:55 -05:00
  • a1d5beab95 Update O3 ref outputs: very minor stats change due to previous cset. (from Steve on behalf of m5test). Steve Reinhardt 2008-01-15 13:13:08 -05:00
  • 0b6876a0c0 The reason is that the event is supposed to put the instructions ready to execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state. Ke Meng 2008-01-14 11:47:32 -05:00
  • c08b7802a9 X86: Redo the bit test instructions. Gabe Black 2008-01-12 06:41:32 -05:00
  • b705eba6e5 X86: Fix the wrmsr instruction. Gabe Black 2008-01-12 06:40:55 -05:00
  • 0ee67d4210 X86: Make the effective segment base shadow the regular one, not the selector. Gabe Black 2008-01-12 06:40:10 -05:00
  • 223e48e6ae X86: Make the IO ports work using extra physical address lines. Add a serial port. Gabe Black 2008-01-12 06:39:15 -05:00
  • 0e394fdfa4 X86: Fix the general IO instructions dataSize. Gabe Black 2008-01-12 06:37:35 -05:00
  • f9c54d5a4b Temporary fix for ll/sc bug see flyspray task for more info: http://www.m5sim.org/flyspray/task/197 Geoffrey Blake 2008-01-06 00:19:45 -05:00
  • d4cca11bdb Very minor memtest regression stats changes from recent coherence bug fixes. Steve Reinhardt 2008-01-02 15:35:09 -08:00
  • 6c5a3ab8b2 Add ReadRespWithInvalidate to handle multi-level coherence situation where we defer a response to a read from a far-away cache A, then later defer a ReadExcl from a cache B on the same bus as us. We'll assert MemInhibit in both cases, but in the latter case MemInhibit will keep the invalidation from reaching cache A. This special response tells cache A that it gets the block to satisfy its read, but must immediately invalidate it. Steve Reinhardt 2008-01-02 15:22:38 -08:00
  • bf9b3821bd Mark cache-to-cache MSHRs as downstreamPending when necessary. Don't mark upstream MSHR as pending if downstream MSHR is already in service. Steve Reinhardt 2008-01-02 15:18:33 -08:00
  • 538da9e24d Don't DPRINTF in the middle of a PrintReq. Steve Reinhardt 2008-01-02 14:42:42 -08:00
  • 87e5fd1755 Bug fix: functional cache port now needs otherPort set. Steve Reinhardt 2008-01-02 14:42:24 -08:00
  • cde5a79eab Additional comments and helper functions for PrintReq. Steve Reinhardt 2008-01-02 13:46:22 -08:00
  • 3952e41ab1 Add functional PrintReq command for memory-system debugging. Steve Reinhardt 2008-01-02 12:20:15 -08:00
  • 659aef3eb8 Fix formatting and comments in cache_impl.hh Steve Reinhardt 2008-01-02 12:15:48 -08:00
  • 2cb7d4f068 SPARC: Fix a bug where the TLB would match against the wrong entries. Gabe Black 2008-01-01 18:20:08 -05:00
  • 45ea1549c9 Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something. Ali Saidi 2007-12-18 01:52:57 -05:00
  • 71909a50de CPU: Update where the simple cpus read their cpu id from the thread context to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations. Ali Saidi 2007-12-16 03:48:13 -05:00
  • b7ea470a97 Fix minor bug in util/style.py Steve Reinhardt 2007-12-11 10:41:30 -08:00
  • 948269d8aa X86: Update the parser reference output which has mysteriously changed again? Gabe Black 2007-12-03 14:33:33 -08:00
  • 27cc351688 X86: Please excuse my dear Aunt Sally. (precedence bug) Gabe Black 2007-12-03 14:32:56 -08:00
  • 73caca57a8 X86: Make sure the memory index is calculated using the address size for bit test instructions. Gabe Black 2007-12-02 01:46:38 -08:00
  • b5d4018382 X86: Fix a copy/paste mistake where the bit test instructions were using an immediate where they should use a register. Gabe Black 2007-12-02 01:46:29 -08:00
  • 62ad1d2872 X86: Make the page not present panic more descriptive. Gabe Black 2007-12-02 01:46:14 -08:00
  • 82e705d713 X86: Start setting up the real mode data structure. Gabe Black 2007-12-02 00:04:31 -08:00
  • 5de71e39d8 X86: Make the 0xA0-0xA3 versions of mov use the right sized immediates. Gabe Black 2007-12-02 00:02:51 -08:00
  • 4c37f828f1 X86: Add in a missing "break". Gabe Black 2007-12-01 23:11:23 -08:00
  • 9805916cec X86: Actually do something for the MiscRegFile clear function. Gabe Black 2007-12-01 23:10:42 -08:00
  • 42ae409746 X86: Move startup code to the system object to initialize a Linux system. Gabe Black 2007-12-01 23:09:56 -08:00
  • e7fc5c42f3 X86: Add a missing microcode file to the sconscript. Gabe Black 2007-12-01 23:07:41 -08:00
  • 67fee01026 X86: Fix a copy paste error in the bts microcode. Gabe Black 2007-12-01 23:06:52 -08:00
  • 988c6f227a X86: Implement mov from control register. Gabe Black 2007-12-01 23:06:03 -08:00
  • fe833dd2c3 X86: First crack at far returns. This is grossly approximate. Gabe Black 2007-12-01 23:05:01 -08:00
  • dc6f960171 X86: Reorganize segmentation and implement segment selector movs. Gabe Black 2007-12-01 23:03:39 -08:00
  • a548067b01 X86: Make the "fault" microop predicated. Gabe Black 2007-12-01 23:01:56 -08:00
  • 557bc80647 X86: Implement the LIDT instruction. Gabe Black 2007-12-01 23:01:31 -08:00
  • 62c79ca637 X86: Implement the lgdt instruction. Gabe Black 2007-12-01 23:01:17 -08:00
  • 4e3ff42762 X86: Implement wrbase and wrlimit for loading pseudo descriptors. Gabe Black 2007-12-01 23:00:58 -08:00
  • bfc62d1a70 X86: Separate the effective seg base and the "hidden" seg base. Gabe Black 2007-12-01 23:00:15 -08:00
  • 7433032b39 SPARC: Fixes for invalidateAll and demapAll in the SPARC TLBs. Gabe Black 2007-11-30 16:49:27 -08:00
  • 38e804f7cd SPARC: Fix 32 bit register window flushing endian conversion. Gabe Black 2007-11-29 20:20:18 -08:00
  • fa5e3b47c8 SPARC: Fix the initial stack to match what the Linux kernel does. Gabe Black 2007-11-29 00:00:26 -08:00
  • 16e99e4677 SPARC: Combine the 64 and 32 bit process initialization code. Alignment is done as it was for 32 bit processes. Gabe Black 2007-11-29 00:00:02 -08:00
  • a84d9716d6 merge, no manual changes Ali Saidi 2007-11-29 00:23:14 -05:00
  • 376c7285ee Serialization: Fix serialization of file descriptors. Make sure open file descriptors are reopened and the file pointer is in the same place as when the checkpoint occured. Rick Strong 2007-11-29 00:22:46 -05:00
  • 8a020d40d3 Make ports that aren't connected to anything fail more gracefully. Gabe Black 2007-11-28 14:39:19 -08:00
  • ab598eadbf imported patch pagewalker.patch Gabe Black 2007-11-21 00:04:15 -08:00
  • ce26c3ccec Get rid of a file that should have never been committed. Gabe Black 2007-11-20 22:51:03 -08:00
  • e35c4f2f08 Merge with head. Gabe Black 2007-11-20 15:38:54 -08:00
  • a12d5975cc Simple CPU fix simple mistake in translateDataWriteAddr. Gabe Black 2007-11-20 15:37:56 -08:00
  • 088d7c7096 Might as well ship splash2 scripts since we get questions on the list. Steve Reinhardt 2007-11-20 07:36:49 -08:00
  • ac50694d1a Serialization: Serialize SPARC PTEs last so their nameOut() calls don't interfere with other serialization in the TLB. Ali Saidi 2007-11-19 22:47:08 -05:00
  • 8026ecbb8e Memory: Cache the physical memory start and size so we don't need a dynamic cast on every access. Ali Saidi 2007-11-19 18:23:43 -05:00
  • fed9ee52fc Compiling: Make sure that libelf is also compiled for 64bit on OS X. Ali Saidi 2007-11-19 18:23:43 -05:00
  • 785eb13190 Make EXTRAS work for relative directories. Also print a little feedback when processing EXTRAS. Steve Reinhardt 2007-11-16 20:10:33 -08:00
  • 21a99af009 Update memtest results due to new deferred-target-promotion fix. Turned out this scenario was happening, but due to other activity, the writable block returned by the ReadResp would get downgraded or invalidated before the "unnecessary" ReadExResp/UpgradeResp returned, thus avoiding triggering the assertion that led us to catch this. Steve Reinhardt 2007-11-16 20:10:33 -08:00
  • 7d83cf35e1 Tweak check for writable block fill. Steve Reinhardt 2007-11-16 20:10:33 -08:00
  • f03a62008a Fix bug on exclusive response to ReadReq with pending WriteReq. Steve Reinhardt 2007-11-16 20:10:32 -08:00
  • 5d23f86e98 add back in clobbered MIPS fix for g++ 4.2 Korey Sewell 2007-11-17 00:02:56 -05:00
  • f2fea63c65 go back and fix up MIPS copyright headers Korey Sewell 2007-11-16 21:32:22 -05:00
  • 52e6aa6284 move initCPU, processInterrupts declaration to core_specific file. Korey Sewell 2007-11-16 21:31:37 -05:00
  • 10e0ae5407 Accidently kept hardcoded memory value in merge. Remove that and now ALPHA_FS quick regressions pass Korey Sewell 2007-11-16 19:37:21 -05:00
  • 92724490c9 Gabe's 32-bit X86 fix merge Korey Sewell 2007-11-16 19:16:01 -05:00
  • 3ee0433f7c compile-time fix for setMipsOptions function Korey Sewell 2007-11-16 19:15:20 -05:00
  • 7ffd88a54b X86: Fix 32 bit compilation. Gabe Black 2007-11-16 14:18:47 -08:00
  • 923c385b97 remove unnecessary namespace Korey Sewell 2007-11-15 20:52:59 -05:00
  • d09ab2bd22 add thread id to misc. reg functions Korey Sewell 2007-11-15 20:35:49 -05:00
  • 7c076479e4 add MicroPC functions back to thread context Korey Sewell 2007-11-15 20:35:31 -05:00
  • cf9dc4b151 add microPC stuff back in. got deleted on changeset propragation somehow. Korey Sewell 2007-11-15 19:48:53 -05:00
  • 8f8e7fe08e put the flattenIndex stuff back in O3 AND put fatal() back in faults Korey Sewell 2007-11-15 16:38:09 -05:00
  • 3fd291bc4e merge Ali's config change... Korey Sewell 2007-11-15 14:21:42 -05:00
  • 3110b157e6 fix MIPS headers Korey Sewell 2007-11-15 14:21:01 -05:00
  • 9cff176bbc add setMipsOptions function for MIPS usage Korey Sewell 2007-11-15 14:20:41 -05:00
  • 641ee83e40 add core specific parameter to BaseCPU params Korey Sewell 2007-11-15 14:18:56 -05:00
  • 7ba65aecaa Add CoreSpecific type to all archs Korey Sewell 2007-11-15 14:17:21 -05:00
  • 0896b5b897 Configs: Fix for benchmarks that don't use getopt. Ali Saidi 2007-11-15 12:58:06 -05:00
  • 185f0eb134 Config: Fix some errors in the splash2 config file. Ali Saidi 2007-11-15 03:51:28 -05:00
  • 789153dff6 Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp" Korey Sewell 2007-11-15 03:10:41 -05:00
  • 375ddf8d25 branch merge Korey Sewell 2007-11-15 00:14:20 -05:00
  • 7c8e4ca3a3 Checkpointing: Name SE page table entries better so that there isn't a problem if multiple workloads are being run at once. Ali Saidi 2007-11-14 23:42:08 -05:00
  • 2820a448e2 comment and spacing Korey Sewell 2007-11-14 15:33:43 -05:00
  • 5f7879a935 Get MIPS_SE actually working again by actually by fixing TLB stuff and running hello world Korey Sewell 2007-11-14 06:24:47 -05:00
  • bfdd2f379b remove unnecessary debug messages I added Korey Sewell 2007-11-14 06:18:58 -05:00