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X86: Implement wrbase and wrlimit for loading pseudo descriptors.

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--HG--
extra : convert_revision : fe03c4aed95ef12773e80cdb3d9cff68a2b20f02
This commit is contained in:
Gabe Black
2007-12-01 23:00:58 -08:00
parent bfc62d1a70
commit 4e3ff42762
2 changed files with 19 additions and 0 deletions
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16
src/arch/x86/isa/microops/regop.isa
View File

@@ -936,4 +936,20 @@ let {{
ControlDest = newVal;
}
'''
class Wrbase(RegOp):
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(Wrbase, self).__init__(dest, \
src1, "NUM_INTREGS", flags, dataSize)
code = '''
SegBaseDest = psrc1;
'''
class Wrlimit(RegOp):
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(Wrlimit, self).__init__(dest, \
src1, "NUM_INTREGS", flags, dataSize)
code = '''
SegLimitDest = psrc1;
'''
}};

3
src/arch/x86/isa/operands.isa
View File

@@ -127,5 +127,8 @@ def operands {{
'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 73),
'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 74),
'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
'SegBaseDest': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 75),
'SegLimitDest': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 76),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
}};