X86: Implement the lgdt instruction.

--HG--
extra : convert_revision : d1698a82df3c57cc9bbf8d5d190f271bfc7cb2e4

src/arch/x86/isa/decoder/two_byte_opcodes.isa

@@ -109,7 +109,15 @@
                     default: decode MODRM_REG {
                         0x0: sgdt_Ms();
                         0x1: sidt_Ms();
-                        0x2: lgdt_Ms();
+                        0x2: decode MODE_SUBMODE {
+                            0x0: Inst::LGDT(M);
+                            default: decode OPSIZE {
+                                // 16 bit operand sizes are special, but only
+                                // in legacy and compatability modes.
+                                0x2: Inst::LGDT_16(M);
+                                default: Inst::LGDT(M);
+                            }
+                        }
                         0x3: lidt_Ms();
                         0x4: smsw_Mw();
                         0x6: lmsw_Mw();

src/arch/x86/isa/insts/system/__init__.py

@@ -55,7 +55,8 @@
 
 categories = ["halt",
               "undefined_operation",
-              "msrs"]
+              "msrs",
+              "segmentation"]
 
 microcode = ""
 for category in categories:

src/arch/x86/isa/insts/system/segmentation.py

@@ -0,0 +1,113 @@
+# Copyright (c) 2007 The Hewlett-Packard Development Company
+# All rights reserved.
+#
+# Redistribution and use of this software in source and binary forms,
+# with or without modification, are permitted provided that the
+# following conditions are met:
+#
+# The software must be used only for Non-Commercial Use which means any
+# use which is NOT directed to receiving any direct monetary
+# compensation for, or commercial advantage from such use.  Illustrative
+# examples of non-commercial use are academic research, personal study,
+# teaching, education and corporate research & development.
+# Illustrative examples of commercial use are distributing products for
+# commercial advantage and providing services using the software for
+# commercial advantage.
+#
+# If you wish to use this software or functionality therein that may be
+# covered by patents for commercial use, please contact:
+#     Director of Intellectual Property Licensing
+#     Office of Strategy and Technology
+#     Hewlett-Packard Company
+#     1501 Page Mill Road
+#     Palo Alto, California  94304
+#
+# Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.  Redistributions
+# in binary form must reproduce the above copyright notice, this list of
+# conditions and the following disclaimer in the documentation and/or
+# other materials provided with the distribution.  Neither the name of
+# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.  No right of
+# sublicense is granted herewith.  Derivatives of the software and
+# output created using the software may be prepared, but only for
+# Non-Commercial Uses.  Derivatives of the software may be shared with
+# others provided: (i) the others agree to abide by the list of
+# conditions herein which includes the Non-Commercial Use restrictions;
+# and (ii) such Derivatives of the software include the above copyright
+# notice to acknowledge the contribution from this software where
+# applicable, this list of conditions and the disclaimer below.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+microcode = '''
+def macroop LGDT_M
+{
+    .adjust_env oszForPseudoDesc
+
+    # Get the limit
+    ld t1, seg, sib, disp, dataSize=2
+    # Get the base
+    ld t2, seg, sib, 'adjustedDisp + 2'
+    wrbase gdtr, t2
+    wrlimit gdtr, t1
+};
+
+def macroop LGDT_P
+{
+    .adjust_env oszForPseudoDesc
+
+    rdip t7
+    # Get the limit
+    ld t1, seg, riprel, disp, dataSize=2
+    # Get the base
+    ld t2, seg, riprel, 'adjustedDisp + 2'
+    wrbase gdtr, t2
+    wrlimit gdtr, t1
+};
+
+#
+# These versions are for when the original data size was 16 bits. The base is
+# still 32 bits, but the top byte is zeroed before being used.
+#
+
+def macroop LGDT_16_M
+{
+    .adjust_env oszForPseudoDesc
+
+    # Get the limit
+    ld t1, seg, sib, disp, dataSize=2
+    # Get the base
+    ld t2, seg, sib, 'adjustedDisp + 2', dataSize=4
+    zexti t2, t2, 23
+    wrbase gdtr, t2
+    wrlimit gdtr, t1
+};
+
+def macroop LGDT_16_P
+{
+    .adjust_env oszForPseudoDesc
+
+    rdip t7
+    # Get the limit
+    ld t1, seg, riprel, disp, dataSize=2
+    # Get the base
+    ld t2, seg, riprel, 'adjustedDisp + 2', dataSize=4
+    zexti t2, t2, 23
+    wrbase gdtr, t2
+    wrlimit gdtr, t1
+};
+'''

src/arch/x86/isa/microasm.isa

@@ -80,6 +80,10 @@ let {{
     # Add in symbols for the segment descriptor registers
     for letter in ("C", "D", "E", "F", "G", "S"):
         assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
+
+    for reg in ("LDTR", "TR", "GDTR", "IDTR"):
+        assembler.symbols[reg.lower()] = "SYS_SEGMENT_REG_%s" % reg
+
     # Miscellaneous symbols
     symbols = {
         "reg" : "env.reg",
@@ -138,6 +142,13 @@ let {{
         env.dataSize = 8;
     '''
 
+    assembler.symbols["oszForPseudoDesc"] = '''
+    if (machInst.mode.submode == SixtyFourBitMode)
+        env.dataSize = 8;
+    else
+        env.dataSize = 4;
+    '''
+
     def trimImm(width):
         return "adjustedImm = adjustedImm & mask(%s);" % width
 

src/arch/x86/isa/microops/regop.isa

@@ -942,7 +942,7 @@ let {{
             super(Wrbase, self).__init__(dest, \
                     src1, "NUM_INTREGS", flags, dataSize)
         code = '''
-            SegBaseDest = psrc1;
+            SysSegBaseDest = psrc1;
         '''
 
     class Wrlimit(RegOp):
@@ -950,6 +950,6 @@ let {{
             super(Wrlimit, self).__init__(dest, \
                     src1, "NUM_INTREGS", flags, dataSize)
         code = '''
-            SegLimitDest = psrc1;
+            SysSegLimitDest = psrc1;
         '''
 }};

src/arch/x86/isa/operands.isa

@@ -127,8 +127,8 @@ def operands {{
         'EferOp':        ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 73),
         'CR4Op':         ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 74),
         'CSBase':        ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
-        'SegBaseDest':   ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 75),
-        'SegLimitDest':  ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 76),
+        'SysSegBaseDest':  ('ControlReg', 'uqw', 'MISCREG_SYSSEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 75),
+        'SysSegLimitDest': ('ControlReg', 'uqw', 'MISCREG_SYSSEG_LIMIT(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 76),
 
         'Mem':           ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
 }};

src/arch/x86/segmentregs.hh

@@ -72,6 +72,16 @@ namespace X86ISA
 
         NUM_SEGMENTREGS
     };
+
+    enum SysSegmentRegIndex
+    {
+        SYS_SEGMENT_REG_LDTR,
+        SYS_SEGMENT_REG_TR,
+        SYS_SEGMENT_REG_GDTR,
+        SYS_SEGMENT_REG_IDTR,
+
+        NUM_SYSSEGMENTREGS
+    };
 };
 
 #endif // __ARCH_X86_SEGMENTREGS_HH__