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X86: Fix a copy/paste mistake where the bit test instructions were using an immediate where they should use a register.

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--HG--
extra : convert_revision : b0ee80e4c7fdb58a1eb85b3bcc82a0cdaa93330a
This commit is contained in:
Gabe Black
2007-12-02 01:46:29 -08:00
parent 62ad1d2872
commit b5d4018382
1 changed files with 8 additions and 16 deletions
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24
src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py
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@@ -82,8 +82,7 @@ def macroop BT_R_R {
};
def macroop BT_M_R {
limm t1, imm
srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
add t2, t2, base
ld t1, seg, [scale, index, t2], disp
sext t0, t1, reg, flags=(CF,)
@@ -91,8 +90,7 @@ def macroop BT_M_R {
def macroop BT_P_R {
rdip t7
limm t1, imm
srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
ld t1, seg, [1, t2, t7]
sext t0, t1, reg, flags=(CF,)
};
@@ -139,8 +137,7 @@ def macroop BTC_R_R {
};
def macroop BTC_M_R {
limm t1, imm
srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
add t2, t2, base
limm t3, 1
rol t3, t3, reg
@@ -152,8 +149,7 @@ def macroop BTC_M_R {
def macroop BTC_P_R {
rdip t7
limm t1, imm
srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
limm t3, 1
rol t3, t3, reg
ldst t1, seg, [1, t2, t7]
@@ -204,8 +200,7 @@ def macroop BTR_R_R {
};
def macroop BTR_M_R {
limm t1, imm
srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
add t2, t2, base
limm t3, "(uint64_t(-(2ULL)))"
rol t3, t3, reg
@@ -217,8 +212,7 @@ def macroop BTR_M_R {
def macroop BTR_P_R {
rdip t7
limm t1, imm
srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
limm t3, "(uint64_t(-(2ULL)))"
rol t3, t3, reg
ldst t1, seg, [1, t2, t7]
@@ -269,8 +263,7 @@ def macroop BTS_R_R {
};
def macroop BTS_M_R {
limm t1, imm
srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
add t2, t2, base
limm t3, 1
rol t3, t3, reg
@@ -282,8 +275,7 @@ def macroop BTS_M_R {
def macroop BTS_P_R {
rdip t7
limm t1, imm
srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
limm t3, 1
rol t3, t3, reg
ldst t1, seg, [1, t2, t7]