da7f512067
Timer: Fill out the periodic modes a little.
Gabe Black
2008-06-12 00:56:07 -04:00
4f9a0402f6
Dev: Seperate the 8254 timer from tsunami and use it in that and the PC.
Gabe Black
2008-06-12 00:54:48 -04:00
0368ccdeda
BitUnion: Take out namespace declaration so bitunions can be declared inside classes.
Gabe Black
2008-06-12 00:54:32 -04:00
81936ae2ed
X86: Add an event for the apic timer timeout. It doesn't get used yet.
Gabe Black
2008-06-12 00:54:19 -04:00
6b8d0363ee
X86: Rename the divide count register to divide configuration.
Gabe Black
2008-06-12 00:54:12 -04:00
b10742ee2b
X86: Make the apic isr and irr work.
Gabe Black
2008-06-12 00:54:05 -04:00
69000baef3
X86: Make the apic task priority register work.
Gabe Black
2008-06-12 00:54:01 -04:00
e9c481ea4a
X86: Make the logical destination and destination format work.
Gabe Black
2008-06-12 00:53:50 -04:00
ed23a4970b
X86: Make the apic ID register work.
Gabe Black
2008-06-12 00:53:43 -04:00
8a6723e038
X86: Make the apic version register work.
Gabe Black
2008-06-12 00:53:37 -04:00
8d2416c6e9
X86: Implement a partial, sort of correct version of the protected mode variant of iret.
Gabe Black
2008-06-12 00:53:01 -04:00
66f54a6037
X86: Change how segment loading is performed.
Gabe Black
2008-06-12 00:52:12 -04:00
129831c116
X86: Make pushes and pops use the stack size instead of the data size.
Gabe Black
2008-06-12 00:51:57 -04:00
b05299253f
X86: In non 64bit mode, throw a fault when a NULL segment is accessed.
Gabe Black
2008-06-12 00:51:50 -04:00
a8384311d5
X86: Take advantage of the new meta register.
Gabe Black
2008-06-12 00:51:14 -04:00
d4e7c7edd3
X86: Keep handy values like the operating mode in one register.
Gabe Black
2008-06-12 00:50:25 -04:00
fa7c81c6df
X86: Change what the microop chks does. Instead of computing the segment descriptor address, this now checks if a selector value/descriptor are legal for a particular purpose.
Gabe Black
2008-06-12 00:50:10 -04:00
6bd9cf3594
X86: Add a microop to read a segments attribute register.
Gabe Black
2008-06-12 00:50:05 -04:00
e0c20386ac
X86: Add microops and supporting code to manipulate the whole rflags register.
Gabe Black
2008-06-12 00:49:50 -04:00
2bb8933f78
X86: Add microops which panic, fatal, warn, and warn_once.
Gabe Black
2008-06-12 00:49:25 -04:00
bbc1f394ff
X86: Truncate descriptors to 16 bits.
Gabe Black
2008-06-12 00:49:16 -04:00
6106b05b6e
X86: Redo BSF.
Gabe Black
2008-06-12 00:48:58 -04:00
dfc2d44ea3
X86: Flesh out 3dnow instruction decoding a bit and grab the byte immediate.
Gabe Black
2008-06-12 00:48:46 -04:00
f58f99935a
X86: Update the regressions for the new string instructions.
Gabe Black
2008-06-12 00:48:33 -04:00
de6eeaaa27
X86: Make string instructions work when rcx=0.
Gabe Black
2008-06-12 00:48:15 -04:00
8688ef3fe5
X86: Have all 8 machine check registers since the kernel assumes they're there.
Gabe Black
2008-06-12 00:48:02 -04:00
a8e3001df8
X86: Bypass unaligned access support for register addressed MSRs.
Gabe Black
2008-06-12 00:47:25 -04:00
b3e55339f9
X86: Remove enforcement of APIC register access alignment. Panic if more than one register is accessed at a time.
Gabe Black
2008-06-12 00:46:22 -04:00
561a541797
X86: Force the kernel to use a certain loops per jiffy instead of calculating it.
Gabe Black
2008-06-12 00:46:16 -04:00
8e2991b529
X86: Fix the implementation of BSF.
Gabe Black
2008-06-12 00:46:04 -04:00
16e189fad2
X86: Bit scan forward/reverse were accidentally transposed.
Gabe Black
2008-06-12 00:45:52 -04:00
254cc07650
X86: Fix a byte register indexing issue in the sign extending move from memory microcode.
Gabe Black
2008-06-12 00:45:22 -04:00
f6a97752b0
X86: Make the amount of system memory match the hardcoded e820 info.
Gabe Black
2008-06-12 00:45:11 -04:00
633c585bfa
X86: Make the regular console use the serial port as well.
Gabe Black
2008-06-12 00:45:01 -04:00
9ebd244991
X86: Update the regressions for the fact that rdtsc does something now.
Gabe Black
2008-06-12 00:42:52 -04:00
8501a90f59
X86: Add in some support for the tsc register.
Gabe Black
2008-06-12 00:39:10 -04:00
d093fcb079
CPU: Make the simple cpu trace data for loads/stores.
Gabe Black
2008-06-12 00:35:50 -04:00
5797ff1016
X86: Fix building on *BSD hosts
Ali Saidi
2008-06-11 10:54:12 -04:00
fd3e661cd3
SCons: Fix more SCons version issues
Ali Saidi
2008-06-11 10:54:08 -04:00
87f981e208
Added tag copyright_update for changeset 60a931b03fb1
Nathan Binkert
2008-06-11 09:50:37 -04:00
f5e36d156d
IGbE: Implement sending packet that is contained in more than 2 descriptors.
Ali Saidi
2008-05-20 16:06:56 -04:00
b7af65f414
SCons: Fixing SCons bug 2006 issues for non-alpha ISAs
Stephen Hines
2008-05-20 14:04:53 -04:00
e71a5270a2
Make sure that output files are always checked success before they're used. Make OutputDirectory::resolve() private and change the functions using resolve() to instead use create().
Ali Saidi
2008-05-15 19:10:26 -04:00
4a4317ae18
SCons: More scons fixing for SCons bug 2006
Ali Saidi
2008-05-06 16:22:14 -04:00
8af6dc118c
SCons: add comments to SConscript documenting bug workaround
Ali Saidi
2008-04-10 15:38:10 -04:00
fe12f38353
PhysicalMemory: Add parameter for variance in memory delay.
Ali Saidi
2008-04-10 14:44:52 -04:00
ed27c4c521
SCons: Manually specifying header only directories with Dir() works around the problem
Ali Saidi
2008-04-08 11:08:26 -04:00
bee4d454e8
SCons: Make BATCH options global sticky so libelf is built appropriately.
Ali Saidi
2008-04-07 23:40:24 -04:00
d9d79cebb9
SCons: Add check for SCons version since the latest are broken.
Ali Saidi
2008-04-07 23:40:23 -04:00
1605fbebc8
IGbE: Fix bug that limits wire performance a bit
Ali Saidi
2008-03-25 15:58:54 -04:00
ba1f7d31e0
Automated merge with ssh://daystrom.m5sim.org//repo/m5
Steve Reinhardt
2008-03-25 10:04:52 -04:00
29be31ce31
Fix handling of writeback-induced writebacks in atomic mode.
Steve Reinhardt
2008-03-25 10:01:21 -04:00
93dd1978a7
X86: Put an RTC into the CMOS part of the southbridge.
Gabe Black
2008-03-25 02:15:23 -04:00
e5bdae15f3
Devices: Separate out the MC146818 RTC so both Alpha and X86 can use it.
Gabe Black
2008-03-25 02:15:06 -04:00
af9a57566a
X86: Turn #defines into consts.
Gabe Black
2008-03-25 02:09:18 -04:00
48409ca512
X86: Start implementing the south bridge stuff.
Gabe Black
2008-03-25 02:08:54 -04:00
b0c52885ce
X86: Change the Opteron platform to be the PC platform.
Gabe Black
2008-03-25 02:06:53 -04:00
623dd7ed3a
Delete the Request for a no-response Packet when the Packet is deleted, since the requester can't possibly do it.
Steve Reinhardt
2008-03-24 01:08:02 -04:00
93ab43288a
Don't FastAlloc MSHRs since we don't allocate them on the fly.
Steve Reinhardt
2008-03-24 01:08:02 -04:00
627592c2f2
Add FAST_ALLOC_DEBUG and FAST_ALLOC_STATS as SConstruct options.
Steve Reinhardt
2008-03-24 01:08:02 -04:00
407710d387
Fix cache problem with writes to tempBlock getting wrong writeback address.
Steve Reinhardt
2008-03-22 22:17:15 -04:00
3fe1af7952
MIPS: Check endianness of binaries in SE mode.
Gabe Black
2008-03-20 02:10:21 -04:00
3de8a78a04
Update long regression stats for semi-recent cache changes.
Steve Reinhardt
2008-03-17 23:07:22 -04:00
b051ae6acc
Fix a few Packet memory leaks.
Steve Reinhardt
2008-03-17 03:08:28 -04:00
131c65f429
Restructure bus timing calcs to cope with pkt being deleted by target.
Steve Reinhardt
2008-03-17 03:07:38 -04:00
19c367fa8f
Fix subtle cache bug where read could return stale data if a prior write miss arrived while an even earlier read miss was still outstanding.
Steve Reinhardt
2008-03-15 05:03:55 -07:00
969688154d
Simpoints: Fix regression bug/Don't set process.simpoint, if simpoint doesn't exist
Ali Saidi
2008-03-15 22:20:09 -04:00
50946b1673
Merge
Gabe Black
2008-03-06 21:09:15 -05:00
a245b0eedf
X86: Refine the local APIC.
Gabe Black
2008-03-06 20:37:28 -05:00
21fd15ad9a
O3CPU: Don't call dumpInsts if DEBUG is not defined
Vilas Sridharan
2008-03-06 00:27:09 -05:00
66aaabf4ae
X86: Don't map the local APIC into the physical address space in SE mode.
Gabe Black
2008-03-01 00:05:12 -05:00
65332ef3a9
Added tag m5_2.0_beta4 for changeset cad8c2b5d2ec
Ali Saidi
2008-02-29 18:08:49 -05:00
ead7dd4bb1
Added tag m5_2.0_beta5 for changeset fb826c79a385
Ali Saidi
2008-02-29 17:59:45 -05:00
02a56d8d01
Error out if -s is used without --caches (instead of saying you must specify a CPU).
Lisa Hsu
2008-02-29 01:49:36 -05:00
0273533adb
Configs: Make sure options don't conflict
Ali Saidi
2008-02-29 01:23:18 -05:00
3cb7df428c
Configs: Fix some bugs we introduced in the simpoints code
Ali Saidi
2008-02-28 20:39:01 -05:00
19dfde2317
Automated merge with ssh://daystrom.m5sim.org//repo/m5
Steve Reinhardt
2008-02-27 18:18:56 -05:00
2f41006e44
Update outputs for quick tests to reflect fixed cache stats. Will update long tests later.
Steve Reinhardt
2008-02-27 18:17:37 -05:00
8fb74c238c
Add comments in code to describe bug conditions. This should help if somebody gets to the bug fix before me (or someone else)...
Korey Sewell
2008-02-27 17:50:29 -05:00
b45cf21a8e
Fix Load/Store Queue squashing after a SMT thread is removed but ensuring you are squashing from the current instruction # causing the thread exit.
Korey Sewell
2008-02-27 16:53:08 -05:00
34715cc691
Fix offset in removeThread() function so that float registers start freeing up from the right point (#32 usually) instead of restarting at 0 and double-freeing.
Korey Sewell
2008-02-27 16:48:33 -05:00
e6d6adc731
Revamp cache timing access mshr check to make stats sane again.
Steve Reinhardt
2008-02-26 22:03:28 -08:00
fcfc8b8c4f
Configs: Make using Simpoints easier with some config files that support them easily
Rick Strong
2008-02-27 00:35:09 -05:00
43ecce5fda
X86: Put in initial implementation of the local APIC.
Gabe Black
2008-02-26 23:39:53 -05:00
98d2ca403e
X86: Implement the INVLPG instruction and the TIA microop.
Gabe Black
2008-02-26 23:39:22 -05:00
8b4796a367
TLB: Make a TLB base class and put a virtual demapPage function in it.
Gabe Black
2008-02-26 23:38:51 -05:00
7bde0285e5
X86: Get PCI config space to work, and adjust address space prefix numbering scheme.
Gabe Black
2008-02-26 23:38:01 -05:00
8c0baf2ce4
Update make release, README, and RELEASE_NOTES for b5
Ali Saidi
2008-02-26 17:28:31 -05:00
8833b4cd44
Bus: Update the stats for the recent bus fix.
Gabe Black
2008-02-26 02:20:40 -05:00
ec1a4cbbc7
Bus: Fix the bus timing to be more realistic.
Gabe Black
2008-02-26 02:20:08 -05:00
2e079ce038
add instruction count fast forwaing and max instruction options
Vilas Sridharan
2008-02-22 17:48:10 -05:00
ceee3ba96e
Added ARM_SE as a build option.
Stephen Hines
2008-02-19 16:42:32 -05:00
3204f96809
Update stats for new writeback behavior.
Steve Reinhardt
2008-02-16 14:58:37 -05:00
4597a71cef
Make L2+ caches allocate new block for writeback misses instead of forwarding down the line.
Steve Reinhardt
2008-02-16 14:58:03 -05:00
69ce7f953b
Update stats for some unknown minor x86 changes (assuming someone just forgot to do this... tsk tsk).
Steve Reinhardt
2008-02-16 13:53:12 -05:00
9faec83ac5
CPU: move the PC Events code to a place where the code won't be executed multiple times if an instruction faults.
Ali Saidi
2008-02-14 16:14:35 -05:00
fc38e9c630
Configs: Change Simulation.py to return a subclass of the CPU models rather than the original class. Without this changes elsewhere in the config script (e.g. the DriveSys frequency can change the TestSys frequency.
Ali Saidi
2008-02-14 16:13:50 -05:00
a33a3f7c55
Update copyright dates
Ali Saidi
2008-02-11 12:35:28 -05:00
71835d42df
Automated merge with file:/home/stever/hg/m5-orig
Steve Reinhardt
2008-02-11 08:31:26 -08:00
Gabe Black