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SPARC: Fix the initial stack to match what the Linux kernel does.

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--HG--
extra : convert_revision : a4451710d8463e52227fd8f760ab737ea8f404b5
This commit is contained in:
Gabe Black
2007-11-29 00:00:26 -08:00
parent 16e99e4677
commit fa5e3b47c8
42 changed files with 2057 additions and 2039 deletions
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74
src/arch/sparc/process.cc
View File

@@ -198,7 +198,7 @@ SparcLiveProcess::argsInit(int pageSize)
//Even for a 32 bit process, the ABI says we still need to
//maintain double word alignment of the stack pointer.
Addr alignmentMask = ~(sizeof(uint64_t) - 1);
uint64_t align = 16;
// load object file into target memory
objFile->loadSections(initVirtMem);
@@ -263,7 +263,7 @@ SparcLiveProcess::argsInit(int pageSize)
//Figure out how big the initial stack needs to be
// The unaccounted for 8 byte 0 at the top of the stack
int mysterious_size = 8;
int sentry_size = 8;
//This is the name of the file which is present on the initial stack
//It's purpose is to let the user space linker examine the original file.
@@ -278,12 +278,13 @@ SparcLiveProcess::argsInit(int pageSize)
arg_data_size += argv[i].size() + 1;
}
//The info_block - This seems to need an pad for some reason.
int info_block_size =
(mysterious_size +
file_name_size +
env_data_size +
arg_data_size + intSize);
//The info_block.
int base_info_block_size =
sentry_size + file_name_size + env_data_size + arg_data_size;
int info_block_size = roundUp(base_info_block_size, align);
int info_block_padding = info_block_size - base_info_block_size;
//Each auxilliary vector is two words
int aux_array_size = intSize * 2 * (auxv.size() + 1);
@@ -294,16 +295,26 @@ SparcLiveProcess::argsInit(int pageSize)
int argc_size = intSize;
int window_save_size = intSize * 16;
int space_needed =
info_block_size +
//Figure out the size of the contents of the actual initial frame
int frame_size =
aux_array_size +
envp_array_size +
argv_array_size +
argc_size +
window_save_size;
//There needs to be padding after the auxiliary vector data so that the
//very bottom of the stack is aligned properly.
int aligned_partial_size = roundUp(frame_size, align);
int aux_padding = aligned_partial_size - frame_size;
int space_needed =
info_block_size +
aux_padding +
frame_size;
stack_min = stack_base - space_needed;
stack_min &= alignmentMask;
stack_min = roundDown(stack_min, align);
stack_size = stack_base - stack_min;
// Allocate space for the stack
@@ -311,19 +322,22 @@ SparcLiveProcess::argsInit(int pageSize)
roundUp(stack_size, pageSize));
// map out initial stack contents
IntType window_save_base = stack_min;
IntType argc_base = window_save_base + window_save_size;
IntType argv_array_base = argc_base + argc_size;
IntType envp_array_base = argv_array_base + argv_array_size;
IntType auxv_array_base = envp_array_base + envp_array_size;
//The info block is pushed up against the top of the stack, while
//the rest of the initial stack frame is aligned to an 8 byte boudary.
IntType arg_data_base = stack_base - info_block_size + intSize;
IntType env_data_base = arg_data_base + arg_data_size;
IntType file_name_base = env_data_base + env_data_size;
IntType mysterious_base = file_name_base + file_name_size;
IntType sentry_base = stack_base - sentry_size;
IntType file_name_base = sentry_base - file_name_size;
IntType env_data_base = file_name_base - env_data_size;
IntType arg_data_base = env_data_base - arg_data_size;
IntType auxv_array_base = arg_data_base -
info_block_padding - aux_array_size - aux_padding;
IntType envp_array_base = auxv_array_base - envp_array_size;
IntType argv_array_base = envp_array_base - argv_array_size;
IntType argc_base = argv_array_base - argc_size;
#if TRACING_ON
IntType window_save_base = argc_base - window_save_size;
#endif
DPRINTF(Sparc, "The addresses of items on the initial stack:\n");
DPRINTF(Sparc, "%#x - sentry NULL\n", sentry_base);
DPRINTF(Sparc, "filename = %s\n", filename);
DPRINTF(Sparc, "%#x - file name\n", file_name_base);
DPRINTF(Sparc, "%#x - env data\n", env_data_base);
DPRINTF(Sparc, "%#x - arg data\n", arg_data_base);
@@ -334,16 +348,18 @@ SparcLiveProcess::argsInit(int pageSize)
DPRINTF(Sparc, "%#x - window save\n", window_save_base);
DPRINTF(Sparc, "%#x - stack min\n", stack_min);
assert(window_save_base == stack_min);
// write contents to stack
// figure out argc
IntType argc = argv.size();
IntType guestArgc = TheISA::htog(argc);
//Write out the mysterious 0
uint64_t mysterious_zero = 0;
initVirtMem->writeBlob(mysterious_base,
(uint8_t*)&mysterious_zero, mysterious_size);
//Write out the sentry void *
uint64_t sentry_NULL = 0;
initVirtMem->writeBlob(sentry_base,
(uint8_t*)&sentry_NULL, sentry_size);
//Write the file name
initVirtMem->writeString(file_name_base, filename.c_str());
@@ -359,8 +375,10 @@ SparcLiveProcess::argsInit(int pageSize)
//Write out the terminating zeroed auxilliary vector
const IntType zero = 0;
initVirtMem->writeBlob(auxv_array_base + 2 * intSize * auxv.size(),
(uint8_t*)&zero, 2 * intSize);
initVirtMem->writeBlob(auxv_array_base + intSize * 2 * auxv.size(),
(uint8_t*)&zero, intSize);
initVirtMem->writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1),
(uint8_t*)&zero, intSize);
copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);

570
tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
View File

@@ -1,122 +1,122 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 183932235 # Number of BTB hits
global.BPredUnit.BTBLookups 208089812 # Number of BTB lookups
global.BPredUnit.BTBHits 183466846 # Number of BTB hits
global.BPredUnit.BTBLookups 207793260 # Number of BTB lookups
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 84447535 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 256528366 # Number of conditional branches predicted
global.BPredUnit.lookups 256528366 # Number of BP lookups
global.BPredUnit.condIncorrect 83278105 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 256324661 # Number of conditional branches predicted
global.BPredUnit.lookups 256324661 # Number of BP lookups
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
host_inst_rate 135731 # Simulator instruction rate (inst/s)
host_inst_rate 134979 # Simulator instruction rate (inst/s)
host_mem_usage 184868 # Number of bytes of host memory used
host_seconds 10355.84 # Real time elapsed on the host
host_tick_rate 105976601 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 458856790 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 141228058 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 745627925 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 302069201 # Number of stores inserted to the mem dependence unit.
host_seconds 10413.54 # Real time elapsed on the host
host_tick_rate 105577175 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 466269652 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 147193104 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 745571091 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 302033091 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405610550 # Number of instructions simulated
sim_seconds 1.097477 # Number of seconds simulated
sim_ticks 1097476890500 # Number of ticks simulated
sim_insts 1405610551 # Number of instructions simulated
sim_seconds 1.099432 # Number of seconds simulated
sim_ticks 1099431876500 # Number of ticks simulated
system.cpu.commit.COM:branches 86246390 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 9005633 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 8078603 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 1955398373
system.cpu.commit.COM:committed_per_cycle.samples 1959484906
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 1080294174 5524.68%
1 576226777 2946.85%
2 118746551 607.28%
3 121516054 621.44%
4 26673737 136.41%
5 9328411 47.71%
6 9370387 47.92%
7 4236649 21.67%
8 9005633 46.06%
0 1081809823 5520.89%
1 578489124 2952.25%
2 119799391 611.38%
3 120342305 614.15%
4 28015342 142.97%
5 8264992 42.18%
6 10398281 53.07%
7 4287045 21.88%
8 8078603 41.23%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 1489528973 # Number of instructions committed
system.cpu.commit.COM:loads 402516086 # Number of loads committed
system.cpu.commit.COM:count 1489528974 # Number of instructions committed
system.cpu.commit.COM:loads 402516087 # Number of loads committed
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
system.cpu.commit.COM:refs 569373868 # Number of memory references committed
system.cpu.commit.COM:refs 569373869 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 84447535 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489528973 # The number of committed instructions
system.cpu.commit.branchMispredicts 83278105 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489528974 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243501 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 1399558822 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1405610550 # Number of Instructions Simulated
system.cpu.committedInsts_total 1405610550 # Number of Instructions Simulated
system.cpu.cpi 1.561566 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.561566 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 422711094 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 22402.386533 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4523.374198 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 422473888 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 5313980500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000561 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 237206 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 708416 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1072971500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000561 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 237206 # number of ReadReq MSHR misses
system.cpu.commit.commitSquashedInsts 1400697440 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1405610551 # Number of Instructions Simulated
system.cpu.committedInsts_total 1405610551 # Number of Instructions Simulated
system.cpu.cpi 1.564348 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.564348 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 419995861 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 23168.139352 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4590.459997 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 419768838 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 5259700500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000541 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 227023 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 708214 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1042140000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000541 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 227023 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 7025 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5025 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_miss_latency 7075 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5075 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 281000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency 283000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 201000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency 203000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 165053813 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 45668.908621 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5916.368381 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 164707389 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 15820806000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002099 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 346424 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1802643 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2049572000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002099 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 346424 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_accesses 165070864 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 45748.072998 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5912.450070 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 164728882 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 15645017500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002072 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 341982 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1785592 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2021951500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002072 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 341982 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1145.843040 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 1170.889248 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 587764907 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 36212.645854 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5350.210750 # average overall mshr miss latency
system.cpu.dcache.demand_hits 587181277 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 21134786500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000993 # miss rate for demand accesses
system.cpu.dcache.demand_misses 583630 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2511059 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 3122543500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000993 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 583630 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 585066725 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 36739.076107 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5384.999253 # average overall mshr miss latency
system.cpu.dcache.demand_hits 584497720 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 20904718000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000973 # miss rate for demand accesses
system.cpu.dcache.demand_misses 569005 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2493806 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 3064091500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000973 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 569005 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 587764907 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 36212.645854 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5350.210750 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 585066725 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 36739.076107 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5384.999253 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 587181277 # number of overall hits
system.cpu.dcache.overall_miss_latency 21134786500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000993 # miss rate for overall accesses
system.cpu.dcache.overall_misses 583630 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2511059 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 3122543500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000993 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 583630 # number of overall MSHR misses
system.cpu.dcache.overall_hits 584497720 # number of overall hits
system.cpu.dcache.overall_miss_latency 20904718000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000973 # miss rate for overall accesses
system.cpu.dcache.overall_misses 569005 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2493806 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 3064091500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000973 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 569005 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -128,89 +128,89 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 508412 # number of replacements
system.cpu.dcache.sampled_refs 512508 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 495156 # number of replacements
system.cpu.dcache.sampled_refs 499252 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.762102 # Cycle average of tags in use
system.cpu.dcache.total_refs 587253725 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 80526000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 343259 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 406688141 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 3452580675 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 760521931 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 785512506 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 239555254 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 2675795 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 256528366 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 355016142 # Number of cache lines fetched
system.cpu.fetch.Cycles 1201036760 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 10894008 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 3738352844 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 89458561 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.116872 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 355016142 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 183932235 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.703158 # Number of inst fetches per cycle
system.cpu.dcache.tagsinuse 4095.762604 # Cycle average of tags in use
system.cpu.dcache.total_refs 584568799 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 80527000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 338816 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 411395405 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 3450318732 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 760917725 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 784307506 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 239378692 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 2864270 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 256324661 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 354575767 # Number of cache lines fetched
system.cpu.fetch.Cycles 1200225955 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 10817828 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 3736159022 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 88285851 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.116571 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 354575767 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 183466846 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.699132 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 2194953627
system.cpu.fetch.rateDist.samples 2198863598
system.cpu.fetch.rateDist.min_value 0
0 1348933053 6145.61%
1 256313247 1167.74%
2 82698191 376.77%
3 38326183 174.61%
4 84519360 385.06%
5 41105906 187.27%
6 32923583 150.00%
7 20556634 93.65%
8 289577470 1319.29%
0 1353213454 6154.15%
1 256648572 1167.19%
2 82308171 374.32%
3 38352394 174.42%
4 84338167 383.55%
5 41018803 186.55%
6 32950598 149.85%
7 20580857 93.60%
8 289452582 1316.37%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 355016079 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 7452.363368 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5292.836041 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 355014725 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 10090500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_accesses 354575701 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 7464.153732 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5301.182557 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 354574348 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 10099000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1354 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 7166500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_misses 1353 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 7172500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1354 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses 1353 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 262196.990399 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 262065.297857 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 355016079 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 7452.363368 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5292.836041 # average overall mshr miss latency
system.cpu.icache.demand_hits 355014725 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 10090500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 354575701 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 7464.153732 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5301.182557 # average overall mshr miss latency
system.cpu.icache.demand_hits 354574348 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 10099000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_misses 1354 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 7166500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_misses 1353 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 7172500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1354 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses 1353 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 355016079 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 7452.363368 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5292.836041 # average overall mshr miss latency
system.cpu.icache.overall_accesses 354575701 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 7464.153732 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5301.182557 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 355014725 # number of overall hits
system.cpu.icache.overall_miss_latency 10090500 # number of overall miss cycles
system.cpu.icache.overall_hits 354574348 # number of overall hits
system.cpu.icache.overall_miss_latency 10099000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_misses 1354 # number of overall misses
system.cpu.icache.overall_mshr_hits 63 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 7166500 # number of overall MSHR miss cycles
system.cpu.icache.overall_misses 1353 # number of overall misses
system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 7172500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1354 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses 1353 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -222,183 +222,183 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 208 # number of replacements
system.cpu.icache.sampled_refs 1354 # Sample count of references to valid blocks.
system.cpu.icache.replacements 206 # number of replacements
system.cpu.icache.sampled_refs 1353 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1042.348080 # Cycle average of tags in use
system.cpu.icache.total_refs 355014725 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1042.511733 # Cycle average of tags in use
system.cpu.icache.total_refs 354574348 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 155 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 128778452 # Number of branches executed
system.cpu.iew.EXEC:nop 354384689 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.865881 # Inst execution rate
system.cpu.iew.EXEC:refs 753461994 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 210026063 # Number of stores executed
system.cpu.idleCycles 156 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 126703550 # Number of branches executed
system.cpu.iew.EXEC:nop 354855190 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.857840 # Inst execution rate
system.cpu.iew.EXEC:refs 743977888 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 207424101 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1497813793 # num instructions consuming a value
system.cpu.iew.WB:count 1867109874 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.963032 # average fanout of values written-back
system.cpu.iew.WB:consumers 1489344820 # num instructions consuming a value
system.cpu.iew.WB:count 1853646743 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.962725 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1442442170 # num instructions producing a value
system.cpu.iew.WB:rate 0.850637 # insts written-back per cycle
system.cpu.iew.WB:sent 1877161076 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 91327681 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 454443 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 745627925 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 21367021 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 17089542 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 302069201 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2889153048 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 543435931 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 103575555 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1900567912 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 61243 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 1433829937 # num instructions producing a value
system.cpu.iew.WB:rate 0.843002 # insts written-back per cycle
system.cpu.iew.WB:sent 1863156113 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 89061580 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 454846 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 745571091 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 21380590 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 17115349 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 302033091 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2890291179 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 536553787 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 102628561 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1886272937 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 61790 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 9772 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 239555254 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 95884 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 9769 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 239378692 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 96720 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 119997179 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 80650 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 115831794 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 46103 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 5250080 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 343111839 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 135211419 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 5250080 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1516982 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 89810699 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.640383 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.640383 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 2004143467 # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 5246415 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 32 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 343055004 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 135175309 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 5246415 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1515897 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 87545683 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.639244 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.639244 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 1988901498 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued
IntAlu 1186366605 59.20% # Type of FU issued
IntAlu 1181296004 59.39% # Type of FU issued
IntMult 0 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 3003253 0.15% # Type of FU issued
FloatAdd 3002910 0.15% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 584611723 29.17% # Type of FU issued
MemWrite 230161886 11.48% # Type of FU issued
MemRead 577085119 29.02% # Type of FU issued
MemWrite 227517465 11.44% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 6010355 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.002999 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 5041207 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.002535 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 143340 2.38% # attempts to use FU when none available
IntAlu 143450 2.85% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 241345 4.02% # attempts to use FU when none available
FloatAdd 241552 4.79% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
FloatCvt 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 5244225 87.25% # attempts to use FU when none available
MemWrite 381445 6.35% # attempts to use FU when none available
MemRead 4269288 84.69% # attempts to use FU when none available
MemWrite 386917 7.68% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 2194953627
system.cpu.iq.ISSUE:issued_per_cycle.samples 2198863598
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 1076765226 4905.64%
1 582878371 2655.54%
2 298125643 1358.23%
3 159003575 724.41%
4 52530250 239.32%
5 16707223 76.12%
6 8404252 38.29%
7 392238 1.79%
8 146849 0.67%
0 1077268268 4899.20%
1 589751497 2682.07%
2 298052129 1355.48%
3 161348809 733.78%
4 50984862 231.87%
5 14316945 65.11%
6 6653209 30.26%
7 347143 1.58%
8 140736 0.64%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 0.913069 # Inst issue rate
system.cpu.iq.iqInstsAdded 2513084593 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2004143467 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 21683766 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 1087893079 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 3817087 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 19440265 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 1299740082 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 275303 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4888.651776 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2888.651776 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 1345860500 # number of ReadExReq miss cycles
system.cpu.iq.ISSUE:rate 0.904513 # Inst issue rate
system.cpu.iq.iqInstsAdded 2513738089 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1988901498 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 21697900 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 1088741621 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1800387 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 19454399 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 1337770636 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 272229 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4890.764761 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2890.764761 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 1331408000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 275303 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 795254500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_misses 272229 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 786950000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 275303 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 238559 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4206.099871 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2206.099871 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 56424 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 766078000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.763480 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 182135 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 401808000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.763480 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 182135 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 71169 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4205.419494 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2205.419494 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 299295500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_mshr_misses 272229 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 228376 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4206.281488 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2206.281488 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 48944 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 754741500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.785687 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 179432 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 395877500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.785687 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 179432 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 69800 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4203.058739 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2203.058739 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 293373500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 71169 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 156957500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_misses 69800 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 153773500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 71169 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 343259 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_mshr_misses 69800 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 338816 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 343259 # number of Writeback misses
system.cpu.l2cache.Writeback_misses 338816 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 343259 # number of Writeback MSHR misses
system.cpu.l2cache.Writeback_mshr_misses 338816 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 4.652891 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 4.378074 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 513862 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4616.884693 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2616.884693 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 56424 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2111938500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.890196 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 457438 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 500605 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4618.839129 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2618.839129 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 48944 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2086149500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.902230 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 451661 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1197062500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.890196 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 457438 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 1182827500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.902230 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 451661 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 513862 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4616.884693 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2616.884693 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 500605 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4618.839129 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2618.839129 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 56424 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2111938500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.890196 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 457438 # number of overall misses
system.cpu.l2cache.overall_hits 48944 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2086149500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.902230 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 451661 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1197062500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.890196 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 457438 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 1182827500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.902230 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 451661 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -410,31 +410,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 19390 # number of replacements
system.cpu.l2cache.sampled_refs 20786 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 19383 # number of replacements
system.cpu.l2cache.sampled_refs 20779 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 8527.413561 # Cycle average of tags in use
system.cpu.l2cache.total_refs 96715 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 8526.680719 # Cycle average of tags in use
system.cpu.l2cache.total_refs 90972 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 2194953782 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 13000888 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244771057 # Number of HB maps that are committed
system.cpu.rename.RENAME:FullRegisterEvents 9 # Number of times there has been no free registers
system.cpu.rename.RENAME:IQFullEvents 47407 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 822770114 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 20101500 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 4935577703 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 3109070263 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2428488542 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 723045080 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 239555254 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 28402170 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 1183717485 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 368180121 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 21968418 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 159248004 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 21723083 # count of temporary serializing insts renamed
system.cpu.numCycles 2198863754 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 14237531 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244771059 # Number of HB maps that are committed
system.cpu.rename.RENAME:FullRegisterEvents 16 # Number of times there has been no free registers
system.cpu.rename.RENAME:IQFullEvents 47995 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 823614564 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 22929026 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 4933879352 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 3107597262 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2428032497 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 721097012 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 239378692 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 32149684 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 1183261438 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 368386115 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 22018362 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 169719231 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 21772913 # count of temporary serializing insts renamed
system.cpu.timesIdled 35 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls

2
tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr
View File

@@ -1,2 +1,2 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7001
0: system.remote_gdb.listener: listening for remote gdb on port 7008
warn: Entering event queue @ 0. Starting simulation...

6
tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
View File

@@ -36,9 +36,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 28 2007 15:13:45
M5 started Wed Nov 28 15:13:46 2007
M5 compiled Nov 28 2007 18:29:37
M5 started Wed Nov 28 18:29:38 2007
M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1097476890500 because target called exit()
Exiting @ tick 1099431876500 because target called exit()

6
tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt
View File

@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3593860 # Simulator instruction rate (inst/s)
host_inst_rate 3930303 # Simulator instruction rate (inst/s)
host_mem_usage 176592 # Number of bytes of host memory used
host_seconds 414.46 # Real time elapsed on the host
host_tick_rate 1796934585 # Simulator tick rate (ticks/s)
host_seconds 378.98 # Real time elapsed on the host
host_tick_rate 1965156849 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489514761 # Number of instructions simulated
sim_seconds 0.744760 # Number of seconds simulated

2
tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr
View File

@@ -1,2 +1,2 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7000
0: system.remote_gdb.listener: listening for remote gdb on port 7007
warn: Entering event queue @ 0. Starting simulation...

4
tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout
View File

@@ -36,8 +36,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 28 2007 15:13:45
M5 started Wed Nov 28 15:13:46 2007
M5 compiled Nov 28 2007 18:29:37
M5 started Wed Nov 28 18:29:38 2007
M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

166
tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
View File

@@ -1,23 +1,23 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2062336 # Simulator instruction rate (inst/s)
host_mem_usage 183952 # Number of bytes of host memory used
host_seconds 722.25 # Real time elapsed on the host
host_tick_rate 2867275090 # Simulator tick rate (ticks/s)
host_inst_rate 2112807 # Simulator instruction rate (inst/s)
host_mem_usage 183960 # Number of bytes of host memory used
host_seconds 704.99 # Real time elapsed on the host
host_tick_rate 2937444703 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489514761 # Number of instructions simulated
sim_seconds 2.070880 # Number of seconds simulated
sim_ticks 2070879986000 # Number of ticks simulated
sim_seconds 2.070879 # Number of seconds simulated
sim_ticks 2070879278000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 23237.213149 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.213149 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4495936000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_avg_miss_latency 23237.386607 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.386607 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 402318223 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4495621000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 4108976000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_misses 193465 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 4108691000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses 193465 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
@@ -31,47 +31,47 @@ system.cpu.dcache.SwapReq_mshr_misses 40 # nu
system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 166527019 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 7990575000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_hits 166527036 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 7990150000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001916 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 319623 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 7351329000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_misses 319606 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 7350938000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001916 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 319623 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 319606 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1255.221220 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 1255.282200 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 24335.291355 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 22335.291355 # average overall mshr miss latency
system.cpu.dcache.demand_hits 568845227 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 12486511000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_avg_miss_latency 24335.366840 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 22335.366840 # average overall mshr miss latency
system.cpu.dcache.demand_hits 568845259 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 12485771000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses
system.cpu.dcache.demand_misses 513103 # number of demand (read+write) misses
system.cpu.dcache.demand_misses 513071 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 11460305000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 11459629000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 513103 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 513071 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 24335.291355 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 22335.291355 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 24335.366840 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 22335.366840 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 568845227 # number of overall hits
system.cpu.dcache.overall_miss_latency 12486511000 # number of overall miss cycles
system.cpu.dcache.overall_hits 568845259 # number of overall hits
system.cpu.dcache.overall_miss_latency 12485771000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses
system.cpu.dcache.overall_misses 513103 # number of overall misses
system.cpu.dcache.overall_misses 513071 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 11460305000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 11459629000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 513103 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 513071 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -83,13 +83,13 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 449136 # number of replacements
system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 449114 # number of replacements
system.cpu.dcache.sampled_refs 453210 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.519446 # Cycle average of tags in use
system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 358580000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 316447 # number of writebacks
system.cpu.dcache.tagsinuse 4095.519523 # Cycle average of tags in use
system.cpu.dcache.total_refs 568906446 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 358652000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 316430 # number of writebacks
system.cpu.icache.ReadReq_accesses 1489519635 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 24978.142077 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22978.142077 # average ReadReq mshr miss latency
@@ -148,78 +148,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 115 # number of replacements
system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 891.566024 # Cycle average of tags in use
system.cpu.icache.tagsinuse 891.565977 # Cycle average of tags in use
system.cpu.icache.total_refs 1489518537 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 259752 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 259745 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 5714544000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 5714390000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 259752 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857272000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_misses 259745 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857195000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 259752 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 194578 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_mshr_misses 259745 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 194563 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 28424 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 3655388000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.853920 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 166154 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1827694000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.853920 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 166154 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 59911 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_hits 28419 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 3655168000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.853934 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 166144 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1827584000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.853934 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 166144 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 59901 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 1318042000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 1317822000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 59911 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 659021000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_misses 59901 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 658911000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 59911 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_mshr_misses 59901 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 316430 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 316447 # number of Writeback misses
system.cpu.l2cache.Writeback_misses 316430 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 316447 # number of Writeback MSHR misses
system.cpu.l2cache.Writeback_mshr_misses 316430 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 3.182232 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 3.181781 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses 454308 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 28424 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 9369932000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.937438 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 425906 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 28419 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 9369558000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.937446 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 425889 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 4684966000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.937438 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 425906 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 4684779000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.937446 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 425889 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 454330 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses 454308 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 28424 # number of overall hits
system.cpu.l2cache.overall_miss_latency 9369932000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.937438 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 425906 # number of overall misses
system.cpu.l2cache.overall_hits 28419 # number of overall hits
system.cpu.l2cache.overall_miss_latency 9369558000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.937446 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 425889 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 4684966000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.937438 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 425906 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 4684779000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.937446 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 425889 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -231,15 +231,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 18201 # number of replacements
system.cpu.l2cache.sampled_refs 19574 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 18200 # number of replacements
system.cpu.l2cache.sampled_refs 19573 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 8449.165713 # Cycle average of tags in use
system.cpu.l2cache.total_refs 62289 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 8449.130406 # Cycle average of tags in use
system.cpu.l2cache.total_refs 62277 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 4141759972 # number of cpu cycles simulated
system.cpu.numCycles 4141758556 # number of cpu cycles simulated
system.cpu.num_insts 1489514761 # Number of instructions executed
system.cpu.num_refs 569364430 # Number of memory references
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls

2
tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr
View File

@@ -1,2 +1,2 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7002
0: system.remote_gdb.listener: listening for remote gdb on port 7009
warn: Entering event queue @ 0. Starting simulation...

6
tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
View File

@@ -36,9 +36,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 28 2007 15:13:45
M5 started Wed Nov 28 15:13:46 2007
M5 compiled Nov 28 2007 18:29:37
M5 started Wed Nov 28 18:29:38 2007
M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 2070879986000 because target called exit()
Exiting @ tick 2070879278000 because target called exit()

8
tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt
View File

@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3488380 # Simulator instruction rate (inst/s)
host_mem_usage 308772 # Number of bytes of host memory used
host_seconds 69.90 # Real time elapsed on the host
host_tick_rate 1748449689 # Simulator tick rate (ticks/s)
host_inst_rate 3600198 # Simulator instruction rate (inst/s)
host_mem_usage 308780 # Number of bytes of host memory used
host_seconds 67.73 # Real time elapsed on the host
host_tick_rate 1804495302 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243829010 # Number of instructions simulated
sim_seconds 0.122213 # Number of seconds simulated

2
tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr
View File

@@ -1,2 +1,2 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7005
0: system.remote_gdb.listener: listening for remote gdb on port 7002
warn: Entering event queue @ 0. Starting simulation...

4
tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
View File

@@ -21,8 +21,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 28 2007 15:13:45
M5 started Wed Nov 28 15:13:46 2007
M5 compiled Nov 28 2007 18:29:37
M5 started Wed Nov 28 18:29:38 2007
M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

174
tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
View File

@@ -1,23 +1,23 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1898653 # Simulator instruction rate (inst/s)
host_inst_rate 2004505 # Simulator instruction rate (inst/s)
host_mem_usage 316136 # Number of bytes of host memory used
host_seconds 128.42 # Real time elapsed on the host
host_tick_rate 2829445602 # Simulator tick rate (ticks/s)
host_seconds 121.64 # Real time elapsed on the host
host_tick_rate 2987214089 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243829010 # Number of instructions simulated
sim_seconds 0.363364 # Number of seconds simulated
sim_ticks 363364127000 # Number of ticks simulated
sim_seconds 0.363367 # Number of seconds simulated
sim_ticks 363367019000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 82219469 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13897.517462 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11897.517462 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 81326673 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 12407648000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_avg_miss_latency 13898.235302 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11898.235302 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 81326625 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 12408956000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 892796 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 10622056000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_misses 892844 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 10623268000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 892796 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses 892844 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
@@ -31,47 +31,47 @@ system.cpu.dcache.SwapReq_mshr_misses 8 # nu
system.cpu.dcache.WriteReq_accesses 22901836 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 22806941 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2372375000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.004144 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 94895 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 2182585000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004144 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 94895 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_hits 22806873 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2374075000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 2184149000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 110.894471 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 110.887563 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 105121305 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14964.217554 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12964.217554 # average overall mshr miss latency
system.cpu.dcache.demand_hits 104133614 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 14780023000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.009396 # miss rate for demand accesses
system.cpu.dcache.demand_misses 987691 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 14965.505407 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12965.505407 # average overall mshr miss latency
system.cpu.dcache.demand_hits 104133498 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 14783031000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses
system.cpu.dcache.demand_misses 987807 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 12804641000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.009396 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 987691 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 12807417000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 987807 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 105121305 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14964.217554 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12964.217554 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 14965.505407 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12965.505407 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 104133614 # number of overall hits
system.cpu.dcache.overall_miss_latency 14780023000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.009396 # miss rate for overall accesses
system.cpu.dcache.overall_misses 987691 # number of overall misses
system.cpu.dcache.overall_hits 104133498 # number of overall hits
system.cpu.dcache.overall_miss_latency 14783031000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses
system.cpu.dcache.overall_misses 987807 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 12804641000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.009396 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 987691 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 12807417000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 987807 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -83,13 +83,13 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 935407 # number of replacements
system.cpu.dcache.sampled_refs 939503 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 935465 # number of replacements
system.cpu.dcache.sampled_refs 939561 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3566.459969 # Cycle average of tags in use
system.cpu.dcache.total_refs 104185688 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134193645000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 94807 # number of writebacks
system.cpu.dcache.tagsinuse 3566.815369 # Cycle average of tags in use
system.cpu.dcache.total_refs 104185630 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134193669000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 94875 # number of writebacks
system.cpu.icache.ReadReq_accesses 244425341 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 24972.696246 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22972.696246 # average ReadReq mshr miss latency
@@ -148,78 +148,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 25 # number of replacements
system.cpu.icache.sampled_refs 879 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 716.846544 # Cycle average of tags in use
system.cpu.icache.tagsinuse 716.847005 # Cycle average of tags in use
system.cpu.icache.total_refs 244424462 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 46707 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 46717 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 1027554000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 1027774000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 46707 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 513777000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_misses 46717 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 513887000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 46707 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 893675 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_mshr_misses 46717 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 893723 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 826023 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1488344000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.075701 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 67652 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 744172000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.075701 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 67652 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 48196 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_hits 826014 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1489598000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.075761 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 67709 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 744799000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.075761 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 67709 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 48254 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 1060312000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 1061588000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 48196 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530156000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_misses 48254 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530794000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 48196 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 94807 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_mshr_misses 48254 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 94807 # number of Writeback misses
system.cpu.l2cache.Writeback_misses 94875 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 94807 # number of Writeback MSHR misses
system.cpu.l2cache.Writeback_mshr_misses 94875 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 48.779815 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 48.787024 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 940382 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses 940440 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 826023 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2515898000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.121609 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 114359 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 826014 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2517372000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.121673 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 114426 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1257949000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.121609 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 114359 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 1258686000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.121673 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 114426 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 940382 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses 940440 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 826023 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2515898000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.121609 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 114359 # number of overall misses
system.cpu.l2cache.overall_hits 826014 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2517372000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.121673 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 114426 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1257949000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.121609 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 114359 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 1258686000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.121673 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 114426 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -232,14 +232,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 829 # number of replacements
system.cpu.l2cache.sampled_refs 11345 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 11344 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 8106.936507 # Cycle average of tags in use
system.cpu.l2cache.total_refs 553407 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 8106.277957 # Cycle average of tags in use
system.cpu.l2cache.total_refs 553440 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 726728254 # number of cpu cycles simulated
system.cpu.numCycles 726734038 # number of cpu cycles simulated
system.cpu.num_insts 243829010 # Number of instructions executed
system.cpu.num_refs 105710359 # Number of memory references
system.cpu.workload.PROG:num_syscalls 428 # Number of system calls

2
tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr
View File

@@ -1,2 +1,2 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7006
0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...

6
tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
View File

@@ -21,9 +21,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 28 2007 15:13:45
M5 started Wed Nov 28 15:13:46 2007
M5 compiled Nov 28 2007 18:29:37
M5 started Wed Nov 28 18:29:38 2007
M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 363364127000 because target called exit()
Exiting @ tick 363367019000 because target called exit()

18
tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt
View File

@@ -1,17 +1,17 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3238071 # Simulator instruction rate (inst/s)
host_mem_usage 185492 # Number of bytes of host memory used
host_seconds 42.04 # Real time elapsed on the host
host_tick_rate 1620906753 # Simulator tick rate (ticks/s)
host_inst_rate 3368510 # Simulator instruction rate (inst/s)
host_mem_usage 185484 # Number of bytes of host memory used
host_seconds 40.42 # Real time elapsed on the host
host_tick_rate 1686201794 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136141055 # Number of instructions simulated
sim_seconds 0.068150 # Number of seconds simulated
sim_ticks 68149604500 # Number of ticks simulated
sim_insts 136139203 # Number of instructions simulated
sim_seconds 0.068149 # Number of seconds simulated
sim_ticks 68148678500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 136299210 # number of cpu cycles simulated
system.cpu.num_insts 136141055 # Number of instructions executed
system.cpu.numCycles 136297358 # number of cpu cycles simulated
system.cpu.num_insts 136139203 # Number of instructions executed
system.cpu.num_refs 58160249 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls

1114
tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr
View File

File diff suppressed because it is too large Load Diff

6
tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
View File

@@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 28 2007 15:13:45
M5 started Wed Nov 28 15:13:46 2007
M5 compiled Nov 28 2007 18:29:37
M5 started Wed Nov 28 18:29:38 2007
M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 68149604500 because target called exit()
Exiting @ tick 68148678500 because target called exit()

178
tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
View File

@@ -1,23 +1,23 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1846845 # Simulator instruction rate (inst/s)
host_mem_usage 192856 # Number of bytes of host memory used
host_seconds 73.72 # Real time elapsed on the host
host_tick_rate 2717419538 # Simulator tick rate (ticks/s)
host_inst_rate 1907380 # Simulator instruction rate (inst/s)
host_mem_usage 192852 # Number of bytes of host memory used
host_seconds 71.38 # Real time elapsed on the host
host_tick_rate 2806502009 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136141055 # Number of instructions simulated
sim_seconds 0.200317 # Number of seconds simulated
sim_ticks 200316584000 # Number of ticks simulated
sim_insts 136139203 # Number of instructions simulated
sim_seconds 0.200315 # Number of seconds simulated
sim_ticks 200314732000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21199.169030 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19199.169030 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 964329000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_avg_miss_latency 21198.421943 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19198.421943 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 964507000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 873351000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 873509000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
@@ -31,13 +31,13 @@ system.cpu.dcache.SwapReq_mshr_misses 40 # nu
system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20754892 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2735300000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2735125000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 109412 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 2516476000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 2516315000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 109412 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks.
@@ -47,31 +47,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 23883.829026 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 21883.829026 # average overall mshr miss latency
system.cpu.dcache.demand_hits 57940704 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 3699629000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_avg_miss_latency 23883.385839 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 21883.385839 # average overall mshr miss latency
system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 3699632000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses
system.cpu.dcache.demand_misses 154901 # number of demand (read+write) misses
system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 3389827000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 3389824000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 154901 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 23883.829026 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 21883.829026 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 23883.385839 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 21883.385839 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 57940704 # number of overall hits
system.cpu.dcache.overall_miss_latency 3699629000 # number of overall miss cycles
system.cpu.dcache.overall_hits 57940701 # number of overall hits
system.cpu.dcache.overall_miss_latency 3699632000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses
system.cpu.dcache.overall_misses 154901 # number of overall misses
system.cpu.dcache.overall_misses 154904 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 3389827000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 3389824000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 154901 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -86,14 +86,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 146582 # number of replacements
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4089.107113 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4089.107586 # Cycle average of tags in use
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 584680000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 107279 # number of writebacks
system.cpu.icache.ReadReq_accesses 136295664 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.warmup_cycle 584704000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 107271 # number of writebacks
system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13638.549063 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.549063 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 136108640 # number of ReadReq hits
system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 2550736000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
@@ -102,16 +102,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # ms
system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 727.760287 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 727.750385 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 136295664 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13638.549063 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency
system.cpu.icache.demand_hits 136108640 # number of demand (read+write) hits
system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 2550736000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses
system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
@@ -122,11 +122,11 @@ system.cpu.icache.demand_mshr_misses 187024 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 136295664 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13638.549063 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 136108640 # number of overall hits
system.cpu.icache.overall_hits 136106788 # number of overall hits
system.cpu.icache.overall_miss_latency 2550736000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses
system.cpu.icache.overall_misses 187024 # number of overall misses
@@ -148,47 +148,47 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 184976 # number of replacements
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 2006.864278 # Cycle average of tags in use
system.cpu.icache.total_refs 136108640 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 142656863000 # Cycle when the warmup percentage was hit.
system.cpu.icache.tagsinuse 2006.863735 # Cycle average of tags in use
system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 142653354000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 105189 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 2314158000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2313938000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 105189 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1157079000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1156969000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 105189 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 232513 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 191480 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 902726000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.176476 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 41033 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 451363000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.176476 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 41033 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 4263 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 21963.875205 # average UpgradeReq miss latency
system.cpu.l2cache.ReadReq_hits 191486 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 902814000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.176486 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 41037 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 451407000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.176486 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 41037 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 21963.900609 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 93632000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 93698000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 4263 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46893000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46926000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 4263 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 107271 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 107279 # number of Writeback misses
system.cpu.l2cache.Writeback_misses 107271 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 107279 # number of Writeback MSHR misses
system.cpu.l2cache.Writeback_mshr_misses 107271 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 5.315911 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 5.316385 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
@@ -197,14 +197,14 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 191480 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3216884000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.432991 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 146222 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 191486 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3216752000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.432973 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 146216 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1608442000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.432991 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 146222 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 1608376000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.432973 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 146216 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
@@ -212,14 +212,14 @@ system.cpu.l2cache.overall_accesses 337702 # nu
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 191480 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3216884000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.432991 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 146222 # number of overall misses
system.cpu.l2cache.overall_hits 191486 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3216752000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.432973 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 146216 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1608442000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.432991 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 146222 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 1608376000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.432973 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 146216 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -231,16 +231,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 22010 # number of replacements
system.cpu.l2cache.sampled_refs 36485 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 22008 # number of replacements
system.cpu.l2cache.sampled_refs 36484 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 6146.948797 # Cycle average of tags in use
system.cpu.l2cache.total_refs 193951 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 6146.828377 # Cycle average of tags in use
system.cpu.l2cache.total_refs 193963 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 400633168 # number of cpu cycles simulated
system.cpu.num_insts 136141055 # Number of instructions executed
system.cpu.numCycles 400629464 # number of cpu cycles simulated
system.cpu.num_insts 136139203 # Number of instructions executed
system.cpu.num_refs 58160249 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls

1112
tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr
View File

File diff suppressed because it is too large Load Diff

6
tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
View File

@@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 28 2007 15:13:45
M5 started Wed Nov 28 15:13:46 2007
M5 compiled Nov 28 2007 18:29:37
M5 started Wed Nov 28 18:29:38 2007
M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 200316584000 because target called exit()
Exiting @ tick 200314732000 because target called exit()

6
tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt
View File

@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2409312 # Simulator instruction rate (inst/s)
host_inst_rate 2449488 # Simulator instruction rate (inst/s)
host_mem_usage 181120 # Number of bytes of host memory used
host_seconds 80.29 # Real time elapsed on the host
host_tick_rate 1204659062 # Simulator tick rate (ticks/s)
host_seconds 78.97 # Real time elapsed on the host
host_tick_rate 1224747555 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193435005 # Number of instructions simulated
sim_seconds 0.096718 # Number of seconds simulated

2
tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr
View File

@@ -1,3 +1,3 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7007
0: system.remote_gdb.listener: listening for remote gdb on port 7006
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.

4
tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
View File

@@ -18,8 +18,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 28 2007 15:13:45
M5 started Wed Nov 28 15:13:46 2007
M5 compiled Nov 28 2007 18:29:37
M5 started Wed Nov 28 18:29:38 2007
M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

8
tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
View File

@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1633041 # Simulator instruction rate (inst/s)
host_mem_usage 188484 # Number of bytes of host memory used
host_seconds 118.45 # Real time elapsed on the host
host_tick_rate 2282781107 # Simulator tick rate (ticks/s)
host_inst_rate 1710803 # Simulator instruction rate (inst/s)
host_mem_usage 188480 # Number of bytes of host memory used
host_seconds 113.07 # Real time elapsed on the host
host_tick_rate 2391482744 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193435005 # Number of instructions simulated
sim_seconds 0.270398 # Number of seconds simulated

2
tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr
View File

@@ -1,3 +1,3 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7008
0: system.remote_gdb.listener: listening for remote gdb on port 7010
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.

4
tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
View File

@@ -18,8 +18,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 28 2007 15:13:45
M5 started Wed Nov 28 15:13:46 2007
M5 compiled Nov 28 2007 18:29:37
M5 started Wed Nov 28 18:29:38 2007
M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second

8
tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
View File

@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1203 # Simulator instruction rate (inst/s)
host_mem_usage 173832 # Number of bytes of host memory used
host_seconds 4.02 # Real time elapsed on the host
host_tick_rate 609327 # Simulator tick rate (ticks/s)
host_inst_rate 1230 # Simulator instruction rate (inst/s)
host_mem_usage 173824 # Number of bytes of host memory used
host_seconds 3.93 # Real time elapsed on the host
host_tick_rate 622698 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4833 # Number of instructions simulated
sim_seconds 0.000002 # Number of seconds simulated

2
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr
View File

@@ -1,2 +1,2 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7003
0: system.remote_gdb.listener: listening for remote gdb on port 7012
warn: Entering event queue @ 0. Starting simulation...

4
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
View File

@@ -5,8 +5,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 28 2007 15:13:45
M5 started Wed Nov 28 15:13:46 2007
M5 compiled Nov 28 2007 18:29:37
M5 started Wed Nov 28 18:29:38 2007
M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

8
tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
View File

@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1173 # Simulator instruction rate (inst/s)
host_mem_usage 181108 # Number of bytes of host memory used
host_seconds 4.12 # Real time elapsed on the host
host_tick_rate 3847579 # Simulator tick rate (ticks/s)
host_inst_rate 1215 # Simulator instruction rate (inst/s)
host_mem_usage 181116 # Number of bytes of host memory used
host_seconds 3.98 # Real time elapsed on the host
host_tick_rate 3985160 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4833 # Number of instructions simulated
sim_seconds 0.000016 # Number of seconds simulated

2
tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr
View File

@@ -1,2 +1,2 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7000
0: system.remote_gdb.listener: listening for remote gdb on port 7004
warn: Entering event queue @ 0. Starting simulation...

4
tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
View File

@@ -5,8 +5,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 28 2007 15:13:45
M5 started Wed Nov 28 15:13:46 2007
M5 compiled Nov 28 2007 18:29:37
M5 started Wed Nov 28 18:29:38 2007
M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second

414
tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt
View File

@@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 2712 # Number of BTB hits
global.BPredUnit.BTBLookups 6973 # Number of BTB lookups
global.BPredUnit.BTBHits 2711 # Number of BTB hits
global.BPredUnit.BTBLookups 6964 # Number of BTB lookups
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 2013 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 7668 # Number of conditional branches predicted
global.BPredUnit.lookups 7668 # Number of BP lookups
global.BPredUnit.condIncorrect 2012 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 7659 # Number of conditional branches predicted
global.BPredUnit.lookups 7659 # Number of BP lookups
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
host_inst_rate 2391 # Simulator instruction rate (inst/s)
host_mem_usage 181652 # Number of bytes of host memory used
host_seconds 4.36 # Real time elapsed on the host
host_tick_rate 3443166 # Simulator tick rate (ticks/s)
host_inst_rate 2546 # Simulator instruction rate (inst/s)
host_mem_usage 181644 # Number of bytes of host memory used
host_seconds 4.09 # Real time elapsed on the host
host_tick_rate 3665441 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 0 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 3078 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 2957 # Number of stores inserted to the mem dependence unit.
memdepunit.memDep.insertedLoads 3077 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 2956 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 10411 # Number of instructions simulated
sim_seconds 0.000015 # Number of seconds simulated
sim_ticks 14995500 # Number of ticks simulated
sim_ticks 14990500 # Number of ticks simulated
system.cpu.commit.COM:branches 2152 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 87 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 26996
system.cpu.commit.COM:committed_per_cycle.samples 26989
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 21423 7935.62%
1 3114 1153.50%
2 1160 429.69%
3 589 218.18%
4 306 113.35%
0 21416 7935.08%
1 3114 1153.80%
2 1160 429.80%
3 589 218.24%
4 306 113.38%
5 84 31.12%
6 196 72.60%
6 196 72.62%
7 37 13.71%
8 87 32.23%
8 87 32.24%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 1462 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 2760 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 2013 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 2012 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 329 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 13215 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 13198 # The number of squashed insts skipped by commit
system.cpu.committedInsts 10411 # Number of Instructions Simulated
system.cpu.committedInsts_total 10411 # Number of Instructions Simulated
system.cpu.cpi 2.880799 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.880799 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 2269 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 9992.424242 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5515.151515 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 2203 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 659500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.029088 # miss rate for ReadReq accesses
system.cpu.cpi 2.879839 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.879839 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 2274 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 9734.848485 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5560.606061 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 2208 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 642500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.029024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 66 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 364000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.029088 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 367000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.029024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
system.cpu.dcache.WriteReq_accesses 1171 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 16051.886792 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5589.622642 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 1065 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1701500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.090521 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 106 # number of WriteReq misses
system.cpu.dcache.WriteReq_avg_miss_latency 16414.285714 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5623.809524 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 1066 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1723500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.089667 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 105 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 121 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 592500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.090521 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_miss_latency 590500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089667 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 21.376623 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 21.703947 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 3440 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13726.744186 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5561.046512 # average overall mshr miss latency
system.cpu.dcache.demand_hits 3268 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2361000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.050000 # miss rate for demand accesses
system.cpu.dcache.demand_misses 172 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 150 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 956500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.050000 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 172 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 3445 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13836.257310 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5599.415205 # average overall mshr miss latency
system.cpu.dcache.demand_hits 3274 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2366000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.049637 # miss rate for demand accesses
system.cpu.dcache.demand_misses 171 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 146 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 957500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.049637 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 3440 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13726.744186 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5561.046512 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 3445 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13836.257310 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5599.415205 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 3268 # number of overall hits
system.cpu.dcache.overall_miss_latency 2361000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.050000 # miss rate for overall accesses
system.cpu.dcache.overall_misses 172 # number of overall misses
system.cpu.dcache.overall_mshr_hits 150 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 956500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.050000 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 172 # number of overall MSHR misses
system.cpu.dcache.overall_hits 3274 # number of overall hits
system.cpu.dcache.overall_miss_latency 2366000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.049637 # miss rate for overall accesses
system.cpu.dcache.overall_misses 171 # number of overall misses
system.cpu.dcache.overall_mshr_hits 146 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 957500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.049637 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -121,87 +121,87 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks.
system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 112.808512 # Cycle average of tags in use
system.cpu.dcache.total_refs 3292 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 111.288485 # Cycle average of tags in use
system.cpu.dcache.total_refs 3299 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 3940 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 38117 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 12825 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 10166 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 2912 # Number of cycles decode is squashing
system.cpu.decode.DECODE:BlockedCycles 3945 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 38084 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 12820 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 10159 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 2909 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 65 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 7668 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 4931 # Number of cache lines fetched
system.cpu.fetch.Cycles 16230 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 591 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 42235 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 2100 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.255668 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 4931 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 2712 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.408209 # Number of inst fetches per cycle
system.cpu.fetch.Branches 7659 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 4927 # Number of cache lines fetched
system.cpu.fetch.Cycles 16219 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 589 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 42202 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 2099 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.255453 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 4927 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 2711 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.407578 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 29908
system.cpu.fetch.rateDist.samples 29898
system.cpu.fetch.rateDist.min_value 0
0 18631 6229.44%
1 4887 1634.01%
2 620 207.30%
3 712 238.06%
4 788 263.47%
5 640 213.99%
6 612 204.63%
7 196 65.53%
8 2822 943.56%
0 18628 6230.52%
1 4885 1633.89%
2 619 207.04%
3 712 238.14%
4 788 263.56%
5 640 214.06%
6 611 204.36%
7 195 65.22%
8 2820 943.21%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 4912 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses 4907 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 7495.945946 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5332.432432 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 4542 # number of ReadReq hits
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5325.675676 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 4537 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 2773500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.075326 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate 0.075402 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 370 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 19 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 1973000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.075326 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 1970500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.075402 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 12.275676 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 12.262162 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 4912 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses 4907 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 7495.945946 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5332.432432 # average overall mshr miss latency
system.cpu.icache.demand_hits 4542 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency 5325.675676 # average overall mshr miss latency
system.cpu.icache.demand_hits 4537 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 2773500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.075326 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate 0.075402 # miss rate for demand accesses
system.cpu.icache.demand_misses 370 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 19 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1973000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.075326 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_hits 20 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1970500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.075402 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 370 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 4912 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses 4907 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 7495.945946 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5332.432432 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5325.675676 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 4542 # number of overall hits
system.cpu.icache.overall_hits 4537 # number of overall hits
system.cpu.icache.overall_miss_latency 2773500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.075326 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate 0.075402 # miss rate for overall accesses
system.cpu.icache.overall_misses 370 # number of overall misses
system.cpu.icache.overall_mshr_hits 19 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1973000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.075326 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_hits 20 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1970500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.075402 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 370 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@@ -217,39 +217,39 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 370 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 233.392727 # Cycle average of tags in use
system.cpu.icache.total_refs 4542 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 233.477311 # Cycle average of tags in use
system.cpu.icache.total_refs 4537 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 84 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 3087 # Number of branches executed
system.cpu.iew.EXEC:branches 3086 # Number of branches executed
system.cpu.iew.EXEC:nop 1794 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.575487 # Inst execution rate
system.cpu.iew.EXEC:refs 4542 # number of memory reference insts executed
system.cpu.iew.EXEC:rate 0.575379 # Inst execution rate
system.cpu.iew.EXEC:refs 4543 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 2116 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 9197 # num instructions consuming a value
system.cpu.iew.WB:count 16627 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.827444 # average fanout of values written-back
system.cpu.iew.WB:consumers 9189 # num instructions consuming a value
system.cpu.iew.WB:count 16618 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.827620 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 7610 # num instructions producing a value
system.cpu.iew.WB:rate 0.554381 # insts written-back per cycle
system.cpu.iew.WB:sent 16839 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2217 # Number of branch mispredicts detected at execute
system.cpu.iew.WB:producers 7605 # num instructions producing a value
system.cpu.iew.WB:rate 0.554266 # insts written-back per cycle
system.cpu.iew.WB:sent 16830 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2216 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 3078 # Number of dispatched load instructions
system.cpu.iew.iewDispLoadInsts 3077 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 612 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 2981 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 2957 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 24347 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 2426 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2842 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 17260 # Number of executed instructions
system.cpu.iew.iewDispSquashedInsts 2973 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 2956 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 24330 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 2427 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2838 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 17251 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 2912 # Number of cycles IEW is squashing
system.cpu.iew.iewSquashCycles 2909 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
@@ -259,17 +259,17 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 57 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1616 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 1659 # Number of stores squashed
system.cpu.iew.lsq.thread.0.squashedLoads 1615 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 1658 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 57 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 695 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1522 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.347126 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.347126 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 20102 # Type of FU issued
system.cpu.iew.predictedTakenIncorrect 1521 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.347242 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.347242 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 20089 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued
IntAlu 14548 72.37% # Type of FU issued
IntAlu 14535 72.35% # Type of FU issued
IntMult 0 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 0 0.00% # Type of FU issued
@@ -278,13 +278,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 2907 14.46% # Type of FU issued
MemWrite 2647 13.17% # Type of FU issued
MemRead 2907 14.47% # Type of FU issued
MemWrite 2647 13.18% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 188 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.009352 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_rate 0.009358 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 50 26.60% # attempts to use FU when none available
@@ -302,90 +302,90 @@ system.cpu.iq.ISSUE:fu_full.start_dist
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 29908
system.cpu.iq.ISSUE:issued_per_cycle.samples 29898
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 21042 7035.58%
1 3623 1211.38%
2 2132 712.85%
3 1562 522.27%
4 750 250.77%
5 405 135.42%
6 293 97.97%
7 62 20.73%
0 21040 7037.26%
1 3621 1211.12%
2 2127 711.42%
3 1561 522.11%
4 748 250.18%
5 407 136.13%
6 293 98.00%
7 62 20.74%
8 39 13.04%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 0.670245 # Inst issue rate
system.cpu.iq.iqInstsAdded 21941 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 20102 # Number of instructions issued
system.cpu.iq.ISSUE:rate 0.670035 # Inst issue rate
system.cpu.iq.iqInstsAdded 21924 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 20089 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 612 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 10302 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsExamined 10307 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 8248 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 88 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4431.818182 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2431.818182 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 390000 # number of ReadExReq miss cycles
system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 86 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4424.418605 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2424.418605 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 380500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 88 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 214000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_misses 86 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 208500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 88 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 86 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 436 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4283.564815 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2283.564815 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 4287.037037 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2287.037037 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1850500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 1852000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.990826 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 432 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 986500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 988000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990826 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 432 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 18 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4416.666667 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2416.666667 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 79500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4421.052632 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2421.052632 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 84000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 18 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 43500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 18 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.009662 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.009685 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 524 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4308.653846 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2308.653846 # average overall mshr miss latency
system.cpu.l2cache.demand_accesses 522 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4309.845560 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2309.845560 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2240500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.992366 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 520 # number of demand (read+write) misses
system.cpu.l2cache.demand_miss_latency 2232500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.992337 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 518 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1200500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.992366 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 520 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 1196500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.992337 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 518 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 524 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4308.653846 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2308.653846 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 522 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4309.845560 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2309.845560 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 4 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2240500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.992366 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 520 # number of overall misses
system.cpu.l2cache.overall_miss_latency 2232500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.992337 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 518 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1200500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.992366 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 520 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 1196500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.992337 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 518 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -398,23 +398,23 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 260.564179 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 259.708792 # Cycle average of tags in use
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 29992 # number of cpu cycles simulated
system.cpu.numCycles 29982 # number of cpu cycles simulated
system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles 14199 # Number of cycles rename is idle
system.cpu.rename.RENAME:RenameLookups 51943 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 30018 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 24503 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 8879 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 2912 # Number of cycles rename is squashing
system.cpu.rename.RENAME:IdleCycles 14192 # Number of cycles rename is idle
system.cpu.rename.RENAME:RenameLookups 51924 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 30001 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 24487 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 8874 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 2909 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 230 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 14635 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 3688 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:UndoneMaps 14619 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 3693 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 648 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 4472 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 685 # count of temporary serializing insts renamed

2
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr
View File

@@ -1,2 +1,2 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7004
0: system.remote_gdb.listener: listening for remote gdb on port 7005
warn: Entering event queue @ 0. Starting simulation...

6
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout
View File

@@ -16,9 +16,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 28 2007 15:13:45
M5 started Wed Nov 28 15:13:46 2007
M5 compiled Nov 28 2007 18:29:37
M5 started Wed Nov 28 18:29:38 2007
M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 14995500 because target called exit()
Exiting @ tick 14990500 because target called exit()

6
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt
View File

@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2681 # Simulator instruction rate (inst/s)
host_inst_rate 2595 # Simulator instruction rate (inst/s)
host_mem_usage 173616 # Number of bytes of host memory used
host_seconds 4.09 # Real time elapsed on the host
host_tick_rate 1346729 # Simulator tick rate (ticks/s)
host_seconds 4.23 # Real time elapsed on the host
host_tick_rate 1303618 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 10976 # Number of instructions simulated
sim_seconds 0.000006 # Number of seconds simulated

4
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout
View File

@@ -16,8 +16,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 28 2007 15:13:45
M5 started Wed Nov 28 15:13:46 2007
M5 compiled Nov 28 2007 18:29:37
M5 started Wed Nov 28 18:29:38 2007
M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

134
tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
View File

@@ -1,38 +1,38 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2502 # Simulator instruction rate (inst/s)
host_inst_rate 2763 # Simulator instruction rate (inst/s)
host_mem_usage 180992 # Number of bytes of host memory used
host_seconds 4.39 # Real time elapsed on the host
host_tick_rate 5561973 # Simulator tick rate (ticks/s)
host_seconds 3.97 # Real time elapsed on the host
host_tick_rate 6131000 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 10976 # Number of instructions simulated
sim_seconds 0.000024 # Number of seconds simulated
sim_ticks 24403000 # Number of ticks simulated
sim_ticks 24355000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1407 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1375000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.037620 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1265000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.037620 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_hits 1408 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1350000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.036936 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1242000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.036936 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 1186 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2650000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.082043 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 106 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 2438000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.082043 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_hits 1187 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2625000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.081269 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 105 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 2415000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.081269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 18.166667 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 18.436620 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
@@ -41,14 +41,14 @@ system.cpu.dcache.cache_copies 0 # nu
system.cpu.dcache.demand_accesses 2754 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 2593 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 4025000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.058460 # miss rate for demand accesses
system.cpu.dcache.demand_misses 161 # number of demand (read+write) misses
system.cpu.dcache.demand_hits 2595 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 3975000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.057734 # miss rate for demand accesses
system.cpu.dcache.demand_misses 159 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 3703000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.058460 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 161 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 3657000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.057734 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 159 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
@@ -56,14 +56,14 @@ system.cpu.dcache.overall_accesses 2754 # nu
system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 2593 # number of overall hits
system.cpu.dcache.overall_miss_latency 4025000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.058460 # miss rate for overall accesses
system.cpu.dcache.overall_misses 161 # number of overall misses
system.cpu.dcache.overall_hits 2595 # number of overall hits
system.cpu.dcache.overall_miss_latency 3975000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.057734 # miss rate for overall accesses
system.cpu.dcache.overall_misses 159 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 3703000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.058460 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 161 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 3657000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.057734 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 159 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -76,10 +76,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks.
system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 101.761875 # Cycle average of tags in use
system.cpu.dcache.total_refs 2616 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 100.373888 # Cycle average of tags in use
system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 11012 # number of ReadReq accesses(hits+misses)
@@ -140,30 +140,30 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 155.854818 # Cycle average of tags in use
system.cpu.icache.tagsinuse 155.977710 # Cycle average of tags in use
system.cpu.icache.total_refs 10729 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 89 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 88 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 1958000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 1936000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 89 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 979000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_misses 88 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 968000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 89 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 338 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_mshr_misses 88 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 337 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 7392000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.994083 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 336 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 3696000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994083 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 336 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_miss_latency 7370000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.994065 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 335 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 3685000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994065 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 335 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
@@ -175,38 +175,38 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1
system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.006270 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.006289 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 427 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses 425 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 9350000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995316 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 425 # number of demand (read+write) misses
system.cpu.l2cache.demand_miss_latency 9306000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995294 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 4675000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.995316 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 425 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 4653000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.995294 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 427 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses 425 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.overall_miss_latency 9350000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995316 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 425 # number of overall misses
system.cpu.l2cache.overall_miss_latency 9306000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995294 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 423 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 4675000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.995316 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 425 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 4653000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.995294 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -219,14 +219,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 319 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 318 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 178.928867 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 178.108320 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 48806 # number of cpu cycles simulated
system.cpu.numCycles 48710 # number of cpu cycles simulated
system.cpu.num_insts 10976 # Number of instructions executed
system.cpu.num_refs 2770 # Number of memory references
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls

2
tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr
View File

@@ -1,2 +1,2 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7002
0: system.remote_gdb.listener: listening for remote gdb on port 7011
warn: Entering event queue @ 0. Starting simulation...

6
tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
View File

@@ -16,9 +16,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 28 2007 15:13:45
M5 started Wed Nov 28 15:13:46 2007
M5 compiled Nov 28 2007 18:29:37
M5 started Wed Nov 28 18:29:38 2007
M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 24403000 because target called exit()
Exiting @ tick 24355000 because target called exit()