Commit Graph

20410 Commits

Author SHA1 Message Date
Roger Chang
f41172f9e4 tests: Add RV32 test binaries 2023-08-22 16:00:16 +08:00
Roger Chang
61488e1e17 tests: Add more tests for RV64 2023-08-22 16:00:16 +08:00
Roger Chang
fee1c3fc7a tests: Update asmtest script
Upload the config script to make it only for riscv asmtest and replace
Resource with obtain_resourse

Change-Id: I0bab96ea352b7ce1c6838203bfa13eee795f41f9
2023-08-22 16:00:16 +08:00
Bobby R. Bruce
f9a4a794b7 misc: Add DRAMSys tests to our weekly tests (#198)
This adds the DRAMSys tests to our weekly-tests.yaml file
2023-08-21 17:31:36 -07:00
Melissa Jost
e611cc66b1 misc: ADD DRAMSys tests to our weekly tests
This adds the DRAMSys tests to our weekly-tests.yaml file

Change-Id: Ieb7903a3a7ffae6359b3de5f66e1dd65eb51fc80
2023-08-21 11:53:08 -07:00
Bobby R. Bruce
63b91b51a2 mem-cache: Allow clflush's uncacheable requests on classic cache (#205)
When a linux kernel changes a page property, it flushes the related
cache lines. The kernel might change the page property before flushing
the cache lines. This results in the clflush might occur in an
uncacheable region.

Currently, an uncacheable request must be a read or a write. However,
clflush request is neither of them.

This change aims to allow clflush requests to work on uncacheable
regions. Since there is no straightforward way to check if a packet is
from a clflush instruction, this change permits all Clean Invalidate
Requests, which is the type of request produced by clflush, to work on
uncacheable regions.
2023-08-21 10:42:10 -07:00
Bobby R. Bruce
f98cd15ec7 arch-riscv,systemc: Update cxx_config_cc.py to use is port.is_source (#196)
Fix for issue #181. Update the port description generation to use the
port.is_source attribute.
2023-08-20 21:00:33 -07:00
Bobby R. Bruce
e5fcc116ec ext: Update DRAMSys README (#202)
This fixes:

1. Most importantly: The submodule recursive update was incorrect. This
adds the recursive obtaining of submodules as a seperate explicity step.
2. Changes the `git clone` to use https.
2023-08-20 20:13:17 -07:00
Thilo Vörtler
73b6e98f51 arch-riscv,systemc: Fix cxx_config_cc.py to use is is_source
Update the cxx_config_cc.oy port description generation to use the
port.is_source attribute.

Github Issue: https://github.com/gem5/gem5/issues/181

Change-Id: I3fa12c2fbb06083379118e57aedb8be414c0d929
2023-08-20 14:06:37 +00:00
Hoa Nguyen
9e007e5bd7 mem-cache: fix wrong function call
Change-Id: I924ede89f373ec21557faf25c96b36f4bc8430dd
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-08-19 22:56:55 +00:00
Hoa Nguyen
f442846d9d mem-cache: Fix another typo
Change-Id: Ib2051f9bda6e6d9002d3be1dbf0b890299098201
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-08-19 22:50:53 +00:00
Hoa Nguyen
7b897a30fa mem-cache: Fix syntax error
Change-Id: I1360879c13d377661e9eeeddf345b785c01efeb6
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-08-19 21:27:53 +00:00
Hoa Nguyen
98daec7d99 mem-cache: Allow clflush's uncacheable requests on classic cache
When a linux kernel changes a page property, it flushes the related cache
lines. The kernel might change the page property before flushing the
cache lines. This results in the clflush might occur in an uncacheable region.

Currently, an uncacheable request must be a read or a write. However,
clflush request is neither of them.

This change aims to allow clflush requests to work on uncacheable regions.
Since there is no straightforward way to check if a packet is from a clflush
instruction, this change permits all Clean Invalidate Requests, which is
the type of request produced by clflush, to work on uncacheable regions.

Change-Id: Ib3ec01d9281d3dfe565a0ced773ed912edb32b8f
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-08-19 18:20:16 +00:00
Bobby R. Bruce
16752b7ca2 ext: Update DRAMSys README
This fixes:

1. Most importantly: The submodule recursive update was incorrect. This
adds the recursive obtaining of submodules as a seperate explicity step.
2. Changes the `git clone` to use https.

Change-Id: Iad69e44b927a5aa982b49dffa6929c52fcc7ee72
2023-08-18 15:43:14 -07:00
Bobby R. Bruce
d7d441becb tests: Add checkpoint tests for all ISAs (#167)
Added save and restore checkpoint tests for arm-hello, x86-hello,
x86-fs, power-hello

Added mips and sparc test but mips does not support checkpoint and there
is a bug in sparc.

Added test file to run the tests.
2023-08-18 15:01:39 -07:00
Bobby R. Bruce
ac88871017 misc: Update matrix runs in scheduled tests (#194)
This changes continue-on-error to be fail-fast instead, as
continue-on-error will mark failed matrix runs as
successful, whereas fail-fast makes sure everything in the matrix runs,
but gets marked as failed if part of it fails.
2023-08-18 10:56:26 -07:00
Bobby R. Bruce
30ab2c19b1 stdlib: Allow passing of func as Exit Event generator (#195)
In this case the function is turned into a generator with the "yield" of
the generator the return the function's execution.

Translation of this stale Gerrit Change:
https://gem5-review.googlesource.com/c/public/gem5/+/62872
2023-08-18 10:55:50 -07:00
Harshil Patel
9d86a559ed tests: removed mips tests and added issue link.
- Removed MIPS tests.
- Added link to github issue sparc test bug.

Change-Id: Ib3c69dca578371ecf0ac2d7694f46f24834a7e5f
2023-08-18 09:51:40 -07:00
Bobby R. Bruce
c0216dbe48 stdlib: Allow passing of func as Exit Event generator
In this case the function is turned into a generator with the
"yield" of the generator the return the function's execution.

Change-Id: I4b06d64c5479638712a11e3c1a2f7bd30f60d188
2023-08-17 16:48:33 -07:00
Jason Lowe-Power
22c52f4fba Fix reporting traps (faults) to GDB in SE mode (#166)
This addresses #123
2023-08-17 16:08:49 -07:00
Melissa Jost
fa49de5b98 misc: Update matrix runs in scheduled tests
This changes continue-on-error to be fail-fast instead, as
continue-on-error will mark failed matrix runs as
successful, whereas fail-fast makes sure everything in the matrix
runs, but gets marked as failed if part of it fails.

Change-Id: Ie20652c229b6cce9f1c0a45958b088391e7aae97
2023-08-17 15:56:02 -07:00
Bobby R. Bruce
fe43e4a3e3 arch-riscv: Check CSR before executing VMem instructions (#187)
Any instructions require vector register should check if vector is
enabled. Any instructions need vtype CSR to execute them should check
vill bit beforehead.
2023-08-17 11:20:21 -07:00
Jan Vrany
3564348eec arch-riscv: Report traps to GDB in SE mode
This commit add code to report illegal instruction and breakpoint traps
to GDB (if connected). This merely follows what POWER does.
2023-08-17 15:55:04 +01:00
Jan Vrany
546b3eac7d arch-riscv: Do not advance PC when handling faults in SE mode
On RISC-V when trap occurs the contents of PC register contains the
address of instruction that caused that trap (as opposed to the address
of instruction following it in instruction stream). Therefore this commit
does not advance the PC before reporting trap in SE mode.

Change-Id: I83f3766cff276312cefcf1b4ac6e78a6569846b9
2023-08-17 15:55:04 +01:00
Jan Vrany
fde58a4365 arch-power: Fix reporting traps to GDB
Due to inverted logic in POWER fault handlers, unimplemented opcode and
trap faults did not report trap to GDB (if connected). This commit fixes
the problem.

While at it, I opted to use `if (! ...) { panic(...) }` rather than
`panic_if(...)`. I find it easier to understand in this case.

Change-Id: I6cd5dfd5f6546b8541d685e877afef21540d6824
2023-08-17 15:55:04 +01:00
Roger Chang
fe142f485a arch-riscv: Add missing vector required check for vmem instructions
The mem instructions usually executed from initiateAcc. We also need
to check vector required in those instructions

Change-Id: I97b4fec7fada432abb55ca58050615e12e00d1ca
2023-08-17 09:53:30 +08:00
Roger Chang
35a6fe6f3d arhc-riscv: Check vill in vector mem instructions
Any vector instructions using vtype should check vill flag is set

Change-Id: Ia9a2695f3005a176422da78e6f413cc789116faa
2023-08-17 09:53:30 +08:00
Bobby R. Bruce
3ff6fe0e90 arch-x86,cpu-kvm: Fix gem5.fast due to unused variable (#189)
Detected via this failing workload:
https://github.com/gem5/gem5/actions/runs/5861958237

Ir caused the following compilation error to be thrown:

```
src/arch/x86/kvm/x86_cpu.cc:1462:22: error: unused variable ‘rv’ [-Werror=unused-variable]
 1462 |                 bool rv = isa->cpuid->doCpuid(tc, function, idx, cpuid);
      |                      ^~
```

`rv` is unused in the .fast compilation as it's only used in the
`assert` statement immediately after.

To fix this, the `[[maybe_unused]]` annotation is used.
2023-08-16 12:52:44 -07:00
Bobby R. Bruce
f6b116d8a0 util-docker: Fix clang-version-8 docker container (#190)
clang v8, when installed in this manner via Docker, did not install the
libstdc++. This caused compilation errors. This patch adds the
libstdc++-10-dev package to this Dockerfile.
2023-08-16 12:52:25 -07:00
Bobby R. Bruce
c835c9faa3 arch-x86,cpu-kvm: Fix gem5.fast due to unused variable
Detected via this failing workload:
https://github.com/gem5/gem5/actions/runs/5861958237

It caused the following compilation error to be thrown:

```
src/arch/x86/kvm/x86_cpu.cc:1462:22: error: unused variable ‘rv’ [-Werror=unused-variable]
 1462 |                 bool rv = isa->cpuid->doCpuid(tc, function, idx, cpuid);
      |                      ^~
```

`rv` is unused in the .fast compilation as it's only used in the
`assert` statement immediately after.

 To fix this, the `[[maybe_unused]]` annotation is used

Change-Id: Ib98dd859c62f171c8eeefae93502f92a8f133776
2023-08-16 10:06:39 -07:00
Bobby R. Bruce
74f6fa34af util-docker: Fix clang-version-8 docker container
clang v8, when installed in this manner via Docker, did not install the
libstdc++. This caused compilation errors. This patch adds the
libstdc++-10-dev package to this Dockerfile.

Change-Id: Ia0f41e82b3df2d4bf32b418b0cb78111a35e0b9f
2023-08-16 10:00:45 -07:00
Matthew Poremba
bc9bbc10f0 gpu-compute: Change kernel-based exit location (#184)
The previous exit event occurs when the dispatcher sends a completion
signal for a kernel, but gem5 does some kernel-based stats updates after
the signal is sent. Therefore, if these exit events are used as a way to
dump per-kernel stats, some of the stats for the kernel that just ended
will be in the next kernel's stat dump which is misleading.

This patch moves the exit event to where the stats are updated and only
exits if the dispatcher has requested a stat dump to prevent situations
where stats are updated mid-kernel.

Change-Id: I74dc1cad5fc90382a2a80564764b3e7c9fb65521
2023-08-16 07:38:12 -07:00
Andreas Sandberg
f6d44ac7b3 fastmodel: Add option to retry licence server connection. (#183)
We're seeing some occasional connection timeouts in CI, possibly when we
aggressively hit the license server, so let's add a parameter to retry
the connection a few times.

Also, print the time required to connect to the server to help debug
issues.
2023-08-16 10:08:59 +01:00
Bobby R. Bruce
9ee400ff92 mem: Port trace in xbar when address error (#180)
When xbar encounters the address error, print out the port trace in the
packet for user to debug if the port trace is enabled.

To gain the packet of the access, the parameter of findPort() function
is changed from AddrRange to PacketPtr.

When running gem5 with "--debug-flags=PortTrace", we can see the full
path of the unexpected access when xbar cannot find the destination of
the address.
2023-08-15 23:27:17 -07:00
Bobby R. Bruce
954328fa28 mem: Fixing memory size type issue in port proxy. (#185)
This patch changes the data type used for image size from int to
uint64_t. Current version allows initializing AbstractMemory types with
a maximum binary size of 2GiB. This will be limiting in many studies.
2023-08-15 21:43:42 -07:00
Mahyar Samani
d869018226 mem: Fixing memory size type issue in port proxy.
This patch changes the data type used for image size from int
to uint64_t. Current version allows initializing AbstractMemory
types with a maximum binary size of 2GiB. This will be limiting
in many studies.

Change-Id: Iea3bbd525d4a67aa7cf606f6311aef66c9b4a52c
2023-08-15 12:40:45 -07:00
Matthew Poremba
df4739929d gpu-compute: Change kernel-based exit location
The previous exit event occurs when the dispatcher sends a completion
signal for a kernel, but gem5 does some kernel-based stats updates after
the signal is sent. Therefore, if these exit events are used as a way to
dump per-kernel stats, some of the stats for the kernel that just ended
will be in the next kernel's stat dump which is misleading.

This patch moves the exit event to where the stats are updated and only
exits if the dispatcher has requested a stat dump to prevent situations
where stats are updated mid-kernel.

Change-Id: I74dc1cad5fc90382a2a80564764b3e7c9fb65521
2023-08-15 11:06:26 -05:00
Nicolas Boichat
3ea7a792b0 fastmodel: Add option to retry licence server connection.
We're seeing some occasional connection timeouts in CI, possibly
when we aggressively hit the license server, so let's add a
parameter to retry the connection a few times.

Also, print the time required to connect to the server to help
debug issues.

Change-Id: I804af28f79f893fcdca615d7bf82dd9b8686a74c
2023-08-15 10:47:32 +00:00
Yan Lee
96d80a41d2 mem: dump out port trace when address decode error
1. Add findPort(PacketPtr pkt) for getting the port trace from the Packet.
   Keep the findPort(AddrRange addr_range) for recvMemBackdoorReq(...)
2. With the debug flag `PortTrace` enabled, user can see the full path of
   the packet with the corresponding address when address error in xbar.

Change-Id: Iaf43ee2d7f8c46b9b84b2bc421a6bc3b02e01b3e
2023-08-15 00:41:42 -07:00
Yan Lee
b01590fdf4 mem: port: add getTraceInString() method
Return the whole port trace of the packet as a string.

Change-Id: I7b1b1fef628a47a6ce147cb5fb75af81948c1d89
2023-08-15 00:40:29 -07:00
Yan Lee
5edb760414 mem: port: add address value in the port trace
Add the address value from the packet with the request port name.

Change-Id: I3d4c75f48ca6fbdbd5656e594d5f85f9e5626be8
2023-08-15 00:38:29 -07:00
Harshil Patel
b19d4beeb8 tests: Removed mips checkpoint tests
Change-Id: I03ad0025ec982245721fd7faad8d75cdbb99cf81
2023-08-11 09:00:11 -07:00
Bobby R. Bruce
41dcd3c5d5 misc: Add continue-on-error to matrix runs (#175)
This sets continue-on-error to true on any scheduled test that uses a
matrix so we can have all sets of tests run regardless if one of them
fails or not.
2023-08-11 07:39:25 -07:00
Bobby R. Bruce
fa918f61d1 tests: Move replacement policy and simulator config files (#173)
Moving these files should address the failures in the daily tests.
2023-08-11 07:39:06 -07:00
Bobby R. Bruce
cfea9afae3 misc: Update MAINTAINERS.yaml (#155)
- Updates the list of current gem5 Maintainers.
- Updates the MAINATAINERS.yaml comments to reflect gem5's contribution
policy and maintainer responsibilities since moving to GitHub.
- Updates the subsystem maintainers, based on maintainer's stated
preferences.
- Adds the optional 'expert' field to subsystems.
2023-08-11 02:05:26 -07:00
Melissa Jost
b08bc5ff56 misc: Add continue-on-error to matrix runs
This sets continue-on-error to true on any scheduled test that
uses a matrix so we can have all sets of tests run regardless
if one of them fails or not.

Change-Id: I8f6137ebdf62a5cecd582387316c330c8a1401ca
2023-08-10 16:58:22 -07:00
Melissa Jost
912b7c06dd tests: Move replacement policy and simulator config files
Moving these files should address the failures in the daily
tests.

Change-Id: I438adba1a45bdf6083651b6b3f610c8bbe4ebdf0
2023-08-10 16:38:20 -07:00
Bobby R. Bruce
6ca9435961 misc: Add Matt P. as maintainer to requested tags
Change-Id: Ifffb34acbf9ebf313e5bc09ebbfd2a44a017359a
2023-08-10 15:52:00 -07:00
Bobby R. Bruce
a41c6f8d84 misc: Remove PMC/Maintainers list from MAINTAINERS.yaml
Change-Id: I772fa31d0aeea5534355731d841cf2d118fa0df4
2023-08-10 15:48:13 -07:00
Bobby R. Bruce
557d532bc3 misc: Add Jason Lowe-Power as website expert
Change-Id: I52ebce434732bb921efc040397a9aa9538a6d1d9
2023-08-10 15:46:02 -07:00