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arhc-riscv: Check vill in vector mem instructions

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Any vector instructions using vtype should check vill flag is set

Change-Id: Ia9a2695f3005a176422da78e6f413cc789116faa
This commit is contained in:
Roger Chang
2023-08-14 13:58:04 +08:00
parent 3ff6fe0e90
commit 35a6fe6f3d
1 changed files with 25 additions and 4 deletions
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29
src/arch/riscv/isa/templates/vector_mem.isa
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@@ -137,6 +137,8 @@ Fault
return std::make_shared<IllegalInstFault>(
"RVV is disabled or VPU is off", machInst);
}
if (machInst.vill)
return std::make_shared<IllegalInstFault>("VILL is set", machInst);
if(!machInst.vm) {
xc->getRegOperand(this, _numSrcRegs - 1, &tmp_v0);
v0 = tmp_v0.as<uint8_t>();
@@ -175,6 +177,9 @@ Fault
%(op_rd)s;
%(ea_code)s;
if (machInst.vill)
return std::make_shared<IllegalInstFault>("VILL is set", machInst);
uint32_t mem_size = width_EEW(this->machInst.width) / 8 * this->microVl;
const std::vector<bool> byte_enable(mem_size, true);
Fault fault = initiateMemRead(xc, EA, mem_size, memAccessFlags,
@@ -297,6 +302,8 @@ Fault
return std::make_shared<IllegalInstFault>(
"RVV is disabled or VPU is off", machInst);
}
if (machInst.vill)
return std::make_shared<IllegalInstFault>("VILL is set", machInst);
if(!machInst.vm) {
xc->getRegOperand(this, _numSrcRegs - 1, &tmp_v0);
v0 = tmp_v0.as<uint8_t>();
@@ -338,6 +345,8 @@ Fault
RiscvISA::vreg_t tmp_v0;
uint8_t *v0;
if (machInst.vill)
return std::make_shared<IllegalInstFault>("VILL is set", machInst);
if(!machInst.vm) {
xc->getRegOperand(this, _numSrcRegs - 1, &tmp_v0);
v0 = tmp_v0.as<uint8_t>();
@@ -761,6 +770,8 @@ Fault
return std::make_shared<IllegalInstFault>(
"RVV is disabled or VPU is off", machInst);
}
if (machInst.vill)
return std::make_shared<IllegalInstFault>("VILL is set", machInst);
%(op_decl)s;
%(op_rd)s;
constexpr uint8_t elem_size = sizeof(Vd[0]);
@@ -799,7 +810,8 @@ Fault
{
Fault fault = NoFault;
Addr EA;
if (machInst.vill)
return std::make_shared<IllegalInstFault>("VILL is set", machInst);
%(op_src_decl)s;
%(op_rd)s;
constexpr uint8_t elem_size = sizeof(Vd[0]);
@@ -953,6 +965,8 @@ Fault
return std::make_shared<IllegalInstFault>(
"RVV is disabled or VPU is off", machInst);
}
if (machInst.vill)
return std::make_shared<IllegalInstFault>("VILL is set", machInst);
%(op_decl)s;
%(op_rd)s;
constexpr uint8_t elem_size = sizeof(Vs3[0]);
@@ -987,7 +1001,8 @@ Fault
{
Fault fault = NoFault;
Addr EA;
if (machInst.vill)
return std::make_shared<IllegalInstFault>("VILL is set", machInst);
RiscvISA::vreg_t tmp_v0;
uint8_t *v0;
if(!machInst.vm) {
@@ -1126,6 +1141,8 @@ Fault
return std::make_shared<IllegalInstFault>(
"RVV is disabled or VPU is off", machInst);
}
if (machInst.vill)
return std::make_shared<IllegalInstFault>("VILL is set", machInst);
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
@@ -1165,7 +1182,8 @@ Fault
using vu = std::make_unsigned_t<ElemType>;
Fault fault = NoFault;
Addr EA;
if (machInst.vill)
return std::make_shared<IllegalInstFault>("VILL is set", machInst);
%(op_src_decl)s;
%(op_rd)s;
constexpr uint8_t elem_size = sizeof(Vd[0]);
@@ -1327,6 +1345,8 @@ Fault
return std::make_shared<IllegalInstFault>(
"RVV is disabled or VPU is off", machInst);
}
if (machInst.vill)
return std::make_shared<IllegalInstFault>("VILL is set", machInst);
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
@@ -1362,7 +1382,8 @@ Fault
using vu = std::make_unsigned_t<ElemType>;
Fault fault = NoFault;
Addr EA;
if (machInst.vill)
return std::make_shared<IllegalInstFault>("VILL is set", machInst);
%(op_src_decl)s;
%(op_rd)s;
%(ea_code)s;