derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-riscv: Do not advance PC when handling faults in SE mode

Browse Source 
On RISC-V when trap occurs the contents of PC register contains the
address of instruction that caused that trap (as opposed to the address
of instruction following it in instruction stream). Therefore this commit
does not advance the PC before reporting trap in SE mode.

Change-Id: I83f3766cff276312cefcf1b4ac6e78a6569846b9
This commit is contained in:
Jan Vrany
2023-08-08 15:07:06 +01:00
parent fde58a4365
commit 546b3eac7d
1 changed files with 6 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/arch/riscv/faults.cc
View File

@@ -164,8 +164,6 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
pc_state.set(addr);
tc->pcState(pc_state);
} else {
inst->advancePC(pc_state);
tc->pcState(pc_state);
invokeSE(tc, inst);
}
}
@@ -234,6 +232,12 @@ BreakpointFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
void
SyscallFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
{
/* Advance the PC to next instruction so - once (simulated) syscall
is executed - execution continues. */
auto pc_state = tc->pcState().as<PCState>();
inst->advancePC(pc_state);
tc->pcState(pc_state);
tc->getSystemPtr()->workload->syscall(tc);
}