From 546b3eac7df292afc387067216b49a485e357923 Mon Sep 17 00:00:00 2001 From: Jan Vrany Date: Tue, 8 Aug 2023 15:07:06 +0100 Subject: [PATCH] arch-riscv: Do not advance PC when handling faults in SE mode On RISC-V when trap occurs the contents of PC register contains the address of instruction that caused that trap (as opposed to the address of instruction following it in instruction stream). Therefore this commit does not advance the PC before reporting trap in SE mode. Change-Id: I83f3766cff276312cefcf1b4ac6e78a6569846b9 --- src/arch/riscv/faults.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc index a929902e8b..9bea0668e8 100644 --- a/src/arch/riscv/faults.cc +++ b/src/arch/riscv/faults.cc @@ -164,8 +164,6 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) pc_state.set(addr); tc->pcState(pc_state); } else { - inst->advancePC(pc_state); - tc->pcState(pc_state); invokeSE(tc, inst); } } @@ -234,6 +232,12 @@ BreakpointFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst) void SyscallFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst) { + /* Advance the PC to next instruction so - once (simulated) syscall + is executed - execution continues. */ + auto pc_state = tc->pcState().as(); + inst->advancePC(pc_state); + tc->pcState(pc_state); + tc->getSystemPtr()->workload->syscall(tc); }