Commit Graph

21217 Commits

Author SHA1 Message Date
Bobby R. Bruce
c4146d8813 misc: Fix 'maybe-uninitialized' warn turn off (#706)
https://github.com/gem5/gem5/pull/696 was implemented incorrectly and
and causes error when running with GCC 12.1. This patch fixes the error.
2023-12-21 18:45:56 -08:00
Bobby R. Bruce
e95389920a misc: Turn off 'maybe-uninitialized' warn for regex include (#696)
https://github.com/gem5/gem5/pull/636 triggered a bug with the GCC
compiler and its interaction with the CPP stdlib regex library, outlined
here: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105562.

This was causing the gem5 Compiler tests to fail for GCC-12:
https://github.com/gem5/gem5/actions/runs/7219055796

This fix turns off the 'maybe-unitialized' warning when we include the
regex headers in "src/kern/linux/helpers.cc".
2023-12-21 18:45:47 -08:00
Bobby R. Bruce
d6b798431f mem-ruby,configs: Enable Ruby with NULL build (#704)
After removing `get_runtime_isa`, the `send_evicts` function in the ruby
configs assumes that there is an ISA built. This change short-circuits
that logic if the current build is the NULL (none) ISA.
2023-12-21 10:22:42 -08:00
Harshil Patel
5288dbbf90 mem: Updated bytesRead and bytesWritten stat (#705)
- The bytesRead and bytesWritten stat had duplicate names. Updated
bytesRead and bytesWritten for dram_interface and nvm_interface

Change-Id: I7658e8a0d12ef6b95819bcafa52a85424f01ac76
2023-12-21 10:21:40 -08:00
Bobby R. Bruce
25e0e96741 misc: Fix 'maybe-uninitialized' warn turn off (#706)
https://github.com/gem5/gem5/pull/696 was implemented incorrectly and
and causes error when running with GCC 12.1. This patch fixes the error.
2023-12-21 10:21:20 -08:00
Jason Lowe-Power
bab8af44fb Revert "tests: Fix garnet and memcheck tests to use X86"
This reverts commit b22ca02a65.
2023-12-20 15:32:57 -08:00
Jason Lowe-Power
7adaaa6f2a mem-ruby,configs: Enable Ruby with NULL build
After removing `get_runtime_isa`, the `send_evicts` function in the ruby
configs assumes that there is an ISA built. This change short-circuits
that logic if the current build is the NULL (none) ISA.

Change-Id: I75fefe3d70649b636b983c4d2145c63a9e1342f7
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2023-12-20 15:26:03 -08:00
Bobby R. Bruce
82b5c332b7 tests: Fix Daily memory tests (#695)
Fixes a series of issues in the Daily memory tests causing test failure.
Discussed in #697.
2023-12-20 13:11:25 -08:00
Bobby R. Bruce
2f58f1c87b misc: Turn off 'maybe-uninitialized' warn for regex include (#696)
https://github.com/gem5/gem5/pull/636 triggered a bug with the GCC
compiler and its interaction with the CPP stdlib regex library, outlined
here: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105562.

This was causing the gem5 Compiler tests to fail for GCC-12:
https://github.com/gem5/gem5/actions/runs/7219055796

This fix turns off the 'maybe-unitialized' warning when we include the
regex headers in "src/kern/linux/helpers.cc".
2023-12-20 13:10:56 -08:00
Bobby R. Bruce
213d0b0bfe cpu: 'suppressFuncErrors' -> 'pkt->suppressFuncError()' fix
Change-Id: If4aa71e9f6332df2a3daa51b69eaad97f6603f6b
2023-12-20 09:15:15 -08:00
Giacomo Travaglini
4f5d4b9baf mem-ruby: Implement WriteUniqueZero CHI transaction (#692)
The WriteUniqueZero is an immediate write to a Snoopable address region
that does not require any data transfer (cacheline is zeroed)

Change-Id: Ia8c9b40e08a3b7d613f0b62ce0ac4b0547860871

Reviewed-by: Tiago Muck <tiago.muck@arm.com>

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-12-19 11:12:50 +00:00
Bobby R. Bruce
211d00f48f misc: Cherry pick changes from develop to the v23.1 staging branch (#699)
This PR includes:

* #689 
* #510
2023-12-18 17:29:46 -08:00
Harshil Patel
d76a01973a util: Added script to copy resources from mongodb (#510)
- This script copies all resources from a mongodb database locally The
script creates a resources.json and downloads all the resources. It also
updates the resources.json to point to these local downloads instead of
the cloud bucket.

Change-Id: I15480c4ba82bbf245425205c9c1ab7c0f3501cc3
2023-12-18 17:28:19 -08:00
Tiberiu Bucur
27d89379d2 sim: Remove trailing / from proc/meminfo special path (#689)
Note: A bug was identified in that the one of the special file paths,
namely /proc/meminfo contained an extra trailing /, implicitly making
the incorrect assumption that meminfo was a directory, when it is, in
fact, a (pseudo-)file. This was causing application in SE mode to fail
opening the meminfo pseudo-file with errno 13. This commit fixes this
issue.

Change-Id: I93fa81cab49645d70775088f1e634f067b300698
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
2023-12-18 17:28:10 -08:00
Alexander Richardson
2700f392cb tests: Silence Clang 16 warnings (#679)
I was trying to build with clang 16 and ran into these -Werror warnings

Change-Id: I9207990fcfe9c1a5485945294969f21d1d812a7c
2023-12-18 14:57:11 -08:00
Bobby R. Bruce
b22ca02a65 tests: Fix garnet and memcheck tests to use X86
These tests previously used "build/NULL" but due to changes in the
"Ruby" and "garnet_synth_traffic.py" scripts, "NULL" fails as the script
exists "X86TimingSimple" with MESI_Two_Level.

This change fixes the tests by compiling and using the correct
compilation of gem5. It shouldn't affect the tests in any negative way.
As far as I'm aware it does not matter what ISA is used for these tests.

Change-Id: I8ae84b49f65968e97bef4904268de5a455f06f5c
2023-12-18 14:39:28 -08:00
Bobby R. Bruce
5d09ff4525 configs: Add hasattr guard to ensure DerivO3CPU compiled
configs/ruby/Ruby.py fails when `DerivO3CPU` is not compiled into the
gem5 binary. The `isinstance` check fails. This fix addds a guard.

Change-Id: I1e5503ab18ec94683056c6eb28cebeda6632ae8e
2023-12-18 14:37:51 -08:00
Harshil Patel
b42d9fabf7 util: Added script to copy resources from mongodb (#510)
- This script copies all resources from a mongodb database locally The
script creates a resources.json and downloads all the resources. It also
updates the resources.json to point to these local downloads instead of
the cloud bucket.

Change-Id: I15480c4ba82bbf245425205c9c1ab7c0f3501cc3
2023-12-18 12:41:52 -08:00
Giacomo Travaglini
ce6fd7f084 configs: Fix SMT cpu type checking (#684)
The args.cpu_type is not a type but a string so the isinstance checking
will always fail and an assertion will always be thrown

Change-Id: I6a88d1a514bb323c517949632f4e76be40e87e8c

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-12-17 22:08:49 -08:00
Tiberiu Bucur
9b0bf33f79 sim: Remove trailing / from proc/meminfo special path (#689)
Note: A bug was identified in that the one of the special file paths,
namely /proc/meminfo contained an extra trailing /, implicitly making
the incorrect assumption that meminfo was a directory, when it is, in
fact, a (pseudo-)file. This was causing application in SE mode to fail
opening the meminfo pseudo-file with errno 13. This commit fixes this
issue.

Change-Id: I93fa81cab49645d70775088f1e634f067b300698
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
2023-12-17 22:07:39 -08:00
Giacomo Travaglini
a008cd2611 mem-ruby: Implement a dummy StashOnceShared/Unique (#688)
Stash requests will simply be discarded by the Home Node This will
return a CompI response to the RNF

Change-Id: I9c2ce5d4d42f380d1a554933d381cf8a8590ba22

Reviewed-by: Tiago Muck <tiago.muck@arm.com>

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-12-16 14:43:45 -08:00
Bobby R. Bruce
9064249fab misc: Cherry-pick PR #666 from develop to release-staging-v23-1 (#683)
This was supposed to be part of the #682 but got missed. Adding now as a
separate PR.
2023-12-14 01:51:40 -08:00
Bobby R. Bruce
29b77260f3 arch-x86: Fix two_byte_opcodes.isa 0x6 -> 0x0 (#666)
This bug was introduced by https://github.com/gem5/gem5/pull/593 and
caused Issue https://github.com/gem5/gem5/issues/664.

Change-Id: Ia55de364ee8260e1fe315e37e1cffbc71ab229fb
2023-12-14 00:41:09 -08:00
Bobby R. Bruce
a84cfd2f0d misc: Cherry-pick from develop to release-staging-v23-1 [Nov 13th] (#682)
This PR includes all the commits from the following PRs which appear on
the `develop` branch but are required in the v23.1 release and are
therefore being cherry-picked to the `release-staging-v23-1` branch.

* https://github.com/gem5/gem5/pull/645
* https://github.com/gem5/gem5/pull/671
* https://github.com/gem5/gem5/pull/675
* https://github.com/gem5/gem5/pull/677
* https://github.com/gem5/gem5/pull/674
2023-12-14 00:10:59 -08:00
Roger Chang
654e7c6019 arch: Fix inst flag of RISC-V vector store macro instructions
Correct the instruction flags of RISC-V vector store instructions, such
as `vse64_v`, `vse32_v`. The `vse64_v`  in `decoder.isa` is
`Mem_vc.as<uint64_t>()[i] = Vs3_ud[i];` and it will generate the code
`Mem.as<uint64_t>()[i] = Vs3[i];`. The current regex of assignRE only
mark the operand `Mem` as `dest` only if meet the formats like `Mem = Rd`
or `Mem[i] = Rd` because the code ` = Rd` or `[i] = Rd` match the
`assignRE` respectively. For the expression `Mem.as<uint64_t>()[i]`,
the operand `Mem` will falsely mark the operand as `src` because the
code `.as<uint64_t>()[i]` is not match the  `assignRE`.

The PR will ensure the operand `Mem` is dest for the format like
`Mem.as<xxx>()[i] = yyy`.

Change-Id: I9c57986a64f1efb81eb9c7ade90712b118e0788d
2023-12-14 00:05:26 -08:00
Roger Chang
a9f8db7044 arch-riscv: Fix the vector store indexed instructions declaration
Change-Id: I6f8701ef0819c22eda8cb20d09c40101f2d001a0
2023-12-14 00:05:17 -08:00
Harshil Patel
9aab380775 arch-riscv: fix riscv matched board for se mode (#677) 2023-12-14 00:05:02 -08:00
Bobby R. Bruce
d8cc530597 stdlib: Add get_local_path() call to Looppoint resources
Due to a change introduced in https://github.com/gem5/gem5/pull/625, a
gem5 resource will not download any external files until
`get_local_path()` is called. In the construction of the Looppoint
Resources this function was not called, the `local_path` variable was
called directly. As such, an error occured.

The downside of this fix is the Looppoint resources external files are
downloaded when `obtain_resource` is called, thus the bandwidth savings
introduced with https://github.com/gem5/gem5/pull/625 will not occur for
Looppoint resources. However, https://github.com/gem5/gem5/issues/644
proposes a fix which would supercede the
https://github.com/gem5/gem5/pull/625 solution.

Change-Id: I52181382a03e492ec1cb58b01e71bc4820af9ccc
2023-12-14 00:04:10 -08:00
Bobby R. Bruce
301fb3f509 stdlib: Remove 'additional_params' value type assert
The value of a `WorkloadResource`'s additional parameter may not always
be a string. It can be any JSON value (integer, a list, a dict, ect.).
For Looppoint resources we have additional parameters such as a List of
region start points.

The assert inside workloads checking the type of the value breaks
certain usecase and is therefore removed in this commit.

Change-Id: Iecb1518082c28ab3872a8de888c76f0800261640
2023-12-14 00:04:00 -08:00
Harshil Patel
34f784f59c tests: fix gapbs and npb tests (#671)
Change-Id: I6090bde7903e302e501319b545fb4b06ef3e3df9
2023-12-14 00:01:39 -08:00
Harshil Patel
5ac9598133 Arch-riscv: Add chosen node
Change-Id: I458665caec08856cd8e61d2cd7a5b0dc5c35d469
2023-12-14 00:00:41 -08:00
Harshil Patel
7ce69b56be arch-riscv: Update riscv matched boad
- Update riscv matched board to work with new
RiscvBootloaderKernelWorkload

Change-Id: Ic20b964f33e73b76775bfe18798bd667f36253f6
2023-12-14 00:00:30 -08:00
Yu-Cheng Chang
6b80a2e81c configs: Make riscv/fs_linux work in build/ALL/gem5.opt (#655)
Change-Id: If9add7dc5e9c5600f769d27817da41466158942b
2023-12-13 23:59:53 -08:00
Yu-Cheng Chang
db286903ee stdlib: Fix the chi protocol of arm boot tests (#658)
Change-Id: I63f17a73b2e16bc26d9b41babc63439a6040791f
2023-12-13 23:59:00 -08:00
Harshil Patel
c66862f6e3 arch-riscv: fix riscv matched board for se mode (#677) 2023-12-13 13:16:08 -08:00
Bobby R. Bruce
695c350f31 stdlib,resources: Fix obtaining gem5 Looppoint resources (#675)
There were two small bugs preventing gem5 from obtaining Looppoint
resources.

1. When obtained via a `WorkloadResource` there was an assert which
assumed the values in the resource's DB entry's `additional_parameter`
field were of type string. This is not the case. For Looppoint resources
there are additional parameters which are arrays.
2. Due to changes introduced in https://github.com/gem5/gem5/pull/625,
the Looppoint CSV and JSON files were not being downloaded when needed.
This was fixed by replacing access to the `local_path` variable with a
call to `get_local_path()`.
2023-12-13 12:49:57 -08:00
Bobby R. Bruce
da3e3b806d arch-riscv: squash walks with tlb hits in startWalkWrapper (#672)
Because each vector load is fragmented into 64 byte cache-aligned
chunks, and one page-table walk is issued per fragment on tlb miss,
walks start to accumulate on a pending queue, which is processed in a
blocking way (no pending walks can be issued while one is being
processed). This adds noticeable latency on vector loads when VLEN is
sufficiently large.

This commit fixes the issue by allowing walks to be squashed if a TLB
lookup hits just before starting the walk on `startWalkWrapper`. This
idea was taken from the ARM walker.
2023-12-13 12:45:40 -08:00
Saúl Adserias
78f23ad2df arch-riscv: squash walks with tlb hits in startWalkWrapper
Change-Id: I1bdfd7b2ee02ddee5a2d4c13bafc8c472f555f61
2023-12-13 16:40:46 +01:00
Giacomo Travaglini
8d09e95420 arch-arm: Partial SVE2 Implementation (#657)
Instructions added:

BGRP, RAX1, EOR3, BCAX,
XAR & TBX, PMUL, PMULLB/T, SMULLB/T and UMULLB/T

Move from gerrit [1]

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/70277

Change-Id: Ia135ba9300eae312b24342bcbda835fef6867113
2023-12-13 10:27:19 +00:00
Bobby R. Bruce
4eb81296b1 stdlib: Add get_local_path() call to Looppoint resources
Due to a change introduced in https://github.com/gem5/gem5/pull/625, a
gem5 resource will not download any external files until
`get_local_path()` is called. In the construction of the Looppoint
Resources this function was not called, the `local_path` variable was
called directly. As such, an error occured.

The downside of this fix is the Looppoint resources external files are
downloaded when `obtain_resource` is called, thus the bandwidth savings
introduced with https://github.com/gem5/gem5/pull/625 will not occur for
Looppoint resources. However, https://github.com/gem5/gem5/issues/644
proposes a fix which would supercede the
https://github.com/gem5/gem5/pull/625 solution.

Change-Id: I52181382a03e492ec1cb58b01e71bc4820af9ccc
2023-12-12 14:28:11 -08:00
Bobby R. Bruce
4adeb24a4f stdlib: Remove 'additional_params' value type assert
The value of a `WorkloadResource`'s additional parameter may not always
be a string. It can be any JSON value (integer, a list, a dict, ect.).
For Looppoint resources we have additional parameters such as a List of
region start points.

The assert inside workloads checking the type of the value breaks
certain usecase and is therefore removed in this commit.

Change-Id: Iecb1518082c28ab3872a8de888c76f0800261640
2023-12-12 14:23:04 -08:00
Bobby R. Bruce
eff08ba113 mem: Add a flag on AbstractMemory to control statistics collection (#656)
The stats initialization in the AbstractMemory allocates the space
according to the max requestors of the System. This may cause issues in
multiple system simulation.
Given there are two system A and B. A has one requestor and a memory,
while B has two requestors. When the requestor with requestor id 2
sending requests to the meomry in A, the simulator would crash because
requestor id 2 is out of the allocated space.

Current solution is adding a SysBridge between across A and B which
would rewrite the requestor id to a valid one. This solution works but
it needs to the bridge at the correct boundary which may not easy. In
addition, the stats would record a mapped data which may not accurate.

To reduce the complexity, we add an flag to AbstractMemory to control
the stats. If users don't want the statistics and want to solve the
cross system issue simply, users can disable the statistics collection.
We also makes the flag by default True to not disturb current users.
2023-12-12 13:13:30 -08:00
Bobby R. Bruce
c8cc193db8 arch,arch-riscv: Fix inst flag of RISC-V vector store macro instructions (#674)
Correct the instruction flags of RISC-V vector store instructions, such
as `vse64_v`, `vse32_v`. The `vse64_v` in `decoder.isa` is
`Mem_vc.as<uint64_t>()[i] = Vs3_ud[i];` and it will generate the code
`Mem.as<uint64_t>()[i] = Vs3[i];`. The current regex of assignRE only
mark the operand `Mem` as `dest` only if meet the formats like `Mem =
Rd` or `Mem[i] = Rd` because the code ` = Rd` or `[i] = Rd` match the
`assignRE` respectively. For the expression `Mem.as<uint64_t>()[i]`, the
operand `Mem` will falsely mark the operand as `src` because the code
`.as<uint64_t>()[i]` is not match the `assignRE`.

The PR will ensure the operand `Mem` is dest for the format like
`Mem.as<xxx>()[i] = yyy`.
2023-12-12 13:07:50 -08:00
Harshil Patel
bc12e7269d tests: fix gapbs and npb tests (#671)
Change-Id: I6090bde7903e302e501319b545fb4b06ef3e3df9
2023-12-12 12:33:22 -08:00
Yu-Cheng Chang
5a6901c405 configs: Make riscv/fs_linux work in build/ALL/gem5.opt (#655)
Change-Id: If9add7dc5e9c5600f769d27817da41466158942b
2023-12-12 08:23:28 -08:00
Bobby R. Bruce
37e4173351 arch-x86: Fix two_byte_opcodes.isa 0x6 -> 0x0 (#666)
This bug was introduced by https://github.com/gem5/gem5/pull/593 and
caused Issue https://github.com/gem5/gem5/issues/664.

Change-Id: Ia55de364ee8260e1fe315e37e1cffbc71ab229fb
2023-12-12 08:21:27 -08:00
Roger Chang
bedc3c597c arch: Fix inst flag of RISC-V vector store macro instructions
Correct the instruction flags of RISC-V vector store instructions, such
as `vse64_v`, `vse32_v`. The `vse64_v`  in `decoder.isa` is
`Mem_vc.as<uint64_t>()[i] = Vs3_ud[i];` and it will generate the code
`Mem.as<uint64_t>()[i] = Vs3[i];`. The current regex of assignRE only
mark the operand `Mem` as `dest` only if meet the formats like `Mem = Rd`
or `Mem[i] = Rd` because the code ` = Rd` or `[i] = Rd` match the
`assignRE` respectively. For the expression `Mem.as<uint64_t>()[i]`,
the operand `Mem` will falsely mark the operand as `src` because the
code `.as<uint64_t>()[i]` is not match the  `assignRE`.

The PR will ensure the operand `Mem` is dest for the format like
`Mem.as<xxx>()[i] = yyy`.

Change-Id: I9c57986a64f1efb81eb9c7ade90712b118e0788d
2023-12-12 17:04:31 +08:00
Roger Chang
10d344a942 arch-riscv: Fix the vector store indexed instructions declaration
Change-Id: I6f8701ef0819c22eda8cb20d09c40101f2d001a0
2023-12-12 16:36:49 +08:00
Bobby R. Bruce
ea1226119c arch-riscv: Update riscv matched board (#654)
- Update riscv matched board to work with new
RiscvBootloaderKernelWorkload

Change-Id: Ic20b964f33e73b76775bfe18798bd667f36253f6
2023-12-08 13:33:09 -08:00
Yu-Cheng Chang
10a0c950da stdlib: Fix the chi protocol of arm boot tests (#658)
Change-Id: I63f17a73b2e16bc26d9b41babc63439a6040791f
2023-12-07 16:10:45 -08:00