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misc: Cherry-pick from develop to release-staging-v23-1 [Nov 13th] (#682)

Browse Source 
This PR includes all the commits from the following PRs which appear on
the `develop` branch but are required in the v23.1 release and are
therefore being cherry-picked to the `release-staging-v23-1` branch.

* https://github.com/gem5/gem5/pull/645
* https://github.com/gem5/gem5/pull/671
* https://github.com/gem5/gem5/pull/675
* https://github.com/gem5/gem5/pull/677
* https://github.com/gem5/gem5/pull/674
This commit is contained in:
Bobby R. Bruce
2023-12-14 00:10:59 -08:00
committed by GitHub
parent d006f866c0 654e7c6019
commit a84cfd2f0d
10 changed files with 64 additions and 37 deletions
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26
configs/common/Options.py
View File

@@ -37,6 +37,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import argparse
from typing import Optional
from common import (
CpuConfig,
@@ -48,6 +49,7 @@ import m5
from m5.defines import buildEnv
from m5.objects import *
from gem5.isas import ISA
from gem5.runtime import get_supported_isas
vio_9p_help = """\
@@ -242,10 +244,13 @@ def addNoISAOptions(parser):
# Add common options that assume a non-NULL ISA.
def addCommonOptions(parser):
def addCommonOptions(parser, default_isa: Optional[ISA] = None):
# start by adding the base options that do not assume an ISA
addNoISAOptions(parser)
isa = list(get_supported_isas())[0]
if default_isa is None:
isa = list(get_supported_isas())[0]
else:
isa = default_isa
# system options
parser.add_argument(
@@ -790,12 +795,20 @@ def addFSOptions(parser):
"files in the gem5 output directory",
)
if buildEnv["USE_ARM_ISA"]:
if buildEnv["USE_ARM_ISA"] or buildEnv["USE_RISCV_ISA"]:
parser.add_argument(
"--bare-metal",
action="store_true",
help="Provide the raw system without the linux specific bits",
)
parser.add_argument(
"--dtb-filename",
action="store",
type=str,
help="Specifies device tree blob file to use with device-tree-"
"enabled kernels",
)
if buildEnv["USE_ARM_ISA"]:
parser.add_argument(
"--list-machine-types",
action=ListPlatform,
@@ -808,13 +821,6 @@ def addFSOptions(parser):
choices=ObjectList.platform_list.get_names(),
default="VExpress_GEM5_V1",
)
parser.add_argument(
"--dtb-filename",
action="store",
type=str,
help="Specifies device tree blob file to use with device-tree-"
"enabled kernels",
)
parser.add_argument(
"--enable-context-switch-stats-dump",
action="store_true",

20
configs/example/riscv/fs_linux.py
View File

@@ -52,6 +52,8 @@ from m5.util import (
)
from m5.util.fdthelper import *
from gem5.utils.requires import requires
addToPath("../../")
from common import (
@@ -68,6 +70,9 @@ from common.FSConfig import *
from common.SysPaths import *
from ruby import Ruby
# Run a check to ensure the RISC-V ISA is complied into gem5.
requires(isa_required=ISA.RISCV)
# ------------------------- Usage Instructions ------------------------- #
# Common system confirguration options (cpu types, num cpus, checkpointing
# etc.) should be supported
@@ -135,20 +140,8 @@ def generateDtb(system):
# ----------------------------- Add Options ---------------------------- #
parser = argparse.ArgumentParser()
Options.addCommonOptions(parser)
Options.addCommonOptions(parser, ISA.RISCV)
Options.addFSOptions(parser)
parser.add_argument(
"--bare-metal",
action="store_true",
help="Provide the raw system without the linux specific bits",
)
parser.add_argument(
"--dtb-filename",
action="store",
type=str,
help="Specifies device tree blob file to use with device-tree-"
"enabled kernels",
)
parser.add_argument(
"--virtio-rng", action="store_true", help="Enable VirtIORng device"
)
@@ -158,6 +151,7 @@ args = parser.parse_args()
# CPU and Memory
(CPUClass, mem_mode, FutureClass) = Simulation.setCPUClass(args)
assert issubclass(CPUClass, RiscvCPU)
MemClass = Simulation.setMemClass(args)
np = args.num_cpus

4
src/arch/isa_parser/util.py
View File

@@ -69,7 +69,9 @@ commentRE = re.compile(
# destination. basically we're looking for an '=' that's not '=='.
# The heinous tangle before that handles the case where the operand
# has an array subscript.
assignRE = re.compile(r"(\[[^\]]+\])?\s*=(?!=)", re.MULTILINE)
assignRE = re.compile(
r"((\.as<[^>]+>\(\s*\))?\[[^\]]+\])?\s*=(?!=)", re.MULTILINE
)
#
# Munge a somewhat arbitrarily formatted piece of Python code

2
src/arch/riscv/isa/templates/vector_mem.isa
View File

@@ -1586,7 +1586,7 @@ Fault
}
if (machInst.vill)
return std::make_shared<IllegalInstFault>("VILL is set", machInst);
%(op_src_decl)s;
%(op_decl)s;
%(op_rd)s;
%(set_vlenb)s;
%(ea_code)s;

1
src/python/gem5/components/cachehierarchies/chi/nodes/directory.py
View File

@@ -61,6 +61,7 @@ class SimpleDirectory(AbstractNode):
self.sequencer = NULL
self.use_prefetcher = False
self.prefetcher = NULL
# Set up home node that allows three hop protocols
self.is_HN = True

2
src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py
View File

@@ -25,6 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import (
NULL,
ClockDomain,
RubyCache,
)
@@ -67,6 +68,7 @@ class DMARequestor(AbstractNode):
self.send_evictions = False
self.use_prefetcher = False
self.prefetcher = NULL
# Some reasonable default TBE params
self.number_of_TBEs = 16
self.number_of_repl_TBEs = 1

2
src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py
View File

@@ -25,6 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import (
NULL,
ClockDomain,
RubyCache,
RubyNetwork,
@@ -56,6 +57,7 @@ class PrivateL1MOESICache(AbstractNode):
self.clk_domain = clk_domain
self.send_evictions = core.requires_send_evicts()
self.use_prefetcher = False
self.prefetcher = NULL
# Only applies to home nodes
self.is_HN = False

30
src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
View File

@@ -45,7 +45,7 @@ from m5.objects import (
PMAChecker,
Port,
RawDiskImage,
RiscvLinux,
RiscvBootloaderKernelWorkload,
RiscvMmioVirtIO,
RiscvRTC,
VirtIOBlock,
@@ -144,7 +144,7 @@ class RISCVMatchedBoard(
@overrides(AbstractSystemBoard)
def _setup_board(self) -> None:
if self._fs:
self.workload = RiscvLinux()
self.workload = RiscvBootloaderKernelWorkload()
# Contains a CLINT, PLIC, UART, and some functions for the dtb, etc.
self.platform = HiFive()
@@ -310,6 +310,22 @@ class RISCVMatchedBoard(
self.mem_ranges = [AddrRange(memory.get_size())]
memory.set_memory_range(self.mem_ranges)
@overrides(AbstractSystemBoard)
def _pre_instantiate(self):
if self._fs:
if len(self._bootloader) > 0:
self.workload.bootloader_addr = 0x0
self.workload.bootloader_filename = self._bootloader[0]
self.workload.kernel_addr = 0x80200000
self.workload.entry_point = (
0x80000000 # Bootloader starting point
)
else:
self.workload.kernel_addr = 0x0
self.workload.entry_point = 0x80000000
self._connect_things()
def generate_device_tree(self, outdir: str) -> None:
"""Creates the ``dtb`` and ``dts`` files.
@@ -336,6 +352,12 @@ class RISCVMatchedBoard(
)
root.append(node)
node = FdtNode(f"chosen")
bootargs = self.workload.command_line
node.append(FdtPropertyStrings("bootargs", [bootargs]))
node.append(FdtPropertyStrings("stdout-path", ["/uart@10000000"]))
root.append(node)
# See Documentation/devicetree/bindings/riscv/cpus.txt for details.
cpus_node = FdtNode("cpus")
cpus_state = FdtState(addr_cells=1, size_cells=0)
@@ -508,7 +530,7 @@ class RISCVMatchedBoard(
uart_node.append(
FdtPropertyWords("interrupt-parent", soc_state.phandle(plic))
)
uart_node.appendCompatible(["ns8250"])
uart_node.appendCompatible(["ns8250", "ns16550a"])
soc_node.append(uart_node)
# VirtIO MMIO disk node
@@ -588,7 +610,7 @@ class RISCVMatchedBoard(
kernel_args: Optional[List[str]] = None,
exit_on_work_items: bool = True,
) -> None:
self.workload = RiscvLinux()
self.workload = RiscvBootloaderKernelWorkload()
KernelDiskWorkload.set_kernel_disk_workload(
self=self,
kernel=kernel,

7
src/python/gem5/resources/resource.py
View File

@@ -578,7 +578,9 @@ class LooppointCsvResource(FileResource, LooppointCsvLoader):
resource_version=resource_version,
downloader=downloader,
)
LooppointCsvLoader.__init__(self, pinpoints_file=Path(local_path))
LooppointCsvLoader.__init__(
self, pinpoints_file=Path(self.get_local_path())
)
def get_category_name(cls) -> str:
return "LooppointCsvResource"
@@ -606,7 +608,7 @@ class LooppointJsonResource(FileResource, LooppointJsonLoader):
downloader=downloader,
)
LooppointJsonLoader.__init__(
self, looppoint_file=local_path, region_id=region_id
self, looppoint_file=self.get_local_path(), region_id=region_id
)
def get_category_name(cls) -> str:
@@ -1098,7 +1100,6 @@ def obtain_resource(
for key in resource_json["additional_params"].keys():
assert isinstance(key, str)
value = resource_json["additional_params"][key]
assert isinstance(value, str)
params[key] = value
resource_json["parameters"] = params
# Once we know what AbstractResource subclass we are using, we create it.

7
tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
View File

@@ -218,10 +218,7 @@ if os.access("/dev/kvm", mode=os.R_OK | os.W_OK):
),
config_args=[
"--benchmark",
"bt",
"--size",
"A",
"--ticks",
"npb-bt-a" "--ticks",
"5000000000",
],
valid_isas=(constants.all_compiled_tag,),
@@ -245,7 +242,7 @@ if os.access("/dev/kvm", mode=os.R_OK | os.W_OK):
"gem5_library",
"x86-gapbs-benchmarks.py",
),
config_args=["--benchmark", "bfs", "--synthetic", "1", "--size", "1"],
config_args=["--benchmark", "gapbs-bfs-test"],
valid_isas=(constants.all_compiled_tag,),
protocol="MESI_Two_Level",
valid_hosts=(constants.host_x86_64_tag,),