From db286903ee7fe8e2441c118db27ed71c40a99cc4 Mon Sep 17 00:00:00 2001 From: Yu-Cheng Chang Date: Fri, 8 Dec 2023 08:10:45 +0800 Subject: [PATCH 01/10] stdlib: Fix the chi protocol of arm boot tests (#658) Change-Id: I63f17a73b2e16bc26d9b41babc63439a6040791f --- .../gem5/components/cachehierarchies/chi/nodes/directory.py | 1 + .../gem5/components/cachehierarchies/chi/nodes/dma_requestor.py | 2 ++ .../cachehierarchies/chi/nodes/private_l1_moesi_cache.py | 2 ++ 3 files changed, 5 insertions(+) diff --git a/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py b/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py index 7d7a16cd5f..b2515d3c84 100644 --- a/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py +++ b/src/python/gem5/components/cachehierarchies/chi/nodes/directory.py @@ -61,6 +61,7 @@ class SimpleDirectory(AbstractNode): self.sequencer = NULL self.use_prefetcher = False + self.prefetcher = NULL # Set up home node that allows three hop protocols self.is_HN = True diff --git a/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py b/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py index 2997c33ce7..850c7e9002 100644 --- a/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py +++ b/src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py @@ -25,6 +25,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.objects import ( + NULL, ClockDomain, RubyCache, ) @@ -67,6 +68,7 @@ class DMARequestor(AbstractNode): self.send_evictions = False self.use_prefetcher = False + self.prefetcher = NULL # Some reasonable default TBE params self.number_of_TBEs = 16 self.number_of_repl_TBEs = 1 diff --git a/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py b/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py index 477c0f9b63..8b056b3967 100644 --- a/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py +++ b/src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py @@ -25,6 +25,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.objects import ( + NULL, ClockDomain, RubyCache, RubyNetwork, @@ -56,6 +57,7 @@ class PrivateL1MOESICache(AbstractNode): self.clk_domain = clk_domain self.send_evictions = core.requires_send_evicts() self.use_prefetcher = False + self.prefetcher = NULL # Only applies to home nodes self.is_HN = False From 6b80a2e81c279d2d6cd4172edb2f373e95aa408c Mon Sep 17 00:00:00 2001 From: Yu-Cheng Chang Date: Wed, 13 Dec 2023 00:23:28 +0800 Subject: [PATCH 02/10] configs: Make riscv/fs_linux work in build/ALL/gem5.opt (#655) Change-Id: If9add7dc5e9c5600f769d27817da41466158942b --- configs/common/Options.py | 26 ++++++++++++++++---------- configs/example/riscv/fs_linux.py | 20 +++++++------------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/configs/common/Options.py b/configs/common/Options.py index c15410d41a..97335f13b9 100644 --- a/configs/common/Options.py +++ b/configs/common/Options.py @@ -37,6 +37,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import argparse +from typing import Optional from common import ( CpuConfig, @@ -48,6 +49,7 @@ import m5 from m5.defines import buildEnv from m5.objects import * +from gem5.isas import ISA from gem5.runtime import get_supported_isas vio_9p_help = """\ @@ -242,10 +244,13 @@ def addNoISAOptions(parser): # Add common options that assume a non-NULL ISA. -def addCommonOptions(parser): +def addCommonOptions(parser, default_isa: Optional[ISA] = None): # start by adding the base options that do not assume an ISA addNoISAOptions(parser) - isa = list(get_supported_isas())[0] + if default_isa is None: + isa = list(get_supported_isas())[0] + else: + isa = default_isa # system options parser.add_argument( @@ -790,12 +795,20 @@ def addFSOptions(parser): "files in the gem5 output directory", ) - if buildEnv["USE_ARM_ISA"]: + if buildEnv["USE_ARM_ISA"] or buildEnv["USE_RISCV_ISA"]: parser.add_argument( "--bare-metal", action="store_true", help="Provide the raw system without the linux specific bits", ) + parser.add_argument( + "--dtb-filename", + action="store", + type=str, + help="Specifies device tree blob file to use with device-tree-" + "enabled kernels", + ) + if buildEnv["USE_ARM_ISA"]: parser.add_argument( "--list-machine-types", action=ListPlatform, @@ -808,13 +821,6 @@ def addFSOptions(parser): choices=ObjectList.platform_list.get_names(), default="VExpress_GEM5_V1", ) - parser.add_argument( - "--dtb-filename", - action="store", - type=str, - help="Specifies device tree blob file to use with device-tree-" - "enabled kernels", - ) parser.add_argument( "--enable-context-switch-stats-dump", action="store_true", diff --git a/configs/example/riscv/fs_linux.py b/configs/example/riscv/fs_linux.py index 075b4a0069..c0643c883d 100644 --- a/configs/example/riscv/fs_linux.py +++ b/configs/example/riscv/fs_linux.py @@ -52,6 +52,8 @@ from m5.util import ( ) from m5.util.fdthelper import * +from gem5.utils.requires import requires + addToPath("../../") from common import ( @@ -68,6 +70,9 @@ from common.FSConfig import * from common.SysPaths import * from ruby import Ruby +# Run a check to ensure the RISC-V ISA is complied into gem5. +requires(isa_required=ISA.RISCV) + # ------------------------- Usage Instructions ------------------------- # # Common system confirguration options (cpu types, num cpus, checkpointing # etc.) should be supported @@ -135,20 +140,8 @@ def generateDtb(system): # ----------------------------- Add Options ---------------------------- # parser = argparse.ArgumentParser() -Options.addCommonOptions(parser) +Options.addCommonOptions(parser, ISA.RISCV) Options.addFSOptions(parser) -parser.add_argument( - "--bare-metal", - action="store_true", - help="Provide the raw system without the linux specific bits", -) -parser.add_argument( - "--dtb-filename", - action="store", - type=str, - help="Specifies device tree blob file to use with device-tree-" - "enabled kernels", -) parser.add_argument( "--virtio-rng", action="store_true", help="Enable VirtIORng device" ) @@ -158,6 +151,7 @@ args = parser.parse_args() # CPU and Memory (CPUClass, mem_mode, FutureClass) = Simulation.setCPUClass(args) +assert issubclass(CPUClass, RiscvCPU) MemClass = Simulation.setMemClass(args) np = args.num_cpus From 7ce69b56be9905bdf05acca6964de5b983cac33d Mon Sep 17 00:00:00 2001 From: Harshil Patel Date: Tue, 5 Dec 2023 14:54:12 -0800 Subject: [PATCH 03/10] arch-riscv: Update riscv matched boad - Update riscv matched board to work with new RiscvBootloaderKernelWorkload Change-Id: Ic20b964f33e73b76775bfe18798bd667f36253f6 --- .../riscvmatched/riscvmatched_board.py | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py index c735313a6a..f827ec7bff 100644 --- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py +++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py @@ -45,7 +45,7 @@ from m5.objects import ( PMAChecker, Port, RawDiskImage, - RiscvLinux, + RiscvBootloaderKernelWorkload, RiscvMmioVirtIO, RiscvRTC, VirtIOBlock, @@ -144,7 +144,7 @@ class RISCVMatchedBoard( @overrides(AbstractSystemBoard) def _setup_board(self) -> None: if self._fs: - self.workload = RiscvLinux() + self.workload = RiscvBootloaderKernelWorkload() # Contains a CLINT, PLIC, UART, and some functions for the dtb, etc. self.platform = HiFive() @@ -310,6 +310,18 @@ class RISCVMatchedBoard( self.mem_ranges = [AddrRange(memory.get_size())] memory.set_memory_range(self.mem_ranges) + @overrides(AbstractSystemBoard) + def _pre_instantiate(self): + if len(self._bootloader) > 0: + self.workload.bootloader_addr = 0x0 + self.workload.bootloader_filename = self._bootloader[0] + self.workload.kernel_addr = 0x80200000 + self.workload.entry_point = 0x80000000 # Bootloader starting point + else: + self.workload.kernel_addr = 0x0 + self.workload.entry_point = 0x80000000 + self._connect_things() + def generate_device_tree(self, outdir: str) -> None: """Creates the ``dtb`` and ``dts`` files. @@ -588,7 +600,7 @@ class RISCVMatchedBoard( kernel_args: Optional[List[str]] = None, exit_on_work_items: bool = True, ) -> None: - self.workload = RiscvLinux() + self.workload = RiscvBootloaderKernelWorkload() KernelDiskWorkload.set_kernel_disk_workload( self=self, kernel=kernel, From 5ac9598133913758099476ddc9d51a03ad17ee4f Mon Sep 17 00:00:00 2001 From: Harshil Patel Date: Wed, 6 Dec 2023 20:10:56 -0800 Subject: [PATCH 04/10] Arch-riscv: Add chosen node Change-Id: I458665caec08856cd8e61d2cd7a5b0dc5c35d469 --- .../gem5/prebuilt/riscvmatched/riscvmatched_board.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py index f827ec7bff..f4e4b381a1 100644 --- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py +++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py @@ -348,6 +348,12 @@ class RISCVMatchedBoard( ) root.append(node) + node = FdtNode(f"chosen") + bootargs = self.workload.command_line + node.append(FdtPropertyStrings("bootargs", [bootargs])) + node.append(FdtPropertyStrings("stdout-path", ["/uart@10000000"])) + root.append(node) + # See Documentation/devicetree/bindings/riscv/cpus.txt for details. cpus_node = FdtNode("cpus") cpus_state = FdtState(addr_cells=1, size_cells=0) @@ -520,7 +526,7 @@ class RISCVMatchedBoard( uart_node.append( FdtPropertyWords("interrupt-parent", soc_state.phandle(plic)) ) - uart_node.appendCompatible(["ns8250"]) + uart_node.appendCompatible(["ns8250", "ns16550a"]) soc_node.append(uart_node) # VirtIO MMIO disk node From 34f784f59cb6938e66a4eff2c842d592f5e21cd5 Mon Sep 17 00:00:00 2001 From: Harshil Patel Date: Tue, 12 Dec 2023 12:33:22 -0800 Subject: [PATCH 05/10] tests: fix gapbs and npb tests (#671) Change-Id: I6090bde7903e302e501319b545fb4b06ef3e3df9 --- .../test_gem5_library_examples.py | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py index 5ffb62873d..9c88ff4307 100644 --- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py +++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py @@ -218,10 +218,7 @@ if os.access("/dev/kvm", mode=os.R_OK | os.W_OK): ), config_args=[ "--benchmark", - "bt", - "--size", - "A", - "--ticks", + "npb-bt-a" "--ticks", "5000000000", ], valid_isas=(constants.all_compiled_tag,), @@ -245,7 +242,7 @@ if os.access("/dev/kvm", mode=os.R_OK | os.W_OK): "gem5_library", "x86-gapbs-benchmarks.py", ), - config_args=["--benchmark", "bfs", "--synthetic", "1", "--size", "1"], + config_args=["--benchmark", "gapbs-bfs-test"], valid_isas=(constants.all_compiled_tag,), protocol="MESI_Two_Level", valid_hosts=(constants.host_x86_64_tag,), From 301fb3f5096b22096db73bd8d0592d28b5e3d230 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Tue, 12 Dec 2023 14:23:04 -0800 Subject: [PATCH 06/10] stdlib: Remove 'additional_params' value type assert The value of a `WorkloadResource`'s additional parameter may not always be a string. It can be any JSON value (integer, a list, a dict, ect.). For Looppoint resources we have additional parameters such as a List of region start points. The assert inside workloads checking the type of the value breaks certain usecase and is therefore removed in this commit. Change-Id: Iecb1518082c28ab3872a8de888c76f0800261640 --- src/python/gem5/resources/resource.py | 1 - 1 file changed, 1 deletion(-) diff --git a/src/python/gem5/resources/resource.py b/src/python/gem5/resources/resource.py index 08d046fc01..d6746487ff 100644 --- a/src/python/gem5/resources/resource.py +++ b/src/python/gem5/resources/resource.py @@ -1098,7 +1098,6 @@ def obtain_resource( for key in resource_json["additional_params"].keys(): assert isinstance(key, str) value = resource_json["additional_params"][key] - assert isinstance(value, str) params[key] = value resource_json["parameters"] = params # Once we know what AbstractResource subclass we are using, we create it. From d8cc5305979edcf6bd90effbcf6307f654d3f149 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Tue, 12 Dec 2023 14:28:11 -0800 Subject: [PATCH 07/10] stdlib: Add `get_local_path()` call to Looppoint resources Due to a change introduced in https://github.com/gem5/gem5/pull/625, a gem5 resource will not download any external files until `get_local_path()` is called. In the construction of the Looppoint Resources this function was not called, the `local_path` variable was called directly. As such, an error occured. The downside of this fix is the Looppoint resources external files are downloaded when `obtain_resource` is called, thus the bandwidth savings introduced with https://github.com/gem5/gem5/pull/625 will not occur for Looppoint resources. However, https://github.com/gem5/gem5/issues/644 proposes a fix which would supercede the https://github.com/gem5/gem5/pull/625 solution. Change-Id: I52181382a03e492ec1cb58b01e71bc4820af9ccc --- src/python/gem5/resources/resource.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/python/gem5/resources/resource.py b/src/python/gem5/resources/resource.py index d6746487ff..591515a6b9 100644 --- a/src/python/gem5/resources/resource.py +++ b/src/python/gem5/resources/resource.py @@ -578,7 +578,9 @@ class LooppointCsvResource(FileResource, LooppointCsvLoader): resource_version=resource_version, downloader=downloader, ) - LooppointCsvLoader.__init__(self, pinpoints_file=Path(local_path)) + LooppointCsvLoader.__init__( + self, pinpoints_file=Path(self.get_local_path()) + ) def get_category_name(cls) -> str: return "LooppointCsvResource" @@ -606,7 +608,7 @@ class LooppointJsonResource(FileResource, LooppointJsonLoader): downloader=downloader, ) LooppointJsonLoader.__init__( - self, looppoint_file=local_path, region_id=region_id + self, looppoint_file=self.get_local_path(), region_id=region_id ) def get_category_name(cls) -> str: From 9aab380775ba59a62ae2b6a26a0557f3e8e1f5df Mon Sep 17 00:00:00 2001 From: Harshil Patel Date: Wed, 13 Dec 2023 13:16:08 -0800 Subject: [PATCH 08/10] arch-riscv: fix riscv matched board for se mode (#677) --- .../riscvmatched/riscvmatched_board.py | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py index f4e4b381a1..0de69a40f2 100644 --- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py +++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py @@ -312,14 +312,18 @@ class RISCVMatchedBoard( @overrides(AbstractSystemBoard) def _pre_instantiate(self): - if len(self._bootloader) > 0: - self.workload.bootloader_addr = 0x0 - self.workload.bootloader_filename = self._bootloader[0] - self.workload.kernel_addr = 0x80200000 - self.workload.entry_point = 0x80000000 # Bootloader starting point - else: - self.workload.kernel_addr = 0x0 - self.workload.entry_point = 0x80000000 + if self._fs: + if len(self._bootloader) > 0: + self.workload.bootloader_addr = 0x0 + self.workload.bootloader_filename = self._bootloader[0] + self.workload.kernel_addr = 0x80200000 + self.workload.entry_point = ( + 0x80000000 # Bootloader starting point + ) + else: + self.workload.kernel_addr = 0x0 + self.workload.entry_point = 0x80000000 + self._connect_things() def generate_device_tree(self, outdir: str) -> None: From a9f8db704483bffe9db96364d0871eed8e81a10c Mon Sep 17 00:00:00 2001 From: Roger Chang Date: Tue, 12 Dec 2023 16:35:01 +0800 Subject: [PATCH 09/10] arch-riscv: Fix the vector store indexed instructions declaration Change-Id: I6f8701ef0819c22eda8cb20d09c40101f2d001a0 --- src/arch/riscv/isa/templates/vector_mem.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/isa/templates/vector_mem.isa b/src/arch/riscv/isa/templates/vector_mem.isa index c405304a4f..1510c106c7 100644 --- a/src/arch/riscv/isa/templates/vector_mem.isa +++ b/src/arch/riscv/isa/templates/vector_mem.isa @@ -1586,7 +1586,7 @@ Fault } if (machInst.vill) return std::make_shared("VILL is set", machInst); - %(op_src_decl)s; + %(op_decl)s; %(op_rd)s; %(set_vlenb)s; %(ea_code)s; From 654e7c60197e94c34ac1bb10246298dacbb03bcf Mon Sep 17 00:00:00 2001 From: Roger Chang Date: Tue, 12 Dec 2023 16:04:09 +0800 Subject: [PATCH 10/10] arch: Fix inst flag of RISC-V vector store macro instructions Correct the instruction flags of RISC-V vector store instructions, such as `vse64_v`, `vse32_v`. The `vse64_v` in `decoder.isa` is `Mem_vc.as()[i] = Vs3_ud[i];` and it will generate the code `Mem.as()[i] = Vs3[i];`. The current regex of assignRE only mark the operand `Mem` as `dest` only if meet the formats like `Mem = Rd` or `Mem[i] = Rd` because the code ` = Rd` or `[i] = Rd` match the `assignRE` respectively. For the expression `Mem.as()[i]`, the operand `Mem` will falsely mark the operand as `src` because the code `.as()[i]` is not match the `assignRE`. The PR will ensure the operand `Mem` is dest for the format like `Mem.as()[i] = yyy`. Change-Id: I9c57986a64f1efb81eb9c7ade90712b118e0788d --- src/arch/isa_parser/util.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/arch/isa_parser/util.py b/src/arch/isa_parser/util.py index 9e330adc1f..ee1758d263 100755 --- a/src/arch/isa_parser/util.py +++ b/src/arch/isa_parser/util.py @@ -69,7 +69,9 @@ commentRE = re.compile( # destination. basically we're looking for an '=' that's not '=='. # The heinous tangle before that handles the case where the operand # has an array subscript. -assignRE = re.compile(r"(\[[^\]]+\])?\s*=(?!=)", re.MULTILINE) +assignRE = re.compile( + r"((\.as<[^>]+>\(\s*\))?\[[^\]]+\])?\s*=(?!=)", re.MULTILINE +) # # Munge a somewhat arbitrarily formatted piece of Python code