mem: Updated bytesRead and bytesWritten stat (#705)
- The bytesRead and bytesWritten stat had duplicate names. Updated bytesRead and bytesWritten for dram_interface and nvm_interface Change-Id: I7658e8a0d12ef6b95819bcafa52a85424f01ac76
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@@ -579,7 +579,7 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
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stats.readBursts++;
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if (row_hit)
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stats.readRowHits++;
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stats.bytesRead += burstSize;
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stats.dramBytesRead += burstSize;
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stats.perBankRdBursts[mem_pkt->bankId]++;
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// Update latency stats
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@@ -608,7 +608,7 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
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stats.writeBursts++;
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if (row_hit)
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stats.writeRowHits++;
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stats.bytesWritten += burstSize;
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stats.dramBytesWritten += burstSize;
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stats.perBankWrBursts[mem_pkt->bankId]++;
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}
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@@ -1885,9 +1885,9 @@ DRAMInterface::DRAMStats::DRAMStats(DRAMInterface &_dram)
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ADD_STAT(bytesPerActivate, statistics::units::Byte::get(),
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"Bytes accessed per row activation"),
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ADD_STAT(bytesRead, statistics::units::Byte::get(),
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ADD_STAT(dramBytesRead, statistics::units::Byte::get(),
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"Total bytes read"),
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ADD_STAT(bytesWritten, statistics::units::Byte::get(),
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ADD_STAT(dramBytesWritten, statistics::units::Byte::get(),
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"Total bytes written"),
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ADD_STAT(avgRdBW, statistics::units::Rate<
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@@ -1948,8 +1948,8 @@ DRAMInterface::DRAMStats::regStats()
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readRowHitRate = (readRowHits / readBursts) * 100;
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writeRowHitRate = (writeRowHits / writeBursts) * 100;
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avgRdBW = (bytesRead / 1000000) / simSeconds;
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avgWrBW = (bytesWritten / 1000000) / simSeconds;
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avgRdBW = (dramBytesRead / 1000000) / simSeconds;
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avgWrBW = (dramBytesWritten / 1000000) / simSeconds;
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peakBW = (sim_clock::Frequency / dram.burstDelay()) *
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dram.bytesPerBurst() / 1000000;
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@@ -610,8 +610,8 @@ class DRAMInterface : public MemInterface
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statistics::Formula writeRowHitRate;
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statistics::Histogram bytesPerActivate;
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// Number of bytes transferred to/from DRAM
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statistics::Scalar bytesRead;
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statistics::Scalar bytesWritten;
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statistics::Scalar dramBytesRead;
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statistics::Scalar dramBytesWritten;
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// Average bandwidth
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statistics::Formula avgRdBW;
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@@ -538,7 +538,7 @@ NVMInterface::doBurstAccess(MemPacket* pkt, Tick next_burst_at,
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// Update the stats
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if (pkt->isRead()) {
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stats.readBursts++;
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stats.bytesRead += burstSize;
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stats.nvmBytesRead += burstSize;
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stats.perBankRdBursts[pkt->bankId]++;
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stats.pendingReads.sample(numPendingReads);
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@@ -548,7 +548,7 @@ NVMInterface::doBurstAccess(MemPacket* pkt, Tick next_burst_at,
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stats.totQLat += cmd_at - pkt->entryTime;
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} else {
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stats.writeBursts++;
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stats.bytesWritten += burstSize;
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stats.nvmBytesWritten += burstSize;
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stats.perBankWrBursts[pkt->bankId]++;
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}
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@@ -650,6 +650,11 @@ NVMInterface::NVMStats::NVMStats(NVMInterface &_nvm)
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statistics::units::Tick, statistics::units::Count>::get(),
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"Average memory access latency per NVM burst"),
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ADD_STAT(nvmBytesRead, statistics::units::Byte::get(),
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"Total bytes read"),
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ADD_STAT(nvmBytesWritten, statistics::units::Byte::get(),
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"Total bytes written"),
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ADD_STAT(avgRdBW, statistics::units::Rate<
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statistics::units::Byte, statistics::units::Second>::get(),
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"Average DRAM read bandwidth in MiBytes/s"),
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@@ -715,8 +720,8 @@ NVMInterface::NVMStats::regStats()
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avgBusLat = totBusLat / readBursts;
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avgMemAccLat = totMemAccLat / readBursts;
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avgRdBW = (bytesRead / 1000000) / simSeconds;
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avgWrBW = (bytesWritten / 1000000) / simSeconds;
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avgRdBW = (nvmBytesRead / 1000000) / simSeconds;
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avgWrBW = (nvmBytesWritten / 1000000) / simSeconds;
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peakBW = (sim_clock::Frequency / nvm.tBURST) *
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nvm.burstSize / 1000000;
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@@ -125,8 +125,8 @@ class NVMInterface : public MemInterface
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statistics::Formula avgBusLat;
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statistics::Formula avgMemAccLat;
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statistics::Scalar bytesRead;
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statistics::Scalar bytesWritten;
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statistics::Scalar nvmBytesRead;
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statistics::Scalar nvmBytesWritten;
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// Average bandwidth
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statistics::Formula avgRdBW;
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