These are now pure virtual methods which more specialized port
subclasses will need to implement. The SlavePort class implements them
by ignoring them and then providing parallel functions for the
MasterPort to call. The MasterPort's methods do basically what they
did before, except now bind() uses dynamic cast to check if its peer
is of the appropriate type and also to convert it into that type before
connecting to it.
Change-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17038
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Error:
build/X86/mem/cache/prefetch/indirect_memory.cc:56:24:
error: result of comparison of constant -1 with expression
of type 'const ByteOrder' is always false
[-Werror,-Wtautological-constant-out-of-range-compare]
fatal_if(byteOrder == -1, "This prefetcher requires a defined ISA\n");
~~~~~~~~~ ^ ~~
build/X86/base/logging.hh:205:14: note: expanded from macro 'fatal_if'
if ((cond)) { \
^~~~
1 error generated.
Fix:
cast of constant (-1) used in comparison
Change-Id: I3deb154c2fe5b92c4ddf499176cb185c4ec7cf64
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17388
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
If BasicLink.hh is modified, the style checker forces a reordering of
the includes, which results in build errors because it ends up including
Topology.hh before including its xxxParams.hh files, which include
forward declarations of the BasicLink family of classes, and so
Topology.hh throws errors that BasicLink etc. are not declared.
Change-Id: I664a0652e53f0cc61763c2190a980c655b85d397
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17270
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Added additional information to the PrefetchInfo data structure
- Whether the event is triggered by a cache miss
- Whether the event is a write or a read
- Size of the data accessed
- Data accessed by the request
Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16583
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Some accesses only need to search for a tag in the tag array, with
no need to touch the data array. This is the case for CleanEvicts,
evicts that don't find a corresponding block entry (since a write
cannot be done in parallel with tag lookup), and maintenance
operations.
Change-Id: I7365a915500b5d7ab636d49a9acc627072a7f58e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14878
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
When dealing with writebacks, as soon as the packet metadata arrives
there will be a tag lookup, done sequentially because a write can't
be done in parallel. While the tag lookup is being done, the payload
will arrive. When both the payload are present and the tag is correct
block entry is determined the fill happens.
Change-Id: If1a0085d742458b675bfc012b6d908d9d9a25e32
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14877
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Previously the bus delay was being ignored for the access latency
calculation, and then applied on top of the access latency. This
patch fixes the order, as first the packet must arrive before the
access starts.
Change-Id: I6d55299a911d54625c147814dd423bfc63ef1b65
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14876
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
The header and payload delay have already been accounted and
zeroed previous to calling this function. The probe is not
allowed to modify the packet, therefore no extra delays are
added, and it is safe to remove the todo note.
Change-Id: I8ddf7e189fbe609cdec34364f3c013427930daf7
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14875
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Garnet utilizes round robin policy to select a VC for
transmission ar Network Interface and Routers. The current logic
for round robin is only fair if all the virtual networks are active
at a given router. If the router or network interface is not
receiving traffic in from any vnet then the priority is always taken
up by the next vnet in numerically (or loops back to 0).
This fix changes the way we perform round robin arbitration. When
a VC is selected in a cycle, the round robin pointer is set to the VC
next to it and is iterated from there on. If any VC does not have a
flit in a given cycle, it will lose its turn until the next round.
At maximum traffic this will model round robin correctly even if
a certain VNET is not active at that unit.
Change-Id: I9bf805221054f9f25bee14b57ff521f4ce4ca980
Reviewed-on: https://gem5-review.googlesource.com/c/16688
Reviewed-by: Jieming Yin <Jieming.Yin@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
A cache that forwards a request to the memory below does not fill and
forwards the response with the data to cache above. This change
ensures that the flags of the original response are also preserved.
Change-Id: I244b20b073c31b976358816c5b14bba413b8271f
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16182
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Many functions that used to return lists (e.g., dict.items()) now
return iterators and their iterator counterparts (e.g.,
dict.iteritems()) have been removed. Switch calls to the Python 2.7
iterator methods to use the Python 3 equivalent and add explicit list
conversions where necessary.
Change-Id: I0c18114955af8f4932d81fb689a0adb939dafaba
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15992
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reference:
Towards Bandwidth-Efficient Prefetching with Slim AMPM.
Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship.
Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already
in gem5).
Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a
Reviewed-on: https://gem5-review.googlesource.com/c/16383
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Based in the description of the following publication:
Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses
for improved correlated prefetching. In Proceedings of the 46th Annual
IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM,
New York, NY, USA, 247-259.
Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165
Reviewed-on: https://gem5-review.googlesource.com/c/15215
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reference:
Multi-level hardware prefetching using low complexity delta correlating
prediction tables with partial matching.
Marius Grannaes, Magnus Jahre, and Lasse Natvig. 2010.
In Proceedings of the 5th international conference on High Performance
Embedded Architectures and Compilers (HiPEAC'10)
Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d
Reviewed-on: https://gem5-review.googlesource.com/c/16062
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.
Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
The constructor assumes the number of nodes (i.e. controllers) equal to
the number of external nodes.
This is a not necessarily valid for all cases (e.g MESI_Three_Level -
where L0s are directly connected to L1s).
MachineType_base_number(MachineType_NUM) provides the total number of
controllers.
Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Change-Id: Id906099dc967ec70aa34dedb0b55351031ff242c
Reviewed-on: https://gem5-review.googlesource.com/c/15716
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Adding back some changes done in patch 676ae57827.
Transient state IS_I, STALE_DATA, Data_Stale event are necessary.
Issue: (cacheline A, initial state for P0 and P1 is I)
| P0 | P1 |
|GETX (A)| |
| |GETS (A)|
|Inv_All | |
P1 never sends the ACK - deadlock
It should ACK, later upon data use it as stale data, and got to I.
Solution:
P1(A):
GETS: I->IS
Inv_All: IS->IS_I, Send ACK
Data: IS_I->I, STALE_DATA to L0
Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Change-Id: I1e7b2c05439d08579c68d8eb444e0f332e75e07f
Reviewed-on: https://gem5-review.googlesource.com/c/15715
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This implementation is based in the description available in:
Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy,
Chris Wilkerson, and Zeshan Chishti. 2016.
Path confidence based lookahead prefetching.
In The 49th Annual IEEE/ACM International Symposium on Microarchitecture
(MICRO-49). IEEE Press, Piscataway, NJ, USA, Article 60, 12 pages.
Change-Id: I4b8b54efef48ced7044bd535de9a69bca68d47d9
Reviewed-on: https://gem5-review.googlesource.com/c/14819
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
A packet queue keeps track of packets that are scheduled to be sent at
a specified time. Packets are sorted such that the packet with the
earliest scheduled time is at the front of the list (unless there are
other ordering requirements). Previouly, the implemented algorithm
didn't allow packets to be placed at the front of the queue resulting
in uneccessary delays. This change fixes the implementation of
schedSendTiming.
Change-Id: Ic74abec7c3f4c12dbf67b5ab26a8d4232e18e19e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15556
Reviewed-by: Bradley Wang <radwang@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
A packet queue is typically used to hold on to packets that are
schedules to be sent in the future or when they need to queue behind
younger packets that have been sent out yet. Due to memory order
requirements, some MemObjects need to maintain the order for packet
(mostly responses) that reference the same cache block.
Prior to this patch the ordering requirements where determined when
the packet was scheduled to be sent. This patch moves the parameter to
the constructor.
Change-Id: Ieb4d94e86bc7514f5036b313ec23ea47dd653164
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15555
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Implementation of the Access Map Pattern Matching prefetcher
Based in the description of the following paper:
Access map pattern matching for high performance data cache prefetch.
Ishii, Y., Inaba, M., & Hiraki, K. (2011).
Journal of Instruction-Level Parallelism, 13, 1-24.
Change-Id: I0d4b7f7afc2ab4938bdd8755bfed26e26a28530c
Reviewed-on: https://gem5-review.googlesource.com/c/15096
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Prefetchers can be configured to operate with virtual or physical addreses.
The option can be configured through the "use_virtual_addresses" parameter
of the Prefetcher object.
Change-Id: I4f8c3687988afecc8a91c3c5b2d44cc0580f72aa
Reviewed-on: https://gem5-review.googlesource.com/c/14416
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Add a getter and a setter function to access CacheBlk::whenReady
to encapsulate the variable and allow error checking. This error
checking consists on verifying that writes to a block after it
has been inserted follow a chronological order.
As a side effect, tickInserted retain its value until updated,
that is, it is not reset in invalidate().
Change-Id: Idc3c5a99c3f002ee9acc2424f00e554877fd3a69
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14715
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Derived classes with virtual functions need to define a virtual
destructor or a protected destructor otherwise calling the base class
destructor has undefined behavior. This change adds a virtual
distructor in the base class.
Change-Id: I1c855aa56dff6585ff99b9147bdb4eb9729a0a53
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14815
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Previously a loop was being done to check whether the
block was valid/secure or not. Variables have been
added to skip this loop and save and update sector
block state when sub-blocks are validated, invalidated
and secured.
Change-Id: Ie1734f7dfda9698c7bf22a1fcbfc47ffb9239cea
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14363
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Neither assert(0) nor assert(false) give any hint as to why control
getting to them is bad, and their more descriptive versions,
assert(0 && "description") and assert(false && "description"), jury
rig assert to add an error message when the utility function panic()
already does that directly with better formatting options.
This change replaces that flavor of call to assert with panic, except
in the actual code which processes the formatting that panic uses (to
avoid infinitely recurring error handling), and in some *.sm files
since I don't know what rules those have to follow and don't want to
accidentaly break them.
Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
Reviewed-on: https://gem5-review.googlesource.com/c/14636
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
In order to allow polymorphism of the block these two
functions have been added, and all direct status
assignments to these bits have been substituted.
We also assert that the block has been invalidated
before insertion. Then the block is validated in
the insertion.
Change-Id: Ie7be42408721ad4c2c9dc880f82a62cb594f8668
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14362
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
