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arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.

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Neither assert(0) nor assert(false) give any hint as to why control
getting to them is bad, and their more descriptive versions,
assert(0 && "description") and assert(false && "description"), jury
rig assert to add an error message when the utility function panic()
already does that directly with better formatting options.

This change replaces that flavor of call to assert with panic, except
in the actual code which processes the formatting that panic uses (to
avoid infinitely recurring error handling), and in some *.sm files
since I don't know what rules those have to follow and don't want to
accidentaly break them.

Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
Reviewed-on: https://gem5-review.googlesource.com/c/14636
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Gabe Black
2018-11-26 17:51:16 -08:00
parent a66d12c235
commit 12311c5540
20 changed files with 68 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
src/arch/arm/insts/fplib.cc
View File

@@ -42,6 +42,7 @@
#include <cassert>
#include "base/logging.hh"
#include "fplib.hh"
namespace ArmISA
@@ -3740,7 +3741,7 @@ fplibRecipEstimate(uint16_t op, FPSCR &fpscr)
overflow_to_inf = false;
break;
default:
assert(0);
panic("Unrecognized FP rounding mode");
}
result = overflow_to_inf ? fp16_infinity(sgn) : fp16_max_normal(sgn);
flags |= FPLIB_OFC | FPLIB_IXC;
@@ -3802,7 +3803,7 @@ fplibRecipEstimate(uint32_t op, FPSCR &fpscr)
overflow_to_inf = false;
break;
default:
assert(0);
panic("Unrecognized FP rounding mode");
}
result = overflow_to_inf ? fp32_infinity(sgn) : fp32_max_normal(sgn);
flags |= FPLIB_OFC | FPLIB_IXC;
@@ -3864,7 +3865,7 @@ fplibRecipEstimate(uint64_t op, FPSCR &fpscr)
overflow_to_inf = false;
break;
default:
assert(0);
panic("Unrecognized FP rounding mode");
}
result = overflow_to_inf ? fp64_infinity(sgn) : fp64_max_normal(sgn);
flags |= FPLIB_OFC | FPLIB_IXC;
@@ -4108,7 +4109,7 @@ fplibRoundInt(uint16_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
x += err >> 1;
break;
default:
assert(0);
panic("Unrecognized FP rounding mode");
}
if (x == 0) {
@@ -4173,7 +4174,7 @@ fplibRoundInt(uint32_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
x += err >> 1;
break;
default:
assert(0);
panic("Unrecognized FP rounding mode");
}
if (x == 0) {
@@ -4238,7 +4239,7 @@ fplibRoundInt(uint64_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
x += err >> 1;
break;
default:
assert(0);
panic("Unrecognized FP rounding mode");
}
if (x == 0) {
@@ -4575,7 +4576,7 @@ FPToFixed_64(int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding,
x += err >> 1;
break;
default:
assert(0);
panic("Unrecognized FP rounding mode");
}
if (u ? sgn && x : x > (1ULL << (FP64_BITS - 1)) - !sgn) {

3
src/arch/arm/insts/pred_inst.hh
View File

@@ -43,6 +43,7 @@
#define __ARCH_ARM_INSTS_PREDINST_HH__
#include "arch/arm/insts/static_inst.hh"
#include "base/logging.hh"
#include "base/trace.hh"
namespace ArmISA
@@ -186,7 +187,7 @@ vfp_modified_imm(uint8_t data, FpDataType dtype)
(bits(bigData, 7) << 63);
break;
default:
assert(0);
panic("Unrecognized FP data type");
}
return bigData;
}

4
src/arch/mips/isa/formats/mem.isa
View File

@@ -121,9 +121,7 @@ output exec {{
return packet->getLE<uint64_t>();
default:
std::cerr << "bad store data size = " << packet->getSize() << std::endl;
assert(0);
panic("bad store data size = %d", packet->getSize());
return 0;
}
}

5
src/base/inet.cc
View File

@@ -51,6 +51,7 @@
#include <string>
#include "base/cprintf.hh"
#include "base/logging.hh"
#include "base/types.hh"
using namespace std;
@@ -238,7 +239,7 @@ cksum(const TcpPtr &tcp)
} else if (Ip6Ptr(tcp.packet())) {
return __tu_cksum6(Ip6Ptr(tcp.packet()));
} else {
assert(0);
panic("Unrecognized IP packet format");
}
// Should never reach here
return 0;
@@ -252,7 +253,7 @@ cksum(const UdpPtr &udp)
} else if (Ip6Ptr(udp.packet())) {
return __tu_cksum6(Ip6Ptr(udp.packet()));
} else {
assert(0);
panic("Unrecognized IP packet format");
}
return 0;
}

6
src/cpu/minor/buffers.hh
View File

@@ -118,7 +118,11 @@ class NoBubbleTraits
{
public:
static bool isBubble(const ElemType &) { return false; }
static ElemType bubble() { assert(false); }
static ElemType
bubble()
{
panic("bubble called but no bubble interface");
}
};
/** Pass on call to the element */

17
src/cpu/minor/lsq.cc
View File

@@ -44,6 +44,7 @@
#include "arch/locked_mem.hh"
#include "arch/mmapped_ipr.hh"
#include "base/logging.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/exec_context.hh"
#include "cpu/minor/execute.hh"
@@ -1121,8 +1122,7 @@ LSQ::tryToSend(LSQRequestPtr request)
request->setState(LSQRequest::StoreBufferIssuing);
break;
default:
assert(false);
break;
panic("Unrecognized LSQ request state %d.", request->state);
}
state = MemoryRunning;
@@ -1144,8 +1144,7 @@ LSQ::tryToSend(LSQRequestPtr request)
request->setState(LSQRequest::StoreBufferNeedsRetry);
break;
default:
assert(false);
break;
panic("Unrecognized LSQ request state %d.", request->state);
}
}
}
@@ -1226,10 +1225,7 @@ LSQ::recvTimingResp(PacketPtr response)
}
break;
default:
/* Shouldn't be allowed to receive a response from another
* state */
assert(false);
break;
panic("Shouldn't be allowed to receive a response from another state");
}
/* We go to idle even if there are more things in the requests queue
@@ -1260,7 +1256,7 @@ LSQ::recvReqRetry()
retryRequest->setState(LSQRequest::StoreInStoreBuffer);
break;
default:
assert(false);
panic("Unrecognized retry request state %d.", retryRequest->state);
}
/* Set state back to MemoryRunning so that the following
@@ -1283,8 +1279,7 @@ LSQ::recvReqRetry()
storeBuffer.countIssuedStore(retryRequest);
break;
default:
assert(false);
break;
panic("Unrecognized retry request state %d.", retryRequest->state);
}
retryRequest = NULL;

7
src/cpu/o3/commit_impl.hh
View File

@@ -49,8 +49,9 @@
#include <string>
#include "arch/utility.hh"
#include "base/loader/symtab.hh"
#include "base/cp_annotate.hh"
#include "base/loader/symtab.hh"
#include "base/logging.hh"
#include "config/the_isa.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/o3/commit.hh"
@@ -127,8 +128,8 @@ DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
} else {
assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
"RoundRobin,OldestReady}");
panic("Invalid SMT commit policy. Options are: Aggressive, "
"RoundRobin, OldestReady");
}
for (ThreadID tid = 0; tid < numThreads; tid++) {

5
src/cpu/o3/inst_queue_impl.hh
View File

@@ -48,6 +48,7 @@
#include <limits>
#include <vector>
#include "base/logging.hh"
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
#include "debug/IQ.hh"
@@ -162,8 +163,8 @@ InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
DPRINTF(IQ, "IQ sharing policy set to Threshold:"
"%i entries per thread.\n",thresholdIQ);
} else {
assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
"Partitioned, Threshold}");
panic("Invalid IQ sharing policy. Options are: Dynamic, "
"Partitioned, Threshold");
}
}

5
src/cpu/o3/lsq_impl.hh
View File

@@ -48,6 +48,7 @@
#include <list>
#include <string>
#include "base/logging.hh"
#include "cpu/o3/lsq.hh"
#include "debug/Drain.hh"
#include "debug/Fetch.hh"
@@ -109,8 +110,8 @@ LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
"%i entries per LQ | %i entries per SQ\n",
maxLQEntries,maxSQEntries);
} else {
assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic,"
"Partitioned, Threshold}");
panic("Invalid LSQ sharing policy. Options are: Dynamic, "
"Partitioned, Threshold");
}
//Initialize LSQs

5
src/cpu/o3/rob_impl.hh
View File

@@ -46,6 +46,7 @@
#include <list>
#include "base/logging.hh"
#include "cpu/o3/rob.hh"
#include "debug/Fetch.hh"
#include "debug/ROB.hh"
@@ -99,8 +100,8 @@ ROB<Impl>::ROB(O3CPU *_cpu, DerivO3CPUParams *params)
maxEntries[tid] = threshold;
}
} else {
assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic,"
"Partitioned, Threshold}");
panic("Invalid ROB sharing policy. Options are: Dynamic, "
"Partitioned, Threshold");
}
resetState();

4
src/gpu-compute/gpu_dyn_inst.hh
View File

@@ -39,6 +39,7 @@
#include <cstdint>
#include <string>
#include "base/logging.hh"
#include "enums/MemType.hh"
#include "enums/StorageClassType.hh"
#include "gpu-compute/compute_unit.hh"
@@ -407,8 +408,7 @@ class GPUDynInst : public GPUExecContext
} else if (isGroupSeg()) {
req->setMemSpaceConfigFlags(Request::GROUP_SEGMENT);
} else if (isFlat()) {
// TODO: translate to correct scope
assert(false);
panic("TODO: translate to correct scope");
} else {
fatal("%s has bad segment type\n", disassemble());
}

21
src/gpu-compute/gpu_tlb.cc
View File

@@ -45,6 +45,7 @@
#include "arch/x86/regs/misc.hh"
#include "arch/x86/x86_traits.hh"
#include "base/bitfield.hh"
#include "base/logging.hh"
#include "base/output.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
@@ -1150,16 +1151,16 @@ namespace X86ISA
if ((inUser && !tlb_entry->user) ||
(mode == BaseTLB::Write && badWrite)) {
// The page must have been present to get into the TLB in
// the first place. We'll assume the reserved bits are
// fine even though we're not checking them.
assert(false);
// The page must have been present to get into the TLB in
// the first place. We'll assume the reserved bits are
// fine even though we're not checking them.
panic("Page fault detected");
}
if (storeCheck && badWrite) {
// This would fault if this were a write, so return a page
// fault that reflects that happening.
assert(false);
// This would fault if this were a write, so return a page
// fault that reflects that happening.
panic("Page fault detected");
}
}
@@ -1362,7 +1363,7 @@ namespace X86ISA
*/
handleTranslationReturn(virtPageAddr, TLB_MISS, pkt);
} else {
assert(false);
panic("Unexpected TLB outcome %d", outcome);
}
}
@@ -1607,7 +1608,7 @@ namespace X86ISA
{
// The CPUSidePort never sends anything but replies. No retries
// expected.
assert(false);
panic("recvReqRetry called");
}
AddrRangeList
@@ -1648,7 +1649,7 @@ namespace X86ISA
{
// No retries should reach the TLB. The retries
// should only reach the TLBCoalescer.
assert(false);
panic("recvReqRetry called");
}
void

2
src/gpu-compute/gpu_tlb.hh
View File

@@ -272,7 +272,7 @@ namespace X86ISA
virtual void recvFunctional(PacketPtr pkt);
virtual void recvRangeChange() { }
virtual void recvReqRetry();
virtual void recvRespRetry() { assert(false); }
virtual void recvRespRetry() { panic("recvRespRetry called"); }
virtual AddrRangeList getAddrRanges() const;
};

3
src/gpu-compute/tlb_coalescer.cc
View File

@@ -37,6 +37,7 @@
#include <cstring>
#include "base/logging.hh"
#include "debug/GPUTLB.hh"
#include "sim/process.hh"
@@ -335,7 +336,7 @@ TLBCoalescer::CpuSidePort::recvTimingReq(PacketPtr pkt)
void
TLBCoalescer::CpuSidePort::recvReqRetry()
{
assert(false);
panic("recvReqRetry called");
}
void

4
src/mem/cache/queue.hh vendored
View File

@@ -52,6 +52,7 @@
#include <cassert>
#include <string>
#include "base/logging.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Drain.hh"
@@ -108,8 +109,7 @@ class Queue : public Drainable
return readyList.insert(i, entry);
}
}
assert(false);
return readyList.end(); // keep stupid compilers happy
panic("Failed to add to ready list.");
}
/** The number of entries that are in service. */

7
src/mem/mem_checker_monitor.cc
View File

@@ -43,6 +43,7 @@
#include <memory>
#include "base/logging.hh"
#include "base/output.hh"
#include "base/trace.hh"
#include "debug/MemCheckerMonitor.hh"
@@ -129,15 +130,13 @@ MemCheckerMonitor::recvFunctionalSnoop(PacketPtr pkt)
Tick
MemCheckerMonitor::recvAtomic(PacketPtr pkt)
{
assert(false && "Atomic not supported");
return masterPort.sendAtomic(pkt);
panic("Atomic not supported");
}
Tick
MemCheckerMonitor::recvAtomicSnoop(PacketPtr pkt)
{
assert(false && "Atomic not supported");
return slavePort.sendAtomicSnoop(pkt);
panic("Atomic not supported");
}
bool

4
src/mem/ruby/filters/H3BloomFilter.cc
View File

@@ -29,6 +29,7 @@
#include "mem/ruby/filters/H3BloomFilter.hh"
#include "base/intmath.hh"
#include "base/logging.hh"
using namespace std;
@@ -437,8 +438,7 @@ H3BloomFilter::set(Addr addr)
void
H3BloomFilter::unset(Addr addr)
{
cout << "ERROR: Unset should never be called in a Bloom filter";
assert(0);
panic("ERROR: Unset should never be called in a Bloom filter");
}
bool

4
src/mem/ruby/filters/MultiBitSelBloomFilter.cc
View File

@@ -31,6 +31,7 @@
#include <vector>
#include "base/intmath.hh"
#include "base/logging.hh"
#include "base/str.hh"
using namespace std;
@@ -111,8 +112,7 @@ MultiBitSelBloomFilter::set(Addr addr)
void
MultiBitSelBloomFilter::unset(Addr addr)
{
cout << "ERROR: Unset should never be called in a Bloom filter";
assert(0);
panic("ERROR: Unset should never be called in a Bloom filter");
}
bool

6
src/mem/ruby/network/garnet2.0/RoutingUnit.cc
View File

@@ -34,6 +34,7 @@
#include "mem/ruby/network/garnet2.0/RoutingUnit.hh"
#include "base/cast.hh"
#include "base/logging.hh"
#include "mem/ruby/network/garnet2.0/InputUnit.hh"
#include "mem/ruby/network/garnet2.0/Router.hh"
#include "mem/ruby/slicc_interface/Message.hh"
@@ -224,7 +225,7 @@ RoutingUnit::outportComputeXY(RouteInfo route,
// x_hops == 0 and y_hops == 0
// this is not possible
// already checked that in outportCompute() function
assert(0);
panic("x_hops == y_hops == 0");
}
return m_outports_dirn2idx[outport_dirn];
@@ -237,6 +238,5 @@ RoutingUnit::outportComputeCustom(RouteInfo route,
int inport,
PortDirection inport_dirn)
{
assert(0);
return -1;
panic("%s placeholder executed", __FUNCTION__);
}

4
src/mem/ruby/structures/CacheMemory.cc
View File

@@ -30,6 +30,7 @@
#include "mem/ruby/structures/CacheMemory.hh"
#include "base/intmath.hh"
#include "base/logging.hh"
#include "debug/RubyCache.hh"
#include "debug/RubyCacheTrace.hh"
#include "debug/RubyResourceStalls.hh"
@@ -637,8 +638,7 @@ CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr)
return false;
}
} else {
assert(false);
return true;
panic("Unrecognized cache resource type.");
}
}