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python: Make iterator handling Python 3 compatible

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Many functions that used to return lists (e.g., dict.items()) now
return iterators and their iterator counterparts (e.g.,
dict.iteritems()) have been removed. Switch calls to the Python 2.7
iterator methods to use the Python 3 equivalent and add explicit list
conversions where necessary.

Change-Id: I0c18114955af8f4932d81fb689a0adb939dafaba
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15992
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Andreas Sandberg
2019-01-26 09:19:22 +00:00
parent 8e5d168332
commit 7d71f6641f
18 changed files with 74 additions and 97 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/SConscript
View File

@@ -826,7 +826,7 @@ buildEnv = m5.util.SmartDict($build_env)
compileDate = _m5.core.compileDate
_globals = globals()
for key,val in _m5.core.__dict__.iteritems():
for key,val in _m5.core.__dict__.items():
if key.startswith('flag_'):
flag = key[5:]
_globals[flag] = val

16
src/cpu/BaseCPU.py
View File

@@ -241,26 +241,26 @@ class BaseCPU(MemObject):
def createInterruptController(self):
if buildEnv['TARGET_ISA'] == 'sparc':
self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)]
self.interrupts = [SparcInterrupts() for i in range(self.numThreads)]
elif buildEnv['TARGET_ISA'] == 'alpha':
self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)]
self.interrupts = [AlphaInterrupts() for i in range(self.numThreads)]
elif buildEnv['TARGET_ISA'] == 'x86':
self.apic_clk_domain = DerivedClockDomain(clk_domain =
Parent.clk_domain,
clk_divider = 16)
self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain,
pio_addr=0x2000000000000000)
for i in xrange(self.numThreads)]
for i in range(self.numThreads)]
_localApic = self.interrupts
elif buildEnv['TARGET_ISA'] == 'mips':
self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)]
self.interrupts = [MipsInterrupts() for i in range(self.numThreads)]
elif buildEnv['TARGET_ISA'] == 'arm':
self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
self.interrupts = [ArmInterrupts() for i in range(self.numThreads)]
elif buildEnv['TARGET_ISA'] == 'power':
self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
self.interrupts = [PowerInterrupts() for i in range(self.numThreads)]
elif buildEnv['TARGET_ISA'] == 'riscv':
self.interrupts = \
[RiscvInterrupts() for i in xrange(self.numThreads)]
[RiscvInterrupts() for i in range(self.numThreads)]
else:
print("Don't know what Interrupt Controller to use for ISA %s" %
buildEnv['TARGET_ISA'])
@@ -318,7 +318,7 @@ class BaseCPU(MemObject):
# If no ISAs have been created, assume that the user wants the
# default ISA.
if len(self.isa) == 0:
self.isa = [ default_isa_class() for i in xrange(self.numThreads) ]
self.isa = [ default_isa_class() for i in range(self.numThreads) ]
else:
if len(self.isa) != int(self.numThreads):
raise RuntimeError("Number of ISA instances doesn't "

2
src/cpu/minor/MinorCPU.py
View File

@@ -102,7 +102,7 @@ def minorMakeOpClassSet(op_classes):
def boxOpClass(op_class):
return MinorOpClass(opClass=op_class)
return MinorOpClassSet(opClasses=map(boxOpClass, op_classes))
return MinorOpClassSet(opClasses=[ boxOpClass(o) for o in op_classes ])
class MinorFU(SimObject):
type = 'MinorFU'

6
src/mem/ruby/network/simple/SimpleNetwork.py
View File

@@ -49,7 +49,7 @@ class SimpleNetwork(RubyNetwork):
for link in self.int_links:
# The network needs number_of_virtual_networks buffers per
# int_link port
for i in xrange(self.number_of_virtual_networks):
for i in range(int(self.number_of_virtual_networks)):
network_buffers.append(MessageBuffer(ordered = True))
network_buffers.append(MessageBuffer(ordered = True))
self.int_link_buffers = network_buffers
@@ -61,14 +61,14 @@ class SimpleNetwork(RubyNetwork):
# unidirectional internal link
for link in self.int_links:
if link.dst_node == router:
for i in xrange(self.number_of_virtual_networks):
for i in range(int(self.number_of_virtual_networks)):
router_buffers.append(MessageBuffer(ordered = True))
# Add message buffers to routers for each external link connection
for link in self.ext_links:
# Routers can only be int_nodes on ext_links
if link.int_node in self.routers:
for i in xrange(self.number_of_virtual_networks):
for i in range(int(self.number_of_virtual_networks)):
router_buffers.append(MessageBuffer(ordered = True))
router.port_buffers = router_buffers

2
src/mem/slicc/symbols/Type.py
View File

@@ -724,7 +724,7 @@ ${{self.c_ident}}_base_number(const ${{self.c_ident}}& obj)
# For each field
code.indent()
code(' case ${{self.c_ident}}_NUM:')
for enum in reversed(self.enums.values()):
for enum in reversed(list(self.enums.values())):
# Check if there is a defined machine with this type
if enum.primary:
code(' base += ${{enum.ident}}_Controller::getNumControllers();')

43
src/python/m5/SimObject.py
View File

@@ -168,7 +168,7 @@ def createCxxConfigDirectoryEntryFile(code, name, simobj, is_header):
code('#include "base/str.hh"')
code('#include "cxx_config/${name}.hh"')
if simobj._ports.values() != []:
if simobj._ports:
code('#include "mem/mem_object.hh"')
code('#include "mem/port.hh"')
@@ -726,7 +726,7 @@ module_init(py::module &m_internal)
for k, v in sorted(cls._params.local.items())
] + [
PyBindProperty("port_%s_connection_count" % port.name)
for port in ports.itervalues()
for port in ports.values()
]
for exp in param_exports:
exp.export(code, "%sParams" % cls)
@@ -813,7 +813,7 @@ module_init(py::module &m_internal)
for param in params:
param.cxx_predecls(code)
for port in ports.itervalues():
for port in ports.values():
port.cxx_predecls(code)
code()
@@ -846,7 +846,7 @@ module_init(py::module &m_internal)
for param in params:
param.cxx_decl(code)
for port in ports.itervalues():
for port in ports.values():
port.cxx_decl(code)
code.dedent()
@@ -886,7 +886,8 @@ def cxxMethod(*args, **kwargs):
# Create tuples of (argument, default)
if defaults:
args = args[:-len(defaults)] + zip(args[-len(defaults):], defaults)
args = args[:-len(defaults)] + \
list(zip(args[-len(defaults):], defaults))
# Don't include self in the argument list to PyBind
args = args[1:]
@@ -1118,7 +1119,7 @@ class SimObject(object):
# Do children before parameter values so that children that
# are also param values get cloned properly.
self._children = {}
for key,val in ancestor._children.iteritems():
for key,val in ancestor._children.items():
self.add_child(key, val(_memo=memo_dict))
# Inherit parameter values from class using multidict so
@@ -1127,7 +1128,7 @@ class SimObject(object):
self._values = multidict(ancestor._values)
self._hr_values = multidict(ancestor._hr_values)
# clone SimObject-valued parameters
for key,val in ancestor._values.iteritems():
for key,val in ancestor._values.items():
val = tryAsSimObjectOrVector(val)
if val is not None:
self._values[key] = val(_memo=memo_dict)
@@ -1135,10 +1136,10 @@ class SimObject(object):
# clone port references. no need to use a multidict here
# since we will be creating new references for all ports.
self._port_refs = {}
for key,val in ancestor._port_refs.iteritems():
for key,val in ancestor._port_refs.items():
self._port_refs[key] = val.clone(self, memo_dict)
# apply attribute assignments from keyword args, if any
for key,val in kwargs.iteritems():
for key,val in kwargs.items():
setattr(self, key, val)
# "Clone" the current instance by creating another instance of
@@ -1310,7 +1311,7 @@ class SimObject(object):
# that when we instantiate all the parameter objects we're still
# inside the configuration hierarchy.
def adoptOrphanParams(self):
for key,val in self._values.iteritems():
for key,val in self._values.items():
if not isSimObjectVector(val) and isSimObjectSequence(val):
# need to convert raw SimObject sequences to
# SimObjectVector class so we can call has_parent()
@@ -1345,7 +1346,7 @@ class SimObject(object):
return self, True
found_obj = None
for child in self._children.itervalues():
for child in self._children.values():
visited = False
if hasattr(child, '_visited'):
visited = getattr(child, '_visited')
@@ -1357,7 +1358,7 @@ class SimObject(object):
(found_obj.path, child.path))
found_obj = child
# search param space
for pname,pdesc in self._params.iteritems():
for pname,pdesc in self._params.items():
if issubclass(pdesc.ptype, ptype):
match_obj = self._values[pname]
if found_obj != None and found_obj != match_obj:
@@ -1370,7 +1371,7 @@ class SimObject(object):
def find_all(self, ptype):
all = {}
# search children
for child in self._children.itervalues():
for child in self._children.values():
# a child could be a list, so ensure we visit each item
if isinstance(child, list):
children = child
@@ -1386,7 +1387,7 @@ class SimObject(object):
child_all, done = child.find_all(ptype)
all.update(dict(zip(child_all, [done] * len(child_all))))
# search param space
for pname,pdesc in self._params.iteritems():
for pname,pdesc in self._params.items():
if issubclass(pdesc.ptype, ptype):
match_obj = self._values[pname]
if not isproxy(match_obj) and not isNullPointer(match_obj):
@@ -1399,7 +1400,7 @@ class SimObject(object):
return self
def unproxyParams(self):
for param in self._params.iterkeys():
for param in self._params.keys():
value = self._values.get(param)
if value != None and isproxy(value):
try:
@@ -1412,7 +1413,7 @@ class SimObject(object):
# Unproxy ports in sorted order so that 'append' operations on
# vector ports are done in a deterministic fashion.
port_names = self._ports.keys()
port_names = list(self._ports.keys())
port_names.sort()
for port_name in port_names:
port = self._port_refs.get(port_name)
@@ -1489,7 +1490,7 @@ class SimObject(object):
cc_params = cc_params_struct()
cc_params.name = str(self)
param_names = self._params.keys()
param_names = list(self._params.keys())
param_names.sort()
for param in param_names:
value = self._values.get(param)
@@ -1513,7 +1514,7 @@ class SimObject(object):
else:
setattr(cc_params, param, value)
port_names = self._ports.keys()
port_names = list(self._ports.keys())
port_names.sort()
for port_name in port_names:
port = self._port_refs.get(port_name, None)
@@ -1550,7 +1551,7 @@ class SimObject(object):
# The order of the dict is implementation dependent, so sort
# it based on the key (name) to ensure the order is the same
# on all hosts
for (name, child) in sorted(self._children.iteritems()):
for (name, child) in sorted(self._children.items()):
for obj in child.descendants():
yield obj
@@ -1567,7 +1568,7 @@ class SimObject(object):
def connectPorts(self):
# Sort the ports based on their attribute name to ensure the
# order is the same on all hosts
for (attr, portRef) in sorted(self._port_refs.iteritems()):
for (attr, portRef) in sorted(self._port_refs.items()):
portRef.ccConnect()
# Default function for generating the device structure.
@@ -1577,7 +1578,7 @@ class SimObject(object):
yield # make this function a (null) generator
def recurseDeviceTree(self, state):
for child in self._children.itervalues():
for child in self._children.values():
for item in child: # For looping over SimObjectVectors
for dt in item.generateDeviceTree(state):
yield dt

6
src/python/m5/main.py
View File

@@ -261,7 +261,7 @@ def main(*args):
print()
print('compiled %s' % defines.compileDate)
print('build options:')
keys = defines.buildEnv.keys()
keys = list(defines.buildEnv.keys())
keys.sort()
for key in keys:
val = defines.buildEnv[key]
@@ -289,12 +289,12 @@ def main(*args):
import SimObject
done = True
print("SimObjects:")
objects = SimObject.allClasses.keys()
objects = list(SimObject.allClasses.keys())
objects.sort()
for name in objects:
obj = SimObject.allClasses[name]
print(" %s" % obj)
params = obj._params.keys()
params = list(obj._params.keys())
params.sort()
for pname in params:
param = obj._params[pname]

2
src/python/m5/objects/__init__.py
View File

@@ -34,6 +34,6 @@ try:
except NameError:
modules = { }
for module in modules.iterkeys():
for module in modules.keys():
if module.startswith('m5.objects.'):
exec("from %s import *" % module)

2
src/python/m5/options.py
View File

@@ -129,7 +129,7 @@ class OptionParser(dict):
def parse_args(self):
opts,args = self._optparse.parse_args()
for key,val in opts.__dict__.iteritems():
for key,val in opts.__dict__.items():
if val is not None or key not in self:
self[key] = val

6
src/python/m5/params.py
View File

@@ -904,7 +904,7 @@ class Bool(ParamValue):
code('%s to_bool(%s, %s);' % (ret, src, dest))
def IncEthernetAddr(addr, val = 1):
bytes = map(lambda x: int(x, 16), addr.split(':'))
bytes = [ int(x, 16) for x in addr.split(':') ]
bytes[5] += val
for i in (5, 4, 3, 2, 1):
val,rem = divmod(bytes[i], 256)
@@ -1282,7 +1282,7 @@ class MetaEnum(MetaParamValue):
raise TypeError("Enum-derived class attribute 'map' " \
"must be of type dict")
# build list of value strings from map
cls.vals = cls.map.keys()
cls.vals = list(cls.map.keys())
cls.vals.sort()
elif 'vals' in init_dict:
if not isinstance(cls.vals, list):
@@ -1453,7 +1453,7 @@ class Enum(ParamValue):
@classmethod
def cxx_ini_parse(cls, code, src, dest, ret):
code('if (false) {')
for elem_name in cls.map.iterkeys():
for elem_name in cls.map.keys():
code('} else if (%s == "%s") {' % (src, elem_name))
code.indent()
code('%s = Enums::%s;' % (dest, elem_name))

4
src/python/m5/util/code_formatter.py
View File

@@ -296,11 +296,11 @@ if __name__ == '__main__':
f(' $y')
f('''$__file__:$__line__
{''')
f("${{', '.join(str(x) for x in xrange(4))}}")
f("${{', '.join(str(x) for x in range(4))}}")
f('${x}')
f('$x')
f.indent()
for i in xrange(5):
for i in range(5):
f('$x')
f('$i')
f('$0', "zero")

2
src/python/m5/util/dot_writer.py
View File

@@ -67,7 +67,7 @@ except:
pydot = False
def simnode_children(simNode):
for child in simNode._children.itervalues():
for child in simNode._children.values():
if isNullPointer(child):
continue
if isSimObjectVector(child):

8
src/python/m5/util/jobfile.py
View File

@@ -40,7 +40,7 @@ class Data(object):
if not isinstance(obj, Data):
raise AttributeError("can only update from Data object")
for key,val in obj.__dict__.iteritems():
for key,val in obj.__dict__.items():
if key.startswith('_') or key in ('name', 'desc'):
continue
@@ -57,7 +57,7 @@ class Data(object):
(key, self.__dict__[key], val))
d = self.__dict__[key]
for k,v in val.iteritems():
for k,v in val.items():
if k in d:
raise AttributeError(
"%s specified more than once in %s" % (k, key))
@@ -100,7 +100,7 @@ class Data(object):
return self.__dict__[key]
def __iter__(self):
keys = self.__dict__.keys()
keys = list(self.__dict__.keys())
keys.sort()
for key in keys:
if not key.startswith('_'):
@@ -115,7 +115,7 @@ class Data(object):
def __repr__(self):
d = {}
for key,value in self.__dict__.iteritems():
for key,value in self.__dict__.items():
if not key.startswith('_'):
d[key] = value

21
src/python/m5/util/multidict.py
View File

@@ -82,27 +82,18 @@ class multidict(object):
def has_key(self, key):
return key in self
def iteritems(self):
def items(self):
for item in self.next():
yield item
def items(self):
return [ item for item in self.next() ]
def iterkeys(self):
def keys(self):
for key,value in self.next():
yield key
def keys(self):
return [ key for key,value in self.next() ]
def itervalues(self):
def values(self):
for key,value in self.next():
yield value
def values(self):
return [ value for key,value in self.next() ]
def get(self, key, default=None):
try:
return self[key]
@@ -152,8 +143,8 @@ if __name__ == '__main__':
test2.setdefault('f', multidict)
print('test1>', test1.items())
print('test2>', test2.items())
print('test1>', list(test1.items()))
print('test2>', list(test2.items()))
#print(test1['a'])
print(test1['b'])
print(test1['c'])
@@ -166,7 +157,7 @@ if __name__ == '__main__':
print(test2['d'])
print(test2['e'])
for key in test2.iterkeys():
for key in test2.keys():
print(key)
test2.get('g', 'foo')

10
src/python/m5/util/smartdict.py
View File

@@ -138,17 +138,11 @@ class SmartDict(attrdict):
dict.__setitem__(self, key, str(item))
def values(self):
return [ Variable(v) for v in dict.values(self) ]
def itervalues(self):
for value in dict.itervalues(self):
for value in dict.values(self):
yield Variable(value)
def items(self):
return [ (k, Variable(v)) for k,v in dict.items(self) ]
def iteritems(self):
for key,value in dict.iteritems(self):
for key,value in dict.items(self):
yield key, Variable(value)
def get(self, key, default='False'):

29
src/python/m5/util/sorteddict.py
View File

@@ -41,7 +41,7 @@ class SortedDict(dict):
try:
return self._sorted_keys
except AttributeError:
_sorted_keys = self.sorted(dict.iterkeys(self))
_sorted_keys = self.sorted(dict.keys(self))
self._sorted_keys = _sorted_keys
return _sorted_keys
@@ -89,7 +89,7 @@ class SortedDict(dict):
def __repr__(self):
return 'SortedDict({%s})' % ', '.join('%r: %r' % item
for item in self.iteritems())
for item in self.items())
def __setitem__(self, key, item):
dict.__setitem__(self, key, item)
self._del_keys()
@@ -107,22 +107,13 @@ class SortedDict(dict):
return t(self)
def keys(self):
return self._keys[:]
return self._keys
def values(self):
return list(self.itervalues())
def items(self):
return list(self.iteritems())
def iterkeys(self):
return iter(self._keys)
def itervalues(self):
for k in self._keys:
yield self[k]
def iteritems(self):
def items(self):
for k in self._keys:
yield k, self[k]
@@ -184,12 +175,12 @@ class SortedDict(dict):
if __name__ == '__main__':
def display(d):
print(d)
print(d.keys())
print(list(d.iterkeys()))
print(d.values())
print(list(d.itervalues()))
print(d.items())
print(list(d.iteritems()))
print(list(d.keys()))
print(list(d.keys()))
print(list(d.values()))
print(list(d.values()))
print(list(d.items()))
print(list(d.items()))
d = SortedDict(x=24,e=5,j=4,b=2,z=26,d=4)
display(d)

4
src/python/m5/util/terminal.py
View File

@@ -63,7 +63,7 @@ capability_map = {
'Normal': 'sgr0'
}
capability_names = capability_map.keys()
capability_names = list(capability_map.keys())
def null_cap_string(s, *args):
return ''
@@ -84,7 +84,7 @@ class ColorStrings(object):
def __init__(self, cap_string):
for i, c in enumerate(color_names):
setattr(self, c, cap_string('setaf', i))
for name, cap in capability_map.iteritems():
for name, cap in capability_map.items():
setattr(self, name, cap_string(cap))
termcap = ColorStrings(cap_string)

6
src/systemc/tests/tlm/endian_conv/testall.py
View File

@@ -93,7 +93,7 @@ def txn_generator(nr):
pr_enabled = 0.5
bus_widths = [1, 2, 4, 8, 16]
data_widths = [1, 2, 4, 8, 16] + [1, 2, 4, 8] + [1, 2, 4] + [1, 2]
lengths = range(1,33) + range(1,17) + range(1,9) + range(1,5) + range(1,3)
lengths = list(range(1,33)) + list(range(1,17)) + list(range(1,9)) + list(range(1,5)) + list(range(1,3))
pr_short_be = 0.2
pr_stream = 0.1
nr_generated = 0
@@ -105,8 +105,8 @@ def txn_generator(nr):
if data_width <= bus_width: break
if random.random() < 0.25: break
length = random.choice(lengths)
addr_base = random.choice(range(0,1024,bus_width))
addr_offset = random.choice(range(bus_width)+[0]*(bus_width/2))
addr_base = random.choice(list(range(0,1024,bus_width)))
addr_offset = random.choice(list(range(bus_width))+[0]*(bus_width/2))
txn = transaction(
bus_width = bus_width,
data_width = data_width,