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mem: Move the Port base class into sim.

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The Port class is going to be officially used for more than just memory
system connections.

Change-Id: I493e721f99051865c5f0c06946a2303ff723c2af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17036
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Gabe Black
2019-03-07 00:45:09 -08:00
parent 6e8be00dff
commit 993c26938c
5 changed files with 154 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/mem/port.cc
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@@ -51,15 +51,6 @@
#include "base/trace.hh"
#include "mem/mem_object.hh"
Port::Port(const std::string &_name, PortID _id)
: portName(_name), id(_id)
{
}
Port::~Port()
{
}
BaseMasterPort::BaseMasterPort(const std::string &name, PortID _id)
: Port(name, _id), _baseSlavePort(NULL)
{

45
src/mem/port.hh
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@@ -52,53 +52,10 @@
#include "base/addr_range.hh"
#include "mem/packet.hh"
#include "sim/port.hh"
class MemObject;
/**
* Ports are used to interface memory objects to each other. A port is
* either a master or a slave and the connected peer is always of the
* opposite role. Each port has a name, an owner, and an identifier.
*/
class Port
{
private:
/** Descriptive name (for DPRINTF output) */
std::string portName;
protected:
/**
* A numeric identifier to distinguish ports in a vector, and set
* to InvalidPortID in case this port is not part of a vector.
*/
const PortID id;
/**
* Abstract base class for ports
*
* @param _name Port name including the owners name
* @param _id A port identifier for vector ports
*/
Port(const std::string& _name, PortID _id);
/**
* Virtual destructor due to inheritance.
*/
virtual ~Port();
public:
/** Return port name (for DPRINTF). */
const std::string name() const { return portName; }
/** Get the port id. */
PortID getId() const { return id; }
};
/** Forward declaration */
class BaseSlavePort;

1
src/sim/SConscript
View File

@@ -54,6 +54,7 @@ Source('global_event.cc')
Source('init.cc', add_tags='python')
Source('init_signals.cc')
Source('main.cc', tags='main')
Source('port.cc')
Source('root.cc')
Source('serialize.cc')
Source('drain.cc')

53
src/sim/port.cc Normal file
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@@ -0,0 +1,53 @@
/*
* Copyright (c) 2011-2012,2015,2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ron Dreslinski
* Andreas Hansson
* William Wang
*/
/**
* @file
* Port Object Declaration.
*/
#include "sim/port.hh"
Port::Port(const std::string& _name, PortID _id) : portName(_name), id(_id) {}
Port::~Port() {}

99
src/sim/port.hh Normal file
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@@ -0,0 +1,99 @@
/*
* Copyright (c) 2011-2012,2015,2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ron Dreslinski
* Andreas Hansson
* William Wang
*/
/**
* @file
* Port Object Declaration.
*/
#ifndef __SIM_PORT_HH__
#define __SIM_PORT_HH__
#include <string>
#include "base/types.hh"
/**
* Ports are used to interface objects to each other.
*/
class Port
{
private:
/** Descriptive name (for DPRINTF output) */
std::string portName;
protected:
/**
* A numeric identifier to distinguish ports in a vector, and set
* to InvalidPortID in case this port is not part of a vector.
*/
const PortID id;
/**
* Abstract base class for ports
*
* @param _name Port name including the owners name
* @param _id A port identifier for vector ports
*/
Port(const std::string& _name, PortID _id);
/**
* Virtual destructor due to inheritance.
*/
virtual ~Port();
public:
/** Return port name (for DPRINTF). */
const std::string name() const { return portName; }
/** Get the port id. */
PortID getId() const { return id; }
};
#endif //__SIM_PORT_HH__