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mem-cache: Fix write hit latency calculation order

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Patch 6d8694a5fb changes the order
at which the access latency is calculated for hits. This order
is incorrect, since the calculations must use the blk's whenReady
value before the access is satisfied.

Change-Id: I30dae5435f54200cc8fdf71fd0dbd2cf9c6f8b17
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17190
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
This commit is contained in:
Daniel
2019-03-14 00:51:35 +01:00
committed by Daniel Carvalho
parent 7bd864c144
commit 94a00fb6d9
1 changed files with 9 additions and 8 deletions
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17
src/mem/cache/base.cc vendored
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@@ -1065,15 +1065,15 @@ BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
incHitCount(pkt);
// A writeback searches for the block, then writes the data
lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency);
// When the packet metadata arrives, the tag lookup will be done while
// the payload is arriving. Then the block will be ready to access as
// soon as the fill is done
blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
std::max(cyclesToTicks(tag_latency), (uint64_t)pkt->payloadDelay));
// A writeback searches for the block, then writes the data
lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency);
return true;
} else if (pkt->cmd == MemCmd::CleanEvict) {
// A CleanEvict does not need to access the data array
@@ -1143,15 +1143,15 @@ BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
incHitCount(pkt);
// A writeback searches for the block, then writes the data
lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency);
// When the packet metadata arrives, the tag lookup will be done while
// the payload is arriving. Then the block will be ready to access as
// soon as the fill is done
blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
std::max(cyclesToTicks(tag_latency), (uint64_t)pkt->payloadDelay));
// A writeback searches for the block, then writes the data
lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency);
// if this a write-through packet it will be sent to cache
// below
return !pkt->writeThrough();
@@ -1159,8 +1159,6 @@ BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
blk->isReadable())) {
// OK to satisfy access
incHitCount(pkt);
satisfyRequest(pkt, blk);
maintainClusivity(pkt->fromCache(), blk);
// Calculate access latency based on the need to access the data array
if (pkt->isRead() || pkt->isWrite()) {
@@ -1169,6 +1167,9 @@ BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency);
}
satisfyRequest(pkt, blk);
maintainClusivity(pkt->fromCache(), blk);
return true;
}