python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

src/arch/alpha/AlphaSystem.py

@@ -28,7 +28,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from System import System
+
+from m5.objects.System import System
 
 class AlphaSystem(System):
     type = 'AlphaSystem'

src/arch/alpha/AlphaTLB.py

@@ -29,7 +29,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class AlphaTLB(BaseTLB):
     type = 'AlphaTLB'

src/arch/arm/ArmISA.py

@@ -40,8 +40,8 @@ from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
-from ArmPMU import ArmPMU
-from ISACommon import VecRegRenameMode
+from m5.objects.ArmPMU import ArmPMU
+from m5.objects.ISACommon import VecRegRenameMode
 
 # Enum for DecoderFlavour
 class DecoderFlavour(Enum): vals = ['Generic']

src/arch/arm/ArmNativeTrace.py

@@ -28,7 +28,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from CPUTracers import NativeTrace
+from m5.objects.CPUTracers import NativeTrace
 
 class ArmNativeTrace(NativeTrace):
     type = 'ArmNativeTrace'

src/arch/arm/ArmPMU.py

@@ -42,7 +42,7 @@ from m5.SimObject import *
 from m5.params import *
 from m5.params import isNullPointer
 from m5.proxy import *
-from Gic import ArmInterruptPin
+from m5.objects.Gic import ArmInterruptPin
 
 class ProbeEvent(object):
     def __init__(self, pmu, _eventId, obj, *listOfNames):

src/arch/arm/ArmSemihosting.py

@@ -38,8 +38,8 @@
 from m5.params import *
 from m5.SimObject import *
 
-from Serial import SerialDevice
-from Terminal import Terminal
+from m5.objects.Serial import SerialDevice
+from m5.objects.Terminal import Terminal
 
 class ArmSemihosting(SimObject):
     type = 'ArmSemihosting'

src/arch/arm/ArmSystem.py

@@ -41,8 +41,8 @@ from m5.options import *
 from m5.SimObject import *
 from m5.util.fdthelper import *
 
-from System import System
-from ArmSemihosting import ArmSemihosting
+from m5.objects.System import System
+from m5.objects.ArmSemihosting import ArmSemihosting
 
 class ArmMachineType(Enum):
     map = {

src/arch/arm/ArmTLB.py

@@ -40,8 +40,8 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
-from BaseTLB import BaseTLB
+from m5.objects.MemObject import MemObject
+from m5.objects.BaseTLB import BaseTLB
 
 # Basic stage 1 translation objects
 class ArmTableWalker(MemObject):

src/arch/arm/tracers/TarmacTrace.py

@@ -38,7 +38,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from InstTracer import InstTracer
+from m5.objects.InstTracer import InstTracer
 
 class TarmacParser(InstTracer):
     type = 'TarmacParser'

src/arch/mips/MipsSystem.py

@@ -32,7 +32,7 @@ from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 
-from System import System
+from m5.objects.System import System
 
 class MipsSystem(System):
     type = 'MipsSystem'

src/arch/mips/MipsTLB.py

@@ -32,7 +32,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class MipsTLB(BaseTLB):
     type = 'MipsTLB'

src/arch/power/PowerTLB.py

@@ -31,7 +31,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class PowerTLB(BaseTLB):
     type = 'PowerTLB'

src/arch/riscv/RiscvSystem.py

@@ -31,8 +31,8 @@
 #          Robert Scheffel
 
 from m5.params import *
-from System import System
 
+from m5.objects.System import System
 
 class RiscvSystem(System):
     type = 'RiscvSystem'

src/arch/riscv/RiscvTLB.py

@@ -32,7 +32,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class RiscvTLB(BaseTLB):
     type = 'RiscvTLB'

src/arch/sparc/SparcNativeTrace.py

@@ -28,7 +28,8 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from CPUTracers import NativeTrace
+
+from m5.objects.CPUTracers import NativeTrace
 
 class SparcNativeTrace(NativeTrace):
     type = 'SparcNativeTrace'

src/arch/sparc/SparcSystem.py

@@ -28,8 +28,8 @@
 
 from m5.params import *
 
-from SimpleMemory import SimpleMemory
-from System import System
+from m5.objects.SimpleMemory import SimpleMemory
+from m5.objects.System import System
 
 class SparcSystem(System):
     type = 'SparcSystem'

src/arch/sparc/SparcTLB.py

@@ -29,7 +29,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class SparcTLB(BaseTLB):
     type = 'SparcTLB'

src/arch/x86/X86LocalApic.py

@@ -41,7 +41,8 @@
 from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
+
+from m5.objects.Device import BasicPioDevice
 
 class X86LocalApic(BasicPioDevice):
     type = 'X86LocalApic'

src/arch/x86/X86NativeTrace.py

@@ -28,7 +28,8 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from CPUTracers import NativeTrace
+
+from m5.objects.CPUTracers import NativeTrace
 
 class X86NativeTrace(NativeTrace):
     type = 'X86NativeTrace'

src/arch/x86/X86System.py

@@ -36,11 +36,12 @@
 # Authors: Gabe Black
 
 from m5.params import *
-from E820 import X86E820Table, X86E820Entry
-from SMBios import X86SMBiosSMBiosTable
-from IntelMP import X86IntelMPFloatingPointer, X86IntelMPConfigTable
-from ACPI import X86ACPIRSDP
-from System import System
+
+from m5.objects.E820 import X86E820Table, X86E820Entry
+from m5.objects.SMBios import X86SMBiosSMBiosTable
+from m5.objects.IntelMP import X86IntelMPFloatingPointer, X86IntelMPConfigTable
+from m5.objects.ACPI import X86ACPIRSDP
+from m5.objects.System import System
 
 class X86System(System):
     type = 'X86System'

src/arch/x86/X86TLB.py

@@ -38,8 +38,8 @@
 from m5.params import *
 from m5.proxy import *
 
-from BaseTLB import BaseTLB
-from MemObject import MemObject
+from m5.objects.BaseTLB import BaseTLB
+from m5.objects.MemObject import MemObject
 
 class X86PagetableWalker(MemObject):
     type = 'X86PagetableWalker'

src/base/vnc/Vnc.py

@@ -37,7 +37,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from Graphics import *
+from m5.objects.Graphics import *
 
 
 class VncInput(SimObject):

src/cpu/BaseCPU.py

@@ -52,51 +52,51 @@ from m5.params import *
 from m5.proxy import *
 from m5.util.fdthelper import *
 
-from XBar import L2XBar
-from InstTracer import InstTracer
-from CPUTracers import ExeTracer
-from MemObject import MemObject
-from SubSystem import SubSystem
-from ClockDomain import *
-from Platform import Platform
+from m5.objects.XBar import L2XBar
+from m5.objects.InstTracer import InstTracer
+from m5.objects.CPUTracers import ExeTracer
+from m5.objects.MemObject import MemObject
+from m5.objects.SubSystem import SubSystem
+from m5.objects.ClockDomain import *
+from m5.objects.Platform import Platform
 
 default_tracer = ExeTracer()
 
 if buildEnv['TARGET_ISA'] == 'alpha':
-    from AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
-    from AlphaInterrupts import AlphaInterrupts
-    from AlphaISA import AlphaISA
+    from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
+    from m5.objects.AlphaInterrupts import AlphaInterrupts
+    from m5.objects.AlphaISA import AlphaISA
     default_isa_class = AlphaISA
 elif buildEnv['TARGET_ISA'] == 'sparc':
-    from SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
-    from SparcInterrupts import SparcInterrupts
-    from SparcISA import SparcISA
+    from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
+    from m5.objects.SparcInterrupts import SparcInterrupts
+    from m5.objects.SparcISA import SparcISA
     default_isa_class = SparcISA
 elif buildEnv['TARGET_ISA'] == 'x86':
-    from X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
-    from X86LocalApic import X86LocalApic
-    from X86ISA import X86ISA
+    from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
+    from m5.objects.X86LocalApic import X86LocalApic
+    from m5.objects.X86ISA import X86ISA
     default_isa_class = X86ISA
 elif buildEnv['TARGET_ISA'] == 'mips':
-    from MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
-    from MipsInterrupts import MipsInterrupts
-    from MipsISA import MipsISA
+    from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
+    from m5.objects.MipsInterrupts import MipsInterrupts
+    from m5.objects.MipsISA import MipsISA
     default_isa_class = MipsISA
 elif buildEnv['TARGET_ISA'] == 'arm':
-    from ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
-    from ArmTLB import ArmStage2IMMU, ArmStage2DMMU
-    from ArmInterrupts import ArmInterrupts
-    from ArmISA import ArmISA
+    from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
+    from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU
+    from m5.objects.ArmInterrupts import ArmInterrupts
+    from m5.objects.ArmISA import ArmISA
     default_isa_class = ArmISA
 elif buildEnv['TARGET_ISA'] == 'power':
-    from PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
-    from PowerInterrupts import PowerInterrupts
-    from PowerISA import PowerISA
+    from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
+    from m5.objects.PowerInterrupts import PowerInterrupts
+    from m5.objects.PowerISA import PowerISA
     default_isa_class = PowerISA
 elif buildEnv['TARGET_ISA'] == 'riscv':
-    from RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
-    from RiscvInterrupts import RiscvInterrupts
-    from RiscvISA import RiscvISA
+    from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
+    from m5.objects.RiscvInterrupts import RiscvInterrupts
+    from m5.objects.RiscvISA import RiscvISA
     default_isa_class = RiscvISA
 
 class BaseCPU(MemObject):

src/cpu/CPUTracers.py

@@ -28,7 +28,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from InstTracer import InstTracer
+from m5.objects.InstTracer import InstTracer
 
 class ExeTracer(InstTracer):
     type = 'ExeTracer'

src/cpu/CheckerCPU.py

@@ -27,7 +27,8 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from BaseCPU import BaseCPU
+
+from m5.objects.BaseCPU import BaseCPU
 
 class CheckerCPU(BaseCPU):
     type = 'CheckerCPU'

src/cpu/DummyChecker.py

@@ -36,7 +36,7 @@
 # Authors: Geoffrey Blake
 
 from m5.params import *
-from CheckerCPU import CheckerCPU
+from m5.objects.CheckerCPU import CheckerCPU
 
 class DummyChecker(CheckerCPU):
     type = 'DummyChecker'

src/cpu/InstPBTrace.py

@@ -28,7 +28,8 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from InstTracer import InstTracer
+
+from m5.objects.InstTracer import InstTracer
 
 class InstPBTrace(InstTracer):
     type = 'InstPBTrace'

src/cpu/kvm/BaseKvmCPU.py

@@ -39,8 +39,8 @@ from m5.SimObject import *
 from m5.params import *
 from m5.proxy import *
 
-from BaseCPU import BaseCPU
-from KvmVM import KvmVM
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.KvmVM import KvmVM
 
 class BaseKvmCPU(BaseCPU):
     type = 'BaseKvmCPU'

src/cpu/kvm/X86KvmCPU.py

@@ -28,7 +28,8 @@
 
 from m5.params import *
 from m5.SimObject import *
-from BaseKvmCPU import BaseKvmCPU
+
+from m5.objects.BaseKvmCPU import BaseKvmCPU
 
 class X86KvmCPU(BaseKvmCPU):
     type = 'X86KvmCPU'

src/cpu/minor/MinorCPU.py

@@ -46,12 +46,12 @@ from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
-from BaseCPU import BaseCPU
-from DummyChecker import DummyChecker
-from BranchPredictor import *
-from TimingExpr import TimingExpr
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.DummyChecker import DummyChecker
+from m5.objects.BranchPredictor import *
+from m5.objects.TimingExpr import TimingExpr
 
-from FuncUnit import OpClass
+from m5.objects.FuncUnit import OpClass
 
 class MinorOpClass(SimObject):
     """Boxing of OpClass to get around build problems and provide a hook for

src/cpu/o3/FUPool.py

@@ -28,8 +28,8 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from FuncUnit import *
-from FuncUnitConfig import *
+from m5.objects.FuncUnit import *
+from m5.objects.FuncUnitConfig import *
 
 class FUPool(SimObject):
     type = 'FUPool'

src/cpu/o3/FuncUnitConfig.py

@@ -41,7 +41,8 @@
 from m5.SimObject import SimObject
 from m5.defines import buildEnv
 from m5.params import *
-from FuncUnit import *
+
+from m5.objects.FuncUnit import *
 
 class IntALU(FUDesc):
     opList = [ OpDesc(opClass='IntAlu') ]

src/cpu/o3/O3CPU.py

@@ -43,10 +43,11 @@ from __future__ import print_function
 from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
-from BaseCPU import BaseCPU
-from FUPool import *
-from O3Checker import O3Checker
-from BranchPredictor import *
+
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.FUPool import *
+from m5.objects.O3Checker import O3Checker
+from m5.objects.BranchPredictor import *
 
 class FetchPolicy(ScopedEnum):
     vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ]
@@ -178,7 +179,7 @@ class DerivO3CPU(BaseCPU):
 
     def addCheckerCpu(self):
         if buildEnv['TARGET_ISA'] in ['arm']:
-            from ArmTLB import ArmTLB
+            from m5.objects.ArmTLB import ArmTLB
 
             self.checker = O3Checker(workload=self.workload,
                                      exitOnError=False,

src/cpu/o3/O3Checker.py

@@ -27,7 +27,7 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from CheckerCPU import CheckerCPU
+from m5.objects.CheckerCPU import CheckerCPU
 
 class O3Checker(CheckerCPU):
     type = 'O3Checker'

src/cpu/o3/probe/ElasticTrace.py

@@ -37,7 +37,7 @@
 #          Andreas Hansson
 #          Thomas Grass
 
-from Probe import *
+from m5.objects.Probe import *
 
 class ElasticTrace(ProbeListenerObject):
     type = 'ElasticTrace'

src/cpu/o3/probe/SimpleTrace.py

@@ -35,7 +35,7 @@
 #
 # Authors: Matt Horsnell
 
-from Probe import *
+from m5.objects.Probe import *
 
 class SimpleTrace(ProbeListenerObject):
     type = 'SimpleTrace'

src/cpu/simple/AtomicSimpleCPU.py

@@ -39,8 +39,8 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from BaseSimpleCPU import BaseSimpleCPU
-from SimPoint import SimPoint
+from m5.objects.BaseSimpleCPU import BaseSimpleCPU
+from m5.objects.SimPoint import SimPoint
 
 class AtomicSimpleCPU(BaseSimpleCPU):
     """Simple CPU model executing a configurable number of

src/cpu/simple/BaseSimpleCPU.py

@@ -30,9 +30,10 @@ from __future__ import print_function
 
 from m5.defines import buildEnv
 from m5.params import *
-from BaseCPU import BaseCPU
-from DummyChecker import DummyChecker
-from BranchPredictor import *
+
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.DummyChecker import DummyChecker
+from m5.objects.BranchPredictor import *
 
 class BaseSimpleCPU(BaseCPU):
     type = 'BaseSimpleCPU'
@@ -41,7 +42,7 @@ class BaseSimpleCPU(BaseCPU):
 
     def addCheckerCpu(self):
         if buildEnv['TARGET_ISA'] in ['arm']:
-            from ArmTLB import ArmTLB
+            from m5.objects.ArmTLB import ArmTLB
 
             self.checker = DummyChecker(workload = self.workload)
             self.checker.itb = ArmTLB(size = self.itb.size)

src/cpu/simple/NonCachingSimpleCPU.py

@@ -36,7 +36,7 @@
 # Authors: Andreas Sandberg
 
 from m5.params import *
-from AtomicSimpleCPU import AtomicSimpleCPU
+from m5.objects.AtomicSimpleCPU import AtomicSimpleCPU
 
 class NonCachingSimpleCPU(AtomicSimpleCPU):
     """Simple CPU model based on the atomic CPU. Unlike the atomic CPU,

src/cpu/simple/TimingSimpleCPU.py

@@ -27,7 +27,8 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from BaseSimpleCPU import BaseSimpleCPU
+
+from m5.objects.BaseSimpleCPU import BaseSimpleCPU
 
 class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'

src/cpu/simple/probes/SimPoint.py

@@ -36,7 +36,7 @@
 # Authors: Curtis Dunham
 
 from m5.params import *
-from Probe import ProbeListenerObject
+from m5.objects.Probe import ProbeListenerObject
 
 class SimPoint(ProbeListenerObject):
     """Probe for collecting SimPoint Basic Block Vectors (BBVs)."""

src/cpu/testers/directedtest/RubyDirectedTester.py

@@ -27,10 +27,11 @@
 # Authors: Brad Beckmann
 
 from m5.SimObject import SimObject
-from MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
 
+from m5.objects.MemObject import MemObject
+
 class DirectedGenerator(SimObject):
     type = 'DirectedGenerator'
     abstract = True

src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py

@@ -26,7 +26,7 @@
 #
 # Authors: Tushar Krishna
 
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
 

src/cpu/testers/memtest/MemTest.py

@@ -38,11 +38,11 @@
 #
 # Authors: Nathan Binkert
 #          Andreas Hansson
-
-from MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
 
+from m5.objects.MemObject import MemObject
+
 class MemTest(MemObject):
     type = 'MemTest'
     cxx_header = "cpu/testers/memtest/memtest.hh"

src/cpu/testers/rubytest/RubyTester.py

@@ -25,11 +25,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-
-from MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
 
+from m5.objects.MemObject import MemObject
+
 class RubyTester(MemObject):
     type = 'RubyTester'
     cxx_header = "cpu/testers/rubytest/RubyTester.hh"

src/cpu/testers/traffic_gen/BaseTrafficGen.py

@@ -39,7 +39,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 # Types of Stream Generators.
 # Those are orthogonal to the other generators in the TrafficGen

src/cpu/testers/traffic_gen/PyTrafficGen.py

@@ -37,7 +37,8 @@
 
 from m5.defines import buildEnv
 from m5.SimObject import *
-from BaseTrafficGen import *
+
+from m5.objects.BaseTrafficGen import *
 
 class PyTrafficGen(BaseTrafficGen):
     type = 'PyTrafficGen'

src/cpu/testers/traffic_gen/TrafficGen.py

@@ -38,7 +38,7 @@
 #          Sascha Bischoff
 
 from m5.params import *
-from BaseTrafficGen import *
+from m5.objects.BaseTrafficGen import *
 
 # The behaviour of this traffic generator is specified in a
 # configuration file, and this file describes a state transition graph

src/cpu/trace/TraceCPU.py

@@ -38,7 +38,7 @@
 #          Thomas Grass
 
 from m5.params import *
-from BaseCPU import BaseCPU
+from m5.objects.BaseCPU import BaseCPU
 
 class TraceCPU(BaseCPU):
     """Trace CPU model which replays traces generated in a prior simulation

src/dev/BadDevice.py

@@ -27,7 +27,7 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
 
 class BadDevice(BasicPioDevice):
     type = 'BadDevice'

src/dev/Device.py

@@ -42,7 +42,8 @@
 from m5.params import *
 from m5.proxy import *
 from m5.util.fdthelper import *
-from MemObject import MemObject
+
+from m5.objects.MemObject import MemObject
 
 class PioDevice(MemObject):
     type = 'PioDevice'

src/dev/Platform.py

@@ -29,6 +29,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
+
 class Platform(SimObject):
     type = 'Platform'
     abstract = True

src/dev/alpha/AlphaBackdoor.py

@@ -29,7 +29,8 @@
 from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
+
+from m5.objects.Device import BasicPioDevice
 
 class AlphaBackdoor(BasicPioDevice):
     type = 'AlphaBackdoor'

src/dev/alpha/Tsunami.py

@@ -28,12 +28,12 @@
 
 from m5.params import *
 from m5.proxy import *
-from BadDevice import BadDevice
-from AlphaBackdoor import AlphaBackdoor
-from Device import BasicPioDevice, IsaFake, BadAddr
-from PciHost import GenericPciHost
-from Platform import Platform
-from Uart import Uart8250
+from m5.objects.BadDevice import BadDevice
+from m5.objects.AlphaBackdoor import AlphaBackdoor
+from m5.objects.Device import BasicPioDevice, IsaFake, BadAddr
+from m5.objects.PciHost import GenericPciHost
+from m5.objects.Platform import Platform
+from m5.objects.Uart import Uart8250
 
 class TsunamiCChip(BasicPioDevice):
     type = 'TsunamiCChip'

src/dev/arm/EnergyCtrl.py

@@ -39,7 +39,7 @@
 
 from m5.params import *
 from m5.SimObject import SimObject
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
 from m5.proxy import *
 from m5.util.fdthelper import *
 

src/dev/arm/FlashDevice.py

@@ -38,7 +38,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from AbstractNVM import *
+
+from m5.objects.AbstractNVM import *
 
 #Distribution of the data.
 #sequential: sequential (address n+1 is likely to be on the same plane as n)

src/dev/arm/Gic.py

@@ -40,8 +40,8 @@ from m5.proxy import *
 from m5.util.fdthelper import *
 from m5.SimObject import SimObject
 
-from Device import PioDevice
-from Platform import Platform
+from m5.objects.Device import PioDevice
+from m5.objects.Platform import Platform
 
 class BaseGic(PioDevice):
     type = 'BaseGic'

src/dev/arm/NoMali.py

@@ -36,8 +36,9 @@
 # Authors: Andreas Sandberg
 
 from m5.params import *
-from Device import BasicPioDevice
-from Gic import *
+
+from m5.objects.Device import BasicPioDevice
+from m5.objects.Gic import *
 
 class NoMaliGpuType(Enum): vals = [
     'T60x',

src/dev/arm/RealView.py

@@ -45,31 +45,32 @@ from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 from m5.util.fdthelper import *
-from ClockDomain import ClockDomain
-from VoltageDomain import VoltageDomain
-from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
-from PciHost import *
-from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
-from Ide import *
-from Platform import Platform
-from Terminal import Terminal
-from Uart import Uart
-from SimpleMemory import SimpleMemory
-from Gic import *
-from EnergyCtrl import EnergyCtrl
-from ClockedObject import ClockedObject
-from ClockDomain import SrcClockDomain
-from SubSystem import SubSystem
-from Graphics import ImageFormat
-from ClockedObject import ClockedObject
-from PS2 import *
-from VirtIOMMIO import MmioVirtIO
+from m5.objects.ClockDomain import ClockDomain
+from m5.objects.VoltageDomain import VoltageDomain
+from m5.objects.Device import \
+    BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
+from m5.objects.PciHost import *
+from m5.objects.Ethernet import NSGigE, IGbE_igb, IGbE_e1000
+from m5.objects.Ide import *
+from m5.objects.Platform import Platform
+from m5.objects.Terminal import Terminal
+from m5.objects.Uart import Uart
+from m5.objects.SimpleMemory import SimpleMemory
+from m5.objects.Gic import *
+from m5.objects.EnergyCtrl import EnergyCtrl
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.ClockDomain import SrcClockDomain
+from m5.objects.SubSystem import SubSystem
+from m5.objects.Graphics import ImageFormat
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.PS2 import *
+from m5.objects.VirtIOMMIO import MmioVirtIO
 
 # Platforms with KVM support should generally use in-kernel GIC
 # emulation. Use a GIC model that automatically switches between
 # gem5's GIC model and KVM's GIC model if KVM is available.
 try:
-    from KvmGic import MuxingKvmGic
+    from m5.objects.KvmGic import MuxingKvmGic
     kvm_gicv2_class = MuxingKvmGic
 except ImportError:
     # KVM support wasn't compiled into gem5. Fallback to a

src/dev/arm/UFSHostDevice.py

@@ -38,8 +38,8 @@
 import sys
 from m5.params import *
 from m5.proxy import *
-from Device import DmaDevice
-from AbstractNVM import *
+from m5.objects.Device import DmaDevice
+from m5.objects.AbstractNVM import *
 
 class UFSHostDevice(DmaDevice):
     type = 'UFSHostDevice'

src/dev/arm/VirtIOMMIO.py

@@ -41,9 +41,9 @@ from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
 
-from Device import BasicPioDevice
-from Gic import ArmInterruptPin
-from VirtIO import VirtIODeviceBase, VirtIODummyDevice
+from m5.objects.Device import BasicPioDevice
+from m5.objects.Gic import ArmInterruptPin
+from m5.objects.VirtIO import VirtIODeviceBase, VirtIODummyDevice
 
 class MmioVirtIO(BasicPioDevice):
     type = 'MmioVirtIO'

src/dev/i2c/I2C.py

@@ -37,7 +37,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
 
 class I2CDevice(SimObject):
     type = 'I2CDevice'

src/dev/mips/Malta.py

@@ -29,10 +29,10 @@
 from m5.params import *
 from m5.proxy import *
 
-from BadDevice import BadDevice
-from Device import BasicPioDevice
-from Platform import Platform
-from Uart import Uart8250
+from m5.objects.BadDevice import BadDevice
+from m5.objects.Device import BasicPioDevice
+from m5.objects.Platform import Platform
+from m5.objects.Uart import Uart8250
 
 class MaltaCChip(BasicPioDevice):
     type = 'MaltaCChip'

src/dev/net/Ethernet.py

@@ -42,7 +42,7 @@ from m5.defines import buildEnv
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from PciDevice import PciDevice
+from m5.objects.PciDevice import PciDevice
 
 class EtherObject(SimObject):
     type = 'EtherObject'

src/dev/pci/CopyEngine.py

@@ -29,7 +29,8 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from PciDevice import PciDevice
+
+from m5.objects.PciDevice import PciDevice
 
 class CopyEngine(PciDevice):
     type = 'CopyEngine'

src/dev/pci/PciDevice.py

@@ -41,8 +41,8 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from Device import DmaDevice
-from PciHost import PciHost
+from m5.objects.Device import DmaDevice
+from m5.objects.PciHost import PciHost
 
 class PciDevice(DmaDevice):
     type = 'PciDevice'

src/dev/pci/PciHost.py

@@ -39,8 +39,8 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from Device import PioDevice
-from Platform import Platform
+from m5.objects.Device import PioDevice
+from m5.objects.Platform import Platform
 
 class PciHost(PioDevice):
     type = 'PciHost'

src/dev/serial/Terminal.py

@@ -29,7 +29,8 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from Serial import SerialDevice
+
+from m5.objects.Serial import SerialDevice
 
 class Terminal(SerialDevice):
     type = 'Terminal'

src/dev/serial/Uart.py

@@ -40,8 +40,9 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
-from Serial import SerialDevice
+
+from m5.objects.Device import BasicPioDevice
+from m5.objects.Serial import SerialDevice
 
 class Uart(BasicPioDevice):
     type = 'Uart'

src/dev/sparc/T1000.py

@@ -28,10 +28,11 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
-from Platform import Platform
-from Terminal import Terminal
-from Uart import Uart8250
+
+from m5.objects.Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
+from m5.objects.Platform import Platform
+from m5.objects.Terminal import Terminal
+from m5.objects.Uart import Uart8250
 
 
 class MmDisk(BasicPioDevice):

src/dev/storage/Ide.py

@@ -28,7 +28,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from PciDevice import PciDevice
+from m5.objects.PciDevice import PciDevice
 
 class IdeID(Enum): vals = ['master', 'slave']
 

src/dev/virtio/VirtIO.py

@@ -40,8 +40,8 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from Device import PioDevice
-from PciDevice import PciDevice
+from m5.objects.Device import PioDevice
+from m5.objects.PciDevice import PciDevice
 
 
 class VirtIODeviceBase(SimObject):

src/dev/virtio/VirtIO9P.py

@@ -39,7 +39,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from VirtIO import VirtIODeviceBase
+from m5.objects.VirtIO import VirtIODeviceBase
 
 class VirtIO9PBase(VirtIODeviceBase):
     type = 'VirtIO9PBase'

src/dev/virtio/VirtIOBlock.py

@@ -39,7 +39,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from VirtIO import VirtIODeviceBase
+from m5.objects.VirtIO import VirtIODeviceBase
 
 class VirtIOBlock(VirtIODeviceBase):
     type = 'VirtIOBlock'

src/dev/virtio/VirtIOConsole.py

@@ -39,8 +39,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from VirtIO import VirtIODeviceBase
-from Serial import SerialDevice
+from m5.objects.VirtIO import VirtIODeviceBase
+from m5.objects.Serial import SerialDevice
 
 class VirtIOConsole(VirtIODeviceBase):
     type = 'VirtIOConsole'

src/dev/x86/Cmos.py

@@ -28,8 +28,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSourcePin
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSourcePin
 
 class Cmos(BasicPioDevice):
     type = 'Cmos'

src/dev/x86/I8042.py

@@ -28,9 +28,9 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSourcePin
-from PS2 import *
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSourcePin
+from m5.objects.PS2 import *
 
 class I8042(BasicPioDevice):
     type = 'I8042'

src/dev/x86/I82094AA.py

@@ -28,8 +28,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSinkPin
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSinkPin
 
 class I82094AA(BasicPioDevice):
     type = 'I82094AA'

src/dev/x86/I8237.py

@@ -28,7 +28,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
 
 class I8237(BasicPioDevice):
     type = 'I8237'

src/dev/x86/I8254.py

@@ -28,8 +28,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSourcePin
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSourcePin
 
 class I8254(BasicPioDevice):
     type = 'I8254'

src/dev/x86/I8259.py

@@ -28,8 +28,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSourcePin, X86IntSinkPin
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSourcePin, X86IntSinkPin
 
 class X86I8259CascadeMode(Enum):
     map = {'I8259Master' : 0,

src/dev/x86/Pc.py

@@ -29,12 +29,12 @@
 from m5.params import *
 from m5.proxy import *
 
-from Device import IsaFake
-from Platform import Platform
-from SouthBridge import SouthBridge
-from Terminal import Terminal
-from Uart import Uart8250
-from PciHost import GenericPciHost
+from m5.objects.Device import IsaFake
+from m5.objects.Platform import Platform
+from m5.objects.SouthBridge import SouthBridge
+from m5.objects.Terminal import Terminal
+from m5.objects.Uart import Uart8250
+from m5.objects.PciHost import GenericPciHost
 
 def x86IOAddress(port):
     IO_address_space_base = 0x8000000000000000

src/dev/x86/PcSpeaker.py

@@ -28,7 +28,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
 
 class PcSpeaker(BasicPioDevice):
     type = 'PcSpeaker'

src/dev/x86/SouthBridge.py

@@ -28,15 +28,15 @@
 
 from m5.params import *
 from m5.proxy import *
-from Cmos import Cmos
-from I8042 import I8042
-from I82094AA import I82094AA
-from I8237 import I8237
-from I8254 import I8254
-from I8259 import I8259
-from Ide import IdeController
-from PcSpeaker import PcSpeaker
-from X86IntPin import X86IntLine
+from m5.objects.Cmos import Cmos
+from m5.objects.I8042 import I8042
+from m5.objects.I82094AA import I82094AA
+from m5.objects.I8237 import I8237
+from m5.objects.I8254 import I8254
+from m5.objects.I8259 import I8259
+from m5.objects.Ide import IdeController
+from m5.objects.PcSpeaker import PcSpeaker
+from m5.objects.X86IntPin import X86IntLine
 from m5.SimObject import SimObject
 
 def x86IOAddress(port):

src/gpu-compute/GPU.py

@@ -33,16 +33,17 @@
 #  Author: Steve Reinhardt
 #
 
-from ClockedObject import ClockedObject
-from Device import DmaDevice
 from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
-from MemObject import MemObject
-from Process import EmulatedDriver
-from Bridge import Bridge
-from LdsState import LdsState
+
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.Device import DmaDevice
+from m5.objects.MemObject import MemObject
+from m5.objects.Process import EmulatedDriver
+from m5.objects.Bridge import Bridge
+from m5.objects.LdsState import LdsState
 
 class PrefetchType(Enum): vals = [
     'PF_CU',

src/gpu-compute/LdsState.py

@@ -35,7 +35,7 @@ from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class LdsState(MemObject):
     type = 'LdsState'

src/learning_gem5/part2/SimpleCache.py

@@ -29,7 +29,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class SimpleCache(MemObject):
     type = 'SimpleCache'

src/learning_gem5/part2/SimpleMemobj.py

@@ -28,7 +28,7 @@
 # Authors: Jason Lowe-Power
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class SimpleMemobj(MemObject):
     type = 'SimpleMemobj'

src/mem/AbstractMemory.py

@@ -40,7 +40,7 @@
 #          Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class AbstractMemory(MemObject):
     type = 'AbstractMemory'

src/mem/AddrMapper.py

@@ -36,7 +36,7 @@
 # Authors: Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 # An address mapper changes the packet addresses in going from the
 # slave port side of the mapper to the master port side. When the

src/mem/Bridge.py

@@ -40,7 +40,7 @@
 #          Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class Bridge(MemObject):
     type = 'Bridge'

src/mem/CommMonitor.py

@@ -38,8 +38,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
-from System import System
+from m5.objects.MemObject import MemObject
+from m5.objects.System import System
 
 # The communication monitor will most typically be used in combination
 # with periodic dumping and resetting of stats using schedStatEvent

src/mem/DRAMCtrl.py

@@ -46,8 +46,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from AbstractMemory import *
-from QoSMemCtrl import *
+from m5.objects.AbstractMemory import *
+from m5.objects.QoSMemCtrl import *
 
 # Enum for memory scheduling algorithms, currently First-Come
 # First-Served and a First-Row Hit then First-Come First-Served

src/mem/ExternalMaster.py

@@ -39,7 +39,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class ExternalMaster(MemObject):
     type = 'ExternalMaster'

src/mem/ExternalSlave.py

@@ -36,7 +36,7 @@
 # Authors: Andrew Bardsley
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class ExternalSlave(MemObject):
     type = 'ExternalSlave'

src/mem/HMCController.py

@@ -39,7 +39,7 @@
 # Authors: Erfan Azarkhish
 
 from m5.params import *
-from XBar import *
+from m5.objects.XBar import *
 
 # References:
 # [1] http://www.open-silicon.com/open-silicon-ips/hmc/

src/mem/MemChecker.py

@@ -35,7 +35,7 @@
 #
 # Authors: Marco Elver
 
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *

src/mem/MemDelay.py

@@ -36,7 +36,7 @@
 # Authors: Andreas Sandberg
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class MemDelay(MemObject):
     type = 'MemDelay'

src/mem/MemObject.py

@@ -26,7 +26,7 @@
 #
 # Authors: Ron Dreslinski
 
-from ClockedObject import ClockedObject
+from m5.objects.ClockedObject import ClockedObject
 
 class MemObject(ClockedObject):
     type = 'MemObject'

src/mem/SerialLink.py

@@ -42,7 +42,7 @@
 #          Erfan Azarkhish
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 # SerialLink is a simple variation of the Bridge class, with the ability to
 # account for the latency of packet serialization.