These instructions were extracting a bitfield by masking it, but then
didn't shift the bit into the correct position. They were then
comparing it with 1, which clang 11 correctly complained would always
be false. That warning became an error which broke the build.
This fixes that problem by switching that line and the few surrounding
lines to use the bits() function which removes the need to manually
mask or shift values. That makes it less likely for there to be a
mistake, and also makes it more obvious which bits are being accessed.
Change-Id: I692214f898e90dc7d5de460d1da2ef6aefda4fb8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25224
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
By using braced initializer lists and dropping the default
unimplementedFunc implementation function, the SyscallDesc tables
become a lot less crowded, and it's now very obvious which syscalls
are implemented just by quickly visually scanning the table.
This will also make it a lot easier to change the underlying type
stored in the table without having to adjust all of the instances
within them.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187
Change-Id: I7821de74812e1c02ca4550fc9c46cc2188cf1bd0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23189
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
+ ArmISA.py: Enabling the feature adding QARMA algorithm as default.
+ faults.cc/faults.hh: Add PACTrapFault
+ includes/insts.isa: Adding new isa files.
+ aarch64.isa: Add decode part for PAC instructions
+ pauth.isa: Isa for PAC instructions
+ misc64.isa: PAC instructions templates
+ miscregs.cc/hh/types: New Registers for PAC Key low/high.
+ types.hh: Modification of system registers that were incomplete
for ARMv8
+ utility.hh: Add isSecureEL2 enabled. The function is there but will
always return false for now.
+ pauth_helpers.hh/cc: Implementation of auxiliar functions and derivates.
+ qarma.hh/cc: This functions follow ARMv8 reference pseudo code
implementing QARMA block cipher algorithms.
Change-Id: I3095a1279204206d9a816a4fb7fc176c18f9680b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25024
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
It may be necessary to initialize the GuestABI Position type based on
the current state of the thread, for instance by reading the current
stack pointer.
This change makes it possible (but not mandantory) for an ABI to supply
a constructor for Position which accepts a ThreadContext * which it can
use to intiialize itself.
Change-Id: I5609b185f746368c5f9eb2a04074dcafa088f925
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23749
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Because the fast models (or at least the one we've looked at) give
access to the integer registers mostly based on the current view of
those registers, it does its own flattening and prevents accessing most
of the raw storage locations without this extra level of mapping. To
store to the flattened locations, we need to unflatten the indexes and
in one case shift the mode so that we get the right values.
Some registers which have irrelevant values for fast model (the "PC"
which is actually diverted elsewhere, the zero register, microcode
registers, and the "dummy" register), and those are left out of the
mapping so that they return 0 and blow up gem5 when someone attempts to
set them.
Change-Id: Ia2d315d5ca4c8a65b17ad52beff3a366ca8b3d46
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23791
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
These don't have anything in them at the moment since making some ISA
methods virtual and not inlined will likely add overhead, specifically
the ones for flattening registers. Some code may need to be rearranged
to minimize that overhead before the ISA objects can be truly put
behind a generic interface.
Change-Id: Ie36a771e977535a7996fdff701ce202bb95c8c58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25007
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Some AArch64 system registers report UNDEFINED behaviours if accessed
from EL2 or EL3 in a non-EL2 Host enabled (HCR_EL2.E2H == 0) environment.
Examples of these are seen in the Generic Timer system registers,
namely CNTP_CTL_EL02 or CNTKCTL_EL12.
This patch provides an ISA filter for specifying the above condition.
Change-Id: I240f9afdb000faf5d3c9274ba12bd4cc41fe8604
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24664
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
These two functions were called in exactly one place one right after
the other, and served similar purposes.
This change merges them together, and cleans them up slightly. It also
removes checks for FullSystem, since those functions are only called
in full system to begin with.
Change-Id: I214f7d2d3f88960dccb5895c1241f61cd78716a8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24904
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The call to initCPU was moved into initState in the base CPU class
since it should only really be called when starting a simulation
fresh. Otherwise checkpointed state will be loaded over the state of
the CPU anyway, so there's no reason to set up anything else.
Unfortunately that made it possible for the System level initialization
and the CPU initialization to happen out of order, effectively letting
initCPU clobber the state the System might have set up to prepare for
executing a kernel for instance.
To work around that issue, the call was moved to init which would
necessarily happen before initState, restoring the original ordering.
This change moves the change *back* into initState, but of the System
class instead of the CPU class. This makes it possible to guarantee
that OS initialization happens after initCPU since that's also done
by System subclasses, and they control when they call initCPU of the
base class.
This also slightly simmplifies when initCPU is called since we
shouldn't need to check whether a context is switched out or not. If
it's registered with the System object, then it should be in a
currently swapped in CPU.
This also puts the initCPU and startupCPU calls right next to each
other. A future change will take advantage of that and merge the
calls together.
Also, because there are already ISA specific subclasses of System
which already have specialized versions of initState, we should be
able to move the code in initCPU and startupCPU directly into those
subclasses. That will give those subclasses more flexibilty if, for
instance, they want all CPUs to start running in the BIOS like they
would on a real system, or if they want only the BSP to be active
as if the BIOS had already paused the APs before passing control to
a bootloader or OS.
This will also remove another two TheISA:: style functions, reducing
the number of global dependencies on a single ISA.
Change-Id: Ic56924660a5b575a07844a198f69a0e7fa212b52
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24903
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Some ABIs (including 32 bit ARM, 64 bit x86) allocate their argument
registers differently depending on their return value. For instance,
if the value needs to be returned in memory because it's too big,
the caller could pass a pointer to where the result should be stored
when the function returns. This pointer acts like an invisible first
argument, offsetting where all the normal arguments actually live.
This change adds a mechanism to handle that case. The Result templates
can now declare an allocate() static method which is given a
ThreadContext *, and a reference to the Position object. It can perform
any adjustment it needs to before the normal argument extraction
starts.
Change-Id: Ibda9095f0e8c9882742d24f5effe309ccb514188
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23747
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
A recent-ish change modified ExeTraceRecord::traceInst to make it more
consistent with DPRINTF-s by using dprintf_flag to print the trace
string. The generated string was passed as the format however, and that
means that all % characters in the output (from register names, for
example) are interpreted as format characters, mangling the output and
making cprintf angry since there are no corresponding arguments.
This change sets the format to "%s" instead, and passes the trace
string as the first argument. The argument won't be parsed for format
specifiers, and so should no longer get mangled.
Change-Id: I8fa9c2c22179a5b55104a618a4af4080a3931c5f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24643
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
It looks like this function is supposed to allow you to set up a PC
based event which will trigger when the simulator executes a particular
kernel function. That event doesn't actually do anything, but you can
set a breakpoint there with gdb when debugging gem5 itself.
There are a couple of problems with this function. First, it assumes
that you want to set the breakpoint based on the first system in your
simulation. Frequently simulations have only one system, but there
isn't any rule that says they must, or any way to pick a different
system.
Second, this function assumes that you're in FS mode, that there is a
kernel, and that there is a kernel symbol table to look symbols up in.
On top of that, this function is a bit redundant since you can just use
gdb to debug the kernel inside a simulated system.
Change-Id: I8dadbd42fc7d4ccba2a035a2a72e6ede4b872f3c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24644
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
TheISA::initCPU is basically an ISA specific implementation of reset
logic on architectural state. As such, it only needs to be called if
we're not going to load a checkpoint, ie in initState.
Also, since the implementation was the same across all CPUs, this
change collapses all the individual implementations down into the base
CPU class.
Change-Id: Id68133fd7f31619c90bf7b3aad35ae20871acaa4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24189
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
