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arm: Use static_cast to get access the ARM specific ISA functions.

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Change-Id: I8d237fa60c0fc17c97ed351afd0fa3c623262f0d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25006
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-02-02 15:27:41 -08:00
parent 98b2d7acc5
commit c8a102c6af
4 changed files with 24 additions and 10 deletions
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14
src/arch/arm/insts/misc64.cc
View File

@@ -269,13 +269,19 @@ MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
break;
// GICv3 regs
case MISCREG_ICC_SGI0R_EL1:
if (tc->getIsaPtr()->haveGICv3CpuIfc())
trap_to_hyp = hcr.fmo && el == EL1;
{
auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
if (isa->haveGICv3CpuIfc())
trap_to_hyp = hcr.fmo && el == EL1;
}
break;
case MISCREG_ICC_SGI1R_EL1:
case MISCREG_ICC_ASGI1R_EL1:
if (tc->getIsaPtr()->haveGICv3CpuIfc())
trap_to_hyp = hcr.imo && el == EL1;
{
auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
if (isa->haveGICv3CpuIfc())
trap_to_hyp = hcr.imo && el == EL1;
}
break;
default:
break;

3
src/arch/arm/insts/static_inst.cc
View File

@@ -1166,7 +1166,8 @@ ArmStaticInst::generalExceptionsToAArch64(ThreadContext *tc,
unsigned
ArmStaticInst::getCurSveVecLenInBits(ThreadContext *tc)
{
return tc->getIsaPtr()->getCurSveVecLenInBits(tc);
auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
return isa->getCurSveVecLenInBits(tc);
}
}

3
src/arch/arm/miscregs.cc
View File

@@ -1080,8 +1080,9 @@ snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
int
snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
{
auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
SCR scr = tc->readMiscReg(MISCREG_SCR);
return tc->getIsaPtr()->snsBankedIndex64(reg, scr.ns);
return isa->snsBankedIndex64(reg, scr.ns);
}
/**

14
src/arch/arm/utility.cc
View File

@@ -612,13 +612,19 @@ mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss)
break;
// GICv3 regs
case MISCREG_ICC_SGI0R:
if (tc->getIsaPtr()->haveGICv3CpuIfc())
trapToHype = hcr.fmo;
{
auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
if (isa->haveGICv3CpuIfc())
trapToHype = hcr.fmo;
}
break;
case MISCREG_ICC_SGI1R:
case MISCREG_ICC_ASGI1R:
if (tc->getIsaPtr()->haveGICv3CpuIfc())
trapToHype = hcr.imo;
{
auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
if (isa->haveGICv3CpuIfc())
trapToHype = hcr.imo;
}
break;
// No default action needed
default: