arch,sim: Use _m5opRange in System::allocPhysPages.

This removes the hardcoded assumption that the m5 ops live at the
address they use in x86.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ia551d7cf5b08f926c7756541c92a2af9bb73b88a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23181
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/system.hh

@@ -269,12 +269,6 @@ class ArmSystem : public System
         return mask(physAddrRange());
     }
 
-    /**
-     * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
-     * an invalid/empty range if disabled.
-     */
-    const AddrRange &m5opRange() const { return _m5opRange; }
-
     /** Is Arm Semihosting support enabled? */
     bool haveSemihosting() const { return semihosting != nullptr; }
 

src/sim/system.cc

@@ -432,8 +432,7 @@ System::allocPhysPages(int npages)
 
     Addr next_return_addr = pagePtr << PageShift;
 
-    AddrRange m5opRange(0xffff0000, 0x100000000);
-    if (m5opRange.contains(next_return_addr)) {
+    if (_m5opRange.contains(next_return_addr)) {
         warn("Reached m5ops MMIO region\n");
         return_addr = 0xffffffff;
         pagePtr = 0xffffffff >> PageShift;

src/sim/system.hh

@@ -584,6 +584,12 @@ class System : public SimObject, public PCEventScope
 
     const Params *params() const { return (const Params *)_params; }
 
+    /**
+     * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
+     * an invalid/empty range if disabled.
+     */
+    const AddrRange &m5opRange() const { return _m5opRange; }
+
   public:
 
     /**