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fastmodel: Ensure unset vec reg bits are zero/false.

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These bits won't be overwritten with values from IRIS, and so we should
make sure they're cleared and don't have old values or junk.

Change-Id: Ib81780ab523f00d6a4d31841d68a3d83924982a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24327
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-01-13 17:00:41 -08:00
parent d062a82f11
commit 992454e0f2
1 changed files with 8 additions and 4 deletions
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12
src/arch/arm/fastmodel/iris/thread_context.cc
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@@ -572,12 +572,14 @@ const ArmISA::VecRegContainer &
ThreadContext::readVecReg(const RegId &reg_id) const
{
const RegIndex idx = reg_id.index();
ArmISA::VecRegContainer &reg = vecRegs.at(idx);
reg.zero();
// Ignore accesses to registers which aren't architected. gem5 defines a
// few extra registers which it uses internally in the implementation of
// some instructions.
if (idx >= vecRegIds.size())
return vecRegs.at(idx);
ArmISA::VecRegContainer &reg = vecRegs.at(idx);
return reg;
iris::ResourceReadResult result;
call().resource_read(_instId, result, vecRegIds.at(idx));
@@ -598,10 +600,12 @@ const ArmISA::VecPredRegContainer &
ThreadContext::readVecPredReg(const RegId &reg_id) const
{
RegIndex idx = reg_id.index();
if (idx >= vecPredRegIds.size())
return vecPredRegs.at(idx);
ArmISA::VecPredRegContainer &reg = vecPredRegs.at(idx);
reg.reset();
if (idx >= vecPredRegIds.size())
return reg;
iris::ResourceReadResult result;
call().resource_read(_instId, result, vecPredRegIds.at(idx));