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x86: Handle m5 op accesses directly in the mmapped IPR handlers.

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The common handlers only handle the m5ops, and it takes more plumbing
to get to them than to just handle the m5ops directly from x86.

Also, centralizing the call to PseudoInst::pseudoInst prevents
specializing the ABI per-ISA.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ife9cf0d61ac87605ddc9cf9c84feebb8b23cc33a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23184
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2019-11-25 17:01:56 -08:00
parent 549e0b25e3
commit b3eb2db7e4
2 changed files with 27 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

44
src/arch/x86/mmapped_ipr.hh
View File

@@ -46,47 +46,55 @@
* ISA-specific helper functions for memory mapped IPR accesses.
*/
#include "arch/generic/mmapped_ipr.hh"
#include "arch/x86/regs/misc.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/pseudo_inst.hh"
namespace X86ISA
{
inline Cycles
handleIprRead(ThreadContext *xc, Packet *pkt)
handleIprRead(ThreadContext *tc, Packet *pkt)
{
if (GenericISA::isGenericIprAccess(pkt)) {
return GenericISA::handleGenericIprRead(xc, pkt);
Addr addr = pkt->getAddr();
auto m5opRange = tc->getSystemPtr()->m5opRange();
if (m5opRange.contains(addr)) {
uint8_t func;
PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
uint64_t ret = PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
pkt->setLE(ret);
} else {
Addr offset = pkt->getAddr() & mask(3);
MiscRegIndex index = (MiscRegIndex)(
pkt->getAddr() / sizeof(RegVal));
RegVal data = htole(xc->readMiscReg(index));
Addr offset = addr & mask(3);
MiscRegIndex index = (MiscRegIndex)(addr / sizeof(RegVal));
RegVal data = htole(tc->readMiscReg(index));
// Make sure we don't trot off the end of data.
assert(offset + pkt->getSize() <= sizeof(RegVal));
pkt->setData(((uint8_t *)&data) + offset);
return Cycles(1);
}
return Cycles(1);
}
inline Cycles
handleIprWrite(ThreadContext *xc, Packet *pkt)
handleIprWrite(ThreadContext *tc, Packet *pkt)
{
if (GenericISA::isGenericIprAccess(pkt)) {
return GenericISA::handleGenericIprWrite(xc, pkt);
Addr addr = pkt->getAddr();
auto m5opRange = tc->getSystemPtr()->m5opRange();
if (m5opRange.contains(addr)) {
uint8_t func;
PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
} else {
Addr offset = pkt->getAddr() & mask(3);
MiscRegIndex index = (MiscRegIndex)(
pkt->getAddr() / sizeof(RegVal));
RegVal data = htole(xc->readMiscRegNoEffect(index));
Addr offset = addr & mask(3);
MiscRegIndex index = (MiscRegIndex)(addr / sizeof(RegVal));
RegVal data = htole(tc->readMiscRegNoEffect(index));
// Make sure we don't trot off the end of data.
assert(offset + pkt->getSize() <= sizeof(RegVal));
pkt->writeData(((uint8_t *)&data) + offset);
xc->setMiscReg(index, letoh(data));
return Cycles(1);
tc->setMiscReg(index, letoh(data));
}
return Cycles(1);
}
}

5
src/arch/x86/tlb.cc
View File

@@ -230,10 +230,7 @@ TLB::finalizePhysical(const RequestPtr &req,
Addr paddr = req->getPaddr();
if (m5opRange.contains(paddr)) {
req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
Request::STRICT_ORDER);
req->setPaddr(GenericISA::iprAddressPseudoInst((paddr >> 8) & 0xFF,
paddr & 0xFF));
req->setFlags(Request::MMAPPED_IPR | Request::STRICT_ORDER);
} else if (FullSystem) {
// Check for an access to the local APIC
LocalApicBase localApicBase =