When running gem5, the simulator outputs the following message to
describe the ports used by the VNC server and ther terminal:
Listening for system connection on port 5900
Listening for system connection on port 3456
The code used to extract the basename ('terminal' or 'vncserver') and
print that instead of system. However, this doesn't seem to work any
more. Change the code to output the full object name instead.
Change-Id: Ib27f66a5f8ba64c7a875b4e2f26a2e2ff48db8f3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10026
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
The bits and insertBits assume the first bit is the larger bit and the last
bit is the smaller bit. This commit fixes several X86 and Power calls to
these functions that incorrectly assumed that first was the smaller bit.
Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01
Reviewed-on: https://gem5-review.googlesource.com/10241
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Create a block insertion function to be used when inserting
blocks. This resets the number of references to 1 (the
insertion is taken into account), sets the insertion tick,
and set secure state.
Change-Id: Ifc34cbbd1c125207ce47912d188809221c7a157e
Reviewed-on: https://gem5-review.googlesource.com/9824
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Add a simple memory-mapped device that forwards writes to a serial
devices and treats reads as reads from the device. Unlike real UART
models, this one doesn't support interrupts.
This is useful to implement various debug devices that exist in many
systems.
Change-Id: I1e4300e4d3b70825a15d03f47d4e026941f9066c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10025
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Implementation of a Second-Chance replacement policy. Similar to FIFO,
but every block is given a second chance if it has been touched.
Change-Id: Id4d52b698d0045a4914a4d848fdf9c3c00a28508
Reviewed-on: https://gem5-review.googlesource.com/9441
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Replacement data is specific for each replacement policy, and thus
should be instantiated differently by each policy.
Touch() and reset() do not need to be aware of CacheBlk, as they
only update its ReplacementData.
Invalidate() makes replacement policies independent of cache blocks,
by removing the awareness of the valid state.
An inheritable base ReplaceableEntry class was created to allow usage
of replacement policies with any table-like structure.
Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b
Reviewed-on: https://gem5-review.googlesource.com/9421
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
With this patch a gem5 System will store more info about its Masters.
While it was previously keeping track of the Master name and Master ID
only, it is now adding a per-Master pointer to the SimObject related to
the Master.
This will make it possible for a client to query a System for a Master
using either the master's name or the master's pointer.
Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9781
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Use block iteration instead of numSets and assoc in print(),
cleanupRefs() and computeStats().
This makes these functions rely solely on what they are used for:
printing and calculating stats of blocks. With the addition of
Sectors an extra indirection level is added, and thus these
functions would be skipping blocks.
Change-Id: I0006f82736cce02ba3e501ffafe9236f748daf32
Reviewed-on: https://gem5-review.googlesource.com/10143
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
An access must perform a block search, which is done by findBlock.
The tagHash is indexed by tags, so use extractTag instead of re-
implementing its functionality.
Change-Id: Ib5abacbc65cddf0f2d7e4440eb5355b56998a585
Reviewed-on: https://gem5-review.googlesource.com/10082
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This patch changes the fault being thrown when MSR/MRS to an unknown
Misc register in AArch64. While previously the instruction was decoded
as an Unknown instruction (hence not printing any information), it is
now decoded as a FailUnimplemented and the unrecognized System register
numbers (CRn, op0...) are printed.
Change-Id: I205ff7adcde5934231c77e8d2250db69a34581fc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10061
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Some bits in CPACR_EL1 are RES0 but not RAZ/WI. For instance, bit
CPACR_EL1[31] is RES0 but should be made stateful, since it allows
programing of CPACR.ASEDIS. Therefore the masking of CPACR_EL1
is removed.
Change-Id: If1fa3fa1e06bc38495b8afce2c635f3ddf76ce32
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10046
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This patch fixes the masking of cp10 and cp11 in CPACR according to
NSACR.cp10 / NSACR.cp11 by adding the condition "in Non-secure state,
if EL3 is implemented and is using AArch32...", which is specified in
ARM ARM.
Change-Id: Id00e7bf04d6a985e27dbf1028677da0746b79924
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10044
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This change fixes a few bugs and refactors the mechanism by which
caches that use the FALRU tags can output statistics for multiple
cache sizes ranging from the minimum cache of interest up to the
actual configured cache size.
Change-Id: Ibea029cf275a8c068c26eceeb06c761fc53aede2
Reviewed-on: https://gem5-review.googlesource.com/9826
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
change 2a15bfd79c introduced
a few bugs in the tlb of the cu. asserts in the gpu tlb
and cu expected the page table lookup() function to return
a bool, and this value was used directly in the gpu tlb's
assert and it was kept in the gpu tlb entry, where later
the cu would assert that it is true.
this change fixes the issue by checking the validity of
the pte pointer returned by lookup() in order to set
the validity of the tlb entry itself.
Change-Id: Ief1f205db65f1911fd132acd314e4407c5e3ffdf
Reviewed-on: https://gem5-review.googlesource.com/10001
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
When EL3 is not implemented or it is running on AArch64, Secure banking
does not apply and there is only one flatten register version. In this
scenario gem5 is using the _NS (Non-secure) version as a default backing
storage location: secure mode software must be able to access the
non-secure register.
Change-Id: I5086e6228a5cba4d18c632543a2bcf80ffb069a8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9941
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
The touchscreen model used ad-hoc mechanisms to enable/disable the
device. Use standard PS/2 commands to activate/deactivate the
device. Add proper TouchKit command handling.
Change-Id: I0c5a2e2b47639f36ab3ee07e3e559f11afa54b9d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9768
Reviewed-by: Gabe Black <gabeblack@google.com>
All PS/2 device currently implement various ad-hoc mechanisms to
handle multi-byte commands. This is error-prone and makes it hard to
implement new devices. Create a buffering mechanism in the base class
to avoid this.
Change-Id: If5638b0ab68decea8de7631ecead0a9ebad1547b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9765
Reviewed-by: Gabe Black <gabeblack@google.com>
PS/2 devices are currently emulated both in the i8042 model and the
Arm KMI model. This is undesirable since it leads to code duplication.
This change introduces a common PS/2 device interface and factor out
the x86 keyboard and mouse model. A subsequent commit will implement
support for this interface in the Arm KMI model.
Change-Id: I440e83517fd9dce362fdc1676db477cc6eee5211
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9762
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
There are many devices that need to handle reads/writes of different
word sizes. A common pattern is a switch statement that check for the
size of a packet and then calls the corresponding
Packet::(get|set)<uintXX_t> methods. Simplify this by implementing
Packet::(get|set)UintX helper functions.
The getter reads a word of the size specified in the packet and the
specified endianness. The word is then zero-extended to 64
bits. Conversely, the setter truncates the word down to the size
required in the packet and then byte-swaps it to the desired
endianness.
Change-Id: I2f0c27fe3903abf3859bea13b07c7f5f0fb0809f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9761
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Since a3177645, the MESI_Three_Level protocol does not build. This
changeset addresses the problem by adding the L0Cache machine type
to the static machine type declaration in Ruby's export file.
Change-Id: I6327547fcb34595619caeb73932c0032f5f65c9f
Reviewed-on: https://gem5-review.googlesource.com/8383
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
FALRU was missing MoveToTail functionality within its invalidate
function, and MoveToHead was doing unnecessary passes when the
moved block was the head already.
Besides, added some comments to make the code understandable.
Change-Id: I2430d82b5d53c88b102a62610ea38b46d6e03a55
Reviewed-on: https://gem5-review.googlesource.com/9541
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
These are single byte commands which change the mode of the mouse. They don't
take any additional parameters like the SetRate or SetResolution.
Change-Id: I29194916cfed5d3f4893947ef6d6cc636aee2419
Reviewed-on: https://gem5-review.googlesource.com/9701
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
When we transitioned from having PCs and nextPCs stored as individual items
in the ThreadContext and went to having PC objects with abstracted
components (micro PCs, delay slots, variable instruction lengths, etc.), a
small mistake was made when translating the alpha StackTrace code.
Change-Id: Ib5dd65c53a26920e66899f421902607efd139e71
Reviewed-on: https://gem5-review.googlesource.com/9702
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
