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arch-arm: Using explicit invalidation in TLB

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When setting TLB related MiscRegs, using explicit TLB regs invalidation
rather than implicit switch-case fallthrough

Change-Id: Ia1a7358b6d54dda3811be1c5ce5d676f8c518c4d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10041
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2017-12-11 13:20:07 +00:00
parent 5cebd91336
commit 8a690593f4
1 changed files with 8 additions and 8 deletions
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16
src/arch/arm/isa.cc
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2016 ARM Limited
* Copyright (c) 2010-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1695,8 +1695,11 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
} else {
newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
}
// Invalidate TLB MiscReg
getITBPtr(tc)->invalidateMiscReg();
getDTBPtr(tc)->invalidateMiscReg();
break;
}
M5_FALLTHROUGH;
case MISCREG_TTBR0:
case MISCREG_TTBR1:
{
@@ -1709,15 +1712,12 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
newVal = (newVal & (~ttbrMask));
}
}
}
M5_FALLTHROUGH;
case MISCREG_SCTLR_EL1:
{
// Invalidate TLB MiscReg
getITBPtr(tc)->invalidateMiscReg();
getDTBPtr(tc)->invalidateMiscReg();
setMiscRegNoEffect(misc_reg, newVal);
break;
}
M5_FALLTHROUGH;
case MISCREG_SCTLR_EL1:
case MISCREG_CONTEXTIDR:
case MISCREG_PRRR:
case MISCREG_NMRR: